JP4082820B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a high-frequency semiconductor device used in a microwave band and a millimeter wave band of several GHz or more.
[0002]
[Prior art]
FIG. 15 shows a packaged conventional high-frequency semiconductor device 101. As shown in the figure, the high-frequency semiconductor device 101 is die-bonded to a high-frequency semiconductor device package 104 with a solder material such as AuSn eutectic solder or a conductive adhesive. Further, the high-frequency signal input / output line 102 formed in the package 104 and the semiconductor device 101 are connected by a bonding wire 103 which is an Au wire having a diameter of about 25 μm, and a high-frequency signal is input to the semiconductor device 101 by the bonding wire 103. Output is done.
[0003]
[Problems to be solved by the invention]
However, when the semiconductor device 101 and the signal input / output line 102 are connected by the bonding wire 103 as described above, the inductance component of the bonding wire 103 acts as a resistance component in a high frequency region such as a millimeter wave band, so that the loss of the transmission signal Will increase. In addition, since the bonding wire 103 cannot perform line impedance control as a high-frequency signal transmission line, the bonding wire 103 and the bonding wire 103 and the signal input / output line 102 are connected between the bonding wire 103 and the semiconductor device 101. There is a problem that impedance mismatch occurs between them and the reflection loss of the semiconductor device 101 increases.
[0004]
In order to solve the above problem, JP-A-2-288252 and “DBIT-Direct Backside Interconnect Technology: A Manufacturable, Bond Wire Free Interconnect Technology for Microwave and Millimeter Wave MMICs” (1997 IEEE MTT-S Digest 723-726) Has proposed a semiconductor device that can be mounted without using bonding wires. The semiconductor devices disclosed in these documents include a front electrode provided on the front surface of the substrate and a back electrode on the back surface of the substrate, and a metal layer is formed on the concave portion formed on the side surface of the substrate, thereby forming the front electrode and the back surface. The electrode is electrically connected. Such a semiconductor device can be mounted on a package without using a bonding wire by connecting the back electrode thereof and the signal input / output line of the mounting substrate with a solder material or a conductive resin material.
[0005]
By the way, normally, when evaluating the characteristics of a high-frequency semiconductor device in a wafer state, the wafer is fixed to a metallic stage of the evaluation device by a vacuum chuck method or the like, and a probing needle is brought into contact with the surface electrode of each semiconductor device. The reason why the stage for fixing the wafer is metallic is that the back surface of each high-frequency semiconductor device needs to be grounded. Accordingly, a ground electrode is formed on the back surface of the high-frequency semiconductor device.
[0006]
However, when a semiconductor device having a ground electrode and a back electrode on the back surface of the substrate as described above is fixed to a metallic stage, the back electrode and the ground electrode are electrically connected and electrically separated from the ground electrode. The surface electrode to be shorted with the ground electrode. Therefore, it has been impossible to evaluate the characteristics of the conventional semiconductor device in the wafer state.
[0007]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of evaluating characteristics in a wafer state.
[0008]
[Means for Solving the Problems]
The semiconductor device of the present invention includes a substrate, an IC pattern provided on the surface of the substrate, a recess provided in the side surface of the substrate and extending in the thickness direction of the substrate, and provided in the vicinity of the recess on the surface and connected to the IC pattern. A signal input / output pad, a metal layer formed in the recess and conducting to the signal input / output pad, and a ground conductor formed on the back surface of the substrate, and the IC pattern is formed through the metal layer and the signal input / output pad. A semiconductor device for inputting and outputting signals, wherein the metal layer does not reach the back surface of the substrate in the recess. That is, since the metal layer is not formed around the opening on the back side of the recess, even if the semiconductor device of the present invention is fixed to a metallic stage, the signal input / output pad is short-circuited through the recess. The characteristic evaluation can be performed in the wafer state. Furthermore, the semiconductor device of the present invention can reduce reflection characteristics due to impedance mismatching by mounting on a mounting substrate without using bonding wires.
[0009]
Another semiconductor device of the present invention includes a substrate, an IC pattern provided on the surface of the substrate, a recess provided on a side surface of the substrate and extending in the thickness direction of the substrate, and an IC provided in the vicinity of the recess on the surface. A signal input / output pad connected to the pattern, a metal layer formed in the recess and conducting to the signal input / output pad, a ground conductor formed on the back surface of the substrate, and a metal layer provided in the vicinity of the recess on the back surface A backside pad electrically connected to the signal input / output pad, and a semiconductor device for inputting / outputting a signal to / from the IC pattern via the metal layer and the signal input / output pad. A surface pad portion that is electrically connected to the IC pattern, and an IC side pad portion that is electrically connected to an IC pattern formed away from the surface pad. In addition, the front surface pad portion is provided with a preliminary connection portion provided through a gap, and the preliminary connection portion is crimped and connected to the front surface pad portion so that the front surface pad portion and the IC side pad portion are electrically connected. And That is, before the preliminary connection portion is crimped and connected, the semiconductor device in a wafer state is fixed to a metallic stage, and the probing needle is brought into contact with the IC side pad portion, whereby the characteristics of the semiconductor device can be evaluated. In addition, another semiconductor device of the present invention can reduce reflection characteristics due to impedance mismatch by mounting on a mounting substrate without using bonding wires.
[0010]
Still another semiconductor device of the present invention includes a substrate, an IC pattern provided on the surface of the substrate, a recess provided on a side surface of the substrate and extending in the thickness direction of the substrate, and an IC pattern provided near the recess on the surface. A signal input / output pad connected to the substrate, a metal layer formed in the recess and conducting to the signal input / output pad, a ground conductor formed on the back surface of the substrate, and a signal provided through the metal layer provided around the recess on the back surface A backside pad electrically connected to the input / output pad, and a semiconductor device for inputting / outputting a signal to / from the IC pattern through the metal layer and the signal input / output pad. The signal input / output pad is connected to the backside pad through the recess. A conductive surface pad part, an IC side pad part that conducts to an IC pattern formed away from the surface pad, and a connection part that electrically connects the IC side pad part and the surface pad, At least one of the surface pad portion and the IC side pad portion is made of Au, The connection part is formed after the IC side pad part and the surface pad part are formed. , Deform the above Au It is provided. That is, before forming the connection portion, the semiconductor device in a wafer state is fixed to a metallic stage, and the probing needle is brought into contact with the IC-side pad portion, whereby the characteristics of the semiconductor device can be evaluated. Furthermore, another semiconductor device of the present invention can reduce reflection characteristics due to impedance mismatch by mounting on a mounting substrate without using bonding wires.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0014]
Embodiment 1 FIG.
First, a semiconductor device 50 according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2. As shown in FIG. 1, the semiconductor device 50 includes an IC pattern (not shown in FIG. 1) such as an FET, a signal input / output pad 2 for inputting / outputting a high frequency signal to / from the IC pattern for characteristic evaluation, And a bias pad 5 for applying a bias to the IC pattern. Specifically, the IC pattern, the signal input / output pad 2 and the bias pad 5 are formed on the surface 50a of the substrate 1 having a thickness of 100 μm. Further, the IC pattern and the signal input / output pad 2 and the IC pattern and the bias pad 5 are connected by a wiring pattern 6 formed on the surface 50 a of the substrate 1. A ground conductor 7 is formed on the back surface 50 b of the substrate 1.
[0015]
The wiring pattern 6 is formed by a method such as vapor deposition, and the signal input / output pad 2 and the bias pad 5 are formed by a method such as an electrolytic plating method. The signal input / output pad 2 and the bias pad 5 to which an external bonding wire or probing needle is connected are formed thicker than the wiring pattern 6. The signal input / output pad 2 and the bias pad 5 used in the present embodiment are Au having a thickness of about 5 μm, and the wiring pattern 6 is Au having a thickness of about 2 μm.
[0016]
The semiconductor device 50 includes a semicircular recess 3 extending from the front surface 50 a to the back surface 50 b on the side surface of the substrate 1, and the signal input / output pad 2 and the bias pad 5 are disposed adjacent to the recess 3. ing. Further, a metal layer 4 is formed in a region (hereinafter referred to as a conductive region) from the front surface side 50a of the recess 3 to a depth of about 90 μm, while a region (hereinafter referred to as insulation) from the back surface side 50b of the recess 3 to a depth of 10 μm. The metal layer is not formed in the region). Further, as shown in FIG. 2, the signal input / output pad 2 is connected to the metal layer 4 and becomes conductive. That is, the metal layer 4 formed in the recess 3 is continuously formed up to the middle of the recess 3, but does not reach the back surface side 50b. Further, the ground conductor 7 is not formed around 10 μm around the recess 3 on the back surface 50 b of the substrate 1. This prevents the metal layer 4 and the ground conductor 7 from being short-circuited after the semiconductor device 50 is mounted.
[0017]
Similarly to the recess 3 connected to the signal input / output pad 2 described above, the recess 3 connected to the bias pad 5 includes a conductive region and an insulating region, and is formed on a metal layer formed in the conductive region. The bias pad 5 comes into contact and is conducted.
[0018]
In this embodiment, the signal input / output pad 2 and the bias pad 5 are formed in the vicinity of the recess formed on the side surface of the substrate 1.
[0019]
Next, a method for forming the concave portion will be described. First, the surface 50a of the substrate 1 in a wafer state is divided into a plurality of chip areas, and an IC pattern, a wiring pattern 6 and the like are formed in each chip area. Note that the chip section means a section corresponding to the semiconductor device after the wafer is chipped. Next, a hole having a depth of about 90 μm from the surface 50a is formed across each chip area. In this embodiment using a GaAs wafer, holes are formed by etching using a chlorine-based gas. Next, a metal layer is formed on the wall of the hole by sputtering. At this time, if necessary, Au may be added to the metal layer by a plating method. Further, after a desired pattern is formed on the surface of each chip area, the thickness of the wafer is set to 100 μm. Subsequently, by using an alignment apparatus using infrared rays, a GaAs wafer having a thickness of about 10 μm is removed from the back side of the hole having a depth of about 90 μm previously formed by resist patterning and etching to penetrate the hole. . In this way, a metal layer is formed from the front surface to a depth of about 90 μm, while a through hole in which no metal layer is formed from the back surface to a depth of about 10 μm is formed in the wafer. That is, the vicinity of the back surface side of the through hole is insulated. When such a wafer is chipped, the semiconductor device 50 is obtained. Since the through hole is formed so as to straddle each chip area, when the wafer is formed into chips, the through hole is cut in the depth direction (cut in the vertical direction). It becomes a shape.
[0020]
As described above, since the semiconductor device 50 in the wafer state includes the through hole in which the vicinity of the back surface side is insulated, the back surface 50b of the semiconductor device 50 in the wafer state is in contact with the metallic stage of the evaluation apparatus. Even if fixed in this way, the signal input / output pad 2 and the ground conductor 7 do not conduct. Therefore, the semiconductor device 50 in the wafer state is fixed to the metallic stage, and the probing needle is brought into contact with the signal input / output pad 2 to perform the characteristic evaluation in the wafer state such as the high frequency characteristic and the direct current characteristic of the semiconductor device 50. Can do.
[0021]
Next, a method for mounting the semiconductor device 50 will be described with reference to FIGS. The mounting substrate 12 on which the semiconductor device 50 is mounted includes a signal input / output line 9 that transmits a high-frequency signal, a bias line 10, and a mounting substrate-side ground conductor 13. The signal input / output line 9 is electrically connected to the signal input / output pad 2 of the semiconductor device 50, the bias line 10 is electrically connected to the bias pad 5, and the mounting board side ground conductor 13 is electrically connected to the ground conductor 7.
[0022]
First, the AuSn solder material 11 is applied to the portion of the circuit board that forms the high frequency signal input / output line 9, the bias line 10, and the mounting board side ground conductor 13 of the mounting board 12 that contacts the semiconductor device 50. At this time, the bias line 10 and the input / output line 9 are both provided in the respective recesses 3 by bridging the insulating regions provided in the recesses with the solder material 11. It is necessary to make an electrical connection to the metal layer 4. As described above, since the depth of the insulating region formed in the recess 3 is about 10 μm, the thickness of the solder material 11 applied to the bias line 10 and the input / output line 9 needs to be 10 μm or more. In the present embodiment, the thickness is 20 μm.
[0023]
Thus, after applying the solder material 11 to the mounting substrate 12, the recess 3 provided with the signal input / output pad 2 is located on the signal input / output line 9, and the recess 3 provided with the bias pad 5 is the bias line. The semiconductor device 50 is disposed at a predetermined position of the mounting substrate 12 so as to be located on the semiconductor substrate 10. Further, the temperature of the semiconductor device 50 and the mounting substrate 12 is increased to about 300 ° C., and the solder material 11 is melted to form the semiconductor. The device 50 is mounted on the mounting substrate 12.
[0024]
Thus, in the semiconductor device 50 mounted on the mounting substrate 12, the metal layer 4 and the signal input / output line 9 are applied to the signal input / output line 9 in advance on the side surface of the substrate 1 as shown in FIG. They are connected by solder material 11. The solder material 11 is formed so that the signal input / output line 9, the metal layer 4, and the insulating region of the substrate 1 are continuous.
[0025]
The signal input / output line 9 is electrically connected to the IC pattern 8 via the signal input / output pad 2 and the wiring pattern 6, and the bias line 10 is connected to the IC pattern via the bias pad 5 and the wiring pattern 6. 8 is electrically connected. That is, since the semiconductor device 50 can be mounted on the mounting substrate 12 without using wire bonding, reflection loss due to impedance mismatch can be reduced.
[0026]
In the above embodiment, AuSn is used to mount the semiconductor device 50 on the mounting substrate 12, but the present invention is not limited to this. For example, even if the semiconductor device 50 is mounted on the mounting substrate 12 using a conductive connecting material such as PbSn solder or a conductive resin material, the same operations and effects as in the above embodiment can be obtained.
[0027]
Further, in the above embodiment, the semiconductor device 50 is mounted on the mounting substrate 12, but the present invention is not limited to this, and the method described above is applied to a package for a semiconductor device provided with a bias line and a signal input / output line. The semiconductor device 50 may be mounted by the same method as described above.
[0028]
Embodiment 2. FIG.
Next, a semiconductor device 51 according to the second embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 5, the semiconductor device 51 includes an IC side pad 2 a, a wiring pattern 6, a surface pad 15, and a conductive preliminary connection portion 14 formed on the surface of the substrate 1. The wiring pattern 6 connects the IC side pad 2a to an IC pattern (not shown). The IC side pad 2a inputs / outputs a high frequency signal to / from an IC pattern (not shown) formed on the substrate 1. That is, the signal input / output pad 2 b of the semiconductor device 51 includes the surface pad 15, the IC side pad 2 a, and the preliminary connection portion 14. The semiconductor device 51 includes a semicircular recess 3 extending from the front surface 51a to the back surface 51b on the side surface of the substrate 1, and the recess 3 has a metal layer 4 (not shown in FIG. 5) extending from the front surface 51a to the back surface 51b. ) Is formed.
[0029]
As shown in FIG. 6, the preliminary connection portion 14 is connected to the IC side pad 2. Further, the preliminary connection portion 14 is three-dimensionally crossed with a gap of 2 to 3 μm so as to be insulated from the surface pad 15 (air bridge structure). Further, as shown in FIG. 7, the back surface pad 16 and the ground electrode 7 that are insulated from each other are formed on the back surface 51 b of the substrate 1, and the front surface pad 15 and the back surface pad 16 are metal layers formed in the recess 3. 4 conducts. The surface pad 15 and the connection portion 14 are formed by a known means using Au.
[0030]
The bias pad of the semiconductor device 51 is composed of a surface pad, an IC side pad, and a preliminary connection portion, like the signal input / output pad.
[0031]
As described above, on the surface of the substrate 1, the surface pad 15 and the IC side pad 2a are insulated. Therefore, the semiconductor device 51 in the wafer state is fixed so that the back surface 51b of the semiconductor device 51 is in contact with the metallic stage of the evaluation device, and the probing needle is brought into contact with the IC-side pad 2a or the preliminary connection portion 14, whereby the wafer is obtained. In this state, characteristics such as high frequency characteristics and direct current characteristics of the semiconductor device 50 can be evaluated.
[0032]
Further, after the characteristic evaluation is completed, while the substrate 1 is heated to about 200 ° C., the preliminary connection portion 14 is pressed from above with a metallic needle-shaped member and thermocompression bonded to the surface pad 15, so that the connection portion 14 and the surface pad are 15 is conducted. In addition, a better connection can be obtained by using ultrasonic vibration in combination when pressing. By doing so, the back surface pad 16 and the IC pattern are brought into conduction through the metal layer 4, the front surface pad 15, the pressed preliminary connection portion 14, the IC side pad 2 a, and the wiring pattern 6. In the same manner, the IC side pad forming the bias pad and the surface pad are made conductive.
[0033]
The semiconductor device 51 that has undergone the above-described steps can be mounted on a package or mounting substrate for a semiconductor device including a bias line and an input / output line by using an AuSn solder material or the like. At this time, since wire bonding for connecting the semiconductor device 51 and the package for semiconductor device or the mounting substrate is not required, reflection loss due to impedance mismatch can be reduced.
[0034]
In the second embodiment, after the IC side pad and the surface pad are connected with the air bridge structure, the IC side pad and the surface pad are made conductive. However, the present invention is not limited to this, and As described in the third embodiment, after providing the IC side pad and the surface pad, a connection portion may be formed to make the IC side pad and the surface pad conductive.
[0035]
Embodiment 3 FIG.
As shown in FIG. 8, in the semiconductor device 52 according to the third embodiment of the present invention, the IC-side pads 2a and the surface-side pads 17 are formed on the surface of the substrate 1 with an interval of about 20 μm. The front surface pad 17 is formed by Au plating, and is electrically connected to the back surface pad 16 through the metal layer 4 formed in the recess 3 as in the second embodiment. The IC side pad 2a inputs / outputs a high frequency signal to / from an IC pattern (not shown) formed on the substrate 1. That is, the signal input / output pad of the semiconductor device 52 includes the surface pad 17 and the IC side pad 2a which are insulated from each other. It should be noted that the IC side pad 2a is connected to the IC pattern (not shown) via the wiring pattern 6 and the ground conductor 7 is provided on the back surface 52b. It is the same.
[0036]
Also, the bias pad for applying a bias to the IC pattern of the semiconductor device 52 is separated into an IC side pad that conducts to the IC pattern and a front surface pad that conducts to the back surface pad through the recess, like the signal input / output pad. They are insulated from each other (not shown).
[0037]
As described above, on the surface 52a of the substrate 1, the surface pad 2a and the IC side pad 17 are insulated. Therefore, the semiconductor device 52 in the wafer state is fixed so that the back surface 52b is in contact with the metallic stage of the evaluation device, and the probing needle is brought into contact with the IC-side pad 2a. Characteristic evaluation such as direct current characteristics can be performed.
[0038]
After performing the characteristic evaluation of the semiconductor device 52, the surface pad 2a and the IC side pad 17 are made conductive. Specifically, as shown in FIG. 9, for example, a 25 μmφ Au wire 19 is used to connect the IC side pad 2 a and the surface pad 17, and by a known wedge bonding technique used for mounting a high frequency semiconductor device, It is heated to about 200 ° C. and bonded by the bonding wedge 20 by thermocompression bonding or ultrasonic thermocompression bonding. Next, with a clamper (not shown) provided in the wedge bonding apparatus, the Au wire 19 is pulled upward together with the bonding wedge 20 while pinching the Au wire 19, and the neck portion 21 of the Au wire 19 is broken. In this way, Au wedge studs 18 for connecting the surface pads 17 and the IC side pads 2a as shown in FIG. 10 are formed.
[0039]
In the same way, the IC-side pad constituting the bias pad and the surface pad are connected.
[0040]
When a 25 μmφ Au wire 19 is used, the length of the Au wedge stud 18 is about 70 μm. That is, when a 25 μmφ Au wire is used, the distance between the IC side pad 17a and the surface pad 2a can be arbitrarily set within a range of 70 μm or less.
[0041]
The semiconductor device 52 that has undergone the above-described steps can be mounted on a package or mounting substrate for a semiconductor device including a bias line and an input / output line by using an AuSn solder material or the like. At this time, since wire bonding for connecting the semiconductor device 52 and the package for semiconductor device or the mounting substrate is not required, reflection loss due to impedance mismatch can be reduced.
[0042]
In the above embodiment, the Au wedge stud 18 is formed by using the Au wire. However, the present invention is not limited to this, and the same effect can be obtained by forming the Au ball stud by using ball bonding. Is obtained.
[0043]
In the third embodiment, the IC side pad 2a and the front surface pad 17 are made conductive by the connecting portion 18 formed of an Au wedge stud, but the present invention is not limited to this. As shown in the following modification, the IC side pad 2a and the surface pad 17 may be connected.
[0044]
Modification 1
As shown in FIG. 11, in the first modification of the semiconductor device 52, the IC side pad 2a and the surface pad 17 are connected by the conductive resin 22 containing Ag. Specifically, after evaluating the characteristics of the semiconductor device 52 in a wafer state, the conductive resin 22 is applied using a resin potting device so as to connect the IC-side pad 2a and the surface pad 17, and then the semiconductor The apparatus 52 is heated to about 150 ° C. to cure the conductive resin 22. In the same way, the IC-side pad constituting the bias pad and the surface pad are connected.
[0045]
Modification 2
As shown in FIG. 12, in the second modification of the semiconductor device 52, the IC side pad 2 a and the surface pad 17 are connected by the AuSn solder material 23. Specifically, after evaluating the characteristics of the semiconductor device 52 in the wafer state, the AuSn solder material 23 is installed so as to connect the IC-side pad 2a and the surface pad 17, and then heated to about 300 ° C. The semiconductor device 52 is placed thereon, and the AuSn solder material 23 is melted, whereby the IC side pad 2a and the surface pad 17 are made conductive. The same effect can be obtained even if PbSn is used as the solder material. In the same way, the IC-side pad constituting the bias pad and the surface pad are connected.
[0046]
Modification 3
Next, Modification 3 of the semiconductor device 52 will be described. When manufacturing the semiconductor device according to the modified example 3, first, as shown in FIG. 13, the recess 3, the surface pad 17, the IC side pad 2 a and the wiring pattern 6 are formed on the substrate 1. The IC side pad 2a and the surface pad 17 are both formed by Au plating, and the thickness of each is about 5 μm, and the distance between the IC side pad 2a and the surface pad 17 is 10 μm. The IC side pad 2a is connected to the IC pattern through the wiring pattern 6, and the front surface pad 17 is electrically connected to the back surface pad (not shown) through the metal layer formed in the recess 3. This is the same as the semiconductor device 52 described above.
[0047]
After the IC side pad 2a and the surface pad 17 are insulated from each other, the characteristics of the semiconductor device in the wafer state are evaluated, and then the IC side pad 2a and the surface pad 17 are pressed by the wedge 24 as shown in FIG. Thus, the IC side pad 2a and the surface pad 17 are deformed so as to come into contact with each other. By doing so, the IC side pad 2a and the surface pad 17 are made conductive. When pressing the IC side pad 2a and the surface pad 17 with the wedge 24, ultrasonic vibration is used together. In the same way, the IC-side pad constituting the bias pad and the surface pad are connected.
[0048]
In the modification 3, both the IC side pad 2a and the surface pad 17 are formed of Au, but the present invention is not limited to this, and either the IC side pad 2a or the surface pad 17 is formed of Au. Then, the IC side pad 2a and the surface pad 17 may be electrically connected by deformation.
[0049]
【The invention's effect】
In the semiconductor device of the present invention, a metal layer that is electrically connected to the signal input / output pad and does not reach the back surface of the substrate is formed in the recess. Characteristic evaluation can be performed in a wafer state without shorting the input / output pads.
[0050]
Another semiconductor device of the present invention includes a preliminary connection portion that is electrically connected to the IC side pad portion, is located above the surface pad portion, and is insulated from the surface pad portion through a gap. Can be electrically connected to the surface pad portion by connecting the surface pad to the surface pad portion.
[0051]
Still another semiconductor device of the present invention includes a front surface pad portion, an IC side pad portion that is insulated from the front surface pad and is electrically connected to the IC pattern, and a connection portion that electrically connects the IC side pad portion and the front surface pad. Before the connection part is formed, the semiconductor device in the wafer state is fixed to a metal stage, and probing, that is, before the connection part is formed on the IC side pad part, The semiconductor device characteristics can be evaluated by fixing the semiconductor device in a wafer state to a metallic stage and bringing a probing needle into contact with the IC side pad portion. In addition, another semiconductor device of the present invention can reduce reflection characteristics due to impedance mismatch by mounting on a mounting substrate without using bonding wires.
[0052]
In another semiconductor device of the present invention, the connection portion can be formed by a conventional method by using an Au wire as the connection portion.
[0053]
In another semiconductor device of the present invention, the connection portion can be easily formed by using a conductive resin as the connection portion.
[0054]
In another semiconductor device of the present invention, the connection portion can be easily formed by using the connection portion as a solder material.
[0055]
In another semiconductor device of the present invention, at least one of the surface pad part and the IC side pad part is Au In shape Then, the connection portion can be formed very easily by deforming Au into a connection portion so that the surface pad portion and the IC side pad portion are electrically connected.
[Brief description of the drawings]
FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a front view of the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a plan view of the semiconductor device according to the first embodiment of the present invention mounted on a mounting substrate.
4 shows a cross-sectional view along line IV-IV in FIG.
FIG. 5 is a front view of a semiconductor device according to a second embodiment of the present invention.
6 shows a cross-sectional view along line VI in FIG.
FIG. 7 is a front view of a semiconductor device according to a second embodiment of the present invention.
FIG. 8 is a perspective view of a semiconductor device according to a third embodiment of the present invention.
FIG. 9 is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention;
FIG. 10 is a partial plan view of a semiconductor device according to a third embodiment of the present invention.
FIG. 11 is a partial plan view of a semiconductor device according to Modification 1 of Embodiment 3;
12 is a partial plan view of a semiconductor device according to Modification 2 of Embodiment 3. FIG.
FIG. 13 is a partial plan view illustrating the method for manufacturing the semiconductor device according to the third modification of the third embodiment.
FIG. 14 is a partial cross-sectional view illustrating the method of manufacturing the semiconductor device according to the third modification of the third embodiment.
FIG. 15 shows a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Board | substrate, 2 Input / output pad, 2a IC side pad, 3 Recessed part, 4 Metal layer, 5 Bias pad, 6 Wiring pattern, 7 Ground conductor, 8 IC pattern, 9 Signal input / output line, 10 Bias line, 11 Solder material , 12 mounting substrate, 14 preliminary connection portion, 15 surface pad, 16 back surface pad, 17 surface pad, 18 Au wedge stud, 19 Au wire, 20 bonding wedge, 22 conductive resin, 23 solder material, 24 wedge, 50 semiconductor Device, 51 semiconductor device, 52 semiconductor device.

Claims (3)

A substrate, an IC pattern formed on the surface of the substrate, and a recess extending in the thickness direction of the provided substrate to the side of the substrate, which is connected to the IC pattern provided near vicinity of the recessed portion in the surface A signal input / output pad; a metal layer formed in the recess and electrically connected to the signal input / output pad; and a ground conductor formed on the back surface of the substrate, the metal layer and the signal input / output pad interposed therebetween. A semiconductor device for inputting / outputting a signal to / from the IC pattern,
The semiconductor device, wherein the metal layer does not reach the back surface of the substrate in the recess. A substrate, an IC pattern provided on the surface of the substrate, a recess provided on a side surface of the substrate and extending in a thickness direction of the substrate, and a signal provided in the vicinity of the recess on the surface and connected to the IC pattern An input / output pad; a metal layer formed in the recess and conducting to the signal input / output pad; a ground conductor formed on the back surface of the substrate; and the back surface near the recess through the metal layer. A backside pad electrically connected to the signal input / output pad, and a semiconductor device for inputting / outputting a signal to / from the IC pattern via the metal layer and the signal input / output pad,
The signal input / output pad includes a front surface pad portion that conducts to the back surface pad through the recess, and an IC side pad portion that is formed away from the front surface pad and conducts to the IC pattern,
In addition, a preliminary connection portion is provided which is electrically connected to the IC-side pad portion, is located above the surface pad portion and is separated from the surface pad portion via a gap,
A semiconductor device, wherein the preliminary connection portion is crimped and connected to the front surface pad portion, and the front surface pad portion and the IC side pad portion are made conductive. A substrate, an IC pattern provided on the surface of the substrate, a recess provided on a side surface of the substrate and extending in a thickness direction of the substrate, and a signal provided in the vicinity of the recess on the surface and connected to the IC pattern An input / output pad; a metal layer formed in the recess and conducting to the signal input / output pad; a ground conductor formed on the back surface of the substrate; and the back surface near the recess through the metal layer. A backside pad electrically connected to the signal input / output pad, and a semiconductor device for inputting / outputting a signal to / from the IC pattern via the metal layer and the signal input / output pad,
The signal input / output pad includes a front surface pad portion that is electrically connected to the back surface pad through the recess, an IC side pad portion that is formed apart from the front surface pad and is electrically connected to the IC pattern, and the IC side pad portion. And a connection part for electrically connecting the surface pad,
At least one of the surface pad portion and the IC side pad portion is made of Au,
The semiconductor device according to claim 1, wherein the connection portion is formed by deforming the Au after the IC-side pad portion and the surface pad portion are formed.

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