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JP4068616B2 - Semiconductor device - Google Patents

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JP4068616B2
JP4068616B2 JP2004373097A JP2004373097A JP4068616B2 JP 4068616 B2 JP4068616 B2 JP 4068616B2 JP 2004373097 A JP2004373097 A JP 2004373097A JP 2004373097 A JP2004373097 A JP 2004373097A JP 4068616 B2 JP4068616 B2 JP 4068616B2
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electrode
chip
signal
semiconductor device
power supply
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JP2005210106A (en
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行敏 廣瀬
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Micron Memory Japan Ltd
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Elpida Memory Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing generated electromagnetic noise. <P>SOLUTION: A semiconductor device 100 has a plurality of laminated semiconductor chips 110. In the semiconductor device 100, by a through electrode penetrating the semiconductor chip 110, chips are connected electrically. Power is supplied to each semiconductor chip 110 by a plurality of power supply through electrodes 121 and ground through electrodes 122. Signal through electrodes 123, the power supply through electrodes 121 and the ground through electrodes 122 are adjacently arranged, and a loop area of a current path in which a current flows when the signal through electrode 123 changes its output is reduced. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

本発明は、半導体装置に関し、更に詳しくは、積層された複数のチップを有する半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of stacked chips.

近年デジタル情報家電などの小型軽量化、高機能・高性能化などにより、半導体パッケージの小型化、薄型化、高密度化が進んでおり、また、積層された複数の半導体チップを１つのパッケージに搭載する技術が注目されている。積層された複数の半導体チップを搭載する半導体装置は、例えば、高機能・高性能が要求されると共に小型軽量化が要求される、携帯電話や、デジタルカメラ、ＰＤＡなどの機器に使用される。   In recent years, with the reduction in size and weight of digital information home appliances, higher functionality, and higher performance, semiconductor packages have become smaller, thinner, and higher in density. In addition, a plurality of stacked semiconductor chips are integrated into one package. The technology to be installed is drawing attention. A semiconductor device on which a plurality of stacked semiconductor chips are mounted is used, for example, in devices such as a mobile phone, a digital camera, and a PDA, which are required to have high functionality and high performance, and to be reduced in size and weight.

図８（ａ）は、積層された複数のチップを有する従来の半導体装置を平面図で示し、同図（ｂ）は、同図（ａ）のＡ−Ａ断面を示している。この半導体装置２００は、チップサイズが相互に異なる３つの半導体チップ２０２を有する。同図（ｂ）に示すように、３つの半導体チップ２０２は、チップサイズが大きい半導体チップ２０２の上にチップサイズが小さい半導体チップ２０２が順次に搭載されて、ベース基板２０１上に積層される。   FIG. 8A shows a plan view of a conventional semiconductor device having a plurality of stacked chips, and FIG. 8B shows a cross section taken along the line AA of FIG. The semiconductor device 200 includes three semiconductor chips 202 having different chip sizes. As shown in FIG. 2B, the three semiconductor chips 202 are stacked on the base substrate 201 by sequentially mounting the semiconductor chips 202 having a small chip size on the semiconductor chip 202 having a large chip size.

図８（ａ）に示すように、各半導体チップ２０２は、その周縁領域に電極パッド２０３が形成され、半導体チップ２０２の電極パッド２０３相互間が、また、ベース基板２０１の電極パッド２０３と半導体チップ２０２の電極パッド２０３との間が、ボンディングワイヤ２０４により接続されている。この半導体装置２００では、電極パッド２０３にボンディングワイヤ２０４を接続する空間が必要であるため、ある半導体チップ２０２の上層には、その半導体チップよりもチップサイズが小さい半導体チップ２０２しか積層することができない。   As shown in FIG. 8A, each semiconductor chip 202 has an electrode pad 203 formed in the peripheral region thereof, between the electrode pads 203 of the semiconductor chip 202, and between the electrode pad 203 of the base substrate 201 and the semiconductor chip. The electrode pads 203 of 202 are connected by bonding wires 204. In this semiconductor device 200, since a space for connecting the bonding wire 204 to the electrode pad 203 is necessary, only a semiconductor chip 202 having a smaller chip size than that semiconductor chip can be stacked on an upper layer of the semiconductor chip 202. .

同じチップサイズを有する複数の半導体チップ２０２を積層できる技術としては、例えば特許文献１に記載された技術がある。図９は、特許文献１に記載された半導体装置３００を示している。この技術では、同じチップサイズの半導体チップ３０１を複数積層し、電極パッド３０２の形成位置に、複数の半導体チップ３０１を貫く貫通孔を形成し、その貫通孔に導電性の樹脂を注入して貫通電極３０３を形成し、貫通電極３０３によって半導体チップ３０１の電極パッド３０２間を接続している。この技術によれば、ボンディングワイヤのための空間を必要とせず、半導体チップ３０１をすべて同じサイズで形成することができる。
特開平１０−１６３４１１号公報 As a technique capable of stacking a plurality of semiconductor chips 202 having the same chip size, there is a technique described in Patent Document 1, for example. FIG. 9 shows a semiconductor device 300 described in Patent Document 1. In this technique, a plurality of semiconductor chips 301 of the same chip size are stacked, a through hole is formed through the plurality of semiconductor chips 301 at a position where the electrode pad 302 is formed, and a conductive resin is injected into the through hole. Electrodes 303 are formed, and the electrode pads 302 of the semiconductor chip 301 are connected by the through electrodes 303. According to this technique, a space for bonding wires is not required, and the semiconductor chips 301 can be formed with the same size.
JP-A-10-163411

ところで、図８に示す従来の半導体装置２００では、ボンディングワイヤ２０４と電極パッド２０３との接続の信頼性を確保するために、電極パッド２０３のパッドサイズは１００μｍ程度の大きさが必要である。また、隣接する２つのボンディングワイヤ２０４が接近しすぎるとクロストークやショートが発生するおそれがあるため、隣接する２つの電極パッド２０３間の距離をあまり短くすることはできない。このため、半導体チップ２０２上に作ることができる電極パッド２０３の数は制限されている。   In the conventional semiconductor device 200 shown in FIG. 8, the pad size of the electrode pad 203 needs to be about 100 μm in order to ensure the reliability of the connection between the bonding wire 204 and the electrode pad 203. In addition, if the two adjacent bonding wires 204 are too close, there is a possibility that a crosstalk or a short circuit may occur. Therefore, the distance between the two adjacent electrode pads 203 cannot be made too short. For this reason, the number of electrode pads 203 that can be formed on the semiconductor chip 202 is limited.

例えば、半導体チップ２０２がＤＲＡＭチップとして構成されるとき、電極パッド２０３には、電源端子やグランド端子に加えて、アドレス信号や、コマンド信号、コントロール信号、データ信号等の多数の信号端子が割り当てられる。上記のように、半導体チップ２０２では、形成できる電極パッド２０３の数が制限されている上に、電極パッド２０３には多数の信号端子を割り当てる必要があるため、半導体チップ２０２では、電源端子やグランド端子を割り当てることができる電極パッド２０３の数は更に制限されていた。   For example, when the semiconductor chip 202 is configured as a DRAM chip, a number of signal terminals such as an address signal, a command signal, a control signal, and a data signal are assigned to the electrode pad 203 in addition to a power supply terminal and a ground terminal. . As described above, in the semiconductor chip 202, the number of electrode pads 203 that can be formed is limited, and a large number of signal terminals need to be assigned to the electrode pads 203. The number of electrode pads 203 to which terminals can be assigned is further limited.

特許文献１に記載の半導体装置３００では、図８に示す従来の半導体装置２００に比して、チップ上に形成できる電極パッド数を増やすことができる。しかし、この半導体装置３００においても、電源端子及びグランド端子と信号端子とが近接して配置されていない場合には、以下に示すような問題が発生することとなる。   In the semiconductor device 300 described in Patent Document 1, the number of electrode pads that can be formed on a chip can be increased as compared with the conventional semiconductor device 200 shown in FIG. However, also in this semiconductor device 300, when the power supply terminal, the ground terminal, and the signal terminal are not arranged close to each other, the following problems occur.

図１０は、信号端子に近接して電源端子及びグランド端子が配置されない比較例の半導体装置を斜視図で示している。この半導体装置４００は、ＩＦ（インターフェース）チップ４０１と、ＤＲＡＭとして構成される４つの半導体チップ４０２とを有する。ＩＦチップ４０１に外部から供給された電源は、電源貫通電極４０３及びグランド貫通電極４０４を介して、各半導体チップ４０２内のチップ内電源配線４０５及びチップ内グランド配線４０６にそれぞれ供給される。ドライバ４０７は、半導体チップ２０２の周辺部分に配置されており、チップ内電源配線４０５及びチップ内グランド配線４０６から電源の供給を受けて動作する。ドライバ４０７が出力する信号は、信号貫通電極４０８を介してＩＦチップ４０１に入力される。   FIG. 10 is a perspective view of a semiconductor device of a comparative example in which a power supply terminal and a ground terminal are not disposed adjacent to the signal terminal. The semiconductor device 400 includes an IF (interface) chip 401 and four semiconductor chips 402 configured as a DRAM. The power supplied from the outside to the IF chip 401 is supplied to the in-chip power supply wiring 405 and the in-chip ground wiring 406 in each semiconductor chip 402 via the power supply through electrode 403 and the ground through electrode 404, respectively. The driver 407 is disposed in the peripheral portion of the semiconductor chip 202 and operates by receiving power from the in-chip power supply wiring 405 and the in-chip ground wiring 406. A signal output from the driver 407 is input to the IF chip 401 via the signal through electrode 408.

半導体装置４００において、最上層の半導体チップ４０２（３）のドライバ４０７が出力をＬレベルからＨレベルに変化させる場合について考える。この場合、図１０中に矢印４０９で示すような経路を流れる電流によって信号貫通電極４０８が充電される。この充電電流は、高電位側の電源から、ＩＦチップ４０１、電源貫通電極４０３、チップ内電源配線４０５、信号貫通電極４０８、及び、ＩＦチップ４０１をたどって低電位側の電源に帰還し、その電流経路は、立体的なループ状の電流経路を構成している。   In the semiconductor device 400, consider a case where the driver 407 of the uppermost semiconductor chip 402 (3) changes the output from the L level to the H level. In this case, the signal through electrode 408 is charged by a current flowing through a path indicated by an arrow 409 in FIG. This charging current is fed back from the high potential side power source to the low potential side power source through the IF chip 401, the power supply through electrode 403, the in-chip power supply wiring 405, the signal through electrode 408, and the IF chip 401. The current path constitutes a three-dimensional loop-shaped current path.

上記のようにして、最上層の半導体チップ４０２の出力がＬレベルからＨレベルに変化すると、半導体装置４００の外部では、上記のループの面積や、ループを流れる電流、その周波数成分に応じた電磁ノイズが発生する。比較例の半導体装置４００では、電源貫通電極４０３と信号貫通電極４０８とが離れているためループ面積が大きく、電磁ノイズが大きいという問題がある。また、半導体装置４００では、２つの信号貫通電極４０８が隣接して配置されていると、隣接する信号貫通電極４０８間でクロストークが発生することがあるという問題もある。   As described above, when the output of the uppermost semiconductor chip 402 changes from the L level to the H level, outside the semiconductor device 400, the area of the loop, the current flowing through the loop, and the electromagnetic wave corresponding to the frequency component Noise is generated. The semiconductor device 400 of the comparative example has a problem that the loop area is large and the electromagnetic noise is large because the power supply through electrode 403 and the signal through electrode 408 are separated. Further, in the semiconductor device 400, when the two signal through electrodes 408 are arranged adjacent to each other, there is a problem that crosstalk may occur between the adjacent signal through electrodes 408.

本発明は、積層された複数の半導体チップを有する半導体装置であって、発生する電磁ノイズを低減できる半導体装置を提供することを目的とする。また、本発明は、前記目的を達成した上で、隣接する信号線間のクロストークを抑制できる半導体装置を提供することを目的とする。   An object of the present invention is to provide a semiconductor device having a plurality of stacked semiconductor chips and capable of reducing generated electromagnetic noise. Another object of the present invention is to provide a semiconductor device that can suppress crosstalk between adjacent signal lines while achieving the above object.

上記目的を達成するために、本発明の半導体装置は、それぞれがチップ外信号線を介してチップ外に信号を出力する、積層された複数の半導体チップと、それぞれが前記チップ外信号線、電源線、及び、グランド線を構成し前記複数の半導体チップを貫通して延びる複数の貫通電極とを備える半導体装置において、少なくとも１つの前記チップ外信号線を構成する貫通電極が、前記電源線を構成する貫通電極と前記グランド線を構成する貫通電極の双方に隣接して配置されることを特徴とする。   In order to achieve the above object, a semiconductor device of the present invention includes a plurality of stacked semiconductor chips, each of which outputs a signal to the outside of the chip via an out-of-chip signal line, and the out-of-chip signal line and the power source. And a plurality of through electrodes extending through the plurality of semiconductor chips and forming at least one through-chip signal line constitutes the power supply line It is characterized by being disposed adjacent to both the penetrating electrode and the penetrating electrode constituting the ground line.

本発明の半導体装置では、上記構成を採用することにより、チップ外信号線が出力状態を変化させた際に、その信号線を構成する貫通電極と電源線を構成する貫通電極とを流れる電流の電流経路、又は、その信号線を構成する貫通電極とグランド線を構成する貫通電極とを流れる電流の電流経路のループ面積を小さくでき、半導体装置から発生する電磁ノイズを低減することができる。   In the semiconductor device of the present invention, by adopting the above-described configuration, when the signal line outside the chip changes the output state, the current flowing through the through electrode constituting the signal line and the through electrode constituting the power supply line is reduced. The loop area of the current path of the current flowing through the current path or the through electrode constituting the signal line and the through electrode constituting the ground line can be reduced, and electromagnetic noise generated from the semiconductor device can be reduced.

本発明の半導体装置では、順次に配列された、電源線を構成する貫通電極、前記チップ外信号線を構成する貫通電極、及び、前記グランド線を構成する貫通電極を含む構成を採用することができる。この場合、チップ外信号線を構成する貫通電極が、その両側から電源線を構成する貫通電極とグランド線を構成する貫通電極とによって挟み込まれていることにより、チップ外信号線を構成する貫通電極と電源線を構成する貫通電極、又は、チップ外信号線を構成する貫通電極とグランド線を構成する貫通電極とによって構成される立体的な電流ループの面積を小さくすることができ、発生する電磁ノイズを低減できる。   In the semiconductor device of the present invention, it is possible to employ a configuration including a through electrode that constitutes a power supply line, a through electrode that constitutes the off-chip signal line, and a through electrode that constitutes the ground line, which are sequentially arranged. it can. In this case, the through electrode constituting the signal line outside the chip is sandwiched between the through electrode constituting the power supply line and the through electrode constituting the ground line from both sides of the through electrode constituting the signal line outside the chip. The area of the three-dimensional current loop formed by the through electrode constituting the power line and the through electrode constituting the off-chip signal line and the through electrode constituting the ground line can be reduced, and the generated electromagnetic Noise can be reduced.

本発明の半導体装置では、隣接する２つのチップ外信号線を構成する貫通電極の間に、前記電源線を構成する貫通電極及び前記グランド線を構成する貫通電極の少なくとも一方が配置される構成を採用することができる。この場合、隣接する２つのチップ外信号線を構成する貫通電極の間のクロストークを抑制できる。   In the semiconductor device of the present invention, at least one of the through electrode constituting the power supply line and the through electrode constituting the ground line is disposed between the through electrodes constituting the adjacent two off-chip signal lines. Can be adopted. In this case, it is possible to suppress crosstalk between the through electrodes constituting the two adjacent off-chip signal lines.

本発明の半導体装置では、前記少なくとも１つのチップ外信号線を構成する貫通電極が、前記電源線を構成する貫通電極及び前記グランド線を構成する貫通電極の少なくとも一方を含む貫通電極によって囲まれる構成を採用することができる。この場合、チップ外信号線を構成する貫通電極に侵入するノイズ等を低減することができる。   In the semiconductor device of the present invention, the through electrode constituting the at least one off-chip signal line is surrounded by the through electrode including at least one of the through electrode constituting the power supply line and the through electrode constituting the ground line. Can be adopted. In this case, it is possible to reduce noise or the like entering the through electrode constituting the off-chip signal line.

本発明の半導体装置では、前記複数の半導体チップがＤＲＡＭを含む構成とすることができる。   In the semiconductor device of the present invention, the plurality of semiconductor chips may include a DRAM.

本発明の半導体装置では、チップ外信号線を構成する貫通電極と、電源線又はグランド線を構成する貫通電極とにより構成される立体的な電流経路のループの面積を小さくできるため、発生する電磁ノイズを低減することができる。また、隣接する２つのチップ外信号線を構成する貫通電極の間に、電源線又はグランド線を構成する貫通電極の少なくとも一方を配置する場合には、チップ外信号線を構成する貫通電極間で発生するクロストークを低く抑えることができる。   In the semiconductor device of the present invention, since the area of the three-dimensional current path loop formed by the through electrode constituting the off-chip signal line and the through electrode constituting the power supply line or the ground line can be reduced, the generated electromagnetic wave Noise can be reduced. When at least one of the through electrodes constituting the power supply line or the ground line is arranged between the through electrodes constituting the two adjacent off-chip signal lines, between the through electrodes constituting the off-chip signal lines. The generated crosstalk can be kept low.

以下、図面を参照し、本発明の実施形態例に基づいて、本発明を更に詳細に説明する。図１は、本発明の半導体装置を斜視図で示している。この半導体装置１００は、ＩＦチップ１０１と、その上に積層された３つの半導体チップ１１０（０）〜１１０（３）とを有し、各チップ間は、電源線を構成する電源貫通電極１２１と、グランド線を構成するグランド貫通電極１２２と、チップ外信号線を構成する信号貫通電極１２３とによって接続されている。電源貫通電極１２１、グランド貫通電極１２２、及び、信号貫通電極１２３は、それぞれ半導体チップ１１０の周縁部に形成される。   Hereinafter, with reference to the drawings, the present invention will be described in more detail based on exemplary embodiments of the present invention. FIG. 1 is a perspective view of a semiconductor device of the present invention. The semiconductor device 100 includes an IF chip 101 and three semiconductor chips 110 (0) to 110 (3) stacked on the IF chip 101, and a power supply through electrode 121 constituting a power supply line is provided between the chips. The ground through electrode 122 constituting the ground line and the signal through electrode 123 constituting the off-chip signal line are connected. The power supply through electrode 121, the ground through electrode 122, and the signal through electrode 123 are each formed on the peripheral edge of the semiconductor chip 110.

ＩＦチップ１０１は、ＩＦ内電源配線１０２と、ＩＦ内グランド配線１０３と、レシーバ１０４とを有する。各半導体チップ１１０は、ＤＲＡＭチップとして構成され、チップ内電源配線１１１と、チップ内グランド配線１１２と、ＤＲＡＭセル（内部回路）１１３と、ドライバ１１４とを有する。ＩＦチップ１０１に外部から供給された電源は、ＩＦ内電源配線１０２及びＩＦ内グランド配線１０３と、電源貫通電極１２１及びグランド貫通電極１２２とを介して、各半導体チップ１１０内のチップ内電源配線１１１及びチップ内グランド配線１１２に供給される。   The IF chip 101 includes an IF power supply wiring 102, an IF ground wiring 103, and a receiver 104. Each semiconductor chip 110 is configured as a DRAM chip, and includes an in-chip power supply wiring 111, an in-chip ground wiring 112, a DRAM cell (internal circuit) 113, and a driver 114. The power supplied from the outside to the IF chip 101 is supplied to the power supply wiring 111 in the chip in each semiconductor chip 110 through the power supply wiring 102 in the IF, the ground wiring 103 in the IF, the power supply through electrode 121 and the ground through electrode 122. And supplied to the intra-chip ground wiring 112.

図２は、図１の半導体装置１００の周縁部を断面図で示している。ＩＦチップ１０１及び各半導体チップ１１０には、それぞれチップ内を貫通するチップ内貫通電極が設けられており、ＩＦチップ１０１のチップ内貫通電極と半導体チップ１１０のチップ内貫通電極とをバンプ１２４によって接続することで、Ｚ方向に延びる貫通電極１２０が形成される。貫通電極１２０は、電源貫通電極１２１、グランド貫通電極１２２、又は、信号貫通電極１２３（図１）を含む。電源貫通電極１２１及びグランド貫通電極１２２は、信号が変化する際の電流経路のループ面積削減を目的として、或いは、信号貫通電極１２３間のクロストーク削減を目的として挿入されるものを含む。電源貫通電極１２１及びグランド貫通電極１２２と、信号貫通電極１２３との間隔は例えば５０μm程度であり、各貫通電極１２０の直径は例えば２０μm程度である。なお、貫通電極１２０間の間隔、貫通電極１２０の直径に関しては、貫通電極製造技術の進歩に従い、これらの値よりも小さくなることも考えられる。   FIG. 2 shows a peripheral portion of the semiconductor device 100 of FIG. 1 in a cross-sectional view. Each of the IF chip 101 and each semiconductor chip 110 is provided with an in-chip through electrode penetrating through the chip, and the in-chip through electrode of the IF chip 101 and the in-chip through electrode of the semiconductor chip 110 are connected by a bump 124. Thus, the through electrode 120 extending in the Z direction is formed. The through electrode 120 includes a power supply through electrode 121, a ground through electrode 122, or a signal through electrode 123 (FIG. 1). The power supply through electrode 121 and the ground through electrode 122 include those inserted for the purpose of reducing the loop area of the current path when the signal changes or for reducing the crosstalk between the signal through electrodes 123. The intervals between the power supply through electrode 121 and the ground through electrode 122 and the signal through electrode 123 are, for example, about 50 μm, and the diameter of each through electrode 120 is, for example, about 20 μm. Note that the distance between the through electrodes 120 and the diameter of the through electrodes 120 may be smaller than these values as the through electrode manufacturing technology advances.

図３は、半導体チップ１１０のドライバ１１４付近を平面図として示している。各電源貫通電極１２１は、それぞれチップ内電源配線１１１に接続され、各グランド貫通電極１２２は、それぞれチップ内グランド配線１１２に接続される。また、各信号貫通電極１２３は、ドライバ１１４の出力に接続される。電源貫通電極１２１及びグランド貫通電極１２２は、それぞれドライバ１１４及び信号貫通電極１２３に近接して配置されている。電源貫通電極１２１、グランド貫通電極１２２、及び、信号貫通電極１２３は、一列に並ぶように配置され、信号貫通電極１２３、Ｙ方向の両側から、電源貫通電極１２１及びグランド貫通電極１２２によって挟み込まれている。   FIG. 3 is a plan view showing the vicinity of the driver 114 of the semiconductor chip 110. Each power supply through electrode 121 is connected to the in-chip power supply wiring 111, and each ground through electrode 122 is connected to the in-chip ground wiring 112. Each signal through electrode 123 is connected to the output of the driver 114. The power supply through electrode 121 and the ground through electrode 122 are arranged close to the driver 114 and the signal through electrode 123, respectively. The power supply through electrode 121, the ground through electrode 122, and the signal through electrode 123 are arranged in a line, and are sandwiched by the signal through electrode 123 and the ground through electrode 122 from both sides in the Y direction. Yes.

信号貫通電極１２３と、電源貫通電極１２１及びグランド貫通電極１２２の比率は、それら貫通電極１２０の長さに応じて変更できる。例えば、積層されるチップ数が少ない場合には、貫通電極１２０の長さは短くなり、電流経路のループ面積は小さくなるため、信号貫通電極１２３間のクロストークの影響は小さい。このような場合には、信号貫通電極１２３と、電源貫通電極１２１及びグランド貫通電極１２２との比率を１：１とする必要はなく、複数の信号貫通電極１２３に対して、それぞれ１本の電源貫通電極１２１及びグランド貫通電極１２２を配置してもよい。   The ratio of the signal through electrode 123, the power supply through electrode 121, and the ground through electrode 122 can be changed according to the length of the through electrode 120. For example, when the number of stacked chips is small, the length of the through electrode 120 is reduced and the loop area of the current path is reduced, so that the influence of crosstalk between the signal through electrodes 123 is small. In such a case, the ratio of the signal through electrode 123 to the power through electrode 121 and the ground through electrode 122 does not have to be 1: 1, and one power source is provided for each of the plurality of signal through electrodes 123. The through electrode 121 and the ground through electrode 122 may be disposed.

図４は、図１の半導体装置１００を、チップ内の回路図の一部と共に模式的に示している。同図では、ＩＦチップ１０１に形成されるレシーバ１０４の１つ、及び、半導体チップ１１０に形成されるドライバ１１４の１つの回路部分を示している。以下、図１及び図４を参照し、最上層の半導体チップ１１０（３）のドライバ１１４（１）が、出力する信号をＬレベルからＨレベルに変化させる際の動作、及び、出力する信号をＨレベルからＬレベルに変化させる際の動作について説明する。   FIG. 4 schematically shows the semiconductor device 100 of FIG. 1 together with a part of a circuit diagram in the chip. In the figure, one circuit portion of one receiver 104 formed on the IF chip 101 and one driver 114 formed on the semiconductor chip 110 is shown. Hereinafter, referring to FIGS. 1 and 4, the operation when the driver 114 (1) of the uppermost semiconductor chip 110 (3) changes the output signal from the L level to the H level and the output signal are described. The operation when changing from the H level to the L level will be described.

ドライバ１１４（１）の出力がＨレベルであるとき、ドライバ１１４（１）を構成するｐＭＯＳトランジスタＭ１及びｎＭＯＳトランジスタＭ２のゲートにＬレベルの信号が入力されると、ｐＭＯＳトランジスタＭ１がオンに、ｎＭＯＳトランジスタがオフになって、ドライバ１１４（１）は、出力をＨレベルに変化させる。このとき、ドライバ１１４（１）には、外部電源から、ＩＦ内電源配線１０２、複数の電源貫通電極１２１のうち最もドライバ１１４に近接して配置される電源貫通電極１２１（１）、及び、チップ内電源配線１１１を介して、充電電流が供給される。この充電電流は、ｐＭＯＳトランジスタＭ１、信号貫通電極１２３（１）、レシーバ１０４の入力とＩＦ内グランド配線１０３との間の寄生容量Ｃ２、及び、ＩＦ内グランド配線１０３を介して、外部電源に帰還する。   When the output of the driver 114 (1) is at the H level, when an L level signal is input to the gates of the pMOS transistor M1 and the nMOS transistor M2 constituting the driver 114 (1), the pMOS transistor M1 is turned on, and the nMOS The transistor is turned off, and the driver 114 (1) changes the output to the H level. At this time, the driver 114 (1) includes, from an external power supply, the power supply wiring in the IF 102, the power supply through electrode 121 (1) disposed closest to the driver 114 among the plurality of power supply through electrodes 121, and the chip. A charging current is supplied through the internal power supply wiring 111. This charging current is fed back to the external power supply via the pMOS transistor M1, the signal through electrode 123 (1), the parasitic capacitance C2 between the input of the receiver 104 and the IF ground wiring 103, and the IF ground wiring 103. To do.

上記とは逆に、ドライバ１１４（１）の出力がＬレベルであるときドライバ１１４（１）を構成するｐＭＯＳトランジスタＭ１及びｎＭＯＳトランジスタＭ２のゲートにＨレベルの信号が入力されると、ｐＭＯＳトランジスタＭ１がオフに、ｎＭＯＳトランジスタがオンになって、ドライバ１１４（１）は、出力をＬレベルに変化させる。このとき、ドライバ１１４（１）には、外部電源から、ＩＦ内電源配線１０２、レシーバ１０４の入力とＩＦ内電源配線１０２との間の寄生容量Ｃ１、及び、信号貫通電極１２３（１）を介して、放電電流が供給される。この放電電流は、ｎＭＯＳトランジスタＭ２、チップ内グランド配線１１２、複数のグランド貫通電極１２２のうち最もドライバ１１４に近接して配置されるグランド貫通電極１２２（１）、及び、ＩＦ内グランド配線１０３を介して、外部電源に帰還する。   Contrary to the above, when an H level signal is input to the gates of the pMOS transistor M1 and the nMOS transistor M2 constituting the driver 114 (1) when the output of the driver 114 (1) is at the L level, the pMOS transistor M1. Is turned off, the nMOS transistor is turned on, and the driver 114 (1) changes the output to the L level. At this time, the driver 114 (1) is supplied from an external power source through the IF power line 102, the parasitic capacitance C 1 between the input of the receiver 104 and the IF power line 102, and the signal through electrode 123 (1). Thus, a discharge current is supplied. This discharge current passes through the nMOS transistor M2, the in-chip ground wiring 112, the ground through electrode 122 (1) disposed closest to the driver 114 among the plurality of ground through electrodes 122, and the IF in-ground ground wiring 103. Return to the external power supply.

ここで、本実施形態例の半導体装置１００におけるドライバ１１４の出力が変化した際に流れる電流の立体的な電流経路と、図１０に示した比較例の半導体装置４００における立体的な電流経路とを比較する。比較例の半導体装置４００では、電源貫通電極４０３及びグランド貫通電極４０４がドライバ４０７から離れた位置に形成されており、ドライバ４０７が出力を変化させた際に流れる充電電流又は放電電流の立体的な電流経路のループの面積が大きい。これに対して、本実施形態例の半導体装置１００では、充電電流又は放電電流は、それぞれ複数の電源貫通電極１２１及びグランド貫通電極１２２のうち、出力が変化するドライバ１１４に最も近い電源貫通電極１２１又はグランド貫通電極１２２によって供給されるため、比較例の半導体装置４００に比して、立体的な電流経路のループの面積を小さくできる。   Here, the three-dimensional current path of the current that flows when the output of the driver 114 in the semiconductor device 100 of this embodiment changes, and the three-dimensional current path of the semiconductor device 400 of the comparative example shown in FIG. Compare. In the semiconductor device 400 of the comparative example, the power supply through electrode 403 and the ground through electrode 404 are formed at positions away from the driver 407, and the three-dimensional charge current or discharge current that flows when the driver 407 changes the output. The loop area of the current path is large. On the other hand, in the semiconductor device 100 of this embodiment, the charging current or the discharging current is the power supply through electrode 121 closest to the driver 114 whose output changes among the plurality of power supply through electrodes 121 and the ground through electrode 122, respectively. Alternatively, since it is supplied by the ground through electrode 122, the area of the three-dimensional current path loop can be reduced as compared with the semiconductor device 400 of the comparative example.

本実施形態例では、貫通電極１２０（図２）を用いて上層側と下層側とを接続しており、半導体チップ１１０上に多数の電極パッドを形成できるため、信号電極パッドの近傍に、電源電極パッド及びグランド電極パッドを形成できる。このため、半導体装置１００では、信号貫通電極１２３の近傍に、電源貫通電極１２１及びグランド貫通電極１２２を配置する構成を採用することができ、この構成により、アドレスや、コマンド、データ等の信号が変化する際の電流経路のループ面積を小さくしている。一般に、面積Ｓの回路ループに周波数成分ｆを持つ電流ｉが流れた場合には、ループから距離ｒ離れた点における電界の大きさＥは、
Ｅ＝１．３１６×１０-14×（ｉ・ｆ2・Ｓ/ｒ） （１）
で表すことができ、本実施形態例の半導体装置１００では、上記のようにループ面積Ｓを小さくできるため、半導体装置１００から発生する電磁ノイズを低減することができる。 In the present embodiment example, the upper layer side and the lower layer side are connected using the through electrode 120 (FIG. 2), and a large number of electrode pads can be formed on the semiconductor chip 110. Electrode pads and ground electrode pads can be formed. For this reason, the semiconductor device 100 can employ a configuration in which the power supply through electrode 121 and the ground through electrode 122 are disposed in the vicinity of the signal through electrode 123. With this configuration, signals such as addresses, commands, and data can be transmitted. The loop area of the current path when changing is reduced. In general, when a current i having a frequency component f flows in a circuit loop having an area S, the electric field magnitude E at a point away from the loop by a distance r is:
E = 1.316 × 10 −14 × (i · f 2 · S / r) (1)
In the semiconductor device 100 of the present embodiment example, the loop area S can be reduced as described above, so that electromagnetic noise generated from the semiconductor device 100 can be reduced.

図５は、本発明の第２実施形態例の半導体装置における半導体チップの一部を平面図として示している。本実施形態例の半導体装置１００ａは、図１に示す第１実施形態例の半導体装置１００と同様に、積層された複数の半導体チップ１１０ａを有する。なお、図５では、半導体チップ１１０ａを図３と同様に示し、電源貫通電極１２１、グランド貫通電極１２２、及び、信号貫通電極１２３以外については省略して図示している。本実施形態例では、電源貫通電極１２１及びグランド貫通電極１２２は、隣接する２つの信号貫通電極１２３の間に配置される。   FIG. 5 is a plan view showing a part of the semiconductor chip in the semiconductor device according to the second embodiment of the present invention. Similar to the semiconductor device 100 of the first embodiment shown in FIG. 1, the semiconductor device 100a of this embodiment has a plurality of stacked semiconductor chips 110a. In FIG. 5, the semiconductor chip 110 a is shown in the same manner as in FIG. 3, and components other than the power supply through electrode 121, the ground through electrode 122, and the signal through electrode 123 are omitted. In the present embodiment example, the power supply through electrode 121 and the ground through electrode 122 are disposed between two adjacent signal through electrodes 123.

第１実施形態例の半導体装置１００では、図３に示すように、隣接する２つの電源貫通電極１２１同士、グランド貫通電極１２２同士、及び、信号貫通電極１２３同士が、それぞれＸ方向に沿って一列に並んで配列されており、隣接する２つの信号貫通電極１２３間でクロストークが問題になる可能性があった。本実施形態例の半導体装置１００ａでは、隣接する２つの信号貫通電極１２３の間に、電源貫通電極１２１及びグランド貫通電極１２２が配置されるため、第１実施形態例と同様に、信号貫通電極１２３に電流が流れた際のループ面積を小さくして電磁ノイズ発生を低減できると共に、第１実施形態例に比して、隣接する２つの信号貫通電極１２３間でのクロストークを抑制できる。   In the semiconductor device 100 of the first embodiment, as shown in FIG. 3, two adjacent power supply through electrodes 121, ground through electrodes 122, and signal through electrodes 123 are arranged in a row along the X direction. The crosstalk may be a problem between the two adjacent signal penetration electrodes 123. In the semiconductor device 100a of the present embodiment example, the power supply through electrode 121 and the ground through electrode 122 are disposed between two adjacent signal through electrodes 123. Therefore, the signal through electrode 123 is the same as in the first embodiment. In addition to reducing the loop area when a current flows through and reducing electromagnetic noise, crosstalk between two adjacent signal through electrodes 123 can be suppressed as compared to the first embodiment.

なお、図５では、隣接する２つの信号貫通電極１２３の間に電源貫通電極１２１及びグランド貫通電極１２２を配置する例について示したが、これに加えて、図６に示すように、信号貫通電極１２３をＹ方向の両側から挟みこむ位置に、電源貫通電極１２１及びグランド貫通電極１２２を配置してもよい。この場合には、信号貫通電極１２３は、電源貫通電極１２１とグランド貫通電極１２２とによって、その周囲を囲まれることになる。   5 shows an example in which the power supply through electrode 121 and the ground through electrode 122 are arranged between two adjacent signal through electrodes 123, but in addition to this, as shown in FIG. The power supply through electrode 121 and the ground through electrode 122 may be arranged at positions where the 123 is sandwiched from both sides in the Y direction. In this case, the signal through electrode 123 is surrounded by the power through electrode 121 and the ground through electrode 122.

貫通電極を備える半導体装置では、貫通電極が、Ｎ行×Ｍ列（Ｎ、Ｍは２以上の整数）の格子状に配置されることが考えられる。このような場合、信号貫通電極１２３を配置する格子点に隣接する格子点の貫通電極を、電源貫通電極１２１又はグランド貫通電極１２２として構成し、信号貫通電極１２３を電源貫通電極１２１又はグランド貫通電極１２２で囲うことで、ループ面積を削減し、信号貫通電極１２３間のクロストークを低減することができる。   In a semiconductor device provided with a through electrode, it is conceivable that the through electrode is arranged in a grid of N rows × M columns (N and M are integers of 2 or more). In such a case, the through electrode at the lattice point adjacent to the lattice point where the signal through electrode 123 is disposed is configured as the power through electrode 121 or the ground through electrode 122, and the signal through electrode 123 is configured as the power through electrode 121 or the ground through electrode. By enclosing with 122, the loop area can be reduced and the crosstalk between the signal through electrodes 123 can be reduced.

本発明の半導体装置では、全ての信号貫通電極１２３の近傍に電源貫通電極１２１及びグランド貫通電極１２２が配置されている必要はない。例えば、回路ブロックのレイアウトなどの都合によっては、すべての信号貫通電極１２３の近傍に電源貫通電極１２１及びグランド貫通電極１２２を配置できない場合もある。その場合には、複数の信号貫通電極１２３の近傍に、それぞれ１つの電源貫通電極１２１及びグランド貫通電極１２２が配置されていればよい。また、式（１）からわかるように、半導体装置１００から距離ｒ離れた点における電界の大きさは、電流の周波数成分ｆや電流値ｉによっても決まるため、信号貫通電極１２３を流れる電流によって発生するノイズが小さい場合には、その信号貫通電極１２３の近傍には、電源貫通電極１２１及びグランド貫通電極１２２を配置しなくてもよい。   In the semiconductor device of the present invention, the power supply through electrode 121 and the ground through electrode 122 do not have to be disposed in the vicinity of all the signal through electrodes 123. For example, depending on the layout of the circuit block, the power supply through electrode 121 and the ground through electrode 122 may not be disposed in the vicinity of all the signal through electrodes 123. In that case, one power supply through electrode 121 and one ground through electrode 122 may be disposed in the vicinity of the plurality of signal through electrodes 123. Further, as can be seen from equation (1), the magnitude of the electric field at a point r away from the semiconductor device 100 is also determined by the frequency component f of the current and the current value i. When the noise to be transmitted is small, the power supply through electrode 121 and the ground through electrode 122 may not be disposed in the vicinity of the signal through electrode 123.

図７（ａ）及び（ｂ）は、それぞれ、２つの信号貫通電極に対してそれぞれ２つの電源貫通電極及びグランド貫通電極が配置される半導体装置を示している。同図（ａ）では、４つの信号貫通電極１２３がＸ方向に沿って等間隔で１列に配列されており、２つの信号貫通電極１２３（１）及び１２３（２）の近傍には、電源貫通電極１２１（１）及びグランド貫通電極１２２（１）が配置され、別の２つの信号貫通電極１２３（３）及び１２３（４）の近傍には、電源貫通電極１２１（２）及びグランド貫通電極１２２（２）が配置されている。   FIGS. 7A and 7B each show a semiconductor device in which two power supply through electrodes and ground through electrodes are arranged for two signal through electrodes, respectively. In FIG. 5A, four signal through electrodes 123 are arranged in a line at equal intervals along the X direction, and a power source is located near the two signal through electrodes 123 (1) and 123 (2). The through electrode 121 (1) and the ground through electrode 122 (1) are arranged, and in the vicinity of the other two signal through electrodes 123 (3) and 123 (4), the power through electrode 121 (2) and the ground through electrode 122 (2) is arranged.

図７（ａ）に示す構成では、隣接する２つの信号貫通電極１２３間のクロストークが問題になる場合がある。そのような場合には、同図（ｂ）に示すように、各信号貫通電極１２３のＹ方向の位置をずらして配置すればよい。このようにすることで、Ｘ方向での隣接する２つの信号貫通電極１２３の間隔を変えずに、信号貫通電極１２３間の距離を長くすることができ、クロストークの発生を抑制できる。   In the configuration shown in FIG. 7A, crosstalk between two adjacent signal through electrodes 123 may be a problem. In such a case, as shown in FIG. 5B, the Y-direction position of each signal penetration electrode 123 may be shifted. By doing so, the distance between the signal through electrodes 123 can be increased without changing the interval between the two adjacent signal through electrodes 123 in the X direction, and the occurrence of crosstalk can be suppressed.

上記各実施形態例では、信号貫通電極１２３がドライバ１１４の出力に接続される例について示したが、信号貫通電極１２３が接続されるのは、ドライバ１１４の出力には限定されない。また、ドライバ１１４は、ｐＭＯＳトランジスタＭ１及びｎＭＯＳトランジスタＭ２によって構成されるプッシュ・プル型のドライバに限定されず、例えばｎＭＯＳトランジスタによって構成されるオープン・ドレイン型のドライバであってもよい。半導体チップ１１０は、ＤＲＡＭチップには限定されず、半導体装置１００の最下層はＩＦチップ１０１に限定されない。   In each of the embodiments described above, an example in which the signal through electrode 123 is connected to the output of the driver 114 has been described. However, the connection of the signal through electrode 123 is not limited to the output of the driver 114. The driver 114 is not limited to a push-pull driver configured by the pMOS transistor M1 and the nMOS transistor M2, and may be an open drain driver configured by an nMOS transistor, for example. The semiconductor chip 110 is not limited to a DRAM chip, and the lowermost layer of the semiconductor device 100 is not limited to the IF chip 101.

以上、本発明をその好適な実施形態例に基づいて説明したが、本発明の半導体装置は、上記実施形態例にのみ限定されるものではなく、上記実施形態例の構成から種々の修正及び変更を施したものも、本発明の範囲に含まれる。   Although the present invention has been described based on the preferred embodiment, the semiconductor device of the present invention is not limited to the above embodiment, and various modifications and changes can be made to the configuration of the above embodiment. Those subjected to are also included in the scope of the present invention.

本発明の半導体装置を示す斜視図。The perspective view which shows the semiconductor device of this invention. 半導体装置１００の周縁部を示す断面図。FIG. 6 is a cross-sectional view showing a peripheral portion of the semiconductor device 100. 半導体チップ１１０のドライバ１１４付近を示す平面図。FIG. 3 is a plan view showing the vicinity of a driver 114 of a semiconductor chip 110. 図１の半導体装置１００を、チップ内の回路図の一部と共に模式的に示す平面図。FIG. 2 is a plan view schematically showing the semiconductor device 100 of FIG. 1 together with a part of a circuit diagram in a chip. 本発明の第２実施形態例の半導体装置における半導体チップの一部を示す平面図。The top view which shows a part of semiconductor chip in the semiconductor device of 2nd Embodiment of this invention. 本発明の第２実施形態例の変形の半導体装置における半導体チップの一部を示す平面図。The top view which shows a part of semiconductor chip in the semiconductor device of the modification of 2nd Embodiment of this invention. （ａ）及び（ｂ）は、それぞれ、２つの信号貫通電極に対してそれぞれ２つの電源貫通電極及びグランド貫通電極が配置される半導体装置の一部を示す平面図。(A) And (b) is a top view which shows a part of semiconductor device with which two power supply penetration electrodes and ground penetration electrodes are each arrange | positioned with respect to two signal penetration electrodes. （ａ）は、積層された複数のチップを有する従来の一般的な半導体装置を示す平面図、同図（ｂ）は、同図（ａ）のＡ−Ａ断面を示す断面図。(A) is a top view which shows the conventional general semiconductor device which has the some chip | tip laminated | stacked, The same figure (b) is sectional drawing which shows the AA cross section of the figure (a). 特許文献１に記載された半導体装置３００を示す断面図。FIG. 6 is a cross-sectional view showing a semiconductor device 300 described in Patent Document 1. 信号端子に近接して電源端子及びグランド端子が配置されない比較例の半導体装置を示す斜視図。The perspective view which shows the semiconductor device of the comparative example by which a power supply terminal and a ground terminal are not arrange | positioned adjacent to a signal terminal.

符号の説明Explanation of symbols

１００：半導体装置
１０１：ＩＦチップ
１０２：ＩＦ内電源配線
１０３：ＩＦ内グランド配線
１０４：レシーバ
１１０：半導体チップ
１１１：チップ内電源配線
１１２：チップ内グランド配線
１１３：ＤＲＡＭセル（内部回路）
１１４：ドライバ
１２０：貫通電極
１２１：電源貫通電極
１２２：グランド貫通電極
１２３：信号貫通電極 DESCRIPTION OF SYMBOLS 100: Semiconductor device 101: IF chip 102: IF power supply wiring 103: IF ground wiring 104: Receiver 110: Semiconductor chip 111: In-chip power wiring 112: In-chip ground wiring 113: DRAM cell (internal circuit)
114: Driver 120: Through electrode 121: Power supply through electrode 122: Ground through electrode 123: Signal through electrode

Claims (5)

それぞれがチップ外信号線を介してチップ外に信号を出力する、積層された複数の半導体チップと、それぞれが前記チップ外信号線、電源線、及び、グランド線を構成し前記複数の半導体チップを貫通して延びる複数の貫通電極とを備える半導体装置において、
少なくとも１つの前記チップ外信号線を構成する貫通電極が、前記電源線を構成する貫通電極と前記グランド線を構成する貫通電極の双方に隣接して配置され、前記電源線を構成する貫通電極と前記グランド線を構成する貫通電極は電流方向が互いに逆向きであることを特徴とする半導体装置。 A plurality of stacked semiconductor chips, each of which outputs a signal to the outside of the chip via an off-chip signal line, and each of the plurality of semiconductor chips comprising the off-chip signal line, a power supply line, and a ground line In a semiconductor device comprising a plurality of through electrodes extending through,
At least one through-electrode constituting the off-chip signal line is disposed adjacent to both the through-electrode constituting the power supply line and the through-electrode constituting the ground line, and the through-electrode constituting the power supply line; 2. A semiconductor device according to claim 1, wherein the through electrodes constituting the ground line have current directions opposite to each other . 順次に配列された、電源線を構成する貫通電極、前記チップ外信号線を構成する貫通電極、及び、前記グランド線を構成する貫通電極を含む、請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, comprising a through electrode constituting a power supply line, a through electrode constituting the off-chip signal line, and a through electrode constituting the ground line, which are sequentially arranged. 隣接する２つのチップ外信号線を構成する貫通電極の間に、前記電源線を構成する貫通電極及び前記グランド線を構成する貫通電極の少なくとも一方が配置されている、請求項１又は２に記載の半導体装置。   The at least one of the penetration electrode which comprises the said power supply line, and the penetration electrode which comprises the said ground line is arrange | positioned between the penetration electrodes which comprise two adjacent signal signals outside a chip | tip. Semiconductor device. 前記少なくとも１つのチップ外信号線を構成する貫通電極が、前記電源線を構成する貫通電極及び前記グランド線を構成する貫通電極の少なくとも一方を含む貫通電極によって囲まれる、請求項３に記載の半導体装置。   4. The semiconductor according to claim 3, wherein the through electrode constituting the at least one off-chip signal line is surrounded by a through electrode including at least one of the through electrode constituting the power supply line and the through electrode constituting the ground line. apparatus. 前記複数の半導体チップがＤＲＡＭを含む、請求項１乃至４の何れか一項に記載の半導体装置。 The semiconductor device according to claim 1 , wherein the plurality of semiconductor chips includes a DRAM.
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