JP4030844B2 - Digital microwave receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a received signal synchronizing circuit of a digital microwave receiver, and more particularly to a digital microwave receiver for wirelessly transmitting video / audio for broadcasting.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, on the transmission side for transmitting video / audio and the like for broadcasting using digital microwaves, a plurality of carrier waves having different frequencies from each other in a TS signal sent from an MPEG2 TS (Transport Stream) multiplexer are used. Are separately modulated with information signals to be transmitted, and are converted into symbols to form a transmission frame. The configuration of the transmission frame symbolized in this way is shown in FIG.
[0003]
As shown in the figure, the transmission frame is composed of data symbols made up of effective data and guard intervals that generate frequency division multiplexed signals, and synchronization symbols made up of known reference signals, and is transmitted from the transmission side.
[0004]
On the other hand, in the digital microwave receiver, in order to detect a synchronization symbol from the received transmission frame, a known reference signal inserted in the synchronization symbol is prepared, and the synchronization symbol of the received transmission frame is detected. A comparison is made to generate synchronization symbol synchronization. To generate synchronization symbol synchronization, first, the synchronization symbol of the received transmission frame and the known reference signal inserted in the synchronization symbol are integrated. The accumulated data is accumulated in symbol units, and a point where the accumulated value is maximum is generated as symbol synchronization. The demodulated data is controlled by adjusting the timing of symbol synchronization generated in this way.
[0005]
In other words, when digital transmission is performed, information data and synchronization data are transmitted in symbol units in the configuration of the digital transmission frame, and a synchronization symbol is inserted in the transmission frame configuration. It was possible to easily detect frame synchronization.
[0006]
[Problems to be solved by the invention]
However, the conventional technique has a problem that the transmission bit rate is lowered because the amount of information (effective data) in transmission data per second is reduced when a synchronization symbol is inserted.
[0007]
Therefore, in view of such a problem, the present invention transmits only information data without inserting a synchronization symbol. Therefore, even if a TS signal is directly converted and transmitted without being converted into a transmission frame structure, stable reception synchronization is achieved. An object of the present invention is to provide a digital microwave receiver that can output a TS signal.
[0008]
It is another object of the present invention to provide a digital microwave receiver that can reduce the cost and hardware scale by simplifying the reception signal synchronization circuit.
[0009]
As prior art related to the present invention with respect to digital microwave transmission / reception synchronization detection, the techniques described in JP-A-11-32025, JP-A-10-117189, and JP-A-10-28105 are known. Yes.
[0010]
[Means for Solving the Problems]
In order to achieve this object, a digital microwave receiver according to the present invention is a digital microwave receiver that receives a modulated wave obtained by digitally modulating a TS signal error-coded by a digital microwave transmitter. The B8 detection circuit that detects the sync byte “B8” from the TS signal and outputs the B8 detection pulse, checks the TS signal packet position, performs synchronization monitoring, and starts the TS signal and the start position of the packet A synchronization monitoring circuit for outputting an out-of-synchronization detection pulse indicating that the pulse and the out-of-synchronization have been detected; a B8 period counter circuit for counting a B8 period based on the input of the B8 detection pulse and outputting a B8 period pulse; and the B8 A delay unit for delaying a detection pulse, and a phase timing between the B8 period pulse and the B8 detection pulse delayed by the delay unit The phase timing adjustment circuit that outputs a counter load pulse when the phase timing matches, and the B8 period pulse input is counted, and when the counter load pulse is input, the counter is reset to monitor B8 synchronization. When a predetermined count value is reached, the B8 synchronization monitoring counter that outputs a B8 synchronization loss detection pulse and the packet start pulse indicating the packet start position by counting the packet period based on the input of the counter load pulse are synchronized. When a packet start pulse generation circuit that outputs to the circuit and the B8 out-of-sync detection pulse or at least one out-of-sync detection pulse is input, the B8 cycle counter circuit outputs a reset pulse. With detection circuit And that it has.
[0011]
In this case, the digital microwave receiver has a parallel-serial converter for parallel / serial conversion of the demodulated TS signal, and the B8 detection circuit is a TS signal of serial data converted in parallel / serial by the parallel-serial conversion circuit. A serial-parallel conversion circuit that performs serial / parallel conversion, B8 constant output circuit that outputs B8 constant parallel data with “B8” as a constant, parallel data converted by the B8 constant parallel data and the serial-parallel conversion circuit And a B8 comparison and detection circuit for detecting the B8 of the synchronization byte and outputting the B8 detection pulse, and further converted by the serial-to-parallel conversion circuit based on the B8 period pulse. A serial control circuit that outputs serial pulses to adjust the phase of the TS signal of parallel data When it is desirable to have a phase adjusting circuit for outputting the combined TS signal of the parallel data to the phase of the Shiriparaparusu.
[0012]
The packet start pulse generation circuit counts a packet period based on the input of the counter load pulse and outputs a packet pulse indicating a head position of the packet, and a phase obtained by delaying the packet pulse. It is desirable to have a delay device that adjusts and outputs the packet start pulse.
[0013]
On the other hand, the digital microwave receiver is provided with a code determination device and an equalizer for performing equivalent and code determination of the received signal,
When the reset pulse is output from the out-of-synchronization detection circuit, the sign determination unit and the equalizer are reset, and the equivalent and sign determination of the received signal is performed again.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments according to the present invention will be described with reference to the drawings.
[0015]
FIG. 1 is a block diagram illustrating a digital microwave receiver according to the present embodiment, and FIG. 2 is a diagram illustrating a configuration of a TS signal received by the digital microwave receiver.
[0016]
First, the TS signal is composed of 188-byte packets having a synchronization byte “47 (hexadecimal number)” at the head, and is transmitted and received in one frame structure with 8 packets as one set. At this time, in order to improve the reliability of the TS signal, it is converted into an error correction code (Reed-Solomon).
[0017]
In this correction encoding, 16 parity bytes are added and one packet is expanded to 204 bytes. In addition, in order to facilitate synchronization by synchronization, interleaving, and RS coding, the synchronization byte at the head of the packet is inverted by synchronizing the synchronization byte “47 (hexadecimal number)” every 8 packets in one frame to “B8 ( Hexadecimal number) ”. FIG. 2 shows the configuration of the TS signal that has been corrected and encoded.
[0018]
Next, the configuration of the digital microwave receiver according to the present invention will be described.
[0019]
The digital microwave receiver detects a synchronization byte B8 from the serial data 203 and the parallel-serial converter 210 that outputs serial data 203 by parallel / serial conversion of the real part data 201 and the imaginary part data 202 that have been amplified by operation. The B8 detection circuit 211 that outputs the BS detection pulse 204 and the TS signal 232 and the position of the TS signal 232 packet are confirmed to perform synchronization monitoring, and the TS signal 233, the start pulse 235, and the synchronization loss detection pulse 234 are output. Synchronization monitoring circuit 219, B8 period counter circuit 212 that counts the B8 period based on the input of the B8 detection pulse 204 and outputs the B8 period pulse 205, B8 detection pulse delayed by the B8 period pulse 205 and the delay unit 213 The logical sum of 206 is taken and the position of the B8 detection pulse 204 is calculated. The logical sum circuit 214 that checks the timing and outputs the counter load pulse 207 and the input of the B8 cycle pulse 205 are counted, and when the counter load pulse 207 is input, the counter is reset to monitor the B8 synchronization. A B8 synchronization monitoring counter 216 that outputs a B8 synchronization loss detection pulse 208 when a predetermined count value is reached, and a packet start pulse generation circuit 218 that counts the packet period based on the input of the counter load pulse 207 and outputs a packet start pulse 231. And an OR circuit 217 that outputs a reset pulse 236 to the B8 cycle counter circuit 212 when at least one of the B8 synchronization detection pulse 208 or the synchronization detection pulse 234 is input.
[0020]
Further, as shown in FIG. 3, the B8 detection circuit 211 further receives the serial data 203 and converts it into 8-bit parallel data, and “B8” which is a synchronization byte of the first packet of the TS signal. B8 constant 314 that outputs B8 constant 8-bit parallel data with B8 constant as the constant, and B8 constant 8-bit parallel data from B8 constant 314 are compared to detect B8 of the synchronization byte from 8-bit parallel data 301, and B8 detection pulse A comparator 311 that outputs 204, and a serial-para control circuit 312 that divides the serial clock based on the B8 period pulse 205 and outputs the serial-para pulse 302 in order to match the 8-bit parallel data 301 to the phase of the parallel clock; 8-bit parallel data 301 is converted to the position of serial pulse 302. And a flip-flop 313 outputs a TS signal 232 together to.
[0021]
Further, as shown in FIG. 4, the packet start pulse generation circuit 218 further starts the count by inputting the counter load pulse 207 and outputs the packet pulse 401, and the packet pulse 401 is synchronized with the TS signal 232. A delay unit 411 that adjusts the timing and outputs a packet start pulse 231 in order to match the phase relationship with the byte.
[0022]
Next, the operation of the digital microwave receiver according to the present invention will be described.
[0023]
First, the digitally modulated SHF band analog wave signal is SHF downconverted by the SHF downconverter when the signal is input to the digital microwave receiver, and is quadrature amplitude demodulated by the IF downconverter and A / D converter. Thus, a TS signal that is a digital modulation signal that is frequency-converted from the IF band to the baseband band and separated into real part data and imaginary part data is output.
[0024]
The real part data 201 and the imaginary part data are parallel / serial converted by the parallel-serial converter 210 and output as 1-bit serial data 203 of the TS signal.
[0025]
The B8 detection circuit 211 detects “B8” of the synchronization byte from the serial data 203 and outputs a TS signal 232 synchronized with the B8 detection pulse 204 and the parallel clock.
[0026]
The operation of the B8 detection circuit 211 will be described in detail. First, the serial data 203 is output as 8-bit parallel data 301 by the shift register 310. The output 8-bit parallel data 301 and the B8 constant 8-bit parallel data output from the B8 constant 314 are compared by the comparator 311. When “B8” is detected from the 8-bit parallel data 301, the B8 detection pulse 204 is output. To do. This is because, as shown in FIG. 2, the configuration of the TS signal is the synchronization byte “B8” only once in 8 packets, and therefore synchronization byte “B8” needs to be detected in order to perform reception synchronization. .
[0027]
The B8 detection pulse 204 that detects “B8” in the TS signal is input to the B8 cycle counter circuit 212.
[0028]
The B8 cycle counter circuit 212 starts counting when the power is turned on, or when the B8 detection pulse 204 is first input after the reception state is lost due to a bad line condition. Then, “B8” period, that is, 8 × 204 × 8 = 13056 minutes, which is 8 packets of TS (serial) signal, is counted, and a B8 period pulse 205 is output every time 13056 count is completed.
[0029]
On the other hand, the B8 detection pulse 204 is delayed by the delay unit 213 in order to adjust the phase timing with the B8 cycle pulse 205, and is output as the B8 detection pulse 206.
[0030]
The OR circuit 214 confirms the position of the phase between the B8 detection pulse 206 delayed by the delay unit 213 and the B8 period pulse 205 output from the B8 period counter circuit 212, and the B8 detection pulse 206 and the B8 period pulse 205 are confirmed. The counter load pulse 207 whose position is “LOW” is output. If the positional relationship between the B8 detection pulse 206 and the B8 cycle pulse 205 is different, the counter load pulse 207 is output with “HIGH”.
[0031]
The counter load pulse 207 is input to the B8 synchronization monitoring counter 216 and the packet start pulse generation circuit 218.
[0032]
When the counter load pulse 207 is input, the B8 synchronization monitoring counter 216 initializes the count value of the counter using this as a load pulse, and counts up every “B8” period by the input of the B8 period pulse 205. If the positional relationship between the B8 detection pulse 206 and the B8 synchronization pulse 205 is matched in the OR circuit 214, that is, if the detection position of the synchronization byte “B8” of the TS signal is appropriate, the counter load pulse 207 is enabled “LOW”. , The count value of the B8 synchronization monitoring counter 216 is returned to the initial value, and starts counting up again. If the positional relationship between the B8 detection pulse 206 and the B8 synchronization pulse 205 is different in the OR circuit 214, that is, if the detection position of the synchronization byte “B8” of the TS signal is inappropriate, the counter load pulse 207 is “HIGH. The B8 synchronization monitoring counter 216 counts up.
[0033]
A counter initial value 209 is set in the B8 synchronization monitoring counter 216. This counter initial value 209 indicates the allowable number of deviations of the synchronization byte “B8” within a predetermined period (such as every B8 period pulse). Is counted up to the counter initial value 209 or more within a predetermined period, the B8 synchronization loss detection pulse 208 is outputted as “HIGH”. Note that the counter initial value 209 has different characteristics depending on the receiving system. In the present invention, the counter initial value 209 can be variably set from 0 to 15.
[0034]
Further, the B8 period pulse 205 is input to the serial parallax control circuit 312 of the B8 detection circuit 211.
[0035]
The serial para control circuit 312 divides the serial clock based on the B8 periodic pulse 205 and outputs the serial para pulse 302 in order to match the 8-bit parallel data 301 to the phase of the parallel clock. The flip-flop 313 adjusts the timing of the 8-bit parallel data 301 output from the shift register 310 with the serial pulse 302 output from the serial control circuit 312, and outputs this as a TS signal 232.
[0036]
When the position of the synchronization byte “B8” is normally detected by the above circuit, the 8-bit parallel data 301 output from the shift register 310 is serial / parallel converted from the beginning of the packet, so that more stable TS The signal 232 can be output.
[0037]
On the other hand, the counter load pulse 207 output from the OR circuit 214 is input to the packet start generation circuit 218.
[0038]
In the packet start generation circuit, the packet counter 410 starts counting when the counter load pulse 207 is input. When 204 counts corresponding to one packet of the TS signal are output, “HIGH” enable is output as a packet pulse 401. After 204 counts, the count returns to the initial value and starts counting again.
[0039]
The packet pulse 401 is adjusted in timing by the delay unit 411 so as to match the phase relationship with the synchronization byte of the TS signal 232 output from the B8 detection circuit 211, and is output to the synchronization monitoring circuit 219 as a packet start pulse 231.
[0040]
The synchronization monitoring circuit 219 receives the TS signal 232 output from the B8 detection circuit 211 and the packet start pulse 231 as input, and the positional relationship between the synchronization byte (“B8” and “47”) of the TS signal 232 and the packet start pulse 231. Check.
[0041]
If the determination result is “good”, the (positional relationship) state is maintained as it is, and the TS signal 233 and the start pulse 235 are output to the error correction circuit at the next stage. In this case, since the start pulse 235 and the TS signal 233 are synchronized with each other, it can be expected that the error-decoded TS signal is stable. However, if the determination result is “NO”, the same operation as the B8 synchronization monitoring counter 216 is performed, and the synchronization loss detection pulse 234 is output as “HIGH”. In this case, the error-decoded TS signal 233 cannot be expected to be stable.
[0042]
The out-of-synchronization detection pulse 234 and the B8 out-of-synchronization detection pulse 208 thus output are input to the OR circuit 217, and the OR circuit 217 becomes “HIGH” if any pulse becomes “HIGH”. The other pulse is output as the reset pulse 236. That is, when the synchronization of the packet period or the B8 period is lost, the reset pulse 236 is set to “HIGH” and is input to the B8 period counter circuit 212.
[0043]
The B8 cycle counter circuit 212 resets the counter by the input of the reset pulse 236, starts counting again based on the input of the B8 detection pulse 204, and detects the B8 synchronization loss detection pulse 208 and the synchronization monitoring counter 219 from the B8 synchronization monitoring counter 216. The operation is repeated until the synchronization loss detection pulse 234 becomes “LOW”. That is, since the monitoring is constantly performed until the detection position of the synchronization byte of the TS signal is matched, a more stable TS signal 233 can be supplied to the error correction circuit.
[0044]
Note that when the reset pulse 236 that becomes “HIGH” is output from the OR circuit 217, the synchronization of the system itself may not be detected. That is, since the local wave itself is not transmitted or there is a possibility of deterioration of the received signal due to the influence of multipath or the like, the reset pulse 236 output from the OR circuit 217 becomes “HIGH”. In the case of a failure, the code decision unit and the equalizer in the receiver are reset, and the received signal is equivalent and the code is discriminated again.
[0045]
【The invention's effect】
As described above, since reception synchronization is constantly monitored by the B8 synchronization monitoring counter and the synchronization monitoring circuit, when the line state is good, it is possible to always output a stable TS signal, and the line state is broken → good. Even in such a case, it is possible to control the reception synchronization to be detected again and to output a stable TS signal again. Therefore, the error correction circuit in the next stage performs error correction processing stably for each packet. be able to.
[0046]
Further, according to the present invention that does not use a transmission frame configuration, the received signal synchronization circuit in the digital microwave receiver can be simplified, so that the hardware scale can be greatly reduced and the cost can be reduced. There is.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a digital microwave receiver according to the present invention.
FIG. 2 is a configuration diagram of a TS signal.
FIG. 3 is a block diagram showing a configuration of a B8 detection circuit.
FIG. 4 is a block diagram showing a configuration of a packet start pulse generation circuit.
FIG. 5 is a configuration diagram of a synchronization symbol insertion frame.
[Explanation of symbols]
201 Real part data 202 Imaginary part data 203 Serial data 204 B8 detection pulse 205 B8 period pulse 206 B8 detection pulse 207 Counter load pulse 208 B8 synchronization loss detection pulse 209 Counter initial value 210 Parasiri converter 211 B8 detection circuit 212 B8 period counter circuit 213 delay circuit 214 OR circuit 216 B8 synchronization monitoring counter 217 OR circuit 218 packet start pulse generation circuit 232 TS signal 233 TS signal 234 synchronization loss detection pulse 235 start pulse 236 reset pulse 310 shift register 311 comparator 312 serial control circuit 313 Flip-flop 314 B8 constant 401 Packet pulse 410 Packet counter 411 Delay device

Claims (5)

In a digital microwave receiver that receives a modulated wave obtained by digitally modulating a TS signal error-coded by a digital microwave transmitter,
The B8 detection circuit that detects the synchronization byte “B8” from the demodulated TS signal and outputs a B8 detection pulse, and confirms the TS signal packet position to perform synchronization monitoring, and indicates the TS signal and the start position of the packet. A synchronization monitoring circuit that outputs an out-of-synchronization detection pulse indicating a start pulse and out-of-synchronization; a B8 period counter circuit that counts a B8 period based on the input of the B8 detection pulse and outputs a B8 period pulse; A delay unit that delays the B8 detection pulse, a phase timing adjustment circuit that checks a phase timing of the B8 period pulse and the B8 detection pulse delayed by the delay unit, and outputs a counter load pulse when the phase timings coincide with each other; The B8 period pulse input is counted, and when the counter load pulse is input, the counter is reset. B8 synchronization is monitored, and when a predetermined count value is reached, a B8 synchronization monitoring counter that outputs a B8 synchronization loss detection pulse, and a packet period is counted based on the input of the counter load pulse to determine the head position of the packet. A packet start pulse generation circuit that outputs a packet start pulse to the synchronization monitoring circuit, and the B8 period counter circuit when at least one of the synchronization detection pulse of the B8 synchronization detection pulse or the synchronization detection pulse is input. A digital microwave receiver comprising: an out-of-synchronization detection circuit that outputs a reset pulse. The digital microwave receiver includes a parallel-serial converter that performs parallel / serial conversion on the demodulated TS signal, and the B8 detection circuit inputs a TS signal of serial data that is parallel / serial converted by the parallel-serial conversion circuit. Serial-parallel conversion circuit for serial / parallel conversion, B8 constant output circuit for outputting B8 constant parallel data with "B8" as a constant, TS signal of parallel data converted by the B8 constant parallel data and the serial-parallel conversion circuit The digital microwave receiver according to claim 1, further comprising: a B8 comparison detection circuit that detects the B8 of the synchronization byte by comparing the B8 and outputs the B8 detection pulse. A serial-parallel control circuit for outputting a serial-parallel pulse for adjusting the phase of the TS signal of parallel data converted by the serial-parallel conversion circuit with reference to the B8 period pulse, and the phase of the serial-parallel pulse for the TS signal of the parallel data The digital microwave receiver according to claim 2, further comprising a phase adjustment circuit that outputs the signal in accordance with the frequency. The packet start pulse generation circuit adjusts the phase by delaying the packet pulse, and a packet counter that counts the packet period based on the input of the counter load pulse and outputs a packet pulse indicating the start position of the packet. The digital microwave receiver according to claim 1, further comprising a delay unit that outputs the packet start pulse. The digital microwave receiver includes a code determination device and an equalizer for performing equality and code determination of the received signal received,
5. When the reset pulse is output from the out-of-synchronization detection circuit, the sign determination unit and the equalizer are reset, and the reception signal is equivalent and the code determination is performed again. A digital microwave receiver according to claim 1.

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