JP4025527B2 - Memory, writing device, reading device and method thereof - Google Patents

Description

第１の記録層３と第２の記録層５の両方が非晶質相である場合（状態１）、第１の記録層３の抵抗と第２の記録層５の抵抗の和は、Ｒ_a1＋Ｒ_a2となる。第１の記録層３が結晶相であり、第２の記録層５が非晶質相である場合（状態２）、第１の記録層３の抵抗と第２の記録層５の抵抗の和は、Ｒ_c1＋Ｒ_a2となる。第１の記録層３が非晶質相であり、第２の記録層５が結晶相である場合（状態３）、第１の記録層３の抵抗と第２の記録層５の抵抗の和は、Ｒ_a1＋Ｒ_c2となる。第１の記録層３と第２の記録層５の両方が結晶相である場合（状態４）、第１の記録層３の抵抗と第２の記録層５の抵抗の和は、Ｒ_c1＋Ｒ_c2となる。上述したように、各抵抗の和は状態１〜４で異なっている。
【００５８】
次に、メモリ１１の作製手順を以下の工程Ｓ１１０１〜Ｓ１１０６に説明する。
【００５９】
Ｓ１１０１：表面を処理した基板１をスパッタリング装置内に準備する。
【００６０】
Ｓ１１０２：Ａｌ、Ａｕ、Ａｇ、Ｃｕ、Ｐｔ、Ｔｉ、Ｗ等の単体金属ターゲットまたはこれらの合金金属ターゲットをＡｒガス雰囲気中でスパッタリングすることにより下部電極２が堆積される。
【００６１】
Ｓ１１０３：Ｇｅ、Ｓｂ、Ｔｅの３つの元素を含む合金ターゲットをＡｒガス雰囲気、Ｋｒガス雰囲気、Ａｒガスと酸素ガスまたは窒素ガスのうち少なくとも一方を含む反応性ガスとの混合ガス雰囲気、およびＫｒガスと反応性ガスとの混合ガス雰囲気からなる群から選択される雰囲気中でスパッタリングすることによって下部電極２上に第１の記録層３が堆積される。
【００６２】
Ｓ１１０４：Ａｌ、Ａｕ、Ａｇ、Ｃｕ、Ｐｔ、Ｔｉ、Ｗ等の単体金属ターゲットまたはこれらの合金金属ターゲットをＡｒガス雰囲気中でスパッタリングすることにより中間層４が第１の記録層３上に堆積される。
【００６３】
Ｓ１１０５：（Ｓｂ−Ｔｅ）−Ｍ１で表される材料系を含む（ここでＭ１は、Ａｇ、Ｉｎ、Ｇｅ、Ｓｎ、Ｓｅ、Ｂｉ、ＡｕおよびＭｎからなる群から少なくとも１つ選択される）合金ターゲットをＡｒガス雰囲気、Ｋｒガス雰囲気、Ａｒガスと酸素ガスまたは窒素ガスのうち少なくとも一方を含む反応性ガスとの混合ガス雰囲気、およびＫｒガスと反応性ガスとの混合ガス雰囲気からなる群から選択される雰囲気中でスパッタリングすることによって中間層４上に第２の記録層５が堆積される。
【００６４】
Ｓ１１０６：Ａｌ、Ａｕ、Ａｇ、Ｃｕ、Ｐｔ、Ｔｉ、Ｗ等の単体金属ターゲットまたはこれらの合金金属ターゲットをＡｒガス雰囲気中でスパッタリングすることにより上部電極６が第２の記録層５上に形成される。
【００６５】
上述した作製手順の工程Ｓ１１０１〜Ｓ１１０６において、下部電極２、第１の記録層３、中間層４、第２の記録層５および上部電極６を堆積するために、スパッタリング装置を用いたが、各層を堆積することができる任意の薄膜堆積装置を用いることができる。実施の形態１では、工程Ｓ１１０１においてＳｉ基板１の表面を窒素雰囲気中で窒化処理した。このようにして作製された下部電極２および上部電極６のそれぞれにＡｕリード線をボンディングし、印加部１３を介して読み出し／書き込み装置１２に接続した。
【００６６】
次にメモリ１１に情報を書き込む方法およびメモリ１１に書き込まれた情報を消去する方法を説明する。メモリ１１への情報の書き込みおよび消去を行う場合、スイッチ９が閉じられ、スイッチ１０が開かれる。パルス発生部７は、第１の記録層３および第２の記録層５の相状態を所望の相状態に変化させるために必要な振幅とパルス幅を有する電流パルスを発生する。パルス発生部７によって発生された電流パルスは、印加部１３を介して第１の記録層３と第２の記録層５とに印加される。
【００６７】
図２は、第１の記録層３および第２の記録層５の相状態に関する状態遷移図である。
【００６８】
本実施の形態１において、表１に示される状態１から状態２、状態１から状態３、状態１から状態４、状態２から状態３、状態２から状態４、状態３から状態２、状態３から状態４、状態４から状態２および状態４から状態３へ変化させる動作を書き込みと呼ぶ。一方、状態２から状態１、状態３から状態１および状態４から状態１へ変化させる動作を消去と呼ぶ。第１の記録層３および第２の記録層５の相状態を所望の相状態に変化させることによって、メモリ１１に情報が書き込まれる、またはメモリ１１に書き込まれた情報が消去される。
【００６９】
以下、図２を参照しながら、メモリ１１に情報を書き込むおよび／または消去する方法を各工程ごとに説明する。
【００７０】
工程Ｓ１：状態１を状態２に、または状態３を状態４に変化させる場合、すなわち、第１の記録層３を非結晶相から結晶相に相変化させ、第２の記録層５の相状態を維持する場合には、パルス発生部７（図１）は第１の電流パルスを発生し、印加部１３（図１）を介してその第１の電流パルスを第１の記録層３および第２の記録層５に印加する。第１の電流パルスは、Ｔ_x1≦Ｔ＜Ｔ_x2なる温度Ｔおよびｔ_x1＜ｔなる時間ｔに相当する電流パルスである。電流パルスの具体的な波形の例は、図３を参照して後述される。
【００７１】
工程Ｓ２：状態１を状態３に、または状態２を状態４に変化させる場合、すなわち、第１の記録層の相状態を維持し、第２の記録層５を非晶質相から結晶相に相変化させる場合には、パルス発生部７は第２の電流パルスを発生し、印加部１３を介してその第２の電流パルスを第１の記録層３および第２の記録層５に印加する。第２の電流パルスは、Ｔ_x2≦Ｔなる温度Ｔおよびｔ_x2≦ｔ＜ｔ_x1なる時間ｔに相当する電流パルスである。
【００７２】
工程Ｓ３：状態４を状態１に変化させる場合、すなわち、第１の記録層３および第２の記録層５を結晶相から非晶質相に相変化させる場合には、パルス発生部７は第３の電流パルスを発生し、印加部１３を介してその第３の電流パルスを第１の記録層３および第２の記録層５に印加する。第３の電流パルスは、第１の記録層３および第２の記録層５の融点のうち低くない方の融点以上の温度に相当する電流パルスである。
【００７３】
工程Ｓ４：状態１を状態４に変化させる場合、すなわち、第１の記録層３および第２の記録層５を非晶質相から結晶相に相変化させる場合には、パルス発生部７は第４の電流パルスを発生し、印加部１３を介してその第４の電流パルスを第１の記録層３および第２の記録層５に印加する。第４の電流パルスは、Ｔ_x2≦Ｔなる温度Ｔおよびｔ_x1≦ｔなる時間ｔに相当する電流パルスである。なお、工程Ｓ４は必須の工程ではない。なぜなら工程Ｓ４は、工程Ｓ２次いで工程Ｓ１、または工程Ｓ１次いで工程Ｓ２を行うことによって代替され得るからである。図２には、工程Ｓ４が必須の工程でないことを示すために、工程Ｓ４に対応する状態遷移を表す矢印が破線で示されている。
【００７４】
工程Ｓ５：第１の記録層３および第２の記録層５の各融点Ｔ_m1、Ｔ_m2が、Ｔ_m1＞Ｔ_m2を満たし、状態４を状態２に変化させる場合、すなわち第１の記録層３を結晶相に維持し、第２の記録層５を結晶相から非晶質相に相変化させる場合には、パルス発生部７は第５の電流パルスを発生し、印加部１３を介してその第５の電流パルスを第１の記録層３および第２の記録層５に印加する。第５の電流パルスは、Ｔ_m2≦Ｔ＜Ｔ_m1なる温度Ｔに相当する電流パルスである。工程Ｓ５は必須の工程ではない。なぜなら工程Ｓ５は、工程Ｓ３次いで工程Ｓ１を行うことによって代替され得るからである。図２には、工程Ｓ５が必須の工程でないことを示すために、工程Ｓ５に対応する状態遷移を破線で示されている。なお、第１の記録層３および第２の記録層５の各融点Ｔ_m1、Ｔ_m2が、Ｔ_m1＜Ｔ_m2を満たす場合には、Ｔ_m1≦Ｔ＜Ｔ_m2なる温度Ｔに相当する第５の電流パルスを第１の記録層３および第２の記録層５に印加することによって、状態４から状態３に変化させることができる。
【００７５】
上述の工程Ｓ１〜Ｓ３さえあれば、第１の記録層３および第２の記録層５の相状態を状態１〜状態４の任意の状態から任意の状態に変化させることができる。例えば、状態２を状態１に変化させる場合には、工程Ｓ２および工程Ｓ３を行えばよい。状態３を状態１に変化させる場合には、工程Ｓ１および工程Ｓ３を行えばよい。状態２を状態３に変化させる場合には、工程Ｓ２、工程Ｓ３、次いで工程Ｓ２を行えばよい。状態３を状態２に変化させる場合には、工程Ｓ１、工程Ｓ３、次いで工程Ｓ１を行えばよい。状態４を状態３に変化させる場合には、工程Ｓ３、次いで工程Ｓ２を行えばよい。
【００７６】
第１の記録層３および第２の記録層５の現在の相状態が既知である場合には、上記の各工程を組み合わせることによって第１の記録層３および第２の記録層５を所望の相状態に相変化させることができる。現在の相状態（初期状態）は、図４を参照して説明される読み出し方法を用いて知ることができる。なお、工程Ｓ２次いで工程Ｓ１、または工程Ｓ１次いで工程Ｓ２を行うことによって、第１の記録層３および第２の記録層５の相状態は、任意の状態から状態４に変化する。このようにして得られた状態４を初期状態として用いて、第１の記録層３および第２の記録層５の相状態を所望の相状態に相変化させてもよい。これによって、読み出し手順が省略される。初期状態として使用することができる状態は、状態４に限定されない。
【００７７】
次に、各状態へ変化させるための電流パルスの波形について説明する。
【００７８】
図３は、２つの記録層の相状態を変化させるための種々の電流パルスの波形を示す。図１に示すパルス発生部７は、種々のパルス振幅（印加電流値）および種々のパルス幅（電流印加時間）を有する電流パルスを発生する。
【００７９】
第１の電流パルス２１：図２で説明したように、第１の電流パルス２１は、状態１を状態２に、または状態３を状態４に変化させる場合に第１の記録層３および第２の記録層５に印加される電流パルスである。第１の電流パルス２１を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５とは、ともに温度上昇し、ｔ_x1≦ｔなる時間ｔの間、Ｔ_x1≦Ｔ＜Ｔ_x2なる温度Ｔになる。実施の形態１では、第１の電流パルス２１のパルス振幅Ｉ_c1およびパルス幅ｔ_c1は、それぞれ２ｍＡおよび１５０ｎｓに設定された。パルス振幅Ｉ_c1およびパルス幅ｔ_c1は、好ましくは、それぞれ０．０２≦Ｉ_c1（ｍＡ）≦１０および５≦ｔ_c1（ｎｓ）≦２００である。第１の電流パルス２１を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３のみが結晶化温度Ｔ_x1および結晶化時間ｔ_x1を達成し、第１の記録層３は非晶質相から結晶相へ相変化し、第２の記録層５は現在の相状態を維持する。
【００８０】
このように、Ｔ_x1≦Ｔ＜Ｔ_x2なる温度Ｔおよびｔ_x1≦ｔなる時間ｔに相当する第１の電流パルス２１を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３を非結晶相から結晶相に相変化させ、第２の記録層５の相状態を維持することができる。
【００８１】
第２の電流パルス２２：第２の電流パルス２２は、状態１を状態３に、または状態２を状態４に変化させる場合に第１の記録層３および第２の記録層５に印加される電流パルスである。第２の電流パルス２２を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、ともに温度上昇し、ｔ_x2≦ｔ＜ｔ_x1なる時間ｔの間、Ｔ_x2≦Ｔなる温度Ｔになる。実施の形態１では、第２の電流パルス２２のパルス振幅Ｉ_c2およびパルス幅ｔ_c2は、それぞれ４ｍＡおよび１００ｎｓに設定された。パルス振幅Ｉ_c2およびパルス幅ｔ_c2は、好ましくは、それぞれ０．０５≦Ｉ_c2（ｍＡ）≦２０および２≦ｔ_c2（ｎｓ）≦１５０である。このような第２の電流パルス２２を第１の記録層３および第２の記録層５に印加することによって、第２の記録層５のみが結晶化温度Ｔ_x2および結晶化時間ｔ_x2を達成し、第１の記録層３は現在の相状態を維持し、第２の記録層５は非晶質相から結晶相へ相変化する。
【００８２】
このように、Ｔ_x2≦Ｔなる温度Ｔおよびｔ_x2≦ｔ＜ｔ_x1なる時間ｔに相当する第２の電流パルス２２を第１の記録層３および第２の記録層５に印加することによって、第１の記録層の相状態を維持し、第２の記録層を非晶質相から結晶相に相変化させることができる。
【００８３】
第３の電流パルス２３：第３の電流パルス２３は、状態４を状態１に変化させる場合に第１の記録層３および第２の記録層５に印加される電流パルスである。第３の電流パルス２３を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、ともに温度上昇し、両方の記録層の低くない方の融点以上の温度Ｔになる。実施の形態１では、第３の電流パルス２３のパルス振幅Ｉ_a1およびパルス幅ｔ_a1は、それぞれ５０ｍＡおよび５０ｎｓに設定された。パルス振幅Ｉ_a1およびパルス幅ｔ_a1は、好ましくは、それぞれ０．１≦Ｉ_a1（ｍＡ）≦２００および１≦ｔ_a1（ｎｓ）≦１００である。このような第３の電流パルス２３を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５の両方がそれらの低くない方の融点（実施の形態１ではＴ_m1＝６３０℃）以上を達成し、ともに溶融された後に急冷され、その結果第１の記録層３および第２の記録層５の両方が結晶相から非晶質相へ相変化する。第３の電流パルス２３のパルス振幅Ｉ_a1は、第１の記録層３および第２の記録層５を非晶質相から結晶相へ相変化させるために必要な電流値Ｉ_c1、Ｉ_c2と比較して大きい。これは、第１の記録層３および第２の記録層５の結晶化温度Ｔ_x1、Ｔ_x2よりも高い温度（Ｔ_m1＝６３０℃）を達成するためである。
【００８４】
このように、第１の記録層３および第２の記録層５の融点のうち低くない方の融点以上の温度に相当する第３の電流パルス２３を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５を結晶相から非晶質相に相変化させることができる。
【００８５】
第１〜第３の電流パルス２１〜２３が、書き込み／読み出し装置１２を用いて情報を書き込む際の必須の電流パルスである。これら第１〜第３の電流パルス２１〜２３を組み合わせることによって、メモリ１１を任意の状態から別の任意の状態へ変化させることができる。
【００８６】
第４の電流パルス２４：第４の電流パルス２４は、状態１を状態４に変化させる場合に第１の記録層３および第２の記録層５に印加される電流パルスである。第４の電流パルス２４を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、ともに温度上昇し、ｔ_x1≦ｔなる時間ｔの間、Ｔ_x2≦Ｔなる温度Ｔになる。第４の電流パルス２４のパルス振幅Ｉ_c12およびパルス幅ｔ_c12は、それぞれ第２の電流パルス２２のパルス振幅Ｉ_c2および第１の電流パルス２１のパルス幅ｔ_c1に等しい。実施の形態１では、第４の電流パルス２４のパルス振幅Ｉ_c12およびパルス幅ｔ_c12は、それぞれ４ｍＡ（＝Ｉ_c2）および１５０ｎｓ（＝ｔ_c1）に設定された。パルス振幅Ｉ_c12およびパルス幅ｔ_c12は、好ましくは、それぞれ０．０５≦Ｉ_c12（ｍＡ）≦２０および５≦ｔ_c12（ｎｓ）≦２００である。このような第４の電流パルス２４を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５の両方が高い方の結晶化温度Ｔ_x2および長い方の結晶化時間ｔ_x1を達成し、第１の記録層３および第２の記録層５の両方が非晶質相から結晶相へ相変化する。
【００８７】
このように、Ｔ_x2≦Ｔなる温度Ｔおよびｔ_x1≦ｔなる時間ｔに相当する第４の電流パルス２４を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５を非晶質相から結晶相に相変化させることができる。
【００８８】
上述したように、第４の電流パルス２４は必須の電流パルスではない。なぜなら、第４の電流パルス２４の代わりに、第１の電流パルス２１および第２の電流パルス２２が代替され得る。しかし、第１の電流パルス２１および第２の電流パルス２２をメモリ１１に印加することに比較して、第４の電流パルス２４をメモリ１１に印加することは、状態１を状態４へより短時間で変化させることができるという利点を有する。
【００８９】
第５の電流パルス２５：第５の電流パルス２５は、第１の記録層３の融点Ｔ_m1および第２の記録層５の融点Ｔ_m2の関係がＴ_m1＞Ｔ_m2であり、状態４を状態２に変化させる場合に第１の記録層３および第２の記録層５に印加される電流パルスである。第５の電流パルス２５を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、ともに温度上昇し、Ｔ_m2≦Ｔ＜Ｔ_m1なる温度Ｔになる。第５の電流パルス２５のパルス振幅Ｉ_a2およびパルス幅ｔ_a2は、それぞれ３０ｍＡおよび５０ｎｓに設定された。パルス振幅Ｉ_a2およびパルス幅ｔ_a2は、好ましくは、それぞれそれぞれ０．０５≦Ｉ_a2（ｍＡ）≦１６０および１≦ｔ_a2（ｎｓ）≦１００である。このような第５の電流パルス２５を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、第１の記録層３の融点には達しないが第２の記録層５の融点（実施の形態１ではＴ_m2＝５５０℃）以上に達する。従って第１の記録層３は結晶相を維持し、第２の記録層５のみが溶融され、急冷されて結晶相から非晶質相に相変化する。なお、第５の電流パルス２５は、第１の記録層３の融点Ｔ_m1および第２の記録層５の融点Ｔ_m2の関係がＴ_m1＜Ｔ_m2の場合には、状態４を状態３に変化させるために用いられ得る。
【００９０】
このように、第１の記録層３の融点Ｔ_m1と第２の記録層５の融点Ｔ_m2との関係がＴ_m1≠Ｔ_m2である場合に、低い方の融点以上かつ高い方の融点未満の温度に相当する第５の電流パルス２５を第１の記録層３および第２の記録層５に印加することによって、低い方の融点を有する記録層を結晶相から非晶質相に相変化させ、高い方の融点を有する記録層を結晶相に維持することができる。
【００９１】
上述したように、第５の電流パルス２５は、第１の記録層３と第２の記録層５の融点が異なる場合に有用であるが、必須の電流パルスではない。なぜなら第５の電流パルスの代わりに、第３の電流パルス２３（または第２の電流パルス２２）および第１の電流パルス２１が代替され得る。しかし、第３の電流パルス２３（または第２の電流パルス２２）および第１の電流パルス２１をメモリ１１に印加することに比較して、第５の電流パルス２５をメモリ１１に印加することは、状態４を状態２（または状態３）へより短時間で変化させることができるという利点を有する。
【００９２】
次に第１〜第５の電流パルス２１〜２５のうち少なくとも２つ以上を組み合わせた電流パルス２６〜３３について説明する。
【００９３】
電流パルス２６：電流パルス２６は、第３の電流パルス２３と第１の電流パルス２１とを組み合わせた電流パルスである。状態４を状態２へ変化させる場合、電流パルス２６は、第５の電流パルス２５の代わりに用いられ得る。電流パルス２６を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、ともに温度上昇し、ｔ_x1≦ｔなる時間ｔの間に、両方の記録層の低くない方の融点以上の温度Ｔになり溶融され、その後、急冷されて、Ｔ_x1≦Ｔ＜Ｔ_x2なる温度Ｔになる。電流パルス２６は、振幅Ｉ_a1（実施の形態１ではＩ_a1＝５０ｍＡ）に次いで振幅Ｉ_c1（実施の形態１ではＩ_c1＝２ｍＡ）全体でｔ_c1（実施の形態１ではｔ_c1＝１５０ｎｓ）となるように設定された。
【００９４】
上述したように、電流パルス２６は必須の電流パルスではない。なぜなら電流パルス２６の代わりに、第５の電流パルス２５が代替され得る。しかし、第５の電流パルス２５をメモリ１１に印加することに比較して、電流パルス２６をメモリ１１に印加することは、第１の記録層３および第２の記録層５の融点が等しい場合であっても状態４を状態２へ変化させることができるという利点を有する。
【００９５】
このように、両方の記録層の低くない方の融点以上、次いでＴ_x1≦Ｔ＜Ｔ_x2なる温度Ｔを全体でｔ_x1＜ｔなる時間ｔに相当する電流パルス２６を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、結晶相から非晶質相に相変化した後、第１の記録層３を非晶質相から結晶相に相変化させ、第２の記録層５を非晶質相に維持することができる。すなわち、メモリ１１は、状態４から状態１を介して状態２へと変化する。
【００９６】
電流パルス２７：電流パルス２７は、第３の電流パルス２３と第２の電流パルス２２を組み合わせた電流パルスである。状態４を状態３に変化させる場合に、電流パルス２７が用いられる。電流パルス２７を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、ともに温度上昇し、ｔ_x2≦ｔ＜ｔ_x1なる時間ｔの間、両方の記録層の低くない方の融点以上の温度Ｔになり溶融される。その後急冷されて、Ｔ_x2≦Ｔなる温度Ｔになる。電流パルス２７は、振幅Ｉ_a1に次いで振幅Ｉ_c2（実施の形態１ではＩ_c2＝４ｍＡ）全体でｔ_c2（実施の形態１ではｔ_c2＝１００ｎｓ）となるように設定された。
【００９７】
このように、両方の記録層の低くない方の融点以上、次いでＴ_x2≦Ｔなる温度Ｔを全体でｔ_x2≦ｔ＜ｔ_x1なる時間ｔに相当する電流パルス２７を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層は、結晶相から非晶質相に相変化した後、第１の記録層３を非晶質相に維持し、第２の記録層５を非晶質相から結晶相に相変化させることができる。すなわち、メモリ１１は、状態４から状態１を介して状態３へと変化する。
【００９８】
電流パルス２８：電流パルス２８は、第１の電流パルス２１と第３の電流パルス２３とを組み合わせた電流パルスである。状態３を状態１に変化させる場合に、電流パルス２８が用いられる。電流パルス２８を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、ともに温度上昇し、ｔ_x1≦ｔなる時間ｔの間、Ｔ_x1≦Ｔ＜Ｔ_x2なる温度Ｔになり、次いで両方の記録層の低くない方の融点以上の温度Ｔになる。電流パルス２８は、振幅Ｉ_c1、パルス幅ｔ_c1に次いで振幅Ｉ_a1、パルス幅ｔ_a1（実施の形態１ではｔ_a1＝５０ｎｓ）となるように設定された。
【００９９】
このように、Ｔ_x1≦Ｔ＜Ｔ_x2なる温度Ｔおよびｔ_x1≦ｔなる時間ｔ、次いで第１の記録層３および第２の記録層５の融点のうち低くない方の融点以上の温度に相当する電流パルス２８を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３を非晶質相から結晶相に相変化させ、第２の記録層５を結晶相に維持し、次いで両方の記録層の結晶相を非晶質相に相変化させることができる。すなわち、メモリ１１の状態は、状態３から状態４を介して状態１へと変化する。
【０１００】
電流パルス２９：電流パルス２９は、第２の電流パルス２２と第３の電流パルス２３とを組み合わせた電流パルスである。状態２を状態１に変化させる場合に、電流パルス２９が用いられる。電流パルス２９を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、ともに温度上昇し、ｔ_x2≦ｔ＜ｔ_x1なる時間ｔの間、Ｔ_x2≦Ｔなる温度Ｔになり、次いで両方の記録層の低くない方の融点以上の温度Ｔになる。電流パルス２９は、振幅Ｉ_c2、パルス幅ｔ_c2に次いで振幅Ｉ_a1、パルス幅ｔ_a1となるように設定された。
【０１０１】
このように、Ｔ_x2≦Ｔなる温度Ｔおよびｔ_x2≦ｔ＜ｔ_x1なる時間ｔ、次いで第１の記録層３および第２の記録層５の融点のうち低くない方の融点以上の温度に相当する電流パルス２９を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３を結晶相に維持し、第２の記録層５を非晶質相から結晶相に相変化させ、次いで両方の記録層の結晶相を非晶質相に相変化させることができる。すなわち、メモリ１１の状態は、状態２から状態４を介して状態１へと変化する。
【０１０２】
電流パルス３０：電流パルス３０は、第４の電流パルスと第３の電流パルスとを組み合わせた電流パルスである。状態２または状態３を状態１に変化させる場合に、電流パルス３０が用いられる。電流パルス３０は、電流パルス２８および電流パルス２９の代わりに用いることができる。電流パルス３０を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、ともに温度上昇し、ｔ_x1≦ｔなる時間ｔの間、Ｔ_x2≦Ｔなる温度Ｔになり、次いで両方の記録層の低くない方の融点以上の温度Ｔになる。電流パルス３０は、振幅Ｉ_c2、パルス幅ｔ_c1に次いで、振幅Ｉ_a1、パルス幅ｔ_a1となるように設定された。
【０１０３】
このように、Ｔ_x2≦Ｔなる温度Ｔおよびｔ_x1≦ｔなる時間ｔ、次いで第１の記録層３および第２の記録層５の融点のうち低くない方の融点以上の温度に相当する電流パルス３０を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５の各々が結晶相または非晶質相のいずれの相状態であっても、第１の記録層３および第２の記録層５をともに結晶相に相変化させ、次いで両方の記録層の結晶相を非晶質相に相変化させることができる。すなわち、メモリ１１の状態は、状態２または状態３を状態４を介して状態１へと変化する。
【０１０４】
電流パルス３１：電流パルス３１は、第２の電流パルス２２と電流パルス２７（第３の電流パルス２３と第２の電流パルス２２との組み合わせ）とを組み合わせた電流パルスである。状態２を状態３に変化させる場合に、電流パルス３１が用いられる。電流パルス３１を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、ともに温度上昇し、ｔ_x2≦ｔ＜ｔ_x1なる時間ｔの間、Ｔ_x2≦Ｔなる温度Ｔになり、次いでｔ_x2≦ｔ＜ｔ_x1なる時間ｔの間、両方の記録層の低くない方の融点以上の温度Ｔになり、その後急冷されて、Ｔ_x2≦Ｔなる温度Ｔになる。電流パルス３１は振幅Ｉ_c2、パルス幅ｔ_c2、次いで振幅Ｉ_a1、振幅Ｉ_c2全体でｔ_c2となるように設定された。
【０１０５】
このように、Ｔ_x2≦Ｔなる温度Ｔおよびｔ_x2≦ｔ＜ｔ_x1なる時間ｔ、次いでｔ_x2≦ｔ＜ｔ_x1なる時間ｔの間、両方の記録層の低くない方の融点以上の温度Ｔその後Ｔ_x2≦Ｔなる温度Ｔに相当する電流パルス３１を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３を結晶相に維持し、第２の記録層５を非晶質相から結晶相に相変化させ、次いで第１の記録層３および第２の記録層５を結晶相から非晶質相に相変化させる。その後第１の記録層３を非晶質相に維持し、第２の記録層５を非晶質相から結晶相に相変化させることができる。すなわち、メモリ１１の状態は、状態２から状態４次いで状態１を介して状態３へと変化する。
【０１０６】
電流パルス３２：電流パルス３２は、第１の電流パルス２１と第５の電流パルス２５とを組み合わせた電流パルスである。状態３を状態２に変化させる場合に、電流パルス３２が用いられる。電流パルス３２を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、ともに温度上昇し、ｔ_x1≦ｔなる時間ｔの間、Ｔ_x1≦Ｔ＜Ｔ_x2なる温度Ｔになり、次いでＴ_m2なる温度Ｔになる。電流パルス３２は、振幅Ｉ_c1、パルス幅ｔ_c1、次いで振幅Ｉ_a2（実施の形態１ではＩ_a2＝３０ｍＡ）、パルス幅ｔ_a2（実施の形態１ではｔ_a2＝５０ｎｓ）となるように設定された。
【０１０７】
このように、Ｔ_x1≦Ｔ＜Ｔ_x2なる温度Ｔおよびｔ_x1≦ｔなる時間ｔ、次いでＴ_m2なる温度Ｔに相当する電流パルス３２を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３を非晶質相から結晶相に相変化させ、第２の記録層５を結晶相に維持し、次いで第１の記録層３を結晶相に維持し、第２の記録層５を結晶相から非晶質相に相変化させることができる。すなわち、メモリ１１の状態は、状態３から状態４を介して状態２へと変化する。
【０１０８】
電流パルス３３：電流パルス３３は、第１の電流パルス２１と電流パルス２６（第３の電流パルス２３と第１の電流パルス２１との組み合わせ）とを組み合わせた電流パルスである。状態３を状態２に変化させる場合、電流パルス３３が、電流パルス３２の代わりに用いられ得る。電流パルス３３を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３および第２の記録層５は、ともに温度上昇し、ｔ_x1≦ｔなる時間ｔの間、Ｔ_x1≦Ｔ＜Ｔ_x2なる温度Ｔになり、次いでｔ_x1≦ｔなる時間ｔの間に、両方の記録層の低くない方の融点以上の温度Ｔになり溶融され、その後急冷されて、Ｔ_x1≦Ｔ＜Ｔ_x2なる温度Ｔになる。電流パルス３３は、振幅Ｉ_c1、パルス幅ｔ_c1、次いで振幅Ｉ_a1、振幅Ｉ_c1全体でｔ_c1となるように設定された。
【０１０９】
このように、Ｔ_x1≦Ｔ＜Ｔ_x2なる温度Ｔおよびｔ_x1≦ｔなる時間ｔ、その後両方の記録層の低くない方の融点以上、次いでＴ_x1≦Ｔ＜Ｔ_x2なる温度Ｔを全体でｔ_x1≦ｔなる時間ｔに相当する電流パルス３３を第１の記録層３および第２の記録層５に印加することによって、第１の記録層３を非晶質相から結晶相に相変化させ、第２の記録層５を結晶相に維持し、次いで第１の記録層３および第２の記録層５を結晶相から非晶質相に相変化させる。その後第１の記録層３を非晶質相から結晶相に相変化させ、第２の記録層５を非晶質相に維持することができる。すなわち、メモリ１１の状態は、状態３から状態４次いで状態１を介して状態２へと変化する。
【０１１０】
電流パルス２８〜３３では、メモリ１１は、一旦状態４を介して所望の状態へ変化している。これは、第１の記録層３または第２の記録層５のいずれか一方が非晶質相（高抵抗状態）である場合、印加された電流パルスの電気エネルギーの大部分が、非晶質相である記録層で消費されるので、他方の結晶相（低抵抗状態）のみを非晶質相に相変化させるために必要な電気エネルギーを結晶相である記録層に印加できないためである。従って、一旦両方の記録層を結晶相に相変化させ、次いでその両方の記録層を非晶質相に相変化させるように、電流パルス２８〜３３は設定されている。
【０１１１】
本発明による書き込み／読み出し装置１２によれば、３つの電流パルスおよび３つの電流パルスの組み合わせを用いることで、第１の記録層３および第２の記録層５の相状態を結晶相と非晶質相との間で制御し、第１の記録層３および第２の記録層５の任意の相状態から所望の相状態へ相変化させることができる。
【０１１２】
次にメモリ１１に書き込まれた情報を読み出す方法を説明する。メモリ１１に書き込まれた情報を読み出す際には、図１に示すスイッチ１０が閉じられ、書き込み／読み出し装置１２が印加部１３を介してメモリ１１に接続される。抵抗測定部８は、第１の記録層３および第２の記録層５に電流パルスＩ_rを印加し、その際に下部電極２（図１）と上部電極６（図１）との間に発生する電位差に基づいて、第１の記録層３および第２の記録層５の抵抗値（第１の記録層３の抵抗値と第２の記録層５の抵抗値との和）を検出する。電流パルスＩ_rは、抵抗測定部８が発生する代わりに、パルス発生部７が発生してもよい。この場合には、スイッチ９が閉じられる。電流パルスＩ_rは、第１の記録層３および第２の記録層５の相変化が生じない大きさの振幅およびパルス幅を有する。電流パルスＩ_rは、好ましくは、Ｉ_r（ｍＡ）≦０．０２である。
【０１１３】
図４は、本発明による、書き込み／読み出し装置を用いたメモリ１１に書き込まれた情報を読み出す方法を示すフローチャートである。以下、図４を参照しながら、メモリ１１に書き込まれた情報を読み出す方法を各工程ごとに説明する。
【０１１４】
工程４０１：第１の記録層３および第２の記録層５に電流パルスＩ_rを印加部１３を介して印加する。
【０１１５】
工程４０２：抵抗測定部８が第１の記録層３および第２の記録層５の抵抗の和を測定する。
【０１１６】
工程４０３：判定部１６が、測定された抵抗の和が、状態１〜４のいずれの状態の第１の記録層３および第２の記録層５の抵抗の和に一致するかを判定する。これにより、メモリ１１に書き込まれた情報が読み出される。
【０１１７】
図２と図４を参照して説明した例では、書き込み／読み出し装置１２が、書き込みと読み出しの機能を兼ね備えるものとして説明した。しかしながら、書き込み／読み出し装置１２は、書き込み（および消去）と読み出しとのいずれかのみを行うように構成されていてもよい。書き込み／読み出し装置１２が、書き込み（および消去）のみを行う場合には、抵抗測定器８および判定部１６は省略され得る。この場合には、書き込み／読み出し装置１２は、メモリ１１への情報の書き込み（および消去）装置として機能する。書き込み／読み出し装置１２が、読み出しのみを行う場合には、パルス発生部７は省略してもよい。また、書き込み／読み出し装置１２が、書き込み（および消去）と読み出しの機能を切り換えるためのスイッチ９、１０は、手動で切り換えられてもよいし、書き込み／読み出し装置１２の外部から与えられるコマンドに基づいて、スイッチ９、１０を制御する制御部が設けられていてもよい。
【０１１８】
図１に示される例では、１つのメモリ１１のみが用いられていた。しかし、複数のメモリ１１をマトリクス状に配置した構成を採用してもよい。
【０１１９】
図５は、本発明のメモリをマトリクス状に配置した記憶装置と記憶装置に接続された外部回路の構成を示す。図１に示す構成要素と同一の構成要素には同一の参照符号を付し、これらについての詳細な説明は省略する。
【０１２０】
外部回路５４は、パルス発生部７と、抵抗測定部８、スイッチ９および１０と、判定部１６と、制御部５１とを含む。記憶装置５８は、ロウデコーダおよびカラムデコーダを含む印加部１３と、ビット線５２と、ワード線５３と、複数のメモリ１１から構成されるメモリアレイ５５とを含む。
【０１２１】
制御部５１は、書き込み動作または読み出し動作のいずれの動作を行うかを示すコマンド等の制御情報をライン５６を介してそれぞれパルス発生部７および抵抗測定部８に送る。パルス発生部７および抵抗測定部８のそれぞれは、受け取った制御情報に応じて、スイッチ９およびスイッチ１０の開閉を行い、書き込み動作または読み出し動作を行う。制御部５１はまた、メモリアレイ５５のうちどのメモリ１１に電流パルスを印加するかを示すアドレス情報をライン５７を介して印加部１３に送る。
【０１２２】
印加部１３のロウデコーダおよびカラムデコーダはそれぞれ、受け取ったアドレス情報によって指定されるメモリ１１のワード線５３およびビット線５２を指定する。次いで、指定されたメモリ１１に電流パルスが印加されて、書き込み動作または読み出し動作が行われる。
【０１２３】
図５に示すように図１のメモリ１１をマトリクス状に配置することによって、記憶装置の記憶容量を増大させることができる。
【０１２４】
（実施の形態２）
実施の形態１では、メモリ１１を構成する記録層が２層の場合を説明した。しかし、メモリ１１を構成する記録層の数は、２に限定されない。実施の形態２では、メモリを構成する記録層がＮ層（Ｎ＞２、Ｎは自然数）の場合を説明する。
【０１２５】
図６は、Ｎ個の記録層６２から構成されるメモリ６０を示す。図１に示す構成要素と同一の構成要素には同一の参照符号を付し、これらについての詳細な説明は省略する。メモリ６０は、基板１と、下部電極２と、第１〜第Ｎ−１の中間層６１と、Ｎ個の記録層６２と、上部電極６とを含む。
【０１２６】
第１〜第Ｎ−１の中間層６１は、図１の中間層４と同様に、Ｎ個の記録層６２間で各記録層を構成する原子が拡散することを防ぐために設けられる。第１〜第Ｎ−１の中間層６１は好ましくは導電性であり、Ａｌ、Ａｕ、Ａｇ、Ｃｕ、Ｐｔ、Ｔｉ、Ｗ等の単体金属材料、およびこれらの組み合わせ（合金材料）が挙げられるが、これらに限定されない。
【０１２７】
なお、下部電極２および／または上部電極６に代えて、Ｎ個の記録層６２に電流パルスを印加することが可能な任意の構成が採用され得る。例えば、基板１が導電性である場合には、下部電極２は省略され得る。第１〜第Ｎ−１の中間層６１は、Ｎ個の記録層６２の材質が、それらの間で互いに原子が拡散しないような材質である場合には、省略してもよい。
【０１２８】
Ｎ個の記録層６２は、それぞれ電流パルスなどの電気エネルギーの印加による温度上昇に起因して結晶相と非晶質相との間で可逆的な相変化を起こす材料から構成される。Ｎ個の記録層６２の材料は、以下の条件１〜条件３を満たすように選択される。
【０１２９】
条件１：Ｎ個の記録層６２のうち第ｍ（１≦ｍ≦Ｎ）の記録層の結晶化温度Ｔ_xmは、関係Ｔ_x1＜Ｔ_x2＜…＜Ｔ_xm-1＜Ｔ_xm＜Ｔ_xm+1＜…＜Ｔ_xNを満たす。
【０１３０】
条件２：Ｎ個の記録層６２のうち第ｍの記録層の結晶化時間ｔ_xmは、関係ｔ_x1＞ｔ_x2＞…＞ｔ_xm-1＞ｔ_xm＞ｔ_xm+1＞…＞ｔ_xNを満たす。
【０１３１】
条件３：Ｎ個の記録層の各記録層が非晶質相の場合の抵抗値、およびＮ個の記録層の各記録層が結晶相の場合の抵抗値がすべて異なり、Ｎ個の記録層の抵抗の和は、２^N個の異なる値をとる。
【０１３２】
条件１と条件２とが満たされることによって、Ｎ個の記録層６２のそれぞれの相状態を所望の状態（非晶質相または結晶相）に設定することが可能になる。さらに、条件３が満たされることによって、Ｎ個の記録層６２のそれぞれの相状態の組み合わせである２^N個の状態を区別して検出することができる。２^N個の状態に対応する２^N値（すなわちＮビット）の情報を担持することができる。各記録層を結晶相と非晶質相との間でのみ制御すればよいので、１つの記録層の相状態を段階的に制御することに比べて制御が容易である。
【０１３３】
このように構成されたメモリ６０は、図１に示すメモリ１１の代わりに用いられる。図１に示す書き込み／読み出し装置１２をメモリ６０への情報の書き込みおよびメモリ６０に書き込まれた情報の読み出しに用いる。
【０１３４】
Ｎ個の記録層６２のそれぞれが、非晶質相または結晶相のいずれかの状態をとることによって、メモリ６０は２^N個の状態のいずれかをとる。状態１は、Ｎ個の記録層６２すべてが非晶質相である状態とする。状態２^Nは、Ｎ個の記録層６２すべてが結晶相である状態とする。状態１から任意の状態へ変化させる動作を書き込みと呼ぶ。一方、状態１を除く任意の状態から状態１へ変化させる動作を消去と呼ぶ。Ｎ個の記録層６２の相状態を所望の相状態に変化させることによって、メモリ６０に情報が書き込まれるおよび／またはメモリ６０に書き込まれた情報が消去される。
【０１３５】
次に、メモリ６０に情報を書き込むまたはメモリ６０に書き込まれた情報を消去する方法を説明する。
【０１３６】
メモリ６０への情報の書き込みおよび消去を行う場合、スイッチ９が閉じられ、スイッチ１０が開かれる。パルス発生部７は、Ｎ個の記録層６２の相状態を所望の相状態に変化させるために必要な振幅とパルス幅とを有する電流パルスを発生する。電流パルスは、印加部１３を介してＮ個の記録層６２に印加される。
【０１３７】
図７は、Ｎ個の記録層６２の相状態を変化させるための種々の電流パルスの波形を示す。
【０１３８】
電流パルス（結晶化電流パルス）７０：結晶化電流パルス７０は、第ｍの記録層のみを非晶質相から結晶相に相変化させる場合に、Ｎ個の記録層６２に印加される電流パルスである。１≦ｍ≦Ｎなるｍのそれぞれについて、結晶化電流パルスが存在する。結晶化電流パルス７０をＮ個の記録層６２に印加することによって、Ｎ個の記録層６２すべてが温度上昇し、ｔ_xm≦ｔ_x＜ｔ_x(m-1)なる時間ｔ_xの間、Ｔ_xm≦Ｔ_x＜Ｔ_x(m+1)なる温度Ｔ_xになる。振幅Ｉ_cmおよびパルス幅ｔ_cmを有する結晶化電流パルス７０をＮ個の記録層６２に印加することによって、第ｍの記録層のみが、第ｍの記録層の結晶化温度Ｔ_xmおよび結晶化時間ｔ_xmを達成し、非晶質相から結晶相に相変化する。
【０１３９】
このように、Ｔ_xm≦Ｔ_x＜Ｔ_x(m+1)なる温度Ｔ_xおよびｔ_xm≦ｔ_x＜ｔ_x(m-1)なる時間ｔ_xに相当する結晶化電流パルス７０を印加部１３を介してＮ個の記録層６２に印加することによって、第ｍの記録層のみを非晶質相から結晶相に相変化させ、第ｍの記録層を除く記録層の相状態を維持することができる。なお、上述した関係ｔ_xm≦ｔ_x＜ｔ_x(m-1)は、ｍ＝１の場合には、関係ｔ_x1≦ｔ_xと読みかえられる。また、ｍ＝Ｎの場合には、関係Ｔ_xm≦Ｔ_x＜Ｔ_x(m+1)は、Ｔ_xN≦Ｔ_xと読みかえられる。
【０１４０】
電流パルス（非晶質化電流パルス）７１：非晶質化電流パルス７１は、メモリ６０の状態を状態２^Nから状態１に変化させる場合、Ｎ個の記録層６２に印加される電流パルスである。非晶質化電流パルス７１をＮ個の記録層６２に印加することによって、Ｎ個の記録層６２のすべてが、温度上昇し、Ｎ個の記録層６２の融点のうちもっとも高い融点以上の温度になる。振幅Ｉ_aN+1およびパルス幅ｔ_aN+1を有する非晶質化電流パルス７１をＮ個の記録層６２に印加することによって、Ｎ個の記録層６２のすべてが融点Ｔ_m1を達成し溶融される。その後急冷されて、結晶相から非晶質相に相変化する。
【０１４１】
このように、Ｎ個の記録層の融点のうちもっとも高い融点以上の温度に相当する非晶質化電流パルス７１を印加部１３を介してＮ個の記録層６２に印加することによって、Ｎ個の記録層６２のすべてを結晶相から非晶質相に相変化させることができる。
【０１４２】
Ｎ個の記録層６２のうち非晶質相である記録層のそれぞれについての結晶化電流パルス７０をメモリ６０に順次印加することにより、任意の状態にあるメモリ６０を状態２^Nに変化させることができる。また、状態２^Nにあるメモリ６０に非晶質化電流パルス７１を印加することにより、メモリ６０を状態１に変化させることができる。さらに、状態１にあるメモリ６０に、結晶相に相変化させることが所望されるＮ個の記録層６２のうちの１つ以上の記録層についての結晶化電流パルス７０を順次印加することにより、メモリ６０を状態１から任意の状態に変化させることができる。このように、結晶化電流パルス７０および／または非晶質化電流パルス７１を単独または組み合わせて用いることにより、２^N個の状態のうち任意の状態にあるメモリ６０を任意の別の状態へ変化させることができる。
【０１４３】
電流パルス７２：電流パルス７２は、Ｎ個の記録層６２のうち第ｍの記録層から第（ｍ＋ｎ−１）の記録層を非晶質相から結晶相に相変化させる場合に、Ｎ個の記録層６２に印加部１３を介して印加される電流パルスである。電流パルス７２をＮ個の記録層６２に印加することによって、Ｎ個の記録層６２のすべてが、温度上昇し、ｔ_xm≦ｔ_x＜ｔ_x(m-1)なる時間ｔ_x間、Ｔ_x(m+n-1)≦Ｔ_x＜Ｔ_x(m+n)なる温度Ｔ_xになる。振幅Ｉ_c(m+n-1)およびパルス幅ｔ_cmを有する電流パルス７２をＮ個の記録層６２に印加することによって、第ｍ〜第（ｍ＋ｎ−１）の記録層が結晶化温度Ｔ_x(m+n-1)および結晶化時間ｔ_xmを達成し、非晶質相から結晶相に相変化する。
【０１４４】
このように、Ｔ_x(m+n-1)≦Ｔ_x＜Ｔ_x(m+n)なる温度Ｔ_xおよびｔ_xm≦ｔ_x＜ｔ_x(m-1)なる時間ｔ_xに相当する電流パルス７２を印加部１３を介してＮ個の記録層６２に印加することによって、Ｎ個の記録層６２のうち第ｍ〜第（ｍ＋ｎ−１）の記録層を非晶質相から結晶相に相変化させることができる。
【０１４５】
電流パルス７２は必須の電流パルスではない。なぜなら、結晶化電流パルス７０をメモリ６０に順次印加することによっても、第ｍ〜第（ｍ＋ｎ−１）の記録層を非晶質相から結晶相に相変化させることができるからである。しかし、結晶化電流パルス７０をメモリ６０に順次印加することに比較して、電流パルス７２をメモリ６０に印加することは、第ｍ〜第（ｍ＋ｎ−１）の記録層をより短時間で非晶質相から結晶相に相変化させることができるという利点を有する。
【０１４６】
電流パルス７３：電流パルス７３は、状態１を状態２^Nに変化させる場合、印加部１３を介してＮ個の記録層６２に印加される電流パルスである。電流パルス７３をＮ個の記録層６２に印加することによって、Ｎ個の記録層６２のすべてが、温度上昇し、ｔ_x1≦ｔ_xなる時間ｔ_xの間、Ｔ_xN≦Ｔ_xなる温度Ｔ_xになる。振幅Ｉ_cNおよびパルス幅ｔ_c1を有する電流パルス７３をＮ個の記録層６２に印加することによって、Ｎ個の記録層６２のすべてが結晶化温度Ｔ_xNおよび結晶化時間ｔ_x1を達成し、非晶質相から結晶相に相変化する。
【０１４７】
このように、Ｔ_xN≦Ｔ_xなる温度Ｔ_xおよびｔ_x1≦ｔ_xなる時間ｔ_xに相当する電流パルス７３をＮ個の記録層６２に印加することによって、Ｎ個の記録層６２すべてを非晶質相から結晶相に相変化させることができる。
【０１４８】
電流パルス７３は必須の電流パルスではない。なぜなら、結晶化電流パルス７０をメモリ６０に順次印加することによっても、Ｎ個の記録層６２のすべてを非晶質相から結晶相に相変化させることができるからである。しかし、結晶化電流パルス７０をメモリ６０に順次印加することに比較して、電流パルス７３をメモリ６０に印加することは、状態１を状態２^Nにより短時間で変化させることができるという利点を有する。
【０１４９】
電流パルス７４：電流パルス７４は、電流パルス７３と非晶質化電流パルス７１とを組み合わせた電流パルスである。このような電流パルス７４は、Ｎ個の記録層６２のうち少なくとも１つの記録層が非晶質相であり、メモリ６０を状態１に変化させる場合に、印加部１３を介してＮ個の記録層６２に印加される電流パルスである。電流パルス７４をＮ個の記録層６２に印加することによって、Ｎ個の記録層６２のすべてが、温度上昇し、ｔ_x1≦ｔ_xなる時間ｔ_xの間、Ｔ_x≧Ｔ_xNなる温度Ｔ_xになり、次いでＮ個の記録層６２のうち最も融点の高い温度になる。振幅Ｉ_cNおよびパルス幅ｔ_c1、次いで振幅Ｉ_aN+1およびパルス幅ｔ_aN+1を有する電流パルス７４をＮ個の記録層６２に印加することによって、Ｎ個の記録層６２のすべてが結晶化温度Ｔ_xNおよび結晶化時間ｔ_x1を達成し、非晶質相から結晶相に相変化する。次いで、Ｎ個の記録層６２のすべてが、Ｎ個の記録層６２の各融点のうち最も高い融点以上に達し溶融し、急冷されて結晶相から非晶質相に相変化する。
【０１５０】
電流パルス７４は必須の電流パルスではない。なぜなら、結晶化電流パルス７０をメモリ６０に順次印加して、Ｎ個の記録層６２を状態２^Nに変化させ、次いで非晶質化電流パルス７１をメモリ６０に印加することによっても、状態２^Nから状態１に変化することができるからである。しかし、結晶化電流パルス７０をメモリ６０に順次印加し、非晶質化電流パルス７１を印加することに比較して、電流パルス７４をメモリ６０に印加することは、状態２^Nを除く任意の状態から状態１により短時間で変化させることができるという利点を有する。
【０１５１】
電流パルス７５：電流パルス７５は、Ｎ個の記録層６２のうち少なくとも１つの記録層のそれぞれが温度Ｔ_m以下の融点を有し、Ｎ個の記録層のうちの少なくとも１つの記録層を除く記録層のそれぞれが温度Ｔ_mよりも高い融点を有し、少なくとも１つの記録層のそれぞれを結晶相から非晶質相に相変化させ、少なくとも１つの記録層のそれぞれを除く記録層を結晶相に維持する場合に、Ｎ個の記録層６２に印加される電流パルスである。電流パルス７５をＮ個の記録層６２に印加することによって、Ｎ個の記録層６２すべてが、温度上昇し、少なくとも１つの記録層のそれぞれが温度Ｔ_mとなる。振幅Ｉ_cmおよびパルス幅ｔ_amを有する電流パルス７５をＮ個の記録層６２に印加することによって、温度Ｔ_m以下の融点を有する少なくとも１つの記録層のそれぞれのみが温度Ｔ_mを達成し、結晶相から非晶質相に相変化する。
【０１５２】
温度Ｔ_mは、Ｎ個の記録層６２の融点のうち最も低い融点以上かつＮ個の記録層６２のうち最も高い融点未満となるように任意に選択され得る。このように温度Ｔ_mを選択することにより、Ｎ個の記録層６２を温度Ｔ_m以下の融点を有する少なくとも１つの記録層からなる低融点側のグループと、温度Ｔ_mより高い融点を有する少なくとも１つの記録層からなる高融点側のグループとに分けることができる。温度Ｔ_mに相当する電流パルス７５をＮ個の記録層６２に印加することによって、低融点側のグループに含まれる記録層のそれぞれを結晶相から非晶質相に相変化させることができる。
【０１５３】
電流パルス７５は、Ｎ個の記録層６２の融点が異なる場合に有用であるが、必須の電流パルスではない。なぜなら電流パルス７５の代わりに、非晶質化電流パルス７１および結晶化電流パルス７０をメモリ６０に順次印加することによっても、Ｎ個の記録層６２のうち所望の記録層のみを結晶相に相変化させることができるからである。しかし、非晶質化電流パルス７１および結晶化電流パルス７０をメモリ６０に印加することに比較して、電流パルス７５をメモリ６０に印加することは、メモリ６０をより短時間でＮ個の記録層６２のうち所望の記録層のみを結晶相に相変化させることができるという利点を有する。
【０１５４】
Ｎ個の記録層６２の現在の相状態が既知である場合には、上記の結晶化電流パルス７０と非晶質化電流パルス７１とを組み合わせることによって、Ｎ個の記録層６２を所望の相状態に相変化させることができる。現在の相状態（初期状態）は、図８を参照して説明される読み出し方法を用いて知ることができる。なお、ｍ＝１〜Ｎのそれぞれについての結晶化電流パルス７０をメモリ６０に順次印加することによって（あるいは、電流パルス７３をメモリ６０に印加することによって）、メモリ６０の状態は、任意の状態から状態２^Nに変化する。このようにして得られた状態２^Nを初期状態として用いて、Ｎ個の記録層６２の相状態を所望の相状態に相変化させてもよい。これによって、読み出し手順が省略される。初期状態として使用することができる状態は、状態２^Nに限定されない。
【０１５５】
次にメモリ６０に書き込まれた情報を読み出す方法を説明する。読み出し方法は、実施の形態１において図４を参照して説明された読み出し方法と同様である。メモリ６０に書き込まれた情報を読み出す際には、図１に示すスイッチ１０が閉じられ、書き込み／読み出し装置１２が印加部１３を介してメモリ６０に接続される。抵抗測定部８は、Ｎ個の記録層６２に電流パルスＩ_rを印加し、その際に下部電極２（図１）と上部電極６（図１）との間に発生する電位差に基づいて、Ｎ個の記録層６２の抵抗値（Ｎ個の記録層６２のそれぞれの抵抗値の和）を検出する。電流パルスＩ_rは、Ｎ個の記録層６２が相変化しない大きさの振幅およびパルス幅を有する。
【０１５６】
図８は、本発明による、書き込み／読み出し装置１２を用いたメモリ６０に書き込まれた情報を読み出す方法を示すフローチャートである。以下、図８を参照しながら、メモリ６０に書き込まれた情報を読み出す方法を各工程について説明する。
【０１５７】
工程８０１：Ｎ個の記録層６２に電流パルスＩ_rを印加部１３を介して印加する。
【０１５８】
工程８０２：抵抗測定部８がＮ個の記録層６２の抵抗の和を測定する。
【０１５９】
工程８０３：判定部１６が、測定された抵抗の和が、状態１〜２^Nのいずれの状態のＮ個の記録層６２の抵抗の和に一致するかを判定する。これにより、メモリ６０に書き込まれた情報が読み出される。
【０１６０】
なお、図６のメモリ６０を図５に示されるようにマトリクス状に配置し、記憶装置の記憶容量を増大させることもまた可能である。
【０１６１】
図６のメモリ６０は、Ｎ個の記録層６２が、第１〜第Ｎの記録層の順で堆積されていた。しかしながら、第１〜第Ｎの記録層は、任意の順番（例えば、ランダムな順番）で堆積されてもよい。
【０１６２】
【発明の効果】
本発明のメモリは、電流パルスの印加による温度上昇に起因して結晶相と非晶質相との間で可逆的な相変化を起こすことにより情報を記録する第１の記録層と、電流パルスの印加による温度上昇に起因して結晶相と非晶質相との間で可逆的な相変化を起こすことにより情報を記録する第２の記録層とを備える。第１の記録層の結晶化温度Ｔ_x1と第２の記録層の結晶化温度Ｔ_x2との関係が、Ｔ_x1＜Ｔ_x2であり、第１の記録層の結晶化時間ｔ_x1と第２の記録層の結晶化時間ｔ_x2との関係が、ｔ_x1＞ｔ_x2を満たすので、第１の記録層の相状態と第２の記録層の相状態とをそれぞれ所望の状態（非晶質相または結晶相）に設定することが可能になる。さらに、第１の記録層が非晶質相の場合の抵抗値をＲ_a1、第１の記録層が結晶相の場合の抵抗値をＲ_c1、第２の記録層が非晶質相の場合の抵抗値をＲ_a2、第２の記録層が結晶相の場合の抵抗値をＲ_c2とすると、Ｒ_a1＋Ｒ_a2、Ｒ_a1＋Ｒ_c2、Ｒ_a2＋Ｒ_c1、Ｒ_c1＋Ｒ_c2が互いに異なるので、第１の記録層の相状態と第２の記録層の相状態との組み合わせである４つの状態を区別して検出することができる。第１の記録層および第２の記録層の相状態を結晶相と非晶質相との間で制御するだけなので、制御が容易である。なお、このようなメモリは、２つの記録層の限定されず、２つより多くの記録層を用いた場合にも同様の効果が得られる。
【図面の簡単な説明】
【図１】本発明によるメモリに接続された書き込み／読み出し装置の構成を示す図
【図２】第１の記録層および第２の記録層の相状態に関する状態遷移図
【図３】２つの記録層の相状態を変化させるための種々の電流パルスの波形を示す図
【図４】本発明による、書き込み／読み出し装置を用いたメモリに書き込まれた情報を読み出す方法を示すフローチャート
【図５】本発明のメモリをマトリクス状に配置した記憶装置と記憶装置に接続された外部回路の構成を示す図
【図６】Ｎ個の記録層から構成されるメモリを示す図
【図７】Ｎ個の記録層の相状態を変化させるための種々の電流パルスの波形を示す図
【図８】本発明による、書き込み／読み出し装置を用いたメモリに書き込まれた情報を読み出す方法を示すフローチャート
【符号の説明】
１ 基板
２ 下部電極
３ 第１の記録層
４ 中間層
５ 第２の記録層
６ 上部電極
７ パルス発生部
８ 抵抗測定部
９、１０ スイッチ
１１ メモリ
１２ 書き込み／読み出し装置
１３ 印加部
１６ 判定部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a phase change memory that stores information using a reversible phase change that occurs between a crystalline phase and an amorphous phase, a writing device that writes information to the memory, and information written to the memory. The present invention relates to a reading device and a method for reading.
[0002]
[Prior art]
2. Description of the Related Art A phase change memory capable of recording or erasing information by applying electric energy such as current is known. The material of the recording layer used for the phase change memory causes a reversible change between the crystalline phase and the amorphous phase due to the temperature rise caused by the application of electrical energy. Usually, the electrical resistance of the crystal phase is low, and the electrical resistance of the amorphous phase is high. A phase change memory is a non-volatile memory that records binary values by utilizing the difference in electrical resistance between the crystalline phase and the amorphous phase.
[0003]
In recent years, with an increase in the amount of information to be recorded in a memory, a memory having a larger capacity has been demanded. In order to increase the capacity of the phase change memory, (1) the area of the memory cell that records binary values is reduced and the memory cells are arranged in a matrix (improvement of surface density), or (2) one It has been proposed to store multivalued information in memory cells. In the present specification, multivalue refers to a number of values greater than two.
[0004]
[Problems to be solved by the invention]
In order to improve the surface density of (1), there is a limit to the miniaturization process in manufacturing technology such as photolithography, and the storage capacity of the phase change memory cannot be increased dramatically. As a technique for recording multi-value information in one memory cell of {circle around (2)}, a conventional technique disclosed in JP-T-11-510317 is known. In this prior art, multi-value information is stored in a memory cell by controlling the resistance value of one recording layer of the memory cell in a stepwise manner. However, it is very difficult to control the phase state of one recording layer step by step compared to controlling the two phase states of the crystalline phase and the amorphous phase.
[0005]
The present invention has been made in consideration of such problems, and is a phase change memory that stores multi-value information and is easy to write and read, a writing device that writes information to the phase change memory, and a phase change memory thereof. It is an object of the present invention to provide a reading apparatus and method for reading information written in a change memory.
[0006]
[Means for Solving the Problems]
The memory according to the present invention includes a first recording layer for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse, and a current pulse. And a second recording layer for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by the application of Recording layer crystallization temperature T _x1 And the crystallization temperature T of the second recording layer _x2 The relationship with T _x1 <T _x2 And the crystallization time t of the first recording layer _x1 And the crystallization time t of the second recording layer _x2 Is the relationship t _x1 > T _x2 And the resistance value when the first recording layer is in an amorphous phase is R _a1 , The resistance value when the first recording layer is in the crystalline phase is R _c1 The resistance value when the second recording layer is in an amorphous phase is R _a2 , The resistance value when the second recording layer is in the crystalline phase is R _c2 Then R _a1 + R _a2 , R _a1 + R _c2 , R _a2 + R _c1 , R _c1 + R _c2 Are different from each other, thereby achieving the above-mentioned object.
[0007]
Melting point T of the first recording layer _m1 Is the relationship 400 ≦ T _m1 (° C.) ≦ 800 may be satisfied.
[0008]
Melting point T of the second recording layer _m2 Is the relationship 300 ≦ T _m2 (° C.) ≦ 700 may be satisfied.
[0009]
The crystallization temperature T of the first recording layer _x1 Is the relation 130 ≦ T _x1 (° C.) ≦ 230 may be satisfied.
[0010]
The crystallization temperature T of the second recording layer _x2 Is the relationship 160 ≦ T _x2 (° C.) ≦ 260 may be satisfied.
[0011]
Crystallization time t of the first recording layer _x1 Is the relationship 5 ≦ t _x1 (Ns) ≦ 200 may be satisfied.
[0012]
Crystallization time t of the second recording layer _x2 Is the relationship 2 ≦ t _x2 (Ns) ≦ 150 may be satisfied.
[0013]
The first recording layer includes three elements of Ge, Sb, and Te, and the second recording layer includes (Sb-Te) -M1, where M1 is Ag, In, Ge, Sn. , Se, Bi, Au, and Mn may be selected.
[0014]
The first recording layer may be deposited on a substrate, and an upper electrode may be deposited on the second recording layer.
[0015]
A lower electrode may be deposited between the substrate and the first recording layer.
[0016]
An intermediate layer may be deposited between the first recording layer and the second recording layer.
[0017]
Specific resistance r when the first recording layer is in an amorphous phase _a1 Is 1.0 ≦ r _a1 (Ω · cm) ≦ 1 × 10 ⁷ It may be.
[0018]
Specific resistance r when the second recording layer is in an amorphous phase _a2 Is 2.0 ≦ r _a2 (Ω · cm) ≦ 2 × 10 ⁷ It may be.
[0019]
Specific resistance r when the first recording layer is in a crystalline phase _c1 Is 1 × 10 ^-3 ≦ r _c1 (Ω · cm) ≦ 1.0 may be sufficient.
[0020]
Specific resistance r when the second recording layer is in a crystalline phase _c2 Is 1 × 10 ^-3 ≦ r _c2 (Ω · cm) ≦ 1.0 may be sufficient.
[0021]
A writing device according to the present invention is a writing device for writing information into a memory, and the memory causes a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise due to application of a current pulse. A first recording layer for recording information by waking up and a first recording layer for recording information by causing a reversible phase change between the crystalline phase and the amorphous phase due to the temperature rise caused by application of a current pulse. A crystallization temperature T of the first recording layer. _x1 And the crystallization temperature T of the second recording layer _x2 The relationship with T _x1 <T _x2 And the crystallization time t of the first recording layer _x1 And the crystallization time t of the second recording layer _x2 Is the relationship t _x1 > T _x2 And the resistance value when the first recording layer is in an amorphous phase is R _a1 , The resistance value when the first recording layer is in the crystalline phase is R _c1 The resistance value when the second recording layer is in an amorphous phase is R _a2 , The resistance value when the second recording layer is in the crystalline phase is R _c2 Then R _a1 + R _a2 , R _a1 + R _c2 , R _a2 + R _c1 , R _c1 + R _c2 Are different from each other, and the writing device includes a pulse generator for generating at least first to third current pulses, and the at least first to third current pulses to the first recording layer and the second recording layer. The pulse generator is configured to change the phase of the first recording layer from an amorphous phase to a crystalline phase and maintain the phase state of the second recording layer. _x1 ≦ T <T _x2 Temperature T and t _x1 When the first current pulse corresponding to a time t of ≦ t is generated, the phase state of the first recording layer is maintained, and the phase of the second recording layer is changed from an amorphous phase to a crystalline phase T _x2 ≦ T T and t _x2 ≦ t <t _x1 When the second current pulse corresponding to the time t is generated to change the phase of the first recording layer and the second recording layer from the crystalline phase to the amorphous phase, the first and second The third current pulse corresponding to a temperature equal to or higher than the lower melting point of the two recording layers is generated, whereby the above-mentioned object is achieved.
[0022]
The amplitude I of the first current pulse _c1 And pulse width t _c1 Are each 0.02 ≦ I _c1 (MA) ≦ 10 and 5 ≦ t _c1 (Ns) ≦ 200 may be satisfied.
[0023]
The amplitude I of the second current pulse _c2 And pulse width t _c2 Respectively, 0.05 ≦ I _c2 (MA) ≦ 20 and 2 ≦ t _c2 (Ns) ≦ 150 may be satisfied.
[0024]
The amplitude I of the third current pulse _a1 And pulse width t _a1 Respectively, 0.1 ≦ I _a1 (MA) ≦ 200 and 1 ≦ t _a1 (Ns) ≦ 100 may be satisfied.
[0025]
The pulse generation unit is configured to change T when the first recording layer and the second recording layer are changed from an amorphous phase to a crystalline phase. _x2 ≦ T T and t _x1 A fourth current pulse corresponding to time t satisfying ≦ t may be generated.
[0026]
The amplitude I of the fourth current pulse _c12 And pulse width t _c12 Respectively, 0.05 ≦ I _c12 (MA) ≦ 20 and 5 ≦ t _c12 (Ns) ≦ 200 may be satisfied.
[0027]
The pulse generator has a melting point T of the first recording layer. _m1 And the melting point T of the second recording layer _m2 Relationship with T _m1 ≠ T _m2 And the melting point T _m1 Or T _m2 Of the recording layer having a lower melting point is changed from a crystalline phase to an amorphous phase, and the melting point T _m1 Or T _m2 When the recording layer having the higher melting point is maintained in the crystalline phase, a fifth current pulse corresponding to a temperature not lower than the lower melting point and lower than the higher melting point may be generated.
[0028]
The amplitude I of the fifth current pulse _a2 And pulse width t _a2 Are each 0.05 ≦ I _a2 (MA) ≦ 160 and 1 ≦ t _a2 (Ns) ≦ 100 may be satisfied.
[0029]
A reading device according to the present invention is a reading device that reads information written in a memory, and the memory is reversible between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse. The information is obtained by causing a reversible phase change between the first recording layer for recording information by causing a phase change and a temperature increase due to application of a current pulse between the crystalline phase and the amorphous phase. A second recording layer for recording, the crystallization temperature T of the first recording layer _x1 And the crystallization temperature T of the second recording layer _x2 The relationship with T _x1 <T _x2 And the crystallization time t of the first recording layer _x1 And the crystallization time t of the second recording layer _x2 Is the relationship t _x1 > T _x2 And the resistance value when the first recording layer is in an amorphous phase is R _a1 , The resistance value when the first recording layer is in the crystalline phase is R _c1 The resistance value when the second recording layer is in an amorphous phase is R _a2 , The resistance value when the second recording layer is in the crystalline phase is R _c2 Then R _a1 + R _a2 , R _a1 + R _c2 , R _a2 + R _c1 , R _c1 + R _c2 Are different from each other, and the reading device includes: an application unit that applies a current pulse to the first and second recording layers; a resistance measuring instrument that measures a sum of resistances of the first and second recording layers; A determination unit for determining which of the four different resistances matches the sum of the resistances, thereby achieving the object.
[0030]
The current pulse has an amplitude I having a magnitude that does not cause a phase change in the first and second recording layers. _r You may have.
[0031]
The amplitude I of the current pulse _r I _r (MA) ≦ 0.02 may be sufficient.
[0032]
The memory according to the present invention has N recording layers (N> 2) for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse. , N is a natural number), and the crystallization temperature of the m-th recording layer is T _xm If (1 ≦ m ≦ N), the crystallization temperature of each of the N recording layers is expressed by the relationship T _x1 <T _x2 <... <T _xm-1 <T _xm <T _{xm + 1} <... <T _xN And the crystallization time of the m-th recording layer is t _xm Then, the crystallization time of each of the N recording layers is expressed by the relationship t. _x1 > T _x2 >...> t _xm-1 > T _xm > T _{xm + 1} >...> t _xN And the resistance value when the recording layers of the N recording layers are in an amorphous phase and the resistance value when the recording layers of the N recording layers are in a crystalline phase are all different. The sum of the resistance of the recording layer is 2 ^N It takes a number of different values, thereby achieving the above objective.
[0033]
The writing device according to the present invention is a writing device for writing information into a memory, and the memory performs a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse. The memory includes N recording layers (N> 2, N is a natural number) for recording information by waking up, and the crystallization temperature of the mth recording layer is T _xm If (1 ≦ m ≦ N), the crystallization temperature of each of the N recording layers is expressed by the relationship T _x1 <T _x2 <... <T _xm-1 <T _xm <T _{xm + 1} <... <T _xN And the crystallization time of the m-th recording layer is t _xm Then, the crystallization time of each of the N recording layers is expressed by the relationship t. _x1 > T _x2 >...> t _xm-1 > T _xm > T _{xm + 1} >...> t _xN And the resistance value when the recording layers of the N recording layers are in an amorphous phase and the resistance value when the recording layers of the N recording layers are in a crystalline phase are all different. The sum of the resistance of the recording layer is 2 ^N The writing device has a pulse generator for generating at least N crystallization current pulses and an amorphization current pulse, and the at least N crystallization current pulses and an amorphization current. An application unit that applies a pulse to the N recording layers, wherein the pulse generation unit changes only the m-th recording layer from an amorphous phase to a crystalline phase, and the m-th recording layer When maintaining the phase state of the recording layer excluding _xm ≦ T _x <T _{x (m + 1)} Temperature T _x And t _xm ≦ t _x <T _{x (m-1)} Time t _x When a crystallization current pulse corresponding to is generated and all of the N recording layers change from a crystalline phase to an amorphous phase, a temperature equal to or higher than the highest melting point among the melting points of the N recording layers. The amorphizing current pulse corresponding to is generated, whereby the above object is achieved.
[0034]
The pulse generator may be configured to change T when all of the N recording layers are changed from an amorphous phase to a crystalline phase. _xN ≦ T _x Temperature T _x And t _x1 ≦ t _x Time t _x A current pulse corresponding to may be generated.
[0035]
The pulse generation unit is configured to change T from the mth recording layer to the (m + n−1) th recording layer of the N recording layers from an amorphous phase to a crystalline phase. _{x (m + n-1)} ≦ T _x <T _{x (m + n)} Temperature T _x And t _xm ≦ t _x <T _{x (m-1)} Time t _x A current pulse corresponding to may be generated.
[0036]
In the pulse generator, at least one of the N recording layers has a temperature T _m Each of the recording layers excluding the at least one recording layer of the N recording layers has a temperature T _m Having a higher melting point, changing each of the at least one recording layer from a crystalline phase to an amorphous phase, and maintaining the recording layer excluding each of the at least one recording layer in a crystalline phase, Temperature T _m A current pulse corresponding to may be generated.
[0037]
A reading device according to the present invention is a reading device that reads information written in a memory, and the memory is reversible between a crystalline phase and an amorphous phase due to a temperature rise due to application of a current pulse. A memory having N recording layers (N> 2, N is a natural number) for recording information by causing a phase change, wherein the crystallization temperature of the mth recording layer is T _xm If (1 ≦ m ≦ N), the crystallization temperature of each of the N recording layers is expressed by the relationship T _x1 <T _x2 <... <T _xm-1 <T _xm <T _{xm + 1} <... <T _xN And the crystallization time of the m-th recording layer is t _xm Then, the crystallization time of each of the N recording layers is expressed by the relationship t. _x1 > T _x2 >...> t _xm-1 > T _xm > T _{xm + 1} >...> t _xN And the resistance value when the recording layers of the N recording layers are in an amorphous phase and the resistance value when the recording layers of the N recording layers are in a crystalline phase are all different. The sum of the resistance of the recording layer is 2 ^N The readout device takes different values, and the reading device includes an application unit that applies a current pulse to the N recording layers, a resistance measuring device that measures a sum of resistances of the N recording layers, and a sum of the resistances. 2 ^N And a determination unit for determining which of the different resistances is the same, thereby achieving the above object.
[0038]
A writing method according to the present invention is a writing method for writing information into a memory, and the memory causes a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse. A first recording layer for recording information by waking up and a first recording layer for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse. A crystallization temperature T of the first recording layer. _x1 And the crystallization temperature T of the second recording layer _x2 The relationship with T _x1 <T _x2 And the crystallization time t of the first recording layer _x1 And the crystallization time t of the second recording layer _x2 Is the relationship t _x1 > T _x2 And the resistance value when the first recording layer is in an amorphous phase is R _a1 , The resistance value when the first recording layer is in the crystalline phase is R _c1 The resistance value when the second recording layer is in an amorphous phase is R _a2 , The resistance value when the second recording layer is in the crystalline phase is R _c2 Then R _a1 + R _a2 , R _a1 + R _c2 , R _a2 + R _c1 , R _c1 + R _c2 Are different from each other, and the writing method includes the steps of generating at least first to third current pulses and applying the at least first to third current pulses to the first recording layer and the second recording layer. The step of generating includes a step of changing the phase of the first recording layer from an amorphous phase to a crystalline phase and maintaining the phase state of the second recording layer. _x1 ≦ T <T _x2 Temperature T and t _x1 When the first current pulse corresponding to a time t of ≦ t is generated, the phase state of the first recording layer is maintained, and the phase of the second recording layer is changed from an amorphous phase to a crystalline phase T _x2 ≦ T T and t _x2 ≦ t <t _x1 When the second current pulse corresponding to the time t is generated to change the phase of the first recording layer and the second recording layer from the crystalline phase to the amorphous phase, the first and second And generating the third current pulse corresponding to a temperature equal to or higher than the lower melting point of the two recording layers, thereby achieving the above object.
[0039]
A reading method according to the present invention is a reading method for reading information written in a memory, and the memory is reversible between a crystalline phase and an amorphous phase due to a temperature rise due to application of a current pulse. The first recording layer that records information by causing a phase change, and the information by causing a reversible phase change between the crystalline phase and the amorphous phase due to a temperature rise due to application of a current pulse. A second recording layer for recording, the crystallization temperature T of the first recording layer _x1 And the crystallization temperature T of the second recording layer _x2 The relationship with T _x1 <T _x2 And the crystallization time t of the first recording layer _x1 And the crystallization time t of the second recording layer _x2 Is the relationship t _x1 > T _x2 And the resistance value when the first recording layer is in an amorphous phase is R _a1 , The resistance value when the first recording layer is in the crystalline phase is R _c1 The resistance value when the second recording layer is in an amorphous phase is R _a2 , The resistance value when the second recording layer is in the crystalline phase is R _c2 Then R _a1 + R _a2 , R _a1 + R _c2 , R _a2 + R _c1 , R _c1 + R _c2 Are different from each other, and the reading method includes a step of applying a current pulse to the first and second recording layers, a step of measuring a sum of resistances of the first and second recording layers, and a sum of the resistances. Determining which one of the four different resistances matches, thereby achieving the above object.
[0040]
A writing method according to the present invention is a writing method for writing information into a memory, and the memory causes a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse. The memory includes N recording layers (N> 2, N is a natural number) for recording information by waking up, and the crystallization temperature of the mth recording layer is T _xm If (1 ≦ m ≦ N), the crystallization temperature of each of the N recording layers is expressed by the relationship T _x1 <T _x2 <... <T _xm-1 <T _xm <T _{xm + 1} <... <T _xN And the crystallization time of the m-th recording layer is t _xm Then, the crystallization time of each of the N recording layers is expressed by the relationship t. _x1 > T _x2 >...> t _xm-1 > T _xm > T _{xm + 1} >...> t _xN And the resistance value when the recording layers of the N recording layers are in an amorphous phase and the resistance value when the recording layers of the N recording layers are in a crystalline phase are all different. The sum of the resistance of the recording layer is 2 ^N The writing method takes at least N crystallization current pulses and an amorphization current pulse, and includes at least N crystallization current pulses and an amorphization current pulse. Applying to the N recording layers, wherein the generating step changes the phase of only the m-th recording layer from an amorphous phase to a crystalline phase and removes the m-th recording layer. To maintain the phase state of the layer, T _xm ≦ T _x <T _{x (m + 1)} Temperature T _x And t _xm ≦ t _x <T _{x (m-1)} Time t _x When the crystallization current pulse corresponding to is generated and all the N recording layers are phase-changed from the crystalline phase to the amorphous phase, the temperature equal to or higher than the highest melting point among the melting points of the N recording layers. The amorphization current pulse corresponding to the above is generated, and the above object is achieved.
[0041]
A reading method according to the present invention is a reading method for reading information written in a memory, and the memory is reversible between a crystalline phase and an amorphous phase due to a temperature rise due to application of a current pulse. A memory having N recording layers (N> 2, N is a natural number) for recording information by causing a phase change, wherein the crystallization temperature of the mth recording layer is T _xm If (1 ≦ m ≦ N), the crystallization temperature of each of the N recording layers is expressed by the relationship T _x1 <T _x2 <... <T _xm-1 <T _xm <T _{xm + 1} <... <T _xN And the crystallization time of the m-th recording layer is t _xm Then, the crystallization time of each of the N recording layers is expressed by the relationship t. _x1 > T _x2 >...> t _xm-1 > T _xm > T _{xm + 1} >...> t _xN And the resistance value when the recording layers of the N recording layers are in an amorphous phase and the resistance value when the recording layers of the N recording layers are in a crystalline phase are all different. The sum of the resistance of the recording layer is 2 ^N Taking the different values, the reading method includes applying a current pulse to the N recording layers, measuring a sum of resistances of the N recording layers, and adding the resistances to the 2 ^N Determining which of the different resistance sums is met, thereby achieving the above objective.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 1 shows a configuration of a writing / reading device connected to a memory according to the present invention. The writing / reading device 12 writes information in the memory 11 or reads information written in the memory 11.
[0043]
The writing / reading device 12 includes a pulse generator 7 that generates current pulses, a resistance measuring unit 8 that measures the resistance of the memory 11, switches 9 and 10, and current pulses generated by the pulse generator 7. And a determination unit 16 that determines the resistance value of the memory 11 measured by the resistance measurement unit 8.
[0044]
The memory 11 includes a substrate 1, a lower electrode 2 deposited on the substrate 1, a first recording layer 3 deposited on the lower electrode 2, and an intermediate layer 4 deposited on the first recording layer 3. And a second recording layer 5 deposited on the intermediate layer 4 and an upper electrode 6 deposited on the second recording layer 5.
[0045]
As the substrate 1, for example, a resin plate such as polycarbonate, a glass plate, alumina (Al ₂ O _Three ), Etc., various metal plates such as Si plate, Cu and the like can be used, but are not limited thereto. In the first embodiment, a Si substrate is used as the substrate 1. As the lower electrode 2 and the upper electrode 6, for example, a single metal material such as Al, Au, Ag, Cu, Pt, Ti, W, or a combination thereof (alloy material) can be used. Any electrode material capable of applying electric energy to the third and second recording layers 5 can be used. The intermediate layer 4 is provided to prevent atoms constituting each recording layer from diffusing between the first recording layer 3 and the second recording layer 5. The intermediate layer 4 is preferably conductive. For example, single metal materials such as Al, Au, Ag, Cu, Pt, Ti, and W, and combinations (alloy materials) thereof can be used, but are not limited thereto. . In the first embodiment, Pt is used for the lower electrode 2, the intermediate layer 4, and the upper electrode 6.
[0046]
Instead of the lower electrode 2 and / or the upper electrode 6, any configuration that can apply a current pulse to the first recording layer 3 and the second recording layer 5 can be adopted. For example, when the substrate 1 is conductive, the lower electrode 2 can be omitted. The intermediate layer 4 may be omitted when the materials of the first recording layer 3 and the second recording layer 5 are such that atoms do not diffuse between each other.
[0047]
The materials of the first recording layer 3 and the second recording layer 5 cause a reversible phase change between the crystalline phase and the amorphous phase due to a temperature rise caused by application of electric energy such as a current pulse. It is a material to wake up. The materials of the first recording layer 3 and the second recording layer 5 are selected so as to satisfy the following conditions 1 to 3.
[0048]
Condition 1: the crystallization temperature T of the first recording layer 3 _x1 And the crystallization temperature T of the second recording layer 5 _x2 The relationship is T _x1 <T _x2 Meet. In this specification, the crystallization temperature refers to a temperature at which the recording layer material changes from an amorphous phase to a crystalline phase.
[0049]
Condition 2: Crystallization time t of the first recording layer 3 _x1 And the crystallization time t of the second recording layer 5 _x2 Is the relationship t _x1 > T _x2 Meet. In this specification, the crystallization time refers to the time required for the recording layer material to change from an amorphous phase to a crystalline phase.
[0050]
Condition 3: When the first recording layer 3 is in an amorphous phase, the resistance value is R _a1 The resistance value when the first recording layer 3 is in the crystalline phase is R _c1 , The resistance value when the second recording layer 5 is in an amorphous phase is R _a2 The resistance value when the second recording layer 5 is in the crystalline phase is R _c2 Then R _a1 + R _a2 , R _a1 + R _c2 , R _c1 + R _a2 , R _c1 + R _c2 Are different from each other.
[0051]
By satisfying Condition 1 and Condition 2, the phase state of the first recording layer 3 and the phase state of the second recording layer 5 are set to desired states (amorphous phase or crystalline phase), respectively. Is possible. Furthermore, when the condition 3 is satisfied, the four states that are combinations of the phase state of the first recording layer 3 and the phase state of the second recording layer 5 can be distinguished and detected. Therefore, the first recording layer 3 and the second recording layer 5 of the memory 11 can carry four-value (2-bit) information corresponding to the four states. Since each recording layer only needs to be controlled between the crystalline phase and the amorphous phase, the control is easier than controlling the phase state of one recording layer stepwise.
[0052]
The crystallization temperature T of the first recording layer 3 _x1 Is preferably 130 ≦ T _x1 (° C.) ≦ 230. The crystallization temperature T of the second recording layer 5 _x2 Is preferably 160 ≦ T _x2 (° C.) ≦ 260. Crystallization time t of the first recording layer 3 _x1 Is preferably 5 ≦ t _x1 (Ns) ≦ 200. Crystallization time t of the second recording layer 5 _x2 Is preferably 3 ≦ t _x2 (Ns) ≦ 150. Specific resistance r when the first recording layer 3 is in an amorphous phase _a1 Is preferably 1.0 ≦ r _a1 (Ω · cm) ≦ 1 × 10 ⁷ It is. Specific resistance r when second recording layer 5 is in an amorphous phase _a2 Is preferably 2.0 ≦ r _a2 (Ω · cm) ≦ 2 × 10 ⁷ It is. Specific resistance r when the first recording layer 3 is a crystalline phase _c1 Is preferably 1 × 10 ^-3 ≦ r _c1 (Ω · cm) ≦ 1.0. Specific resistance r when second recording layer 5 is in a crystalline phase _c2 Is preferably 1 × 10 ^-3 ≦ r _c2 (Ω · cm) ≦ 1.0. The melting point T of the first recording layer 3 and the second recording layer 5 in the first embodiment. _m1 , T _m2 The relationship is T _m1 > T _m2 However, the relationship between these melting points may be arbitrary. In the first embodiment, the melting points T of the first recording layer 3 and the second recording layer 5 _m1 , T _m2 Are 630 ° C. and 550 ° C., respectively. Melting point T of the first recording layer 3 _m1 Is preferably 400 ≦ T _m1 (° C.) ≦ 800. Melting point T of the second recording layer 5 _m2 Is preferably 300 ≦ T _m2 (° C.) ≦ 700.
[0053]
The first recording layer 3 contains three elements of Ge, Sb, and Te. The second recording layer 5 includes a material system represented by (Sb-Te) -M1, where M1 is at least 1 from the group consisting of Ag, In, Ge, Sn, Se, Bi, Au, and Mn. Is selected. In the first embodiment, each of the first recording layer 3 and the second recording layer 5 has Ge. ₈ Sb ₂ Te ₁₁ And (Sb _0.7 Te _0.3 ) ₉₅ Ge _Five Was used.
[0054]
The crystallization temperature T of the first recording layer 3 and the second recording layer 5 used in the first embodiment _x1 , T _x2 Were 170 ° C. and 200 ° C., respectively. Crystallization time t of the first recording layer 3 and the second recording layer 5 _x1 , T _x2 Were 130 ns and 80 ns, respectively.
[0055]
In the first embodiment, the Pt lower electrode 2 has an area of 10 μm × 10 μm and a thickness of 0.1 μm, and the Ge of the first recording layer 3 ₈ Sb ₂ Te ₁₁ Is an area of 5 μm × 5 μm and a thickness of 0.1 μm, and the Pt intermediate layer 4 has an area of 5 μm × 5 μm and a thickness of 0.1 μm. _0.7 Te _0.3 ) ₉₅ Ge _Five The area was 5 μm × 5 μm and the thickness was 0.1 μm, and the Pt upper electrode 6 was area 5 μm × 5 μm and the thickness was 0.1 μm. In this configuration, the resistance value R when the first recording layer 3 and the second recording layer 5 are in the amorphous phase. _a1 , R _a2 Were 1000Ω and 1500Ω, respectively. Resistance value R when first recording layer 3 and second recording layer 5 are in a crystalline phase _c1 , R _c2 Were 5Ω and 10Ω, respectively.
[0056]
As shown in Table 1, the memory 11 has four different states, state 1 to state 4. State 1 to state 4 are combinations of the respective phase states (amorphous phase and crystalline phase) of the first recording layer 3 and the second recording layer 5. Table 1 shows the sum of the phase states and resistances of the first recording layer 3 and the second recording layer 5 in the states 1 to 4 that the memory 11 can take.
[0057]
[Table 1]

When both the first recording layer 3 and the second recording layer 5 are in an amorphous phase (state 1), the sum of the resistance of the first recording layer 3 and the resistance of the second recording layer 5 is R _a1 + R _a2 It becomes. When the first recording layer 3 is in a crystalline phase and the second recording layer 5 is in an amorphous phase (state 2), the sum of the resistance of the first recording layer 3 and the resistance of the second recording layer 5 Is R _c1 + R _a2 It becomes. When the first recording layer 3 is in an amorphous phase and the second recording layer 5 is in a crystalline phase (state 3), the sum of the resistance of the first recording layer 3 and the resistance of the second recording layer 5 Is R _a1 + R _c2 It becomes. When both the first recording layer 3 and the second recording layer 5 are in a crystalline phase (state 4), the sum of the resistance of the first recording layer 3 and the resistance of the second recording layer 5 is R _c1 + R _c2 It becomes. As described above, the sum of the resistances is different in the states 1 to 4.
[0058]
Next, the manufacturing procedure of the memory 11 will be described in the following steps S1101 to S1106.
[0059]
S1101: A substrate 1 having a treated surface is prepared in a sputtering apparatus.
[0060]
S1102: The lower electrode 2 is deposited by sputtering a single metal target such as Al, Au, Ag, Cu, Pt, Ti, W or an alloy metal target thereof in an Ar gas atmosphere.
[0061]
S1103: An alloy target containing three elements of Ge, Sb, and Te is used in an Ar gas atmosphere, a Kr gas atmosphere, a mixed gas atmosphere of Ar gas and a reactive gas containing at least one of oxygen gas and nitrogen gas, and Kr gas. The first recording layer 3 is deposited on the lower electrode 2 by sputtering in an atmosphere selected from the group consisting of a mixed gas atmosphere of reactive gas and reactive gas.
[0062]
S1104: The intermediate layer 4 is deposited on the first recording layer 3 by sputtering a single metal target such as Al, Au, Ag, Cu, Pt, Ti, W or an alloy metal target thereof in an Ar gas atmosphere. The
[0063]
S1105: an alloy including a material system represented by (Sb-Te) -M1 (where M1 is selected from the group consisting of Ag, In, Ge, Sn, Se, Bi, Au, and Mn) The target is selected from the group consisting of an Ar gas atmosphere, a Kr gas atmosphere, a mixed gas atmosphere of Ar gas and a reactive gas containing at least one of oxygen gas and nitrogen gas, and a mixed gas atmosphere of Kr gas and reactive gas The second recording layer 5 is deposited on the intermediate layer 4 by sputtering in an atmosphere to be used.
[0064]
S1106: The upper electrode 6 is formed on the second recording layer 5 by sputtering a single metal target such as Al, Au, Ag, Cu, Pt, Ti, W or an alloy metal target thereof in an Ar gas atmosphere. The
[0065]
In steps S1101 to S1106 of the manufacturing procedure described above, a sputtering apparatus was used to deposit the lower electrode 2, the first recording layer 3, the intermediate layer 4, the second recording layer 5, and the upper electrode 6. Any thin film deposition apparatus capable of depositing can be used. In the first embodiment, the surface of the Si substrate 1 is nitrided in a nitrogen atmosphere in step S1101. An Au lead wire was bonded to each of the lower electrode 2 and the upper electrode 6 thus fabricated, and connected to the read / write device 12 via the application unit 13.
[0066]
Next, a method for writing information in the memory 11 and a method for erasing information written in the memory 11 will be described. When writing and erasing information in the memory 11, the switch 9 is closed and the switch 10 is opened. The pulse generator 7 generates a current pulse having an amplitude and a pulse width necessary for changing the phase state of the first recording layer 3 and the second recording layer 5 to a desired phase state. The current pulse generated by the pulse generator 7 is applied to the first recording layer 3 and the second recording layer 5 via the application unit 13.
[0067]
FIG. 2 is a state transition diagram regarding the phase states of the first recording layer 3 and the second recording layer 5.
[0068]
In the first embodiment, from state 1 to state 2, state 1 to state 3, state 1 to state 4, state 2 to state 3, state 2 to state 4, state 3 to state 2, and state 3 shown in Table 1 The operation of changing from state 4 to state 4, state 4 to state 2 and state 4 to state 3 is called writing. On the other hand, the operation of changing from state 2 to state 1, from state 3 to state 1 and from state 4 to state 1 is called erasure. By changing the phase state of the first recording layer 3 and the second recording layer 5 to a desired phase state, information is written in the memory 11 or information written in the memory 11 is erased.
[0069]
Hereinafter, a method for writing and / or erasing information in the memory 11 will be described for each step with reference to FIG.
[0070]
Step S1: When the state 1 is changed to the state 2 or the state 3 is changed to the state 4, that is, the phase of the second recording layer 5 is changed by changing the phase of the first recording layer 3 from the amorphous phase to the crystalline phase. 1 is maintained, the pulse generator 7 (FIG. 1) generates a first current pulse, and the first current pulse is applied to the first recording layer 3 and the first recording layer via the application unit 13 (FIG. 1). 2 is applied to the second recording layer 5. The first current pulse is T _x1 ≦ T <T _x2 Temperature T and t _x1 A current pulse corresponding to a time t of <t. An example of a specific waveform of the current pulse will be described later with reference to FIG.
[0071]
Step S2: When the state 1 is changed to the state 3 or the state 2 is changed to the state 4, that is, the phase state of the first recording layer is maintained, and the second recording layer 5 is changed from the amorphous phase to the crystalline phase. When the phase is changed, the pulse generator 7 generates a second current pulse, and applies the second current pulse to the first recording layer 3 and the second recording layer 5 via the applying unit 13. . The second current pulse is T _x2 ≦ T T and t _x2 ≦ t <t _x1 Is a current pulse corresponding to the time t.
[0072]
Step S3: When changing the state 4 to the state 1, that is, when changing the phase of the first recording layer 3 and the second recording layer 5 from the crystalline phase to the amorphous phase, the pulse generator 7 3 current pulses are generated, and the third current pulse is applied to the first recording layer 3 and the second recording layer 5 via the applying unit 13. The third current pulse is a current pulse corresponding to a temperature equal to or higher than the lower melting point of the melting points of the first recording layer 3 and the second recording layer 5.
[0073]
Step S4: When the state 1 is changed to the state 4, that is, when the first recording layer 3 and the second recording layer 5 are changed from the amorphous phase to the crystalline phase, the pulse generator 7 4 current pulses are generated, and the fourth current pulse is applied to the first recording layer 3 and the second recording layer 5 via the applying unit 13. The fourth current pulse is T _x2 ≦ T T and t _x1 ≦ t is a current pulse corresponding to time t. Note that step S4 is not an essential step. This is because step S4 can be replaced by performing step S2 and then step S1, or step S1 and then step S2. In FIG. 2, in order to indicate that the step S4 is not an essential step, an arrow indicating a state transition corresponding to the step S4 is indicated by a broken line.
[0074]
Step S5: Respective melting points T of the first recording layer 3 and the second recording layer 5 _m1 , T _m2 But T _m1 > T _m2 When the condition 4 is satisfied and the state 4 is changed to the state 2, that is, the first recording layer 3 is maintained in the crystalline phase and the second recording layer 5 is changed from the crystalline phase to the amorphous phase. The generation unit 7 generates a fifth current pulse and applies the fifth current pulse to the first recording layer 3 and the second recording layer 5 via the application unit 13. The fifth current pulse is T _m2 ≦ T <T _m1 This is a current pulse corresponding to the temperature T. Step S5 is not an essential step. This is because step S5 can be replaced by performing step S3 and then step S1. In FIG. 2, in order to show that step S5 is not an essential step, the state transition corresponding to step S5 is indicated by a broken line. Each melting point T of the first recording layer 3 and the second recording layer 5 _m1 , T _m2 But T _m1 <T _m2 T if _m1 ≦ T <T _m2 The state 4 can be changed to the state 3 by applying a fifth current pulse corresponding to the temperature T to the first recording layer 3 and the second recording layer 5.
[0075]
If there are only the above-described steps S1 to S3, the phase states of the first recording layer 3 and the second recording layer 5 can be changed from an arbitrary state of the state 1 to the state 4 to an arbitrary state. For example, when changing the state 2 to the state 1, the steps S2 and S3 may be performed. When the state 3 is changed to the state 1, the steps S1 and S3 may be performed. When the state 2 is changed to the state 3, the step S2, the step S3, and then the step S2 may be performed. When changing the state 3 to the state 2, the steps S1, S3, and then the step S1 may be performed. When the state 4 is changed to the state 3, the step S3 and then the step S2 may be performed.
[0076]
When the current phase states of the first recording layer 3 and the second recording layer 5 are known, the first recording layer 3 and the second recording layer 5 can be obtained by combining the above steps. The phase can be changed to a phase state. The current phase state (initial state) can be known by using the reading method described with reference to FIG. Note that the phase state of the first recording layer 3 and the second recording layer 5 changes from the arbitrary state to the state 4 by performing step S2 and then step S1, or step S1 and then step S2. Using the state 4 thus obtained as an initial state, the phase states of the first recording layer 3 and the second recording layer 5 may be changed to a desired phase state. Thereby, the reading procedure is omitted. The state that can be used as the initial state is not limited to state 4.
[0077]
Next, the waveform of a current pulse for changing to each state will be described.
[0078]
FIG. 3 shows waveforms of various current pulses for changing the phase state of the two recording layers. The pulse generator 7 shown in FIG. 1 generates current pulses having various pulse amplitudes (applied current values) and various pulse widths (current application time).
[0079]
First current pulse 21: As described with reference to FIG. 2, the first current pulse 21 is generated when the first recording layer 3 and the second recording layer 3 are changed when the state 1 is changed to the state 2 or the state 3 is changed to the state 4. Current pulse applied to the recording layer 5. By applying the first current pulse 21 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 rise in temperature, and t _x1 ≦ t during time t _x1 ≦ T <T _x2 The temperature T becomes In the first embodiment, the pulse amplitude I of the first current pulse 21 _c1 And pulse width t _c1 Were set to 2 mA and 150 ns, respectively. Pulse amplitude I _c1 And pulse width t _c1 Are preferably 0.02 ≦ I _c1 (MA) ≦ 10 and 5 ≦ t _c1 (Ns) ≦ 200. By applying the first current pulse 21 to the first recording layer 3 and the second recording layer 5, only the first recording layer 3 has a crystallization temperature T _x1 And crystallization time t _x1 Thus, the first recording layer 3 changes from an amorphous phase to a crystalline phase, and the second recording layer 5 maintains the current phase state.
[0080]
Thus, T _x1 ≦ T <T _x2 Temperature T and t _x1 By applying a first current pulse 21 corresponding to a time t of ≦ t to the first recording layer 3 and the second recording layer 5, the phase of the first recording layer 3 changes from an amorphous phase to a crystalline phase. Thus, the phase state of the second recording layer 5 can be maintained.
[0081]
Second current pulse 22: The second current pulse 22 is applied to the first recording layer 3 and the second recording layer 5 when the state 1 is changed to the state 3 or the state 2 is changed to the state 4. Current pulse. By applying the second current pulse 22 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 rise in temperature, and t _x2 ≦ t <t _x1 For time t _x2 The temperature T becomes ≦ T. In the first embodiment, the pulse amplitude I of the second current pulse 22 _c2 And pulse width t _c2 Were set to 4 mA and 100 ns, respectively. Pulse amplitude I _c2 And pulse width t _c2 Are preferably 0.05 ≦ I respectively. _c2 (MA) ≦ 20 and 2 ≦ t _c2 (Ns) ≦ 150. By applying such a second current pulse 22 to the first recording layer 3 and the second recording layer 5, only the second recording layer 5 has a crystallization temperature T. _x2 And crystallization time t _x2 The first recording layer 3 maintains the current phase state, and the second recording layer 5 changes from an amorphous phase to a crystalline phase.
[0082]
Thus, T _x2 ≦ T T and t _x2 ≦ t <t _x1 By applying a second current pulse 22 corresponding to time t to the first recording layer 3 and the second recording layer 5, the phase state of the first recording layer is maintained, and the second recording layer is The phase can be changed from an amorphous phase to a crystalline phase.
[0083]
Third current pulse 23: The third current pulse 23 is a current pulse applied to the first recording layer 3 and the second recording layer 5 when the state 4 is changed to the state 1. By applying the third current pulse 23 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 rise in temperature, and both recording layers The temperature T is equal to or higher than the lower melting point. In the first embodiment, the pulse amplitude I of the third current pulse 23 _a1 And pulse width t _a1 Were set to 50 mA and 50 ns, respectively. Pulse amplitude I _a1 And pulse width t _a1 Are preferably 0.1 ≦ I respectively _a1 (MA) ≦ 200 and 1 ≦ t _a1 (Ns) ≦ 100. By applying the third current pulse 23 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 are not lower. Melting point (T in Embodiment 1) _m1 = 630 ° C.) or higher, and after being melted together, they are rapidly cooled. As a result, both the first recording layer 3 and the second recording layer 5 change from a crystalline phase to an amorphous phase. Pulse amplitude I of the third current pulse 23 _a1 Is the current value I required to change the phase of the first recording layer 3 and the second recording layer 5 from the amorphous phase to the crystalline phase. _c1 , I _c2 Big compared to. This is due to the crystallization temperature T of the first recording layer 3 and the second recording layer 5. _x1 , T _x2 Higher temperature (T _m1 = 630 ° C.).
[0084]
In this way, the third current pulse 23 corresponding to a temperature equal to or higher than the lower melting point of the melting points of the first recording layer 3 and the second recording layer 5 is applied to the first recording layer 3 and the second recording layer 5. By applying to the layer 5, the first recording layer 3 and the second recording layer 5 can be phase-changed from the crystalline phase to the amorphous phase.
[0085]
The first to third current pulses 21 to 23 are indispensable current pulses when information is written using the writing / reading device 12. By combining these first to third current pulses 21 to 23, the memory 11 can be changed from an arbitrary state to another arbitrary state.
[0086]
Fourth current pulse 24: The fourth current pulse 24 is a current pulse applied to the first recording layer 3 and the second recording layer 5 when the state 1 is changed to the state 4. By applying the fourth current pulse 24 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 rise in temperature, and t _x1 ≦ t during time t _x2 The temperature T becomes ≦ T. Pulse amplitude I of the fourth current pulse 24 _c12 And pulse width t _c12 Respectively, the pulse amplitude I of the second current pulse 22 _c2 And the pulse width t of the first current pulse 21 _c1 be equivalent to. In the first embodiment, the pulse amplitude I of the fourth current pulse 24 _c12 And pulse width t _c12 Are each 4 mA (= I _c2 ) And 150 ns (= t _c1 ) Was set. Pulse amplitude I _c12 And pulse width t _c12 Are preferably 0.05 ≦ I respectively. _c12 (MA) ≦ 20 and 5 ≦ t _c12 (Ns) ≦ 200. By applying such a fourth current pulse 24 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 are crystallized in the higher direction. Temperature T _x2 And the longer crystallization time t _x1 Thus, both the first recording layer 3 and the second recording layer 5 change from an amorphous phase to a crystalline phase.
[0087]
Thus, T _x2 ≦ T T and t _x1 By applying a fourth current pulse 24 corresponding to a time t of ≦ t to the first recording layer 3 and the second recording layer 5, the first recording layer 3 and the second recording layer 5 are made amorphous. The phase can be changed from a solid phase to a crystalline phase.
[0088]
As described above, the fourth current pulse 24 is not an essential current pulse. This is because the first current pulse 21 and the second current pulse 22 can be substituted for the fourth current pulse 24. However, applying the fourth current pulse 24 to the memory 11 is shorter than the state 1 to the state 4 compared to applying the first current pulse 21 and the second current pulse 22 to the memory 11. It has the advantage that it can be changed over time.
[0089]
Fifth current pulse 25: The fifth current pulse 25 is the melting point T of the first recording layer 3. _m1 And the melting point T of the second recording layer 5 _m2 Relationship is T _m1 > T _m2 These are current pulses applied to the first recording layer 3 and the second recording layer 5 when the state 4 is changed to the state 2. By applying the fifth current pulse 25 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 rise in temperature, and T _m2 ≦ T <T _m1 The temperature T becomes Pulse amplitude I of the fifth current pulse 25 _a2 And pulse width t _a2 Were set to 30 mA and 50 ns, respectively. Pulse amplitude I _a2 And pulse width t _a2 Are preferably 0.05 ≦ I respectively. _a2 (MA) ≦ 160 and 1 ≦ t _a2 (Ns) ≦ 100. By applying such a fifth current pulse 25 to the first recording layer 3 and the second recording layer 5, the first recording layer 3 and the second recording layer 5 become the first recording layer 3. The melting point of the second recording layer 5 (T 1 in the first embodiment) is not reached. _m2 = 550 ° C.) or higher. Accordingly, the first recording layer 3 maintains the crystalline phase, and only the second recording layer 5 is melted and rapidly cooled to change the phase from the crystalline phase to the amorphous phase. The fifth current pulse 25 is the melting point T of the first recording layer 3. _m1 And the melting point T of the second recording layer 5 _m2 Relationship is T _m1 <T _m2 , It can be used to change state 4 to state 3.
[0090]
Thus, the melting point T of the first recording layer 3 _m1 And the melting point T of the second recording layer 5 _m2 Relationship with T _m1 ≠ T _m2 In this case, the fifth current pulse 25 corresponding to a temperature higher than the lower melting point and lower than the higher melting point is applied to the first recording layer 3 and the second recording layer 5, whereby the lower melting point is applied. The recording layer having the melting point can be changed from the crystalline phase to the amorphous phase, and the recording layer having the higher melting point can be maintained in the crystalline phase.
[0091]
As described above, the fifth current pulse 25 is useful when the melting points of the first recording layer 3 and the second recording layer 5 are different, but is not an essential current pulse. This is because the third current pulse 23 (or the second current pulse 22) and the first current pulse 21 can be substituted for the fifth current pulse. However, applying the fifth current pulse 25 to the memory 11 is different from applying the third current pulse 23 (or the second current pulse 22) and the first current pulse 21 to the memory 11. The state 4 can be changed to the state 2 (or the state 3) in a shorter time.
[0092]
Next, the current pulses 26 to 33 obtained by combining at least two of the first to fifth current pulses 21 to 25 will be described.
[0093]
Current pulse 26: The current pulse 26 is a current pulse in which the third current pulse 23 and the first current pulse 21 are combined. When changing state 4 to state 2, the current pulse 26 can be used in place of the fifth current pulse 25. By applying the current pulse 26 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 rise in temperature, and t _x1 ≦ t During time t, both recording layers are melted at a temperature T equal to or higher than the lower melting point of the recording layers, and then rapidly cooled. _x1 ≦ T <T _x2 The temperature T becomes The current pulse 26 has an amplitude I _a1 (In the first embodiment, I _a1 = 50 mA) followed by amplitude I _c1 (In the first embodiment, I _c1 = 2 mA) t in total _c1 (In the first embodiment, t _c1 = 150 ns).
[0094]
As described above, the current pulse 26 is not an essential current pulse. This is because the fifth current pulse 25 can be substituted for the current pulse 26. However, compared to applying the fifth current pulse 25 to the memory 11, applying the current pulse 26 to the memory 11 is when the melting points of the first recording layer 3 and the second recording layer 5 are equal. Even so, there is an advantage that the state 4 can be changed to the state 2.
[0095]
Thus, not less than the lower melting point of both recording layers, then T _x1 ≦ T <T _x2 The temperature T _x1 By applying a current pulse 26 corresponding to a time t of <t to the first recording layer 3 and the second recording layer 5, the first recording layer 3 and the second recording layer 5 are separated from the crystalline phase. After the phase change to the crystalline phase, the first recording layer 3 can be changed from the amorphous phase to the crystalline phase, and the second recording layer 5 can be maintained in the amorphous phase. That is, the memory 11 changes from the state 4 to the state 2 via the state 1.
[0096]
Current pulse 27: The current pulse 27 is a current pulse obtained by combining the third current pulse 23 and the second current pulse 22. When changing the state 4 to the state 3, the current pulse 27 is used. By applying the current pulse 27 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 rise in temperature, and t _x2 ≦ t <t _x1 During this time t, the recording layer is melted at a temperature T equal to or higher than the lower melting point of both recording layers. Then it was quenched and T _x2 The temperature T becomes ≦ T. The current pulse 27 has an amplitude I _a1 Followed by amplitude I _c2 (In the first embodiment, I _c2 = 4 mA) Overall t _c2 (In the first embodiment, t _c2 = 100 ns).
[0097]
Thus, not less than the lower melting point of both recording layers, then T _x2 ≦ T is the temperature T as a whole t _x2 ≦ t <t _x1 By applying a current pulse 27 corresponding to the time t to the first recording layer 3 and the second recording layer 5, the first recording layer 3 and the second recording layer are changed from the crystalline phase to the amorphous phase. After the phase change, the first recording layer 3 can be maintained in an amorphous phase, and the second recording layer 5 can be changed from an amorphous phase to a crystalline phase. That is, the memory 11 changes from the state 4 to the state 3 through the state 1.
[0098]
Current pulse 28: The current pulse 28 is a current pulse in which the first current pulse 21 and the third current pulse 23 are combined. When changing the state 3 to the state 1, the current pulse 28 is used. By applying the current pulse 28 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 rise in temperature, and t _x1 ≦ t during time t _x1 ≦ T <T _x2 And then the temperature T is equal to or higher than the lower melting point of both recording layers. The current pulse 28 has an amplitude I _c1 , Pulse width t _c1 Followed by amplitude I _a1 , Pulse width t _a1 (In the first embodiment, t _a1 = 50 ns).
[0099]
Thus, T _x1 ≦ T <T _x2 Temperature T and t _x1 ≦ t, then the current pulse 28 corresponding to a temperature not lower than the lower melting point of the melting points of the first recording layer 3 and the second recording layer 5 is applied to the first recording layer 3 and the second recording layer. By applying to the layer 5, the first recording layer 3 is changed from an amorphous phase to a crystalline phase, the second recording layer 5 is maintained in the crystalline phase, and then the crystalline phases of both recording layers are made non-crystalline. The phase can be changed to a crystalline phase. That is, the state of the memory 11 changes from the state 3 to the state 1 via the state 4.
[0100]
Current pulse 29: The current pulse 29 is a current pulse in which the second current pulse 22 and the third current pulse 23 are combined. When changing the state 2 to the state 1, the current pulse 29 is used. By applying the current pulse 29 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 rise in temperature, and t _x2 ≦ t <t _x1 For time t _x2 ≦ T, and then the temperature T is equal to or higher than the lower melting point of both recording layers. The current pulse 29 has an amplitude I _c2 , Pulse width t _c2 Followed by amplitude I _a1 , Pulse width t _a1 Was set to be.
[0101]
Thus, T _x2 ≦ T T and t _x2 ≦ t <t _x1 Current pulse 29 corresponding to a temperature equal to or higher than the lower melting point of the melting points of the first recording layer 3 and the second recording layer 5 and then the first recording layer 3 and the second recording layer 5. To maintain the first recording layer 3 in the crystalline phase, change the second recording layer 5 from the amorphous phase to the crystalline phase, and then change the crystalline phase of both recording layers to the amorphous phase. The phase can be changed. That is, the state of the memory 11 changes from the state 2 to the state 1 via the state 4.
[0102]
Current pulse 30: The current pulse 30 is a current pulse obtained by combining the fourth current pulse and the third current pulse. Current pulse 30 is used when changing state 2 or state 3 to state 1. The current pulse 30 can be used in place of the current pulse 28 and the current pulse 29. By applying the current pulse 30 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 rise in temperature, and t _x1 ≦ t during time t _x2 ≦ T, and then the temperature T is equal to or higher than the lower melting point of both recording layers. The current pulse 30 has an amplitude I _c2 , Pulse width t _c1 Followed by amplitude I _a1 , Pulse width t _a1 Was set to be.
[0103]
Thus, T _x2 ≦ T T and t _x1 ≦ t, then a current pulse 30 corresponding to a temperature equal to or higher than the lower melting point of the melting points of the first recording layer 3 and the second recording layer 5 is applied to the first recording layer 3 and the second recording layer. By applying to the layer 5, the first recording layer 3 and the second recording layer 5 can be in either the crystalline phase or the amorphous phase, regardless of whether the first recording layer 3 and the second recording layer 5 are in the crystalline phase or the amorphous phase. Both recording layers 5 of the recording layer 5 can be changed to a crystalline phase, and then the crystalline phases of both recording layers can be changed to an amorphous phase. That is, the state of the memory 11 changes from the state 2 or the state 3 to the state 1 via the state 4.
[0104]
Current pulse 31: The current pulse 31 is a current pulse obtained by combining the second current pulse 22 and the current pulse 27 (combination of the third current pulse 23 and the second current pulse 22). When changing the state 2 to the state 3, the current pulse 31 is used. By applying the current pulse 31 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 rise in temperature, and t _x2 ≦ t <t _x1 For time t _x2 ≦ T, temperature T, then t _x2 ≦ t <t _x1 During the time t, the temperature T becomes equal to or higher than the lower melting point of both recording layers, and then rapidly cooled, _x2 The temperature T becomes ≦ T. The current pulse 31 has an amplitude I _c2 , Pulse width t _c2 Then amplitude I _a1 , Amplitude I _c2 Overall t _c2 Was set to be.
[0105]
Thus, T _x2 ≦ T T and t _x2 ≦ t <t _x1 Time t, then t _x2 ≦ t <t _x1 For a time t, a temperature T above the lower melting point of both recording layers T and then T _x2 By applying a current pulse 31 corresponding to a temperature T of ≦ T to the first recording layer 3 and the second recording layer 5, the first recording layer 3 is maintained in a crystalline phase, and the second recording layer 5 Is changed from an amorphous phase to a crystalline phase, and then the first recording layer 3 and the second recording layer 5 are changed from a crystalline phase to an amorphous phase. Thereafter, the first recording layer 3 can be maintained in an amorphous phase, and the second recording layer 5 can be changed from an amorphous phase to a crystalline phase. That is, the state of the memory 11 changes from the state 2 to the state 4 and then the state 1 to the state 3.
[0106]
Current pulse 32: The current pulse 32 is a current pulse in which the first current pulse 21 and the fifth current pulse 25 are combined. When changing the state 3 to the state 2, the current pulse 32 is used. By applying the current pulse 32 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 rise in temperature, and t _x1 ≦ t during time t _x1 ≦ T <T _x2 Temperature T, then T _m2 The temperature T becomes The current pulse 32 has an amplitude I _c1 , Pulse width t _c1 Then amplitude I _a2 (In the first embodiment, I _a2 = 30 mA), pulse width t _a2 (In the first embodiment, t _a2 = 50 ns).
[0107]
Thus, T _x1 ≦ T <T _x2 Temperature T and t _x1 ≦ t t, then T _m2 By applying a current pulse 32 corresponding to the temperature T to the first recording layer 3 and the second recording layer 5, the first recording layer 3 is changed in phase from the amorphous phase to the crystalline phase. The recording layer 5 can be maintained in the crystalline phase, the first recording layer 3 can be maintained in the crystalline phase, and the second recording layer 5 can be changed from the crystalline phase to the amorphous phase. That is, the state of the memory 11 changes from the state 3 to the state 2 via the state 4.
[0108]
Current pulse 33: The current pulse 33 is a current pulse obtained by combining the first current pulse 21 and the current pulse 26 (combination of the third current pulse 23 and the first current pulse 21). When changing state 3 to state 2, current pulse 33 may be used instead of current pulse 32. By applying the current pulse 33 to the first recording layer 3 and the second recording layer 5, both the first recording layer 3 and the second recording layer 5 rise in temperature, and t _x1 ≦ t during time t _x1 ≦ T <T _x2 Temperature T and then t _x1 ≦ t During time t, both recording layers are melted at a temperature T equal to or higher than the lower melting point of the recording layers, and then rapidly cooled. _x1 ≦ T <T _x2 The temperature T becomes The current pulse 33 has an amplitude I _c1 , Pulse width t _c1 Then amplitude I _a1 , Amplitude I _c1 Overall t _c1 Was set to be.
[0109]
Thus, T _x1 ≦ T <T _x2 Temperature T and t _x1 ≦ t, the time t, then the lower melting point of both recording layers, then T _x1 ≦ T <T _x2 The temperature T _x1 By applying a current pulse 33 corresponding to a time t of ≦ t to the first recording layer 3 and the second recording layer 5, the first recording layer 3 is changed in phase from an amorphous phase to a crystalline phase, The second recording layer 5 is maintained in the crystalline phase, and then the first recording layer 3 and the second recording layer 5 are phase-changed from the crystalline phase to the amorphous phase. Thereafter, the first recording layer 3 can be changed in phase from the amorphous phase to the crystalline phase, and the second recording layer 5 can be maintained in the amorphous phase. That is, the state of the memory 11 changes from the state 3 to the state 4 and then the state 1 to the state 2.
[0110]
In the current pulses 28 to 33, the memory 11 once changes to a desired state via the state 4. This is because when one of the first recording layer 3 and the second recording layer 5 is in an amorphous phase (high resistance state), most of the electric energy of the applied current pulse is amorphous. This is because it is consumed in the recording layer that is a phase, so that the electrical energy required to change the phase of only the other crystal phase (low resistance state) to the amorphous phase cannot be applied to the recording layer that is the crystal phase. Therefore, the current pulses 28 to 33 are set so that both recording layers are once changed into a crystalline phase and then both recording layers are changed into an amorphous phase.
[0111]
According to the writing / reading device 12 of the present invention, the phase state of the first recording layer 3 and the second recording layer 5 can be changed between a crystalline phase and an amorphous state by using three current pulses and a combination of three current pulses. It is possible to change the phase from an arbitrary phase state of the first recording layer 3 and the second recording layer 5 to a desired phase state by controlling between them and the quality phase.
[0112]
Next, a method for reading the information written in the memory 11 will be described. When reading the information written in the memory 11, the switch 10 shown in FIG. 1 is closed, and the writing / reading device 12 is connected to the memory 11 via the application unit 13. The resistance measuring unit 8 applies a current pulse I to the first recording layer 3 and the second recording layer 5. _r Is applied, and the resistance values of the first recording layer 3 and the second recording layer 5 (based on the potential difference generated between the lower electrode 2 (FIG. 1) and the upper electrode 6 (FIG. 1) ( The sum of the resistance value of the first recording layer 3 and the resistance value of the second recording layer 5 is detected. Current pulse I _r Instead of being generated by the resistance measuring unit 8, the pulse generating unit 7 may be generated. In this case, the switch 9 is closed. Current pulse I _r Has an amplitude and a pulse width of such a magnitude that the phase change of the first recording layer 3 and the second recording layer 5 does not occur. Current pulse I _r Is preferably I _r (MA) ≦ 0.02.
[0113]
FIG. 4 is a flowchart illustrating a method of reading information written in the memory 11 using a writing / reading device according to the present invention. Hereinafter, a method of reading information written in the memory 11 will be described for each step with reference to FIG.
[0114]
Step 401: Current pulse I is applied to the first recording layer 3 and the second recording layer 5. _r Is applied via the application unit 13.
[0115]
Step 402: The resistance measurement unit 8 measures the sum of the resistances of the first recording layer 3 and the second recording layer 5.
[0116]
Step 403: The determination unit 16 determines whether the sum of the measured resistances coincides with the sum of the resistances of the first recording layer 3 and the second recording layer 5 in any of the states 1 to 4. Thereby, the information written in the memory 11 is read.
[0117]
In the example described with reference to FIGS. 2 and 4, the writing / reading device 12 has been described as having both writing and reading functions. However, the writing / reading device 12 may be configured to perform only one of writing (and erasing) and reading. When the writing / reading device 12 performs only writing (and erasing), the resistance measuring device 8 and the determination unit 16 can be omitted. In this case, the writing / reading device 12 functions as a device for writing (and erasing) information to the memory 11. When the writing / reading device 12 performs only reading, the pulse generator 7 may be omitted. The switches 9 and 10 for the writing / reading device 12 to switch between writing (and erasing) and reading functions may be switched manually or based on a command given from the outside of the writing / reading device 12. In addition, a control unit that controls the switches 9 and 10 may be provided.
[0118]
In the example shown in FIG. 1, only one memory 11 is used. However, a configuration in which a plurality of memories 11 are arranged in a matrix may be employed.
[0119]
FIG. 5 shows a configuration of a storage device in which memories of the present invention are arranged in a matrix and an external circuit connected to the storage device. The same components as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0120]
External circuit 54 includes a pulse generation unit 7, a resistance measurement unit 8, switches 9 and 10, a determination unit 16, and a control unit 51. The storage device 58 includes an application unit 13 including a row decoder and a column decoder, a bit line 52, a word line 53, and a memory array 55 including a plurality of memories 11.
[0121]
The control unit 51 sends control information such as a command indicating whether to perform a write operation or a read operation to the pulse generation unit 7 and the resistance measurement unit 8 via the line 56, respectively. Each of the pulse generation unit 7 and the resistance measurement unit 8 opens and closes the switch 9 and the switch 10 according to the received control information, and performs a write operation or a read operation. The control unit 51 also sends address information indicating to which memory 11 of the memory array 55 the current pulse is applied to the application unit 13 via the line 57.
[0122]
The row decoder and column decoder of the application unit 13 specify the word line 53 and the bit line 52 of the memory 11 specified by the received address information, respectively. Next, a current pulse is applied to the designated memory 11, and a write operation or a read operation is performed.
[0123]
As shown in FIG. 5, the memory capacity of the storage device can be increased by arranging the memories 11 of FIG. 1 in a matrix.
[0124]
(Embodiment 2)
In the first embodiment, the case where there are two recording layers constituting the memory 11 has been described. However, the number of recording layers constituting the memory 11 is not limited to two. In the second embodiment, the case where the recording layers constituting the memory are N layers (N> 2, N is a natural number) will be described.
[0125]
FIG. 6 shows a memory 60 composed of N recording layers 62. The same components as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. The memory 60 includes a substrate 1, a lower electrode 2, first to (N−1) th intermediate layers 61, N recording layers 62, and an upper electrode 6.
[0126]
As in the case of the intermediate layer 4 in FIG. 1, the first to (N−1) -th intermediate layers 61 are provided to prevent the atoms constituting each recording layer from diffusing between the N recording layers 62. The first to (N-1) -th N-1 intermediate layers 61 are preferably conductive, and include single metal materials such as Al, Au, Ag, Cu, Pt, Ti, and W, and combinations (alloy materials) thereof. However, it is not limited to these.
[0127]
Instead of the lower electrode 2 and / or the upper electrode 6, any configuration that can apply a current pulse to the N recording layers 62 can be adopted. For example, when the substrate 1 is conductive, the lower electrode 2 can be omitted. The first to (N-1) th (N−1) -th intermediate layers 61 may be omitted if the materials of the N recording layers 62 are such that atoms do not diffuse between each other.
[0128]
Each of the N recording layers 62 is made of a material that causes a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of electrical energy such as a current pulse. The materials of the N recording layers 62 are selected so as to satisfy the following conditions 1 to 3.
[0129]
Condition 1: The crystallization temperature T of the mth (1 ≦ m ≦ N) recording layer among the N recording layers 62 _xm Is the relationship T _x1 <T _x2 <... <T _xm-1 <T _xm <T _{xm + 1} <... <T _xN Meet.
[0130]
Condition 2: Of the N recording layers 62, the crystallization time t of the m-th recording layer _xm Is the relationship t _x1 > T _x2 >...> t _xm-1 > T _xm > T _{xm + 1} >...> t _xN Meet.
[0131]
Condition 3: The resistance values when the recording layers of the N recording layers are in an amorphous phase and the resistance values when the recording layers of the N recording layers are in a crystalline phase are all different, and the N recording layers The sum of resistance is 2 ^N Takes different values.
[0132]
By satisfying Condition 1 and Condition 2, it is possible to set the phase state of each of the N recording layers 62 to a desired state (amorphous phase or crystalline phase). Further, when the condition 3 is satisfied, 2 is a combination of the respective phase states of the N recording layers 62. ^N It is possible to distinguish and detect individual states. 2 ^N 2 corresponding to each state ^N Value (ie, N bits) information can be carried. Since each recording layer only needs to be controlled between the crystalline phase and the amorphous phase, the control is easier than controlling the phase state of one recording layer stepwise.
[0133]
The memory 60 configured in this way is used instead of the memory 11 shown in FIG. The writing / reading device 12 shown in FIG. 1 is used for writing information to the memory 60 and reading information written to the memory 60.
[0134]
Each of the N recording layers 62 is in an amorphous phase or a crystalline phase, so that the memory 60 has 2 ^N Take one of the states. State 1 is a state in which all N recording layers 62 are in an amorphous phase. State 2 ^N Is a state in which all of the N recording layers 62 are in a crystalline phase. The operation of changing from state 1 to an arbitrary state is called writing. On the other hand, an operation for changing from any state except state 1 to state 1 is called erasing. By changing the phase state of the N recording layers 62 to a desired phase state, information is written in the memory 60 and / or information written in the memory 60 is erased.
[0135]
Next, a method for writing information in the memory 60 or erasing the information written in the memory 60 will be described.
[0136]
When writing and erasing information in the memory 60, the switch 9 is closed and the switch 10 is opened. The pulse generator 7 generates a current pulse having an amplitude and a pulse width necessary for changing the phase state of the N recording layers 62 to a desired phase state. The current pulse is applied to the N recording layers 62 through the application unit 13.
[0137]
FIG. 7 shows waveforms of various current pulses for changing the phase state of the N recording layers 62.
[0138]
Current pulse (crystallization current pulse) 70: The crystallization current pulse 70 is a current pulse applied to the N recording layers 62 when only the m-th recording layer is changed from an amorphous phase to a crystalline phase. It is. There is a crystallization current pulse for each m where 1 ≦ m ≦ N. By applying the crystallization current pulse 70 to the N recording layers 62, the temperature of all the N recording layers 62 increases, and t _xm ≦ t _x <T _{x (m-1)} Time t _x T _xm ≦ T _x <T _{x (m + 1)} Temperature T _x become. Amplitude I _cm And pulse width t _cm Is applied to the N recording layers 62, so that only the m-th recording layer has a crystallization temperature T of the m-th recording layer. _xm And crystallization time t _xm To achieve a phase change from an amorphous phase to a crystalline phase.
[0139]
Thus, T _xm ≦ T _x <T _{x (m + 1)} Temperature T _x And t _xm ≦ t _x <T _{x (m-1)} Time t _x Is applied to the N recording layers 62 through the applying unit 13 to change only the m-th recording layer from the amorphous phase to the crystalline phase, and thereby the m-th recording layer. The phase state of the recording layer excluding the layer can be maintained. Note that the above-described relationship t _xm ≦ t _x <T _{x (m-1)} Is the relationship t if m = 1. _x1 ≦ t _x It can be read as If m = N, the relationship T _xm ≦ T _x <T _{x (m + 1)} T _xN ≦ T _x It can be read as
[0140]
Current pulse (amorphization current pulse) 71: The amorphization current pulse 71 changes the state of the memory 60 to the state 2 ^N In this case, the current pulse is applied to the N recording layers 62 when the state is changed to the state 1. By applying the amorphizing current pulse 71 to the N recording layers 62, all of the N recording layers 62 rise in temperature, and the temperature is equal to or higher than the highest melting point among the melting points of the N recording layers 62. become. Amplitude I _{aN + 1} And pulse width t _{aN + 1} Is applied to the N recording layers 62 so that all of the N recording layers 62 have a melting point T _m1 Is achieved and melted. Then, it is rapidly cooled to change the phase from the crystalline phase to the amorphous phase.
[0141]
In this way, by applying an amorphizing current pulse 71 corresponding to a temperature equal to or higher than the highest melting point among the melting points of the N recording layers to the N recording layers 62 via the applying unit 13, All of the recording layer 62 can be changed from a crystalline phase to an amorphous phase.
[0142]
By sequentially applying a crystallization current pulse 70 for each of the recording layers in the amorphous phase among the N recording layers 62 to the memory 60, the memory 60 in an arbitrary state is set in the state 2. ^N Can be changed. State 2 ^N The memory 60 can be changed to the state 1 by applying the amorphizing current pulse 71 to the memory 60 in FIG. Further, by sequentially applying to the memory 60 in the state 1 a crystallization current pulse 70 for one or more recording layers of the N recording layers 62 that are desired to change into a crystalline phase, The memory 60 can be changed from state 1 to any state. Thus, by using the crystallization current pulse 70 and / or the amorphization current pulse 71 alone or in combination, 2 ^N The memory 60 in any state among the individual states can be changed to any other state.
[0143]
Current pulse 72: The current pulse 72 is generated when the mth recording layer to the (m + n−1) th recording layer among the N recording layers 62 is changed from an amorphous phase to a crystalline phase. This is a current pulse applied to the recording layer 62 via the applying unit 13. By applying the current pulse 72 to the N recording layers 62, all of the N recording layers 62 increase in temperature, and t _xm ≦ t _x <T _{x (m-1)} Time t _x T _{x (m + n-1)} ≦ T _x <T _{x (m + n)} Temperature T _x become. Amplitude I _{c (m + n-1)} And pulse width t _cm Is applied to the N recording layers 62, so that the mth to (m + n−1) th recording layers have a crystallization temperature T. _{x (m + n-1)} And crystallization time t _xm To achieve a phase change from an amorphous phase to a crystalline phase.
[0144]
Thus, T _{x (m + n-1)} ≦ T _x <T _{x (m + n)} Temperature T _x And t _xm ≦ t _x <T _{x (m-1)} Time t _x Is applied to the N recording layers 62 via the applying unit 13, so that the mth to (m + n−1) th recording layers of the N recording layers 62 are converted into an amorphous phase. To a crystalline phase.
[0145]
The current pulse 72 is not an essential current pulse. This is because the m-th to (m + n−1) th recording layers can also be changed from the amorphous phase to the crystalline phase by sequentially applying the crystallization current pulse 70 to the memory 60. However, as compared with the sequential application of the crystallization current pulse 70 to the memory 60, the application of the current pulse 72 to the memory 60 reduces the m-th to (m + n-1) recording layers in a shorter time. This has the advantage that the phase can be changed from the crystalline phase to the crystalline phase.
[0146]
Current pulse 73: Current pulse 73 changes state 1 to state 2 ^N In this case, the current pulse is applied to the N recording layers 62 via the applying unit 13. By applying the current pulse 73 to the N recording layers 62, all of the N recording layers 62 increase in temperature, and t _x1 ≦ t _x Time t _x T _xN ≦ T _x Temperature T _x become. Amplitude I _cN And pulse width t _c1 Is applied to the N recording layers 62 so that all of the N recording layers 62 have a crystallization temperature T _xN And crystallization time t _x1 To achieve a phase change from an amorphous phase to a crystalline phase.
[0147]
Thus, T _xN ≦ T _x Temperature T _x And t _x1 ≦ t _x Time t _x Is applied to the N recording layers 62, so that all of the N recording layers 62 can be changed from an amorphous phase to a crystalline phase.
[0148]
The current pulse 73 is not an essential current pulse. This is because all of the N recording layers 62 can also be changed from the amorphous phase to the crystalline phase by sequentially applying the crystallization current pulse 70 to the memory 60. However, applying current pulse 73 to memory 60 as compared to sequentially applying crystallization current pulse 70 to memory 60 can cause state 1 to state 2 ^N This has the advantage that it can be changed in a short time.
[0149]
Current pulse 74: The current pulse 74 is a combination of the current pulse 73 and the amorphizing current pulse 71. Such a current pulse 74 is such that at least one recording layer of the N recording layers 62 is in an amorphous phase and the N recordings are made via the application unit 13 when the memory 60 is changed to the state 1. A current pulse applied to the layer 62. By applying the current pulse 74 to the N recording layers 62, all of the N recording layers 62 increase in temperature, and t _x1 ≦ t _x Time t _x T _x ≧ T _xN Temperature T _x Then, the temperature of the melting point of the N recording layers 62 is the highest. Amplitude I _cN And pulse width t _c1 Then amplitude I _{aN + 1} And pulse width t _{aN + 1} Is applied to the N recording layers 62 so that all of the N recording layers 62 have a crystallization temperature T _xN And crystallization time t _x1 To achieve a phase change from an amorphous phase to a crystalline phase. Next, all of the N recording layers 62 reach the highest melting point among the melting points of the N recording layers 62 and are melted and rapidly cooled to change from a crystalline phase to an amorphous phase.
[0150]
The current pulse 74 is not an essential current pulse. This is because the crystallization current pulse 70 is sequentially applied to the memory 60 so that the N recording layers 62 are in the state 2. ^N And then applying an amorphizing current pulse 71 to the memory 60, state 2 ^N This is because the state can be changed from state to state 1. However, applying the current pulse 74 to the memory 60 as compared to applying the crystallization current pulse 70 sequentially to the memory 60 and applying the amorphization current pulse 71 is the state 2 ^N It has the advantage that it can be changed in a short time by state 1 from any state except for.
[0151]
Current pulse 75: The current pulse 75 indicates that at least one of the N recording layers 62 has a temperature T _m Each of the recording layers except for at least one of the N recording layers has a temperature T _m N in the case where each of the at least one recording layer is changed from a crystalline phase to an amorphous phase and the recording layers excluding each of the at least one recording layer are maintained in the crystalline phase. This is a current pulse applied to the recording layer 62. By applying the current pulse 75 to the N recording layers 62, the temperature of all the N recording layers 62 increases, and each of the at least one recording layer has a temperature T _m It becomes. Amplitude I _cm And pulse width t _am Is applied to the N recording layers 62 so that the temperature T _m Only each of the at least one recording layer having the melting point _m To achieve a phase change from a crystalline phase to an amorphous phase.
[0152]
Temperature T _m Can be arbitrarily selected so as to be equal to or higher than the lowest melting point of the N recording layers 62 and lower than the highest melting point of the N recording layers 62. Thus, the temperature T _m To select the N recording layers 62 at the temperature T _m A low melting point group consisting of at least one recording layer having the following melting point and a temperature T _m It can be divided into a high melting point group consisting of at least one recording layer having a higher melting point. Temperature T _m Is applied to the N recording layers 62, each of the recording layers included in the low melting point group can be phase-changed from the crystalline phase to the amorphous phase.
[0153]
The current pulse 75 is useful when the N recording layers 62 have different melting points, but is not an essential current pulse. This is because, by sequentially applying the amorphizing current pulse 71 and the crystallization current pulse 70 to the memory 60 instead of the current pulse 75, only the desired recording layer of the N recording layers 62 is made into a crystalline phase. This is because it can be changed. However, applying the current pulse 75 to the memory 60 compared to applying the amorphizing current pulse 71 and the crystallization current pulse 70 to the memory 60 causes the memory 60 to record N recordings in a shorter time. Of the layers 62, only the desired recording layer can be changed into a crystalline phase.
[0154]
When the current phase state of the N recording layers 62 is known, the N recording layers 62 are formed in a desired phase by combining the crystallization current pulse 70 and the amorphization current pulse 71. The phase can be changed to a state. The current phase state (initial state) can be known by using the reading method described with reference to FIG. In addition, by sequentially applying the crystallization current pulse 70 for each of m = 1 to N to the memory 60 (or by applying the current pulse 73 to the memory 60), the state of the memory 60 is an arbitrary state. From state 2 ^N To change. State 2 obtained in this way ^N May be used as an initial state to change the phase state of the N recording layers 62 to a desired phase state. Thereby, the reading procedure is omitted. The state that can be used as the initial state is state 2 ^N It is not limited to.
[0155]
Next, a method for reading the information written in the memory 60 will be described. The reading method is the same as the reading method described in Embodiment 1 with reference to FIG. When reading the information written in the memory 60, the switch 10 shown in FIG. 1 is closed, and the writing / reading device 12 is connected to the memory 60 via the application unit 13. The resistance measuring unit 8 applies the current pulse I to the N recording layers 62. _r And the resistance values of the N recording layers 62 (the resistances of the N recording layers 62 are determined based on the potential difference generated between the lower electrode 2 (FIG. 1) and the upper electrode 6 (FIG. 1). The sum of each resistance value) is detected. Current pulse I _r The N recording layers 62 have such an amplitude and pulse width that the phase does not change.
[0156]
FIG. 8 is a flowchart illustrating a method for reading information written in the memory 60 using the writing / reading device 12 according to the present invention. Hereinafter, a method of reading information written in the memory 60 will be described with reference to FIG.
[0157]
Step 801: Current pulses I are applied to N recording layers 62. _r Is applied via the application unit 13.
[0158]
Step 802: The resistance measuring unit 8 measures the sum of the resistances of the N recording layers 62.
[0159]
Step 803: The determination unit 16 determines that the sum of the measured resistances is in the state 1-2. ^N Which of the states of the N recording layers 62 is in agreement with the sum of the resistances. Thereby, the information written in the memory 60 is read.
[0160]
It is also possible to increase the storage capacity of the storage device by arranging the memory 60 of FIG. 6 in a matrix as shown in FIG.
[0161]
In the memory 60 of FIG. 6, N recording layers 62 are deposited in the order of the first to Nth recording layers. However, the first to Nth recording layers may be deposited in an arbitrary order (for example, a random order).
[0162]
【The invention's effect】
The memory according to the present invention includes a first recording layer that records information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse, and a current pulse. And a second recording layer for recording information by causing a reversible phase change between the crystalline phase and the amorphous phase due to the temperature rise caused by the application of. Crystallization temperature T of the first recording layer _x1 And the crystallization temperature T of the second recording layer _x2 The relationship with T _x1 <T _x2 And the crystallization time t of the first recording layer _x1 And the crystallization time t of the second recording layer _x2 Is the relationship t _x1 > T _x2 Therefore, the phase state of the first recording layer and the phase state of the second recording layer can be set to desired states (amorphous phase or crystalline phase), respectively. Further, the resistance value when the first recording layer is in an amorphous phase is set to R _a1 , The resistance value when the first recording layer is in the crystalline phase is R _c1 The resistance value when the second recording layer is in an amorphous phase is R _a2 The resistance value when the second recording layer is in the crystalline phase is R _c2 Then R _a1 + R _a2 , R _a1 + R _c2 , R _a2 + R _c1 , R _c1 + R _c2 Since these are different from each other, four states, which are combinations of the phase state of the first recording layer and the phase state of the second recording layer, can be distinguished and detected. Since the phase states of the first recording layer and the second recording layer are only controlled between the crystalline phase and the amorphous phase, the control is easy. Note that such a memory is not limited to two recording layers, and the same effect can be obtained when more than two recording layers are used.
[Brief description of the drawings]
FIG. 1 shows a configuration of a writing / reading device connected to a memory according to the present invention.
FIG. 2 is a state transition diagram regarding the phase states of the first recording layer and the second recording layer.
FIG. 3 shows waveforms of various current pulses for changing the phase state of two recording layers.
FIG. 4 is a flowchart illustrating a method of reading information written in a memory using a writing / reading device according to the present invention.
FIG. 5 shows a configuration of a storage device in which memories of the present invention are arranged in a matrix and an external circuit connected to the storage device.
FIG. 6 is a diagram showing a memory composed of N recording layers.
FIG. 7 is a diagram showing waveforms of various current pulses for changing the phase state of N recording layers.
FIG. 8 is a flowchart illustrating a method of reading information written in a memory using a writing / reading device according to the present invention.
[Explanation of symbols]
1 Substrate
2 Lower electrode
3 First recording layer
4 Middle layer
5 Second recording layer
6 Upper electrode
7 Pulse generator
8 Resistance measurement unit
9, 10 switch
11 memory
12 Writing / reading device
13 Application section
16 Judgment part

Claims (36)

A first recording layer for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature increase due to application of a current pulse, and a temperature increase due to application of a current pulse. A memory comprising a second recording layer for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase,
Relationship between the crystallization temperature T _x2 of the second recording layer and the crystallization temperature T _x1 of the first recording layer is a T _x1 <T _x2,
The relationship between the crystallization time t _x2 of the first recording layer crystallization time t _x1 and the second recording layer is a t _x1> t _x2,
The resistance value when the first recording layer is in an amorphous phase is R _a1 , the resistance value when the first recording layer is in a crystalline phase is R _c1 , and the second recording layer is in an amorphous phase. the resistance value R _a2 when, when the second recording layer is the resistance value in the case of the crystalline phase and the _{R c2, R a1 + R a2} , R a1 + R c2, R a2 + R c1, R c1 + R c2 are different from each other ,memory. 2. The memory according to claim 1, wherein the melting point T _m1 of the first recording layer satisfies the relationship 400 ≦ T _m1 (° C.) ≦ 800. 2. The memory according to claim 1, wherein the melting point T _m2 of the second recording layer satisfies the relationship 300 ≦ T _m2 (° C.) ≦ 700. 2. The memory according to claim 1, wherein the crystallization temperature T _x1 of the first recording layer satisfies the relationship 130 ≦ T _x1 (° C.) ≦ 230. 2. The memory according to claim 1, wherein the crystallization temperature T _x2 of the second recording layer satisfies the relationship 160 ≦ T _x2 (° C.) ≦ 260. The memory according to claim 1, wherein the crystallization time t _x1 of the first recording layer satisfies the relationship 5 ≦ t _x1 (ns) ≦ 200. 2. The memory according to claim 1, wherein the crystallization time t _x2 of the second recording layer satisfies the relationship 2 ≦ t _x2 (ns) ≦ 150. The first recording layer includes three elements of Ge, Sb, and Te, and the second recording layer includes (Sb-Te) -M1, where M1 is Ag, In, Ge, Sn. The memory of claim 1, wherein at least one is selected from the group consisting of: Se, Bi, Au, and Mn. The memory of claim 1, wherein the first recording layer is deposited on a substrate and an upper electrode is deposited on the second recording layer. The memory of claim 9, wherein a lower electrode is deposited between the substrate and the first recording layer. The memory of claim 1, wherein an intermediate layer is deposited between the first recording layer and the second recording layer. 2. The memory according to claim 1, wherein a specific resistance r _a1 when the first recording layer is in an amorphous phase is 1.0 ≦ r _a1 (Ω · cm) ≦ 1 × 10 ⁷ . 2. The memory according to claim 1, wherein a specific resistance r _a2 when the second recording layer is in an amorphous phase is 2.0 ≦ r _a2 (Ω · cm) ≦ 2 × 10 ⁷ . 2. The memory according to claim 1, wherein a specific resistance r _c1 when the first recording layer is in a crystalline phase is 1 × 10 ⁻³ ≦ r _c1 (Ω · cm) ≦ 1.0. 2. The memory according to claim 1, wherein a specific resistance r _c2 when the second recording layer is in a crystalline phase is 1 × 10 ⁻³ ≦ r _c2 (Ω · cm) ≦ 1.0. A writing device for writing information to a memory,
The memory is
A first recording layer for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse;
A memory comprising: a second recording layer for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse;
Relationship between the crystallization temperature T _x2 of the second recording layer and the crystallization temperature T _x1 of the first recording layer is a T _x1 <T _x2,
The relationship between the crystallization time t _x2 of the first recording layer crystallization time t _x1 and the second recording layer is a t _x1> t _x2,
The resistance value when the first recording layer is in an amorphous phase is R _a1 , the resistance value when the first recording layer is in a crystalline phase is R _c1 , and the second recording layer is in an amorphous phase. the resistance value R _a2 when, when the second recording layer is the resistance value in the case of the crystalline phase and the R _c2, unlike _{R a1 + R a2, R a1} + R c2, R a2 + R c1, R c1 + R c2 are mutually ,
The writing device includes:
A pulse generator for generating at least first to third current pulses;
An application unit that applies the at least first to third current pulses to the first recording layer and the second recording layer, and the pulse generation unit includes:
When the phase of the first recording layer is changed from the amorphous phase to the crystalline phase and the phase state of the second recording layer is maintained, the temperature T and T _x1 ≦ t _satisfy T _x1 ≦ T <T _x2. Generating the first current pulse corresponding to time t;
When maintaining the phase state of the first recording layer and changing the phase of the second recording layer from an amorphous phase to a crystalline phase, a temperature T _satisfying T _x2 ≦ T and t _x2 ≦ t <t _x1 Generating the second current pulse corresponding to time t,
When changing the phase of the first recording layer and the second recording layer from a crystalline phase to an amorphous phase, a temperature equal to or higher than the lower melting point of the melting points of the first and second recording layers. A writing device for generating the third current pulse corresponding to _17. The writing device according to claim 16, wherein an amplitude I _c1 and a pulse width t _c1 of the first current pulse _satisfy 0.02 ≦ I _c1 (mA) ≦ 10 and 5 ≦ t _c1 (ns) ≦ 200, respectively. . _17. The writing device according to claim 16, wherein an amplitude I _c2 and a pulse width t _c2 of the second current pulse _satisfy 0.05 ≦ I _c2 (mA) ≦ 20 and 2 ≦ t _c2 (ns) ≦ 150, respectively. . 17. The writing device according to claim 16, wherein an amplitude I _a1 and a pulse width t _a1 of the third current pulse are 0.1 ≦ I _a1 (mA) ≦ 200 and 1 ≦ t _a1 (ns) ≦ 100, respectively. . The pulse generation unit is configured to change the temperature of T _x2 ≦ T and the time t of t _x1 ≦ t when the first recording layer and the second recording layer are changed from an amorphous phase to a crystalline phase. The writing device according to claim 16, wherein the writing device generates a corresponding fourth current pulse. _21. The writing device according to claim 20, wherein the amplitude I _c12 and the pulse width t _c12 of the fourth current pulse are 0.05 ≦ I _c12 (mA) ≦ 20 and 5 ≦ t _c12 (ns) ≦ 200, respectively. . In the pulse generator, the relationship between the melting point T _m1 of the first recording layer and the melting point T _m2 of the second recording layer is T _m1 ≠ T _m2 , which is lower than the melting point T _m1 or T _m2. When the recording layer having the higher melting point is changed from the crystalline phase to the amorphous phase and the recording layer having the higher melting point of the melting points T _m1 or T _m2 is maintained in the crystalline phase, the lower one is used. The writing device according to claim 16, wherein a fifth current pulse corresponding to a temperature equal to or higher than the melting point and lower than the higher melting point is generated. 23. The writing device according to claim 22, wherein an amplitude I _a2 and a pulse width t _{a2 of} the fifth current pulse are 0.05 ≦ I _a2 (mA) ≦ 160 and 1 ≦ t _a2 (ns) ≦ 100, respectively. . A reading device for reading information written in a memory,
The memory is
A first recording layer for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse;
A memory comprising: a second recording layer for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse;
Relationship between the crystallization temperature T _x2 of the second recording layer and the crystallization temperature T _x1 of the first recording layer is a T _x1 <T _x2,
The relationship between the crystallization time t _x2 of the first recording layer crystallization time t _x1 and the second recording layer is a t _x1> t _x2,
The resistance value when the first recording layer is in an amorphous phase is R _a1 , the resistance value when the first recording layer is in a crystalline phase is R _c1 , and the second recording layer is in an amorphous phase. the resistance value R _a2 when, when the second recording layer is the resistance value in the case of the crystalline phase and the R _c2, unlike _{R a1 + R a2, R a1} + R c2, R a2 + R c1, R c1 + R c2 are mutually ,
The reading device includes:
An application unit for applying a current pulse to the first and second recording layers;
A resistance measuring instrument for measuring a sum of resistances of the first and second recording layers;
And a determination unit that determines which of the four different resistances matches the sum of the resistances. The current pulse has an amplitude I _r of the size that does not cause a phase change of said first and second recording layer, reading device according to claim 24. The reading device according to claim 25, wherein the amplitude I _{r of the} current pulse is I _r (mA) ≦ 0.02. N recording layers (N> 2, N is a natural number) for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse
A memory comprising:
_Assuming that the crystallization temperature of the mth recording layer is T _xm (1 ≦ m ≦ N), the crystallization temperatures of the N recording layers have the relationship T _x1 <T _x2 <... <T _xm-1 < T _xm <T _{xm + 1} <... <T _xN is satisfied,
_Assuming that the crystallization time of the mth recording layer is t _xm , the crystallization times of the N recording layers are expressed by the relationship t _x1 > t _x2 >...> T _xm-1 > t _xm > t _{xm + 1} >...> t satisfies _xN ,
The resistance values when the recording layers of the N recording layers are in an amorphous phase and the resistance values when the recording layers of the N recording layers are in a crystalline phase are all different, and the N recording layers The sum of the resistances of the memory takes 2 ^N different values. A writing device for writing information to a memory,
The memory is
N recording layers (N> 2, N is a natural number) for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse
A memory comprising:
_Assuming that the crystallization temperature of the mth recording layer is T _xm (1 ≦ m ≦ N), the crystallization temperatures of the N recording layers have the relationship T _x1 <T _x2 <... <T _xm-1 < T _xm <T _{xm + 1} <... <T _xN is satisfied,
_Assuming that the crystallization time of the mth recording layer is t _xm , the crystallization times of the N recording layers are expressed by the relationship t _x1 > t _x2 >...> T _xm-1 > t _xm > t _{xm + 1} >...> t satisfies _xN ,
The resistance values when the recording layers of the N recording layers are in an amorphous phase and the resistance values when the recording layers of the N recording layers are in a crystalline phase are all different, and the N recording layers The sum of the resistances takes 2 ^N different values,
The writing device includes:
A pulse generator for generating at least N crystallization current pulses and an amorphization current pulse;
An application unit that applies the at least N crystallization current pulses and the amorphization current pulse to the N recording layers, and the pulse generation unit includes:
To change the phase of only the mth recording layer from an amorphous phase to a crystalline phase and maintain the phase state of the recording layers excluding the mth recording layer, T _xm ≦ T _x <T _{x (m +1)} crystallization current pulses corresponding to the temperature T _x and _{t xm ≦ t x <t x} (m-1) becomes the time t _x occurs becomes,
When all of the N recording layers are changed from a crystalline phase to an amorphous phase, the amorphization current pulse corresponding to a temperature equal to or higher than the highest melting point among the melting points of the N recording layers is applied. The writing device that occurs. The pulse generation unit corresponds to a temperature T _{x satisfying} T _xN ≦ T _x and a time t _{x satisfying} t _x1 ≦ t _x when all the N recording layers are changed from an amorphous phase to a crystalline phase. 30. The writing device of claim 28, wherein the writing device generates a current pulse. The pulse generating unit is configured to change T _{x (m + n} ) when the mth recording layer to the (m + n−1) th recording layer among the N recording layers is changed from an amorphous phase to a crystalline phase. _-1) to generate a corresponding current pulse to _{≦ T x <T x (m} + n) becomes the temperature T _x and _{t xm ≦ t x <t x} (m-1) becomes the time t _x, claim 28 Writing device. The pulse generator includes at least one recording layer of the N recording layers, each of which has a melting point of a temperature _Tm or less, and the recording layers of the N recording layers excluding the at least one recording layer Each has a melting point higher than the temperature T _m, each of the at least one recording layer is changed from a crystalline phase to an amorphous phase, and the recording layers excluding each of the at least one recording layer are changed to a crystalline phase in maintaining, generating a current pulse corresponding to the temperature T _m, the writing device according to claim 28. A reading device for reading information written in a memory,
The memory is
N recording layers (N> 2, N is a natural number) for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse
A memory comprising:
_Assuming that the crystallization temperature of the mth recording layer is T _xm (1 ≦ m ≦ N), the crystallization temperatures of the N recording layers have the relationship T _x1 <T _x2 <... <T _xm-1 < T _xm <T _{xm + 1} <... <T _xN is satisfied,
_Assuming that the crystallization time of the mth recording layer is t _xm , the crystallization times of the N recording layers are expressed by the relationship t _x1 > t _x2 >...> T _xm-1 > t _xm > t _{xm + 1} >...> t satisfies _xN ,
The resistance values when the recording layers of the N recording layers are in an amorphous phase and the resistance values when the recording layers of the N recording layers are in a crystalline phase are all different, and the N recording layers The sum of the resistances takes 2 ^N different values,
The reading device includes:
An application unit for applying a current pulse to the N recording layers;
A resistance measuring instrument for measuring a sum of resistances of the N recording layers;
And a determination unit that determines which of the 2 ^N different resistances matches the sum of the resistances. A writing method for writing information to memory,
The memory is
A first recording layer for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse;
A memory comprising: a second recording layer for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse;
Relationship between the crystallization temperature T _x2 of the second recording layer and the crystallization temperature T _x1 of the first recording layer is a T _x1 <T _x2,
The relationship between the crystallization time t _x2 of the first recording layer crystallization time t _x1 and the second recording layer is a t _x1> t _x2,
The resistance value when the first recording layer is in an amorphous phase is R _a1 , the resistance value when the first recording layer is in a crystalline phase is R _c1 , and the second recording layer is in an amorphous phase. the resistance value R _a2 when, when the second recording layer is the resistance value in the case of the crystalline phase and the R _c2, unlike _{R a1 + R a2, R a1} + R c2, R a2 + R c1, R c1 + R c2 are mutually ,
The writing method is:
Generating at least first to third current pulses;
Applying the at least first to third current pulses to the first recording layer and the second recording layer, and generating the step,
When the phase of the first recording layer is changed from the amorphous phase to the crystalline phase and the phase state of the second recording layer is maintained, the temperature T and T _x1 ≦ t _satisfy T _x1 ≦ T <T _x2. Generating the first current pulse corresponding to time t;
When maintaining the phase state of the first recording layer and changing the phase of the second recording layer from an amorphous phase to a crystalline phase, a temperature T _satisfying T _x2 ≦ T and t _x2 ≦ t <t _x1 Generating the second current pulse corresponding to time t,
When changing the phase of the first recording layer and the second recording layer from a crystalline phase to an amorphous phase, a temperature equal to or higher than the lower melting point of the melting points of the first and second recording layers. A writing method, which is a step of generating the third current pulse corresponding to. A reading method for reading information written in a memory,
The memory is
A first recording layer for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse;
A memory comprising: a second recording layer for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse;
Relationship between the crystallization temperature T _x2 of the second recording layer and the crystallization temperature T _x1 of the first recording layer is a T _x1 <T _x2,
The relationship between the crystallization time t _x2 of the first recording layer crystallization time t _x1 and the second recording layer is a t _x1> t _x2,
The resistance value when the first recording layer is in an amorphous phase is R _a1 , the resistance value when the first recording layer is in a crystalline phase is R _c1 , and the second recording layer is in an amorphous phase. the resistance value R _a2 when, when the second recording layer is the resistance value in the case of the crystalline phase and the R _c2, unlike _{R a1 + R a2, R a1} + R c2, R a2 + R c1, R c1 + R c2 are mutually ,
The reading method is:
Applying a current pulse to the first and second recording layers;
Measuring the sum of the resistances of the first and second recording layers;
And determining which of the four different resistances the sum of the resistances matches. A writing method for writing information to memory,
The memory is
N recording layers (N> 2, N is a natural number) for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse
A memory comprising:
_Assuming that the crystallization temperature of the mth recording layer is T _xm (1 ≦ m ≦ N), the crystallization temperatures of the N recording layers have the relationship T _x1 <T _x2 <... <T _xm-1 < T _xm <T _{xm + 1} <... <T _xN is satisfied,
_Assuming that the crystallization time of the mth recording layer is t _xm , the crystallization times of the N recording layers are expressed by the relationship t _x1 > t _x2 >...> T _xm-1 > t _xm > t _{xm + 1} >...> t satisfies _xN ,
The resistance values when the recording layers of the N recording layers are in an amorphous phase and the resistance values when the recording layers of the N recording layers are in a crystalline phase are all different, and the N recording layers The sum of the resistances takes 2 ^N different values,
The writing method is:
Generating at least N crystallization current pulses and an amorphization current pulse;
Applying the at least N crystallization current pulses and amorphization current pulses to the N recording layers, the generating step comprising:
To change the phase of only the mth recording layer from an amorphous phase to a crystalline phase and maintain the phase state of the recording layers excluding the mth recording layer, T _xm ≦ T _x <T _{x (m +1)} crystallization current pulses corresponding to the temperature T _x and _{t xm ≦ t x <t x} (m-1) becomes the time t _x occurs becomes,
When all of the N recording layers are changed from a crystalline phase to an amorphous phase, the amorphization current pulse corresponding to a temperature equal to or higher than the highest melting point among the melting points of the N recording layers is applied. A writing method that is a process that occurs. A reading method for reading information written in a memory,
The memory is
N recording layers (N> 2, N is a natural number) for recording information by causing a reversible phase change between a crystalline phase and an amorphous phase due to a temperature rise caused by application of a current pulse
A memory comprising:
_Assuming that the crystallization temperature of the mth recording layer is T _xm (1 ≦ m ≦ N), the crystallization temperatures of the N recording layers have the relationship T _x1 <T _x2 <... <T _xm-1 < T _xm <T _{xm + 1} <... <T _xN is satisfied,
_Assuming that the crystallization time of the mth recording layer is t _xm , the crystallization times of the N recording layers are expressed by the relationship t _x1 > t _x2 >...> T _xm-1 > t _xm > t _{xm + 1} >...> t satisfies _xN ,
The resistance values when the recording layers of the N recording layers are in an amorphous phase and the resistance values when the recording layers of the N recording layers are in a crystalline phase are all different, and the N recording layers The sum of the resistances takes 2 ^N different values,
The reading method is:
Applying a current pulse to the N recording layers;
Measuring the sum of the resistances of the N recording layers;
And determining which of the 2 ^N different resistances the sum of the resistances matches.

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