JP4023698B2 - Manufacturing method of side-use electronic component with bottom electrode - Google Patents
Manufacturing method of side-use electronic component with bottom electrode Download PDFInfo
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- JP4023698B2 JP4023698B2 JP31850296A JP31850296A JP4023698B2 JP 4023698 B2 JP4023698 B2 JP 4023698B2 JP 31850296 A JP31850296 A JP 31850296A JP 31850296 A JP31850296 A JP 31850296A JP 4023698 B2 JP4023698 B2 JP 4023698B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Description
【0001】
【発明の属する技術分野】
本発明は側面に電子素子を樹脂モールドし、かつ下面電極を設けた電子部品の製造方法に関する。
【0002】
【従来の技術】
基板の上面に電子素子を実装し、電子素子を含めて基板の上面側を封止樹脂でモールドした電子部品は周知である。また多数の電子部品を回路基板に同時にハンダ付けで実装する用法が普及したため、その実装法に用いる、いわゆるSMD(表面実装デバイス)用部品のニーズが高い。SMD用部品の多くのものは直方体のブロック型をしており、その底面あるいは低部に近い側面に電極端子があって、回路基板上の配線パターンに部品を載せ、そのパターンと接触または近接した電極端子とを溶融ハンダで接続し易い構成になっている。そのための従来例の部品の構造を以下に説明する。
【0003】
図5は従来例(1)の電子部品の斜視図、図6は同従来例の製造過程における集合基板の一部の斜視図である。1は基板で、集合基板11から最終工程でカットライン12によって切断分離されたものの1個である。2は側面パターンであって、基板1および集合基板11の平面に貼った銅箔を所定のパターンにエッチングしたものである。3は電子素子で、例えばLEDであり、一対の側面パターン2の一方にダイボンディングされ、他方はボンディングワイヤ4で接続されている。5は下面パターンで、側面パターン2に接続して基板1の下面に設けられた導電性の皮膜であり、集合基板11に予め設けた細長い長穴状のスルーホール6の内側面に無電解メッキ等により形成されたものである。なお、下面や側面等の方位を示す用語は、電子素子を側面に位置させて下面が他の基板に実装される電子部品の完成体の向きを基準にしてあらわしたもので、集合基板の平面の上下と関連するものではない。これは後述する第2の従来例や本発明の実施例についても同じとする。7は封止樹脂で、LEDの発光を透過させるため透明で、電子素子3やその接続部を様々な環境条件から保護するために基板1の平面にエポキシ樹脂等をモールドしたものである。カットライン12による切断は、樹脂モールド後に行う方が合理的であるが切断後にモールドしてもよい。以上は完成した電子部品の内容である。しかし図5では内部構造を実線で明瞭に見せるため、完成後の封止樹脂7の輪郭をあえて2点鎖線(想像線)で示してある。また電子部品のすべての導電性パターンは打点による陰影を付して示してある。
【0004】
図5において、電子部品はその上面電極2を他の回路基板上で、水平に発光が行われるように横向きにし、他の回路基板上の2点鎖線で示した銅箔等の一対の配線パターン8上に表面実装される。やはり2点鎖線で示したハンダ材9は、表面実装のハンダリフロー工程において溶融時に配線パターン8と電子部品の端面パターン5の双方を濡らし接続している。自動表面実装を行うためには両パターンは平行かつ密着できることが望ましいが、本従来例では直交しているため、ハンダが両者を同時に濡らさないことがあったり、接続しても強度が不足してハンダ材の断線が生じたりして十分な信頼性を発揮させる上で困難があった。
【0005】
図7は第2の従来例の電子部品の斜視図、図8はその背面斜視図、図9は第2の従来例における集合基板の斜視図である。本従来例においては1個の電子部品内に2対の側面パターン2と2個の電子素子3が内蔵されている。それらは例えば発光色の異なる複数個のLEDであり、あるいは発光素子と受光素子のペアであり、またはある作用素子とそれを駆動する能動素子である。以下第1の従来例のものと本質的に同じ性格の構成要素に対しては同じ名称と番号を付して基本的説明は反復せずに省略し、相違点のみを説明することにする。スルーホール6は丸穴状で基板1毎に4個づつ設けられ、それらの内面に、側面パターン2と基板1および集合基板11の裏面にある裏面電極10とを接続する下面パターン5が形成される。各下面パターン5は概ね半円筒形になる。
【0006】
下面パターン5は他の回路基板上の配線パターン8の表面と対向させられハンダ材9によりそれぞれ接続される。この場合ハンダ材9は対向面間のかまぼこ形の空間を必ずしもうまく濡れ上って満たすことができない場合が生ずることがある。
【0007】
【発明が解決しようとする課題】
本発明の目的は、側面に作動電子素子を有するブロック状電子部品の下面に、接続しようとする相手回路基板の配線パターンと密着し得る、表面実装に適した平面状の電極端子を設けるための製造方法を提供し、リフロー工程においてハンダの濡れ性が良好で高度の接続の信頼性を発揮する電子素子を得ることである。
【0008】
【課題を解決するための手段】
本発明の下面電極付き側面使用電子部品の製造方法は、下記(1)、(2)の特徴のいずれかを備える。
(1)ほぼブロック状をなし、電子素子を実装するために側面に形成された導電性の複数の側面パターンと、下面に形成されて前記側面パターンと接続する導電性の複数の平面状の下面パターンを有する電子部品の製造方法であって、平面状の上面の一部を前記側面とし、平面状の端面の一部を前記下面とする絶縁性の集合基板を用意する工程と、該集合基板の上面に多数組の前記側面パターンを前記端面に平行するように整列させて形成する工程と、前記平面状の端面に前記側面パターンの各組のそれぞれに接続する下面パターンを形成する工程と、形成された前記側面パターンの各組に対して所定の前記電子素子を実装する工程と、実装された前記電子素子を集合基板上で同時に樹脂封止する工程と、前記樹脂封止工程後に前記側面および下面パターンの各組の境界部分を、前記端面に垂直な平面で前記集合基板を複数個所切断することによって、個々の電子部品に分離する工程とを有すること。
(2)上記(1)において、前記側面パターンと下面パターンの各組は前記集合基板上に複数列設けられると共に、前記平面状の端面は、前記各組の列と交互にかつ平行して前記集合基板に複数本設けられた長穴状のスルーホールの平面状の内側面であること。
【0009】
【発明の実施の形態】
図1は本発明の一つの実施の形態の構造を示す斜視図であり、図2はその製造の段階で用いられる集合基板の一部の斜視図である。電子部品は基板1、側面パターン2、側面パターンにダイボンドされたLED等の電子素子3、接続手段であるボンディングワイヤ4、長穴状スルーホール6の平面状の内側面に形成された下面パターン5、保護用の封止樹脂7(想像線で示す)、必要に応じて設けた裏面電極(図示せず)より成る。11は集合基板、12は完成電子部品を単離するカットラインである。これらは既に説明した従来例の対応する要素のそれぞれと機能をほぼ同じくする。想像線で示した13は表面実装接続された相手回路基板、8はその表面の配線パターン、9はリフロー工程を経て薄層となったハンダ材であり、理想的な実装接続がなされた状態を示している。
【0010】
図3は本発明の他の実施の形態の構造を示す斜視図であり、図4はその裏面斜視図である。これは内部に複数の電子素子を有し、複数対の下面パターンを設けた例であり、各構成要素は第1の実施の形態と共通性があり同一の番号が付されているので、更なる説明は必要ないであろう。集合基板の形態も図2からも十分推測容易であるから図示していない。実装の効果も第1の実施の形態と同様に発揮される。
【0011】
以上二つの実施の形態について述べたが、本発明は更に広い技術を包含する。例えば、電子部品の内部構造や集合基板上の配置、基板の材質、側面パターン、裏面電極の構成は使用目的により自由に選択できる。電子素子は回路基板の側面で作動することが不利でないものであればどのような電磁的・光学的・音響的・熱的・化学的作用を持つものでも良く、個数も混在も接続法も自由である。封止樹脂の材質や封止方法も目的に応じて種々選択可能であるし、工程の位置も集合基板の状態・一部切断して短冊状に基板が集合した状態、個々の基板に分離された状態でのいずれでも封止・モールドは行い得る。
【0012】
またスルーホール内側面に分割された下面パターンを形成する方法も限定されない。例えば
(1)導電性インクの内側面への部分的塗布、(2)無電解メッキ前にメッキレジストの部分的塗布による分割、(3)全面スルーホール形成後に僅かに幅広で内側面に食込むパンチで打抜き、部分的に導電膜を削除する方法、(4)基板にスルーホール形成後、上面全面に無孔の銅箔を貼着し、これをエッチングで成形してからスルーホール上に位置する部分を直角に曲げてスルーホール内に折り込む方法(この場合下面電極とは必ずしも接続しない)等種々考えられる。更には下面パターンはスルーホール内面ではなく、集合基板を個々の部品の単位基板の2次元配置ではなく1次元の直線状に配置し、その短冊状の側面に形成するようにしてもよい。
【0013】
【発明の効果】
本発明の電子部品においては、集合基板に設けたスルーホールの平面状内側面に下面パターンを形成し相手配線パターンと平行かつ密着できる下面電極としたので、表面実装時にハンダの濡れ性が良好でハンダ材の薄層により強固に接続され、実装の高度の信頼性を発揮し得るようになった。しかも設計上の制約やコストアップ要因も特に生ずることがなく、デバイス改良の効果が大きい。
【図面の簡単な説明】
【図1】本発明の一つの実施の形態の斜視図である。
【図2】本発明の電子部品の素材となる集合基板の斜視図である。
【図3】本発明の他の実施の形態の斜視図である。
【図4】本発明の他の実施の形態の背面斜視図である。
【図5】第1の従来例の電子部品の斜視図である。
【図6】第1の従来例の電子部品の素材となる集合基板の斜視図である。
【図7】第2の従来例の電子部品の斜視図である。
【図8】第2の従来例の電子部品の背面斜視図である。
【図9】第2の従来例の集合基板の斜視図である。
【符号の説明】
1 基板
2 側面パターン
3 電子素子
5 下面パターン
6 スルーホール
7 封止樹脂
8 配線パターン
9 ハンダ材
10 裏面電極
11 集合基板
12 カットライン
13 相手回路基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing an electronic component in which an electronic element is resin-molded on a side surface and a bottom electrode is provided .
[0002]
[Prior art]
An electronic component in which an electronic element is mounted on an upper surface of a substrate and the upper surface side of the substrate including the electronic element is molded with a sealing resin is well known. In addition, since a method of mounting a large number of electronic components on a circuit board by soldering has become widespread, there is a high need for so-called SMD (surface mounted device) components used for the mounting method. Many of the SMD components have a rectangular parallelepiped block shape. There are electrode terminals on the bottom surface or a side surface close to the lower portion, and the component is placed on the wiring pattern on the circuit board and is in contact with or close to the pattern. The electrode terminal is easily connected with molten solder. The structure of the conventional part for this purpose will be described below.
[0003]
FIG. 5 is a perspective view of the electronic component of the conventional example (1), and FIG. 6 is a perspective view of a part of the collective substrate in the manufacturing process of the conventional example.
[0004]
In FIG. 5, the electronic component has its
[0005]
FIG. 7 is a perspective view of an electronic component of a second conventional example, FIG. 8 is a rear perspective view thereof, and FIG. 9 is a perspective view of a collective substrate in the second conventional example. In this conventional example, two pairs of
[0006]
The
[0007]
[Problems to be solved by the invention]
An object of the present invention is to provide a planar electrode terminal suitable for surface mounting, which can be in close contact with a wiring pattern of a circuit board to be connected , on the lower surface of a block-shaped electronic component having a working electronic element on a side surface. A manufacturing method is provided, and an electronic device having good solder wettability and high connection reliability in a reflow process is obtained.
[0008]
[Means for Solving the Problems]
The manufacturing method of the side surface use electronic component with a lower surface electrode of this invention is equipped with either of the characteristics of following (1) and (2).
(1) A plurality of conductive side surface patterns which are substantially block-shaped and formed on the side surface for mounting an electronic device, and a plurality of conductive planar lower surfaces which are formed on the lower surface and are connected to the side surface pattern. A method of manufacturing an electronic component having a pattern, comprising: preparing an insulating collective substrate having a part of a planar upper surface as the side surface and a part of a planar end surface as the lower surface; Forming a plurality of sets of the side surface patterns on the upper surface of the substrate so as to be parallel to the end surface, and forming a lower surface pattern connected to each of the sets of the side surface patterns on the planar end surface; a step of mounting a predetermined said electronic element with respect to the formed each set of the side pattern, a step of simultaneously resin-sealed the implemented the electronic element on the set substrate, the side after the resin sealing step And Each set of boundary portions of the lower surface pattern, by cutting a plurality of locations of the collective substrate in a plane perpendicular to said end face, having a step of separating the individual electronic components.
(2) In the above (1), each set of the side surface pattern and the bottom surface pattern is provided in a plurality of rows on the collective substrate, and the planar end surface is alternately and parallel to the rows of each set. It is a planar inner surface of a long hole-shaped through hole provided in a plurality on the collective substrate.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a perspective view showing the structure of one embodiment of the present invention, and FIG. 2 is a perspective view of a part of a collective substrate used in the manufacturing stage.
[0010]
FIG. 3 is a perspective view showing the structure of another embodiment of the present invention, and FIG. 4 is a rear perspective view thereof. It has a plurality of electronic elements therein, an example in which a lower surface pattern of a plurality of pairs, since each component has commonality with the same numbers are assigned to the first embodiment, No further explanation will be necessary. The form of the collective substrate is also not shown because it is sufficiently easy to guess from FIG. The effect of mounting is also exhibited as in the first embodiment.
[0011]
Although the two embodiments have been described above, the present invention includes a broader technique. For example, the arrangement of the internal structure and set on a substrate of an electronic component, a material of the substrate, the side surface pattern, the back surface electrode structure can be freely selected depending on the intended use. The electronic elements can have any electromagnetic, optical, acoustic, thermal, and chemical action, as long as they are not disadvantageous to operate on the side of the circuit board. It is. Various types of sealing resin materials and sealing methods can be selected according to the purpose, and the position of the process is also the state of the collective substrate, partly cut and assembled into strips, separated into individual substrates Sealing and molding can be performed in any state.
[0012]
Moreover, the method of forming the lower surface pattern divided on the inner surface of the through hole is not limited. For example, (1) partial application of conductive ink to the inner surface, (2) division by partial application of plating resist before electroless plating, and (3) slightly wider and bite into the inner surface after through-hole formation. (4) After forming a through hole in the substrate, a non-porous copper foil is attached to the entire upper surface, and this is formed by etching and then positioned on the through hole. Various methods are conceivable, such as a method of bending a portion to be bent at a right angle and folding it into a through hole (in this case, it is not necessarily connected to the bottom electrode). Further the lower surface pattern is not a through hole inner surface, the aggregate substrate was placed in a one-dimensional linear rather than two-dimensional arrangement of unit substrates of each component may be formed on the strip-shaped side.
[0013]
【The invention's effect】
In the electronic component of the present invention, since the lower surface electrode can be parallel and in close contact with the formed mating wiring pattern under surface pattern in a planar shape in side surfaces of the through holes formed in the collective substrate, solder wettability good during surface mounting With a thin layer of solder material, it can be firmly connected, and it is possible to demonstrate high reliability of mounting. In addition, there are no design restrictions or cost increase factors, and the effect of device improvement is great.
[Brief description of the drawings]
FIG. 1 is a perspective view of one embodiment of the present invention.
FIG. 2 is a perspective view of a collective substrate that is a material of an electronic component of the present invention.
FIG. 3 is a perspective view of another embodiment of the present invention.
FIG. 4 is a rear perspective view of another embodiment of the present invention.
FIG. 5 is a perspective view of a first conventional electronic component.
FIG. 6 is a perspective view of a collective substrate that is a material of an electronic component of a first conventional example.
FIG. 7 is a perspective view of a second conventional electronic component.
FIG. 8 is a rear perspective view of a second conventional electronic component.
FIG. 9 is a perspective view of a second conventional collective substrate.
[Explanation of symbols]
1
Claims (2)
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JP31850296A JP4023698B2 (en) | 1996-11-15 | 1996-11-15 | Manufacturing method of side-use electronic component with bottom electrode |
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JP31850296A JP4023698B2 (en) | 1996-11-15 | 1996-11-15 | Manufacturing method of side-use electronic component with bottom electrode |
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JPH10150138A JPH10150138A (en) | 1998-06-02 |
JP4023698B2 true JP4023698B2 (en) | 2007-12-19 |
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JP3919367B2 (en) * | 1998-12-08 | 2007-05-23 | ローム株式会社 | Laser unit and insulation block |
JP2004312065A (en) | 2003-04-01 | 2004-11-04 | Soshin Electric Co Ltd | Passive components |
TW200711190A (en) * | 2005-08-17 | 2007-03-16 | Matsushita Electric Ind Co Ltd | Surface mounted semiconductor device and method for manufacturing same |
US7494920B2 (en) * | 2005-10-14 | 2009-02-24 | Honeywell International Inc. | Method of fabricating a vertically mountable IC package |
JP2007134602A (en) * | 2005-11-11 | 2007-05-31 | Stanley Electric Co Ltd | Surface mount semiconductor light emitting device |
RU2597674C2 (en) | 2010-11-19 | 2016-09-20 | Конинклейке Филипс Электроникс Н.В. | Insular holder for light-emitting device |
JP2013171912A (en) * | 2012-02-20 | 2013-09-02 | Stanley Electric Co Ltd | Light-emitting device |
US8940099B2 (en) | 2012-04-02 | 2015-01-27 | Illinois Tool Works Inc. | Reflow oven and methods of treating surfaces of the reflow oven |
US9170051B2 (en) * | 2012-04-02 | 2015-10-27 | Illinois Tool Works Inc. | Reflow oven and methods of treating surfaces of the reflow oven |
DE102013110733A1 (en) * | 2013-09-27 | 2015-04-02 | Osram Opto Semiconductors Gmbh | Optoelectronic semiconductor component and method for producing an optoelectronic semiconductor component |
JP6888650B2 (en) * | 2013-12-13 | 2021-06-16 | 日亜化学工業株式会社 | Light emitting device |
JP2015207754A (en) * | 2013-12-13 | 2015-11-19 | 日亜化学工業株式会社 | Light emitting device |
US10090448B2 (en) | 2014-02-07 | 2018-10-02 | Rohm Co., Ltd. | Light-emitting module, light-emitting device and method of making light-emitting module |
JP2015149448A (en) * | 2014-02-07 | 2015-08-20 | ローム株式会社 | Light emitting module, light emitting device and method of manufacturing light emitting module |
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JPS6043040B2 (en) * | 1979-02-09 | 1985-09-26 | 松下電器産業株式会社 | light emitting diode |
JPH01163352U (en) * | 1988-04-30 | 1989-11-14 | ||
JPH0529662A (en) * | 1991-07-22 | 1993-02-05 | Sharp Corp | Photosemiconductor device |
JPH0529659A (en) * | 1991-07-23 | 1993-02-05 | Sharp Corp | Side-emitting LED lamp and manufacturing method thereof |
JP3642823B2 (en) * | 1995-03-27 | 2005-04-27 | ローム株式会社 | Side light emitting device |
JP4010424B2 (en) * | 1997-02-05 | 2007-11-21 | シチズン電子株式会社 | Electrode structure of side surface type electronic component and manufacturing method thereof |
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