JP3985000B2 - Imaging recording / playback device - Google Patents

Description

  The present invention relates to an imaging recording / reproducing apparatus suitable for use in a consumer SDVTR that records and reproduces digital video signals and the like when digital video signals and the like are transmitted to other devices using a 1394 digital interface.

First, an outline of a communication system using an IEEE 1394 serial bus as an example of a digital interface will be described.
For example, as shown in FIG. 8, as a digital device, a VGA input compatible personal computer (hereinafter referred to as PC), VTR1, a digital interface compatible digital camera (hereinafter referred to as “DCAM”), and a digital camcorder (hereinafter referred to as PC). (Referred to as “DVCR1”), and DVCR1 and PC, PC and VTR1, and VTR1 and DCAM are connected by the P1394 serial bus. Each device described above has a function of relaying digital data and control data on the P1394 bus. The cable for P1394 has three pairs of shielded wires, and each pair of wires is used for protocol signal transfer and data transfer as well as for power supply. The system can be operated even if there is a power-off device in the system.

  By the way, in P1394, communication is performed in a predetermined communication cycle (125 μs) as shown in FIG. 9, and data having a time axis such as video data and audio data is guaranteed a transfer band at a constant data rate. Isochronous (synchronous) communication is performed, and control data such as a control command is asynchronously (asynchronously) communicated irregularly as necessary. In such communication, there is a cycle start packet at the beginning of each communication cycle, followed by a period for transmitting a packet for isochronous communication. Further, by attaching each channel number to a packet for isochronous communication, isochronous communication of a plurality of channels can be performed simultaneously.

  That is, when channel 1 is assigned to communication from DVCR1 to VTR1, DVCR1 sends an isochronous communication packet of channel number 1 immediately after the cycle start packet on the bus, and VTR1 monitors the packet on the bus and monitors channel number 1. The isochronous communication is executed between the DVCR1 and the VTR1 by fetching the packet with the mark. Similarly, by assigning channel number 2 to a packet from DCAM to PC, isochronous communication is executed between DCAM and PC, and isochronous communication between channel 1 and channel 2 is performed in parallel. After transmission of all isochronous communication packets is completed in each communication cycle, a period until the next cycle packet is used for asynchronous communication.

  In the communication system as described above, when a new digital device is connected at power-on and when the device is disconnected, a node ID (physical address) is automatically assigned to each device (node) according to the connection form. ), (# 0, # 1, # 2, # 3 in FIG. 8) are assigned according to the following procedure based on the address program and address table stored in the memory in the microcomputer and the topology is automatically set. The node ID assignment procedure will be briefly described below. This procedure consists of determining the hierarchical structure of the system and assigning a physical address to each node.

  First, for each of the above devices, if the PC is node A, DVCR1 is node B, VTR1 is node C, and DCAM is node D, each node is the other node to which it is connected. Communicating each other, giving priority to the one that has been communicated to the other party first, finally the parent-child relationship between each node in this system, that is, the root node that is a node that does not become a child with respect to the system hierarchy and other nodes Is determined. Specifically, node D is informed that it is a parent to node C, and node B is informed to node A that it is a parent. Also, when node A communicates to node C that it is the parent and node C communicates to node A that it is the parent, the one that has been transmitted to the other party first takes precedence. If the transmission is early, node A is the parent of node C. As a result, the node A does not become a child to any other node, and in this case, becomes a root node. Thus, after the parent-child relationship is determined, a physical address is assigned.

  The assignment of the physical address is basically performed by allowing the parent node to assign an address to the child node, and further allowing each child node in order from the child node connected to the port number having the smaller port number. In the case of FIG. 8, the node A permits the node B to give an address, and as a result, the node B attaches a physical address # 0 to itself and sends this on the bus, thereby “node # 0 Notify other nodes that it is “allocated”. Next, when node A grants address to node C, node D, which is also a child node of node C, grants address assignment. As a result, node D itself has the next physical address of # 0 as a physical address. This is sent on the bus with # 1. Thereafter, node C attaches itself to physical address # 2 and sends this on the bus, and finally node A attaches itself to physical address # 3 and sends this on the bus. The details of the P1394 serial bus including the node ID assignment procedure are disclosed as "IEEE1394 serial bus specification".

  Next, the data transfer procedure will be described. Data transfer is possible by giving the address as described above, but in the P1394 system, the bus use right is arbitrated by the root node prior to data transfer. That is, in P1394, as shown in FIG. 9, since only one channel of data is transferred at a certain timing, it is necessary to arbitrate first. When each node wants to transfer, it uses the bus for its own parent node. The root node arbitrates bus usage rights from each node. As a result, the node that obtained the bus use right designates the transmission speed before starting the data transfer, and notifies the transmission destination node of whether 100 Mbps is 200 Mbps or 400 Mbps. Thereafter, in the case of isochronous transfer, the transmission source node starts data transfer on the designated channel immediately after receiving the cycle start packet sent in synchronization with the communication cycle by the cycle master as the root node. . Note that the cycle master sends out the cycle start packet and adjusts the time of each node.

  On the other hand, in the case of asynchronous transfer that transfers control data such as commands, arbitration for asynchronous communication is performed after synchronous transfer in each communication cycle is completed, and data transfer from the transmission source node to the transmission destination node is performed. Be started.

The above is the outline of the P1394 serial bus.
In this manner, a moving image conforming to the VGA format can be transmitted from the digital camera to the PC in real time and displayed on the PC monitor.

Conventionally, in order to transmit and display a moving image with a digital interface to a PC, a dedicated digital camera for transmitting in a so-called VGA format converted to a square lattice is required.
In addition, to display video signals such as NTSC on a PC, DIF data encoded by a digital interface is transmitted from a digital VTR such as an SD system to the PC, which is decoded by the PC, converted into a square lattice, and displayed. There is a problem that it is necessary to provide a means for this.

  SUMMARY OF THE INVENTION The present invention solves the above-described problems, and an object thereof is to obtain an imaging recording / reproducing apparatus that can output various types of video signals.

In the present invention, the imaging means for imaging the subject, the recording / reproducing means for recording / reproducing the video signal on the recording medium, and the output of the imaging means to process the first video signal by the first method are output. 1 signal processing means, a second signal processing means for processing the signal reproduced by the recording / reproducing means to output a second video signal by the second method, and a processing for the second video signal. Third signal processing means for outputting a third video signal according to the first method, first selection means for selecting one of the first and third video signals, and the first selection means Conversion means for converting the format of the selected video signal, the video signal selected by the first selection means, the video signal format-converted by the conversion means, and the second video signal are input, and One or more of these were time-division multiplexed A second selection means for outputting the item, is provided an interface means for outputting a signal obtained from the second selection means.
According to the present invention, the converted video signal and the captured video signal are format-converted by the converting unit and transmitted from the interface unit, and the captured video signal and the reproduced video signal are transmitted as a video signal of the same system.

  According to the present invention, for example, a video signal picked up by a first method such as NTSC or PAL or a reproduced video signal of a first method, a video signal of a second method such as DIF data, It is possible to obtain one of the video signals subjected to format conversion such as the VGA format or a time-division multiplexed signal of these signals and send them to a device such as a computer suitable for each of them.

FIG. 1 shows an embodiment of an apparatus in which a camera and an SDVTR as an imaging recording / reproducing apparatus according to the present invention are integrated, and the configuration and operation thereof will be described.
In FIG. 1, a subject image is picked up by a CCD image sensor 2 through a lens 1 and photoelectrically converted to obtain a video signal. This video signal is digitally processed by the camera signal processing unit 3 to become a luminance signal Y and color difference signals U and V of the NTSC system or the like having a so-called 4: 2: 2 ratio, and is input to the switch 4.

  On the other hand, the blocked digital video signal recorded on the track of the magnetic tape 5 is reproduced by the helical scan head 6. The reproduced signal is subjected to error correction processing by an error correction unit (ECC) 7 and then output to the data bus as blocked data. This data is decoded by a digital encoder / decoder (ENC / DEC) 8 and becomes NTSC luminance signal Y and color difference signals U and V having a ratio of 4: 2: 2, and is input to the switch 4.

  The audio signal processing unit 13 processes the stereo audio signal on the data bus and alternately outputs L-channel and R-channel audio serial data as shown in FIG. The L and R audio data are input to the switch 12, converted to an analog audio signal by the D / A converter 17, and output from the output terminal 18.

  The subcode decoder 14 and the AUX data decoder 15 also decode the subcode and AUX code in the subcode area of the track on the data bus, respectively, and input them to the arithmetic processing unit (MPU).

  Further, so-called DIF data from the ECC 7 is directly input to the switch 12 through the data bus. FIG. 3 shows the transfer order of SDVTR DIF format data.

  The MPU 16 selects the 4: 2: 2 luminance signal Y and the color difference signals U and V from one of the camera signal processing unit 3 and the ENC / DEC 8 by switching the switch 4 according to a control signal input from the outside. The selected luminance signal Y and color difference signals U and V are input to the switch 12, converted into an analog signal by the D / A converter 9, and output from the output terminal 10.

  Further, the selected luminance signal Y and color difference signals U and V are decimated in the format conversion unit 11, so that the luminance signal Y is 640 pixels wide and 480 pixels high, and the color difference signals U and V are 320 pixels horizontal. It is thinned out to 240 pixels vertically, converted to a so-called 4: 1: 1 square lattice to become a VGA format, converted from an interlace of 60 fields / second to a non-interlace of 30 frames / second, and inputted to the switch 12. .

FIG. 4 shows the configuration of the format conversion unit 11.
The luminance signal Y is input to the input terminal 100, and the color difference signals U and V are time-multiplexed alternately with U and V and input to the input terminal 106, and further input to the luminance decimation unit 114 and the color difference signal decimation unit 115, respectively. As described above, the luminance signal Y is 640 pixels wide and 480 pixels high, and the color difference signals U and V are subjected to a 4: 1: 1 square lattice conversion of 160 pixels horizontal and 120 pixels high to obtain the luminance signal Y Are input to the switch 101, and the color difference signals U and V are input to the switch 107. Then, the luminance signal Y is input to the Y frame memories 102 and 103 by switching in the frame period and held.

Next, the non-interlace processing is performed by reading the luminance frame signals held in the frame memories 102 and 103 from 1H line-sequentially. The reason why the two frame memories 102 and 103 are used is to prohibit writing during reading.
In this way, a non-interlaced 640 × 480 luminance signal is obtained from the switch 104 and output from the terminal 105.

  On the other hand, since the color difference signal UV is time-multiplexed and input, it is switched and input to the U frame memories 108 and 109 and the V frame memories 110 and 111 by the switch 107, respectively. Similarly to the luminance signal, the color difference signal stored in each frame memory is output from the output terminal 113 in the order shown in FIG. The

In the above description, the format conversion unit 11 performs square lattice conversion to 640 × 480. However, when there is not enough room in the transfer speed of the physical layer of the digital interface, the color difference signal is 160 pixels wide and vertical. Decimation to 120 pixels, and the luminance signal is further converted into a square lattice of 320 × 240, which is a ¼ screen size of 640 × 480, so that the physicality of the 1394 digital interface of Y: U: V = 4: 2: 2 is obtained. It becomes possible to transmit at 100 Mbps, which is the standard of the layer.
FIG. 6 shows the data transmission order in such a mode. Note that K and Pn in FIG. 6 are the same as those in FIG.

As described above, a plurality of different digital data is switched by the switch 12 and input to the 1394 digital interface 19 in a time division manner, and the input digital data is packetized and output from the 1394 physical layer to the digital interface terminals 20 and 21. . Needless to say, in this case, when data is transferred, it conforms to the protocol defined by 1394 and SDVTR.
FIG. 7 shows how different digital data are packetized from the 1394 interface 19 and output.

As described above, by transmitting from the digital interface in the VGA format in addition to the data in the DIF format, a signal of a camera recorder such as a so-called NTSC can be transmitted in a square lattice VGA format having a very good compatibility with the computer. This makes it possible to transmit a moving image to a PC at a very low cost because it is not necessary to prepare a dedicated VGA camera.
Further, as described above, as described in the conventional example, if the devices are connected by the 1394 bus, the same video signal is converted to a digital signal of a different format while maintaining the same time of data of a different format from one node. It can be transmitted to the device.
Furthermore, if display software for the PC1394 VGA camera is prepared, the playback signal from the SD camera recorder can be displayed as a video signal from the VGA camera without changing the PC1394 hardware and software.

It is a block diagram which shows embodiment of this invention. It is a timing chart which shows the process of a reproduction audio signal. It is a sequence chart which shows the transfer order of DIF format data of SDVTR. It is a block diagram which shows the structure of a format conversion part. It is a block diagram which shows the output order of the luminance signal Y and the color difference signals U and V. It is a block diagram which shows the other output order of the luminance signal Y and the color difference signals U and V. It is a timing chart which shows that different digital data is packetized and outputted from a 1394 interface. It is a block diagram showing a communication system using a conventional IEEE 1394 serial bus. It is a timing chart which shows transmission of various conventional data.

Explanation of symbols

2 CCD image sensor 3 Camera signal processing device 4 Switch 5 Magnetic tape 6 Helical scan head 7 Error correction unit 8 Data encoder / decoder 11 Format conversion unit 12 Switch 13 Audio signal processing unit 16 MPU
19 1394 digital interface

Claims (6)

Imaging means for imaging a subject;
Recording and reproducing means for recording and reproducing a video signal on a recording medium;
First signal processing means for processing the output of the imaging means and outputting a first video signal according to a first method;
A second signal processing means for processing the signal reproduced by the recording / reproducing means and outputting a second video signal according to the second method;
Third signal processing means for processing the second video signal and outputting a third video signal according to the first method;
First selection means for selecting one of the first and third video signals;
Conversion means for converting the format of the video signal selected by the first selection means;
The video signal selected by the first selection means, the video signal format-converted by the conversion means, and the second video signal are input, and a signal obtained by time-division multiplexing one or more of them is output. A second selection means;
An imaging recording / reproducing apparatus comprising interface means for outputting a signal obtained from the second selection means.   2. The imaging recording / reproducing apparatus according to claim 1, wherein the first system is a predetermined television system.   2. The imaging recording / reproducing apparatus according to claim 1, wherein the video signal according to the second method is DIF data subjected to error correction processing by the second signal processing means.   2. The imaging recording / reproducing apparatus according to claim 1, wherein the converting means converts the video signal according to the first method into a VGA format.   2. The imaging recording / reproducing apparatus according to claim 1, wherein the interface means is a 1394 digital interface.   2. The imaging recording / reproducing apparatus according to claim 1, further comprising an audio signal processing unit that processes the audio signal reproduced by the recording / reproducing unit and applies the processed audio signal to the second selecting unit.

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