JP3957884B2 - Matrix drive type image display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a matrix drive type image display device such as a liquid crystal image display device, and more particularly to an improved image data transfer technique from a display drive controller to an information signal line driver.
[0002]
[Prior art]
FIG. 2 is a system block diagram of a conventional liquid crystal image display device. In the figure, reference numeral 1 denotes a liquid crystal display panel in which scanning signal electrodes and information signal electrodes are arranged in a matrix, 2 denotes a segment driver which is an information signal line driver arranged to apply information signals to the information signal electrodes, 3 Is a common driver which is a scanning signal line driver, 4 is a segment bus board, 5 is a common bus board, 6 is a liquid crystal drive controller for transferring image data and its sampling clock to the information signal line driver 2, 7 is an image data bus, and 8 is Image data sampling clock signal (SCLK) line, 9 is an image data input control signal (SDI) line, 10 is a latch signal (LATCH) line, 11 is a common control signal group, 12 is a graphic controller, 13 is an image data bus, 14 Is an image data sampling clock signal (FCLK) line, and 15 is image data. Transmission enable signal (ENABLE) lines, 16 horizontal synchronization signal (Hsync) line, 17 is a vertical synchronization signal (Vsync) line.
[0003]
As shown in FIG. 3, each segment driver 2 (2-1, 2-2,..., 2- (n-1), 2-n) arranged in parallel to the liquid crystal panel 1 has image data, The sampling clock SCLK and the latch signal LATCH are input in common, and the adjacent segment drivers 2 are cascade-connected by the image data input control signal (SDI) line 9 and SDO * (SDO1,..., SDOn-1). . SDO * also means a signal output from each segment driver 2 at a timing described later.
[0004]
The graphic controller 12 receives the image data and the control signal from the host computer, and performs data sampling and sampling of the buses 1D0 to ID35 of the image data bus 13 to the liquid crystal drive controller 6 according to a predetermined transfer format shown in FIGS. A clock FCLK, a horizontal synchronization signal Hsync for setting a horizontal scanning period (1H), and a vertical synchronization signal Vsync for setting one frame period are transferred.
[0005]
Here, the bus width of the image data bus 13 is 36 bits. This is because, when the display performance of the liquid crystal panel is a 262,144 color display as 6 gradation representations of each color of R, G, B, image data of 6 bits each for the three colors R, G, B This is because 3 × 6 × 2 = 36 bits because it is sent in two systems (two ports) to reduce the transfer frequency. FIG. 6 is a diagram showing an example of the correspondence between the image data buses ID0 to ID35 and the image data.
[0006]
As shown in FIG. 4, the image data of each of the image data buses ID0 to ID35 from the graphic controller 12 is transferred with valid data Valid during the High period of the enable signal ENABLE, and the liquid crystal is displayed by the rising edge of the sampling clock FCLK. It is sampled by the drive controller 6. The sampled image data is latched by the liquid crystal drive controller 6 as image data for one horizontal scanning period (one scanning line of the liquid crystal panel) at the High timing of the horizontal synchronization signal Hsync. The enable signal ENABLE is set to Low during the High period of the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync and before and after that period, and the image data in this period is invalidated (normally, the image data in this period is set to Low). )
[0007]
Transfer of control signals and image data from the liquid crystal drive controller 6 to the liquid crystal display panel 1 is performed as follows. That is, the liquid crystal drive controller 6 generates a scanning timing control signal for the common driver 3 from the vertical synchronizing signal Vsync and the horizontal synchronizing signal Hsync from the graphic controller 12, and supplies the scanning signal to the common bus substrate 5 via the common control signal line group 11. Send it out. On the other hand, the image data sampled and latched by the liquid crystal drive controller 6 as described above includes 36-bit first-port segment driver data and second-port segment driver data each having 36 bits. The data is sent to the segment bus board 4 via the bit-width image data bus 7.
[0008]
FIG. 7 shows a conventional transfer method of image data to the segment driver 2. As shown in the figure, image data is 18 bits wide × 2 ports (IDB0 to IDB35), and all drivers are transferred serially. The first data IDB0, IDB1,..., IDB34, IDB35 of the image data are sent. At the same time, the image data input control signal SDI becomes High. Then, the first segment driver 2-1 in FIG. 3 starts counting the number of cycles of the sampling clock SCLK simultaneously with the start of sampling the image data by the rising edge of the sampling clock SCLK. Then, when sampling the image data corresponding to the number of outputs of the segment driver × the number of gradations, for example, assuming that the segment driver has 240 outputs, the sampling clock SCLK is counted 40 times (240 lines × 6 gradation data ÷ When the 36-bit bus = 40), the first segment driver 2-1 completes the sampling of the image data and sets the image data input control signal SDO1 to the second segment driver 2-2 to High. The second segment driver 2-2 performs sampling from the image data IDB 1440, IDB 1441,..., IDB 1474, IDB 1475 in the same manner as the first segment driver 2-1, after SDO1 becomes High. Thereafter, similarly, the third, fourth,... Segment drivers 2-3, 2-4,.
[0009]
The image data sampled as described above is latched as image data for driving the liquid crystal panel 1 by a latch signal LATCH transmitted every horizontal scanning period 1H.
[0010]
FIG. 9 shows an example of a circuit configuration for performing sampling and latching of image data in a certain image data bus IDB *. 28 is a control circuit that receives the image data input control signal SDI and the sampling clock SCLK and generates a sampling timing signal of the flip-flop circuit at the next stage, and 29 (29-1 to 29-N) are flip-flops that sample the image data. (N is the number of bits of image data sampled by one image data bus IDB * in one horizontal scanning period 1H), 30 is an N bit for latching data from each flip-flop circuit 29 at the timing of the latch signal LATCH It is a latch circuit. Image data sampled at the rising edge timing of the sampling clock SCLK by the control circuit 28 and the flip-flop circuit 29 is latched in the latch circuit 30 as image data for one horizontal scanning period at the timing of the latch signal LATCH.
[0011]
As described above, in the image data transfer from the liquid crystal drive controller 6 to the segment driver 2, conventionally, sampling of image data is always performed only at the rising edge or the falling edge of the sampling clock SCLK (here, the rising edge). In this case, the sampling clock for image data requires twice as much frequency as the data transfer frequency.
[0012]
[Problems to be solved by the invention]
By the way, as the number of display colors and the definition of liquid crystal panels are increased, the transfer amount of image data from the liquid crystal drive controller to the segment driver is steadily increasing. In order to cope with the transfer of more image data, it is possible to simply increase the data transfer bus width or increase the data transfer frequency. Further, as disclosed in Japanese Patent Laid-Open No. 6-95618, it is conceivable to send image data at the timing of both rising and falling edges.
[0013]
However, if the bus width is increased, problems such as wiring routing on the printed circuit board, the number of connection cables, and an increase in connectors occur. On the other hand, increasing the clock frequency and the data transfer frequency causes problems in transmission line impedance characteristics due to unnecessary radiation noise, an increase in system power consumption, and the shape of the segment bus board 4 in FIG. In view of signal propagation delay, etc., there is a limit to increasing the frequency. Also, when sending image data at the timing of both edges, it is necessary to change the conventional data transfer format that is sent at the timing of one edge, causing problems such as the inability to use standard graphics chips. .
[0014]
An object of the present invention is to make it possible to cope with the transfer of more image data without causing the above-described problems in a matrix drive type image display device in view of the problems of the conventional technology. is there.
[0015]
[Means for Solving the Problems]
In order to achieve this object, in the matrix drive type image display device of the present invention, a display panel in which scanning signal electrodes and information signal electrodes are arranged in a matrix, and
A plurality of information signal line drivers arranged to apply information signals to the information signal electrodes;
A display drive controller for transferring image data to the plurality of information signal line drivers,
Each of the plurality of information signal line drivers is
A frequency dividing circuit receiving said sampling clock, divides the sampling clock to 1/2 times the frequency,
A first terminal for inputting a sampling clock frequency-divided by a factor of 1/2 from the frequency divider circuit, a plurality of flip-flop circuits, and a sampling clock input from the first terminal; having a first control circuit for generating a sampling timing signal of a plurality of flip-flop circuit, and a first sampling means for sampling the image data at the rise of the first sampling clock input to the terminal ,
A second terminal for inputting a sampling clock frequency-divided by a half of the frequency from the frequency divider circuit, a plurality of flip-flop circuits, and a sampling clock input from the second terminal; A second control circuit for generating sampling timing signals of a plurality of flip-flop circuits; and an inverter provided between the second terminal and the second control circuit, the second terminal and having a second sampling means for sampling the image data at the falling edge of the input sampling clock.
[0016]
According to this, the sampling of the image data, which has conventionally been performed only at the timing of either the rising edge or falling edge of the data sampling clock, is halved by the frequency dividing circuit, and the first Since the second sampling means performs the timing at both edges, the operating frequency of the circuits other than the frequency dividing circuit is ½ that of the conventional circuit, reducing the power consumption and unnecessary radiation noise of the information signal line driver. . Further, the conventional data transfer format transmitted at the timing of one edge is used as it is.
[0017]
【Example】
FIG. 1 shows an example of a circuit configuration for sampling and latching image data in one image data bus (IDB *) of a liquid crystal image display device according to an embodiment of the present invention. The system block diagram of the liquid crystal image display device is the same as the conventional FIG. The data transfer format is also the same as the conventional one shown in FIGS.
[0018]
In FIG. 1, reference numeral 18 indicates a sampling circuit that receives the sampling clock SCLK, divides it by half, and sends the divided clock SCLK2 to the control circuit at the next stage, 19-1 and 19-2 Is a control circuit that receives the control signal SDI and the sampling clock SCLK2 and generates a sampling timing signal of the flip-flop circuit at the next stage, and 20 (20-1 to 20-N) is a flip-flop circuit that samples image data ( N is the number of bits of image data sampled from one image data bus IDB * in one horizontal scanning period 1H), and 21 is an N-bit latch circuit that latches data from each flip-flop circuit 20 at the timing of the latch signal LATCH. is there.
[0019]
As shown in FIG. 8, the control circuit 19-1 and the flip-flop circuits 20-1 to 20- (N / 2) sample image data of a total of N / 2 bits at the timing of the rising edge of the sampling clock SCLK2. Do. Further, as shown in FIG. 8, the control circuit 19-2 and the flip-flop circuits 20- (N / 2 + 1) to 29-N have a total of N / 2 bits of image data at the timing of the falling edge of the sampling clock SCLK2. Sampling. The image data sampled in this way is latched by the latch circuit 21 as image data for one horizontal scanning period at the timing of the latch signal LATCH.
[0020]
Since the buffer 22 and the inverter 23 are inserted before the input of the sampling clock SCLK2 to the control circuits 19-1 and 19-2, the control circuits 19-1 and 19-2 have the same circuit configuration. Can be taken.
[0021]
According to the present embodiment, since the part other than the frequency divider circuit 18 operates with the clock signal SCLK2 having a frequency half that of the sampling clock SCLK, the power consumption necessary for the circuit operation is reduced, and unnecessary radiation noise is reduced. Can also be reduced.
[0022]
【The invention's effect】
As described above, according to the present invention, the frequency dividing circuit for halving the frequency of the sampling clock, the first sampling means for sampling the image data at the rise of the divided sampling clock, and the rising edge Second sampling means for sampling image data at the time of going down, and sampling of image data that has been performed only at the timing of either the rising edge or falling edge of the data sampling clock at the timing of both edges. As a result, the operating frequency of the circuits other than the frequency divider circuit is ½ that of the conventional circuit, and the power consumption and unnecessary radiation noise of the information signal line driver can be reduced. Further, the conventional data transfer format transmitted at the timing of one edge can be used as it is.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a circuit configuration for sampling and latching image data in one image data bus of a liquid crystal image display device according to an embodiment of the present invention.
FIG. 2 is a system block diagram of a liquid crystal image display device common to a conventional example to which the circuit configuration of FIG. 1 is applied.
3 is a connection block diagram of a segment driver of the liquid crystal image display device of FIG. 2. FIG.
4 is a signal transfer format diagram from the graphic controller to the liquid crystal drive controller of the liquid crystal image display device of FIG. 2; FIG.
5 is a reduced signal transfer format diagram from the graphic controller of the liquid crystal image display device of FIG. 2 to the liquid crystal drive controller. FIG.
FIG. 6 is a diagram illustrating a correspondence example between an image data bus and image data.
7 is an enlarged signal transfer format diagram from the liquid crystal drive controller to the segment driver of the liquid crystal image display device of FIG. 2; FIG.
8 is a timing chart of image data sampling in the circuit configuration of FIG.
FIG. 9 is a block diagram of an image sampling circuit configuration of a conventional segment driver.
[Explanation of symbols]
1: liquid crystal display panel, 2: segment driver, 3: common driver, 4: segment bus board, 5: common bus board, 6: liquid crystal drive controller, 7: image data bus, 8: image data sampling clock signal (SCLK) line , 9: Image data input control signal (SDI) line, 10: Latch signal (LATCH) line, 11: Common control signal line group, 12: Graphic controller, 13: Image data bus, 14: Image data sampling clock signal (FCLK) ) Line, 15: image data transfer enable (ENABLE) line, 16: horizontal synchronization signal (Hsync) line, 17: vertical synchronization signal (Vsync) line, 18: frequency divider circuit, 19: control circuit, 20: flip-flop circuit , 21: latch circuit, 22: buffer, 23: inverter.

Claims (1)

A display panel in which scanning signal electrodes and information signal electrodes are arranged in a matrix, and
A plurality of information signal line drivers arranged to apply information signals to the information signal electrodes;
A display drive controller for transferring image data to the plurality of information signal line drivers,
Each of the plurality of information signal line drivers is
A frequency dividing circuit receiving said sampling clock, divides the sampling clock to 1/2 times the frequency,
A first terminal for inputting a sampling clock frequency-divided by a factor of 1/2 from the frequency divider circuit, a plurality of flip-flop circuits, and a sampling clock input from the first terminal; having a first control circuit for generating a sampling timing signal of a plurality of flip-flop circuit, and a first sampling means for sampling the image data at the rise of the first sampling clock input to the terminal ,
A second terminal for inputting a sampling clock frequency-divided by a half of the frequency from the frequency divider circuit, a plurality of flip-flop circuits, and a sampling clock input from the second terminal; A second control circuit for generating sampling timing signals of a plurality of flip-flop circuits; and an inverter provided between the second terminal and the second control circuit, the second terminal matrix drive type image display apparatus characterized by having, a second sampling means for sampling the image data at the falling edge of the input sampling clock.

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