JP3243178B2 - Data transfer method and display device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a flat display and a data transfer system for driving the display device, and more particularly to a method for transferring data to a driving integrated circuit to reduce an average data transfer amount. The present invention belongs to a technical field related to a data transfer method and a display device capable of performing such operations.

[0002]

2. Description of the Related Art Conventionally, flat displays (hereinafter referred to as FP)
D: Data for F lat P annel D isplay) of the drive circuit, the display of the FPD is performed in a line sequential system or a point sequential method, it is necessary to transfer one line. That is, in the conventional display, it is required to transfer the display data in all bits in synchronization with the frame frequency. Further, the driving data of the driving integrated circuit is also updated every time display data is transferred.

FIG. 1 is a physical conceptual diagram showing a conventional data transfer system. In the figure, 1 is a display device (panel), 2 is an information line side driving integrated circuit (segment driver), 5 is a segment bus board, 7 is a data bus, 8 is a clock signal, 9 is a serial data input signal, and 10 is It is a controller.

FIG. 2 is a schematic diagram of the segment driver 2 in the conventional data transfer system of FIG. In the figure, the segment driver 2 (2-1, 2-2, 2-3,
‥‥) indicates that the video data bus 7 through which the video data IDs 0 to 7 pass and the clock line 8 through which the clock (CLK) passes are connected to the respective drivers 2-1, 2-2 and 2-3, and the serial data input signal (CSDi) Line 9 is connected to the cascade. The first segment driver 2-1 receives the serial data input signal CSDi from the controller 10. The serial data output signal a output from the first segment driver 2-1 is connected to a serial data input pin of the second segment driver 2-2, and the serial data output signal b output from the second segment driver is It is connected to the serial data input pin of the third segment driver 2-3.

FIG. 3 is a timing chart in the conventional data transfer system of FIG. FIG. 4 is a block diagram showing a driver configuration in the conventional data transfer system of FIG.

Referring to FIGS. 1 to 4, a data transfer method according to a conventional embodiment will be described. As shown in FIG. 3, the segment image data (video data) is transferred serially with an 8-bit width for all drivers, and the first data of this image data, that is, the serial data D0 to D7 is transmitted at the same time. The data input signal CSDi becomes "1". Then, the first segment driver 2-1 in FIG. 2 starts latching the image data and simultaneously counts the number of clocks. At the time when the clock CLK has counted 20 times, the fetching of the data is finished and the serial data output signal a is set to "1". Similarly, the second segment driver and the third segment driver fetch image data in the same procedure. Thereby, D0 to D159 are D160 to D31 as image data of the first segment driver.
9 is the image data of the second segment driver, D
320 to D479 are fetched as image data of the third segment driver, respectively, and the transfer of image data for one horizontal scanning period is completed.

[0007]

However, in the above-mentioned prior art, since the driving integrated circuit is not provided with the latch memory and the multiplexer circuit, the sequentially transferred data is latched only by a necessary data amount (the data of the integrated circuit). In other words, a method of storing only the holding capacity) or a method of forming one-line data by transmitting the data for the sub-scanning by n shifter integrated circuits sequentially by a shift register is adopted.

[0008] Thus, a ferroelectric liquid crystal display by the conventional method (hereinafter FLCD: F erroelectric L iq
The method also data transfer in the case of driving a display device having such a memory of the uid C rystal D isplay) had sent the data for one line.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the conventional example, and has as its object to reduce the average data transfer amount from a controller to a driver in a display device driving circuit. Reduction of the data transfer amount is expected to reduce power consumption and radiation noise.

[0010] Another object of the present invention is to provide, via a common bus,
It is an object of the present invention to provide a display device capable of transmitting two kinds of information in time series.

Another object of the present invention is to provide an IC having the same circuit configuration.
An object of the present invention is to provide a display device that can recognize the arrangement position even when using the display device.

[0012]

In order to achieve the above object, the present invention provides a chip address / video data identification circuit and a unit driver, and includes a plurality of information side driver circuits for driving a display element. In the data transfer method, a chip address and video data are transferred via a common bus line, and according to a chip address of each driver circuit set by a hardware pattern and a control signal for chip address / video data identification. The video data is selectively input to each driver circuit.

[0013] In a preferred aspect of the present invention, the display device is a flat display. The driver circuit comprises an integrated circuit having the chip address / video data identification circuit and one unit driver, and the unit driver has a plurality of pins of chip address terminals for setting its own address. Further, each unit driver has data latch means for holding previous data until receiving new data and outputting according to the data, and only data of the unit driver whose video data has changed is transferred. .
In this case, the output pin of each unit driver is divided into a plurality of blocks, and only the data of the block in which the video data has changed is transferred. Alternatively, of the output pins of each unit driver, only data between the output pin block specified by the start block signal and the output pin block specified by the end block signal is transferred.

According to the present invention, for example, the segment-side drive integrated circuit is provided with a latch circuit, a multiplexer circuit, and a chip address identification circuit, and a data transfer method with control data is used. The transfer makes it possible to reduce the average data transfer amount. That is, a driving integrated circuit of a flat display is mounted around a panel, and data transmission / reception to / from the integrated circuit is transmitted to a target driving integrated circuit by using a bus line provided around the panel. By sending data with block information / start block information / end block information) from the controller, the integrated circuit can receive target data based on the address information / control information. Therefore, the above-described concept can be realized by the controller designating and transmitting data only to the location where the data has changed.

In the conventional example, since a chip select signal is required for each chip, the number of scanning lines increases in a large-sized and high-definition display which will be developed in the future. Therefore, there is a disadvantage that the number of signal lines increases.

According to one embodiment of the present invention, in a display device driving circuit, there is provided a data transfer method in which the number of signals between a controller and a driver is reduced and the number of signals is not dependent on the resolution of the display device.

According to this aspect, a chip address / pin address identification circuit is provided, and in a data transfer method to a plurality of scanning drivers for driving a display element, a chip address and a pin address are transmitted via a common bus line. In addition to transferring in a time-division manner, a pin address is selectively input to each driver circuit according to a chip address of each driver circuit set by a hardware pattern and a control signal for chip address / pin address identification. And

[0018] Preferably, the display device is a flat display. Each of the unit drivers is a one-chip IC, and each has a chip address terminal having a plurality of pins. The chip address information is sent to each driver in one clock or two clocks.

According to this aspect, for example, an integrated circuit having a chip address / pin address identification circuit is mounted around a flat display panel, and each integrated circuit sets its own chip address by a hard pattern. The number of signals between the controller and the driver is reduced by transferring chip address information and pin address information to the target driving integrated circuit in a time-division manner using a bus line provided around the panel for data transmission / reception to the integrated circuit. Further, it is possible to cope with a panel with a higher resolution (the number of scanning lines) without increasing the number of signals between the controller and the driver.

In the prior art, the common side (scanning side) performs data transfer by a method different from that of the segment side, and does not perform data transfer on a common data line. However, there is a drawback that a large number of signal lines are required because the signal must be sent from the controller.

According to still another aspect of the present invention, in the display device driving circuit, the number of signals between the controller and the driver is reduced, and the number of signals is not dependent on the resolution of the display device. Reduce the average data transfer volume.

Therefore, in this aspect, in the data transfer method to the driver circuit for driving the display element, the data transfer to the scanning driver and the information driver is performed by the data to the scanning driver and the data to the information driver. Are transferred in a time-division manner via a common bus line.

Preferably, the display device is a flat display. Each of the scanning driver and the information driver includes one or a plurality of one-chip integrated circuits, and each of the integrated circuits has its own chip address set by a hard pattern. For example, each integrated circuit has a chip address terminal having a plurality of pins, and the chip address is set by fixing each terminal to ground (GND) or VCC. The information to the scanning driver includes chip address information and pin address information, and the information to the information driver includes chip address information and video data information. The information-side driver has data latch means for holding previous data until receiving new data and outputting in accordance with the data. The controller transfers only the driver data whose video data has changed. Further, the driver is arranged on four sides of the display device,
The common bus is formed in a ring shape.

According to this aspect, for example, a latch circuit, a multiplexer circuit and a chip address identification circuit are provided in the segment side drive integrated circuit, the segment / common line is made a common bus, and the format of data sent from the controller is provided. And the data transfer method with control data can be used to reduce the number of signals between the controller and the driving integrated circuit. At the same time, the controller controls the drive integrated circuit (especially the segment side I
By transferring only the changed data to C), it is possible to reduce the average data transfer amount. This is particularly useful for high resolution displays. That is, a driving integrated circuit of a flat display is mounted around a panel, and data transmission / reception to / from the integrated circuit is performed by using a bus line provided around the panel to transmit data with address information and control information to a target driving integrated circuit. By sending the data from the controller, the integrated circuit can receive target data based on the address information / control information. Therefore, the above-described concept can be realized by the controller designating and transmitting data only to the place where the data has changed (arbitrary segment pin address and common pin address).

In the conventional example, a pin address signal, a chip select signal, a waveform information signal, a mode setting signal, and the like are transferred by separate signal lines in the scanning driver, and a video data signal, Since the waveform information signal, the test mode signal, and the like are transferred through separate signal lines, the number of signal lines increases, resulting in an increase in cost and an increase in unnecessary radiation noise.

Also, since no latch memory for output control information is provided, and the output control information signal is connected to a plurality of drivers in parallel, only the same waveform information can be set for all the plurality of drivers. Was out.

Further, since the above-mentioned signals have separate signal structures on the scanning side and the information side, the number of signal lines is further increased.

Another aspect of the present invention has been made in view of the above-described problems in the conventional example. In a display device driving circuit, the number of signal lines connecting a controller and a scanning side or information side driver is reduced. Accordingly, it is an object to reduce cost and unnecessary radiation noise, and to transfer waveform information and the like to each of a plurality of drivers.

In this embodiment, the controller / scanning side /
The data format sent to the information side driver is shared, and the chip address information, pin address information, waveform information and mode setting information of the scanning side driver and the chip address information, video data information and waveform information of the information side driver are shared on a common bus. In addition, test mode information and control data for identifying the test mode information are added and transferred in a time-division manner.

By adopting the above data transfer method, the number of signal lines between the controller and the driver can be reduced, and at the same time, the waveform information and the mode setting information can be separately transferred for each driver. Was.

FIG. 5 shows a configuration of a general matrix type display device to which the present invention is applied and which is also a conventional example. 4, reference numeral 401 denotes a display unit for displaying an image;
02, a driving circuit for driving the scanning lines of the display unit 401; 403, a driving circuit for driving the information lines of the display unit 401; 404, a bus board for supplying power and control signals to the driving circuit 402; 405, a bus board for supplying power and control signals to the drive circuit 403;
407 denotes a power supply to be supplied to the drive circuits 402 and 403 and control means (hereinafter referred to as a controller) for generating a control signal.
Denotes a cable for supplying the power supply and control signals generated by the controller 406 to the bus board 404, and 408 denotes a cable for supplying the power supply and control signals generated by the controller 406 to the bus board 405.

The controller 406 determines the operations of the drive circuits 402 and 403 necessary to draw an intended image on the display unit based on image information transferred from a computer or the like, and transfers the determined operation to the bus boards 404 and 405. That is, control signals and a power supply necessary for image display are transmitted to the bus boards 404 and 40 by the cables 407 and 408.
5 Drive circuits 402 and 403 receive control signals and power supply relating to the operation from bus boards 404 and 405, and perform predetermined operations.

FIG. 6 shows an example of the configuration of a general driving circuit. Here, among the constituent elements shown in FIG. 6, the same elements as those described above are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 6, reference numeral 409 denotes a data bus for image data transferred from the controller 406, reference numeral 410 denotes a clock for synchronizing the timing of taking image data from the image data bus 409 into the drive circuit 403 and the operation timing in the drive circuit, that is, A clock 411 for synchronizing the operation timings of a clock counter and a latch circuit, which will be described later, is a chip select (hereinafter, referred to as CS) signal 411 for designating a drive circuit from which image data is to be captured.
Reference numeral 412 denotes an image data for one line to all drive circuits 4.
03 is a drive signal for outputting image data to the display unit all at once after the data is taken into the display unit 03.

By the way, in the configuration of the driving circuit, for example, when the number of driving circuits is increased due to a large screen or high definition, a CS for designating a driving circuit for taking in image data is used.
The number of signal lines increases, resulting in an increase in the number of control signals transferred from the controller. Further, an increase in the control signal must be avoided as much as possible because it causes noise increase such as unnecessary radiation.

Still another embodiment of the present invention has been devised to solve the above-mentioned problem, and without increasing the number of control signals from the controller, which is a concern when the number of drive circuits is increased. And means for transferring image data to the driving circuit.

In order to solve the above problem, the display device according to this aspect includes a display unit, a plurality of drive circuits for driving the display unit, and control means for generating a power supply and a control signal supplied to the drive circuit. And a power supply and a control signal generated by the control means, and a bus board for supplying the drive circuit with the power supply and a control signal. A start bit for declaring the start is attached, and a timing for taking in image data to each of the drive circuits is determined according to a hard pattern for recognizing a mounting position of the drive circuit provided on the bus board. And

According to this embodiment, when the number of drive circuits is increased,
Image data can be sequentially captured for each drive circuit without increasing the number of control signal lines, and the chip select (CS) signal from the controller is not required, which is effective in suppressing noise such as unnecessary radiation. Demonstrate.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One preferred embodiment of the present invention is a display device adopting a data transfer method for supplying a drive circuit selection signal to a drive circuit via a common bus.

Along with a drive circuit selection signal (chip address) sent via a common bus,
Scan line selection signals (pin addresses) and display data (video data) can be sent in chronological order. Further, additional information such as in-chip block selection information, scan mode information, waveform data information, test mode information, etc. can be sent via the same bus.

Another embodiment of the present invention employs a data transfer method in which a pin address and video data are supplied to a drive circuit via a common bus.

Of course, the chip address can be sent via the same bus, and additional information can be sent.

A control signal for distinguishing various types of information is supplied to each drive circuit from a line different from the bus.

FIG. 42 is a block diagram of a display device according to the former embodiment. Various kinds of information output in a time series from the controller are supplied to each drive circuit DR via a common bus. By sending a control signal synchronized with information to be transferred via a control line (not shown), the type of information passing through the common bus can be distinguished.

In another embodiment of the present invention, as shown in FIG. 43, the drive circuit is provided with means CAD for determining information on the position where the drive circuit is located.

This means CAD is desirably constituted by an external circuit of the IC chip of the drive circuit DR so that an IC chip having the same circuit configuration can be used as the drive circuit DR. Such an external circuit can be easily manufactured with a wiring pattern (hard pattern) formed on a common bus substrate, for example.

As the driving circuit, it is preferable to use an IC packaged in a tape carrier package, and the common wiring board for providing the bus may be a multilayer printed wiring board.

As a display element used in the present invention, an active matrix type liquid crystal element, a plasma display, an electron emission element, a ferroelectric liquid crystal element, and a digital micromirror device can be used.

Hereinafter, a display device adopting the data transfer method of the present invention will be described in detail with reference to each embodiment.

[0049]

【Example】

[Embodiment 1] FIG. 7 is a physical conceptual diagram showing a data transfer system of a display device driving circuit according to a first embodiment of the present invention (common-side data transfer is omitted).
FIG. 8 is a conceptual diagram showing a method of fixing the chip address of each segment driver 2 in FIG. 7 by hardware.
7 and 8, reference numeral 1 denotes a display device (FPD);
Is an information line side drive integrated circuit (segment driver), 3 is a common bus, 4 is a chip select terminal, 5 is a segment bus board, 6 is a control signal (CS), and 8 is a clock signal (C).
LK) and 10 are controllers. FIG. 9 is a schematic diagram showing a data transfer method in the circuit of FIG. FIG.
Is the segment driver 2 in the circuits of FIGS. 7 and 8.
(2-1, 2-2, 2-3,...) Explains in detail the information received, and is a diagram showing a data configuration on a 16-bit width bus and the timing of control signals. FIG.
FIG. 1 is a block diagram showing a configuration of a segment driver in the circuit of FIG.

In this embodiment, as shown in FIG. 7, a plurality of drivers 2 for driving the display device 1 are connected by the same bus 3, and each driver prints a plurality of chip address terminals 4 as shown in FIG. Ground (GND,
For example, a unique chip address is given by fixing to "0") or VCC (upper reference potential, for example, "1"). Then, the controller 10 applies chip addresses CA0 to CA7 and block select signals BS0 to BS in the data configuration shown in FIGS.
3, AS and video data are transmitted in a time-division manner. When the control signal is "1", each driver 2 compares it with its own chip address specified in advance in hardware, and when these are the same, the driver 2 uses the subsequent data as its own information. Recognize. For example, the first driver 2-1 shown in FIG. 8 has a fixed chip address "0, 0, 0, 0,
0, 0, 1, 0 ". Control signal (CS)
6 is "1", the chip address CA in the bus information
If 0 to CA7 is "0, 0, 0, 0, 0, 0, 1, 0", the first driver 2-1 recognizes that the subsequent information is video data received by itself. Here, the block select signal AS in the bus information is "0".
At this time, data according to the combination of BS0 to BS3 is transferred from the controller 10. For example, BS0-B
When S3 is "0, 1, 0, 0", 64 to 9 corresponding to the second block among the blocks obtained by dividing the 256 outputs into 8
The video data of the fifth output pin is transferred. On the other hand, when AS is "1", data for all output pins is transferred regardless of the value of BS. FIG. 12 is a table showing such a block division method.

The driver 2 holds the data until new data is sent, and drives the display device 1 according to the held data. Therefore, according to the data transfer method according to the present embodiment, it is possible to reduce the average data transfer amount by detecting the change in the video data on the controller side and transferring only the changed portion (driver unit). It is possible to apply a drive voltage to the display device 1 only for blocks whose data has been updated while contributing to reduction of power and radiation noise. The data transfer method of the present embodiment is particularly effective in a partial rewrite driving method performed in a memory device such as a ferroelectric liquid crystal, that is, a method of updating display only at a change point of video data.

Embodiment 2 FIG. 13 is a timing chart showing a data transfer method according to a second embodiment of the present invention. FIG. 14 is a block diagram of a segment driver that implements the data transfer method according to the second embodiment.
In this embodiment, a chip address is set in each segment driver as shown in FIG. Further, an output pin address is set for an output pin of the segment driver, and the controller 10 designates an output pin address for transferring data by start block information SB0 to SB3 and end block information EB0 to EB3 in addition to the chip address. I do. For example, if the control signal is "1"
Chip addresses CA0 to CA in the bus information at the time of
If 7 is "0,0,0,0,0,0,1,0", the first driver 2-1 (see FIG. 2) recognizes that the subsequent information is information received by itself. I do. At this time, SB0 to SB3 are "0, 0, 0, 0" and EB0 to EB3
Is “1,1,1,0”, the 0th block, that is, 0
The video data of the 14th block from the output pin, that is, the 239th output pin, is transferred from the controller.
Therefore, according to the data transfer method according to the second embodiment,
Data can be transferred by selecting a plurality of continuous blocks in the driver.

As described above, according to the present invention, the segment-side drive integrated circuit 2 is provided with the latch circuit, the multiplexer circuit, and the chip address identification circuit, and adopts the data transfer method with control data, thereby providing the drive integrated circuit with By transferring only the change data, the average data transfer amount can be reduced.

Further, the driver is divided into a plurality of blocks, an address is set in the output pin block,
By transferring data only to the pins specified by the start block information and the end block information, it is possible to further reduce the average data transfer amount.

By reducing the average data transfer amount in this way, it is possible to reduce the power consumption and radiation noise, and to apply the drive voltage to the display device 1 only for the block whose data has been updated. This is particularly effective in a partial rewrite driving method performed in a memory device such as a ferroelectric liquid crystal, that is, a method of updating display only at a change point of video data.

[Embodiment 3] FIG. 15 is a physical conceptual diagram showing a data transfer system of a display device drive circuit according to a third embodiment of the present invention (however, data transfer on the segment side is not shown). Omitted). FIG. 16 is a conceptual diagram showing a method of setting the chip address of each unit driver in the circuit of FIG. 15 by hardware. 15 and 16
In the figure, 101 is a bus, 102 is a scanning-side drive integrated circuit (common driver), 103 is a fixed chip address input pin, 104 is a common bus board, and 105 is a control.
, 106 is a control signal line, 107 is a clock signal (CL
K) line, 110 is a display device (panel), 111 is an information side driving integrated circuit (segment driver), and 112 is a segment bus board. FIG. 17 is a schematic diagram showing a data transfer method in the circuit of FIG.

In this embodiment, as shown in FIG. 15, a controller 108 and a driver 102 for driving a display device 101 (unit drivers 12-1, 12-2, 12-).
3) are connected by the same bus 1, and each driver 102
Represents a plurality of chip address terminals 1 as shown in FIG.
03 is fixed to ground (corresponding to GND, for example, “0”) or VCC (corresponding to the upper reference potential, for example, “1”) on the printed circuit board 104, thereby giving a unique chip address. Then, the chip address and the pin address are transferred in a time-division manner with the data configuration shown in FIG.

FIG. 18 is a diagram for explaining in detail the information received by the common driver 102 in the circuits of FIGS. 15 and 16, and is a diagram showing the data structure on the bus 101 having a width of 104 bits and the timing of control signals.

Next, the operation of the driver 102 will be described with reference to FIGS. When the control signal is “1”, each driver 102 compares data on the bus 101 with its own address specified in advance by hardware,
When these are the same, the subsequent data is recognized as its own data. For example, the driver 12 shown in FIG.
For -1, the fixed chip address "0, 0, 1, 0" is given. Information in the bus when the control signal is "H" (C
If A0-CA3) is "0,0,1,0", the driver 12-1 recognizes that the subsequent information indicates its own pin address, and starts reading the pin addresses (PA0-PA7). . As described above, according to the present embodiment, 16 × 256 = 40 using a 4-bit bus and one control signal line.
Information of up to 96 scanning lines can be transferred. By adopting the data transfer method according to the present embodiment, it becomes possible to transfer data without increasing the number of signal lines even when the number of scanning lines increases, especially for a large-screen high-definition display in the future. It is valid.

The designation of the address on the common driver side may be performed within one horizontal scanning period.
Even when 048 scanning lines are scanned at a speed of 60 Hz, the speed of the clock CLK at this time may be a slow speed of about several hundred Hz, and the transfer speed is relatively low despite the reduced number of signal lines. Can be sent at

[Embodiment 4] FIG. 19 is a timing chart showing a data transfer method according to a fourth embodiment of the present invention. The chip address is transmitted serially for two clocks with a 4-bit width. This makes it easier to cope with an increase in the number of drivers. For example, it is possible to cope with up to 256 drivers without increasing the number of signal lines.
In other words, it is possible to cope with a large-screen high-definition display of up to 256 × 256 = 65536 scanning lines.

[Embodiment 5] FIG. 20 is a timing chart showing a data transfer method according to a fifth embodiment of the present invention. FIG. 21 is a list showing a method of addressing an output pin according to a mode signal in the fifth embodiment. This method can be used, for example, on a display with 2048 physical scan lines for a lower resolution (eg, 480).
Book) Used to display a graphic mode that has nothing. When the mode setting signal is "0", the driver 102 in FIG. 15 selects output pins one by one according to the table in FIG. When the mode selection signal is "1", the controller 105 side outputs the least significant bit P of the pin address signal.
The chip address is transmitted ignoring A7, and the driver selects two pins at a time according to the table of FIG. Of course, this method is also applicable to simultaneous selection of four or eight lines.

As described above, by using a data format with control data as the data format sent from the controller, it is possible to reduce the number of signals between the controller and the driving integrated circuit.

The present invention can easily cope with an increase in the number of scanning lines, that is, an increase in the number of drive integrated circuits (especially, common-side ICs), and is particularly effective for a high-resolution display.

[Embodiment 6] FIG. 22 is a physical conceptual diagram showing a data transfer system of a display device driving circuit according to a sixth embodiment of the present invention. FIG. 23 is a conceptual diagram showing a method of fixing the chip addresses of the segment driver and the common driver in the circuit of FIG. 22 by hardware. FIG.
23 and FIG. 23, reference numeral 201 denotes a display device (FDP);
202 is a segment driver, 203 is a common driver, 204 is a common bus, 205 is a chip address terminal,
206 is a bus board, 207 is a control signal line, 208 is a controller, and 210 is a clock signal (CLK) line. FIG. 24 is a schematic diagram showing a method of transferring data to the segment driver 202 in the circuit of FIG.

In this embodiment, as shown in FIG. 22, the controller 208 and the drivers 202 and 203 for driving the display device 201 are connected by the same bus 204, and FIG.
A chip address, a pin address, video data, and a data identification signal are transferred in a time-division manner in the data configuration shown in FIG. Then, the designation of the output pins of the common driver 203 and the transfer of the video information of the total number (or the changing points) of the segment drivers 202 are completed within one horizontal scanning period,
The display device 201 is driven.

FIG. 25 shows the common driver 203 (203-1, 203-2, 203-1) in the circuits of FIGS.
203-3, ‥‥) is a diagram for explaining in detail the information received, and is a diagram showing the data configuration on the 16-bit width bus 204 and the timing of control signals.

Next, the operation of the common driver 203 will be described with reference to FIGS. Here, the common driver 203 that needs to specify an output pin address for various kinds of interlace scanning and the like will be described. When the control signal is “1”, each common driver 203
Recognizes data on the bus 204 as chip address information. As shown in FIG. 23, each common driver 203 connects a plurality of chip address terminals 205 to ground (corresponding to GND, eg, “0”) or VCC (corresponding to an upper reference potential, eg, “1”) on a printed circuit board 206. , A unique chip address is given. When the chip address data on the bus 204 is the same as its own chip address, the common driver 203 recognizes the subsequent data as its own pin address information and takes it in. According to the data transfer method of the present embodiment for transferring each pin address information in this manner,
Even when the number of scanning lines increases, data can be transferred without increasing the number of signal lines, which is particularly effective for future large-screen high-definition display.

FIG. 26 shows the segment driver 202 (202-1, 202-) in the circuits of FIGS. 22 and 23.
2, 202-3,...) Is a diagram illustrating in detail the information received by the bus 204 and the timing of control signals on a bus 204 having a width of 16 bits. FIG.
FIG. 23 is a block diagram showing a configuration of a segment driver in the circuit of FIG.

Next, the operation of the segment driver 202 will be described with reference to FIGS. When the control signal is “1”, each segment driver 202 recognizes the data on the bus 204 as chip address information. Each segment driver 202 connects a plurality of chip address terminals 205 to the ground (GND, for example, “0”) on the printed circuit board 206 as shown in FIG.
) Or VCC (upper reference potential, eg, “1”)
), A unique chip address is given. When the chip address data on the bus 204 is the same as its own chip address, the segment driver 202 recognizes the subsequent data as its own video data information. When data of, for example, 10 clocks is transferred with a bus width of 16 bits, transfer of video data of 160 bits is completed. Segment driver 202
Holds the data until new data is sent, and drives the display device according to the held data. Therefore, according to the data transfer method according to the present embodiment, it is possible to reduce the average data transfer amount by detecting a change in the video data on the controller side and transferring only the changed portion (driver unit). And contributes to reduction of power consumption and radiation noise.

[Embodiment 7] FIG. 28 is a physical conceptual diagram showing a data transfer system according to a seventh embodiment of the present invention.
That is, in the drive circuit of the seventh embodiment, the common driver 203 is disposed on the left and right of the display device 201, and the segment driver 202 is disposed on the upper and lower sides of the display device 1 so as to surround four sides of the display device 201. Are connected by a bus line 204. According to the seventh embodiment, even when the number of scanning lines is large enough to require bus boards (printed boards) 206 on four sides of the display device 201,
The number of signal lines from 8 does not change, and wiring can be extremely space-saving. In addition, 4 of the display device 201
The bus board 206 is arranged in a ring on the side, and each driver 2
02 and 203 and the controller 208 are connected by the same bus line 204, so that a connection point with the controller 208 can be provided at an arbitrary position on the bus line 204, and the connectivity with the outside is enhanced.

As described above, according to the present invention, the segment signal line and the common signal line are made a common bus, the data format sent from the controller is shared, and the data transfer method with control data is adopted. , And the number of signals between the driving integrated circuits can be reduced.

Further, the driving integrated circuit (particularly, the segment side I
By transferring only the change data to C), the average data transfer amount can be reduced.

Further, the driving integrated circuit (especially the common side I
It is possible to easily cope with an increase in the number C), and it is particularly effective for a high-resolution display.

Further, by arranging the bus lines in a ring shape, it is possible to provide a connection point with the controller at an arbitrary position on the bus line, thereby improving the connectivity with the outside.

[Eighth Embodiment] FIG. 29 is a physical conceptual diagram showing a display device driving circuit according to an eighth embodiment of the present invention.
0 is a schematic diagram showing a method of fixing the chip addresses of the information side driver 302 and the scanning side driver 303 in the circuit of FIG. 29 by hardware. In the figure, 301
Is a display device (panel), and 302 is an information side (segment).
A driver 303, a scanning side (common) driver, 304
Is a common bus, 305 is a chip select terminal, 306 is a bus board (printed board), 307 is a clock signal, 308
Is a controller, and 309 is a control signal.

FIG. 31 is a schematic diagram showing a data transfer method in the circuit of FIG. FIG. 32 is a diagram showing a data format of the scanning driver 303 in the circuit of FIG. FIG. 33 is a diagram showing a data format of the information side driver 302 in the circuit of FIG. FIG. 34 is a diagram showing a configuration of a data identification signal in the circuit of FIG. FIG. 35 is a block diagram showing a configuration of the information side driver 302 in the circuit of FIG.

As shown in FIG. 29, drivers 302 and 303 for driving a display device 301 are connected by the same bus 304, and chip address information, pin address information, and video data having the data configuration shown in FIGS. Data information, data identification signal, waveform information, mode setting information,
Then, test mode information is added and transferred in a time-division manner.

The control signal of the scanning driver 303 is "1".
At this time, the data on the bus 304 is recognized as the chip address information and the data identification signal. Each scanning side driver 3
03 denotes a plurality of chip address terminals 3 as shown in FIG.
05 is fixed to ground (GND) or VCC (upper reference potential) on the printed circuit board 306 to give a unique chip address. When the chip address data on the bus 304 is the same as its own chip address, the scanning driver 303 recognizes that the subsequent information is its own information. Also, the combination of the data identification signals sent simultaneously with the chip address, ie, FIG.
According to the table shown in FIG. 4, it is determined whether the subsequent information is pin address information, scanning mode information, or waveform information, and is taken in. When the data received at this time is the pin address information, the scanning driver 303 scans from the output pin designated by the pin address information the scanning mode information and the waveform information, that is, the voltages according to the correspondence tables of FIGS. 36 and 37. It is applied to the display device 301. At this time, the scanning mode information and the waveform information retain the previous information until new information is sent, and output according to the information.

The information side driver 302 sets the control signal to “1”.
At this time, the data on the bus is recognized as the chip address information and the data identification signal. As shown in FIG. 30, each information-side driver 302 connects a plurality of chip address terminals 305 to ground (GND) or V on a printed circuit board 306.
A unique chip address is given by fixing to CC (upper reference potential). When the chip address data on the bus 304 is the same as its own chip address, the information side driver 302 recognizes that the subsequent information is its own information. In addition, according to a combination of data identification signals sent simultaneously with the chip address, that is, a table shown in FIG. 34, it is determined whether the subsequent information is video data information, waveform information, or test mode information, and fetched. If the data received at this time is video data information, the information side driver 302 receives the video data for its own output pin, and then outputs the waveform information and the test mode information, that is, the voltage according to the correspondence table of FIG. The signal is applied to the display device 301 in synchronization with the waveform control clock signal. At this time, the waveform information retains the previous information until new information is sent, and outputs according to this.

By performing the above data transfer to all the drivers 302 and 303 on the scanning side and the information side within one horizontal scanning period, the data transfer within one horizontal scanning period is completed. In addition, the mode setting signal and the waveform information signal are transferred using a pause period during which scanning is not performed. For example, in a display device having 1024 scanning lines, even if the mode setting signal or the waveform information signal is updated once while one screen is refreshed, it is only interrupted once every 1024, which has no effect on the display quality. I will not give.

As described above, according to the present invention, the data format sent from the controller to the scanning side / information side driver is shared, and the chip address information, pin address information and waveform information of the scanning side driver are shared on a common bus. And a data transfer method in which the mode setting information, the information side driver's chip address information, video data information, waveform information, test mode information, and control data for identifying these are loaded and transferred in a time-division manner, so that the data transfer between the controller and the driver is performed. The number of signal lines can be reduced to reduce the proportion of cables and printed circuit boards occupying the housing, thereby contributing to downsizing of the housing and cost reduction. In addition, the reduction in the number of signal lines contributes to a reduction in radiation noise. Furthermore, it is also possible to transfer waveform information and mode setting information separately for each driver and output an arbitrary waveform for each driver.

[Embodiment 9] FIG. 38 shows the structure of a drive circuit according to a ninth embodiment of the present invention. In FIG. 38, FIG.
Elements that are the same as or correspond to those in the conventional example of FIG. 6 are denoted by the same reference numerals, and description thereof is omitted. In FIG. 38, 4
13 (413a, 413b, 413c) are the driving circuits 4
This is a CS signal based on a hard pattern on the bus board 405 for causing the drive circuit itself to recognize the mounting position (chip address) of the 03 (403a, 403b, 403c).

FIG. 39 shows a specific configuration example of the drive circuit 403. In the figure, reference numeral 414 denotes each drive circuit 403 based on a start bit (SB) signal transferred from the controller and mounting position information obtained from the bus board.
a clock count number setting circuit for calculating the clock count number until the start of the image data capture of a, 403b, and 403c, and setting the count number in the counter; 415 counts the count number set by the clock count number setting circuit 414; After the count is completed, a first latch circuit 417, which will be described later,
A counter 416 for enabling the AND circuit 416 ANDs the clock and an enable signal output from the clock counter 415 and outputs the result to a first latch circuit described later.
The first latch circuit 418 sends the image data to the next-stage latch circuit 418 after the image data is sequentially taken in from the data bus in synchronization with the signal sent from the data bus 6.
A second latch circuit receives image data from the first latch circuit 417, causes each drive circuit to capture one line, and then sends out the image data all at once.

FIG. 40 shows a timing chart of the drive circuit of FIG. 40A shows image data flowing through the data bus 409, FIG. 40B shows enable signals output from the clock counter units 415a to 415c in the driving circuits 403a to 403c, and FIG. 40C shows output signals from the AND circuit 416. The synchronizing signals for image data capture of the first latch circuit 417, (d) and (e) are the first latch circuits 417a to 417a.
c and the second latch circuits 418a to 418c capture the image data.

The principle of operation of a device in which the driving circuits shown in FIGS. 38 and 39 are applied to the image display device shown in FIG. 5 will be described below. Here, it is assumed that the bus width of the image data bus 409 is 408 bits, and the image data captured by one driving circuit is 160 clocks.

The start bit SB transferred from the controller 406 is input to the clock count number setting circuit 414 of each drive circuit via the data bus 409. On the other hand, mounting position (chip address) information 413 of the drive circuit is input to the clock count number setting circuit 414 from the hardware pattern of the bus board 405. The clock count number setting circuit 414 calculates a timing at which the drive circuit starts capturing image data from the data bus 409 from the two types of input signals. For example, the driving circuit 4 in FIG.
Considering the cases 03a-c, the clock count number setting circuit 4 of the drive circuit 403a receiving the start bit
14 recognizes from the mounting position information 413a from the bus board that the image data after the start bit is to be taken in by itself, and immediately outputs an enable signal from the clock counter unit 415a. The AND circuit 416a receives the enable signal and generates a data latch signal of the first latch circuit 417a in synchronization with the clock 410. The first latch circuit 417a receives the signal output from the AND circuit 416a and receives the signal output from the data bus 409a.
The data is taken in sequentially from. This operation is completed by resetting the enable signal after the clock counter 415a has counted 160 clocks. 1
At the end of storing 60 counts of image data,
The data is transferred to the latch circuit 418a, and the data is kept held until a drive signal is input from the controller. When the start bit SB is input to the clock count number setting circuit 414b, the drive circuit 403b
Recognizing its own mounting position information 413b, after inputting the start bit SB, it is determined that the data from the 161th count is image data to be captured by itself, and the clock count number 160 until the capture is started is stored in the clock count unit 414b. set. The clock count unit 414b counts the set clock count number, and after the count is completed, fetches the image data from the data bus 409 in the same procedure as the drive circuit 403a. Hereinafter, the same operation is performed for each drive circuit. After the capture of the image data into all the drive circuits is completed, the drive signal from the controller is input to all the second latch circuits 418a to 418c, and the data is simultaneously transmitted to the display unit 401.

As described above, the hardware for transferring the image data sent from the controller 406 with the start bit added thereto at the beginning and for allowing the drive circuit itself to recognize the mounting position of the drive circuit on the bus board 5. By providing a pattern and determining the timing of fetching image data based on the information, the drive circuit itself does not require a CS signal from the controller. Thus, even if the number of driving circuits increases, each driving circuit can capture image data without increasing the number of control signals such as CS.

[Embodiment 10] FIG. 41 shows a configuration example of a drive circuit according to a tenth embodiment of the present invention. A feature of the tenth embodiment is that, in addition to the configuration shown in FIG. 40, a signal for designating a driving circuit to start capturing image data is set in a start bit, and a signal is provided at a stage preceding the clock count number setting circuit 414 in the driving circuit. Another point is that an image data capture start determination circuit 419 for determining where the drive circuit that starts capture is, or from which clock the image data capture is started is provided.

Receiving start determination circuits 419 of all the driving circuits 403 receiving the start bit SB determine from which driving circuit the image data to be transmitted is to be started, and use that information as the clock count of the next stage. The number is transmitted to the number setting circuit 414. Clock count number setting circuit 41
4, a clock counter is used to count the number of clocks until the start of image data capture from the data bus 409, based on the drive circuit information for starting the capture of image data and the mounting position information 413 of the hardware pattern on the bus board 405. Set in the section 415. Subsequent operations are described in the ninth embodiment.
This is the same as the embodiment.

As described above, in addition to the effects described in the ninth embodiment, the image data transfer from the controller is a portion requiring rewriting, and the efficiency of image transfer to the data bus can be improved.

As described above, according to the present invention, the start bit is added to the head of the image data sent from the controller, and the drive circuit itself recognizes the mounting position of the drive circuit on the bus board. By providing a hard pattern for the drive circuit and a circuit for determining the timing of fetching image data based on the information by the drive circuit itself,
There is no need to supply signals from the controller. This makes it possible to form a system that allows each drive circuit to capture image data without increasing the number of control signals such as CS even when the number of drive circuits is increased. In addition, since an increase in the number of control signal lines is suppressed, it is effective from the viewpoint of suppressing noise such as unnecessary radiation.

Further, a signal for designating a drive circuit to start reading image data is set in the start bit,
In addition, the drive circuit is provided with a circuit for determining where the drive circuit that starts capturing is located at a stage preceding the clock count number setting circuit, so that image data transfer from the controller can be performed from a portion requiring rewriting. The efficiency of image transfer to the data bus can be improved.

[Brief description of the drawings]

FIG. 1 is a physical conceptual diagram showing a conventional data transfer method.

FIG. 2 is a schematic diagram showing a conventional data transfer method.

FIG. 3 is a timing chart showing a conventional data transfer method.

FIG. 4 is a diagram showing a configuration of a segment driver in a conventional data transfer method.

FIG. 5 is a physical conceptual diagram showing a configuration of a general image display device.

FIG. 6 is a block diagram corresponding to FIG. 1 showing a configuration of a conventional driving circuit.

FIG. 7 is a physical conceptual diagram showing a data transfer method according to a first example of the present invention.

FIG. 8 is a conceptual diagram showing a method of giving a chip address by hardware in the first embodiment of the present invention.

FIG. 9 is a schematic diagram showing a data transfer method according to the first embodiment of the present invention.

FIG. 10 is a timing chart showing a data transfer method according to the first embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of a segment driver according to the first embodiment of the present invention.

FIG. 12 is a table showing a block division method in the data transfer method according to the first embodiment of the present invention.

FIG. 13 is a timing chart showing a data transfer method according to a second embodiment of the present invention.

FIG. 14 is a diagram illustrating a configuration of a segment driver according to a second embodiment of the present invention.

FIG. 15 is a physical conceptual diagram showing a data transfer method according to a third embodiment of the present invention.

FIG. 16 is a conceptual diagram showing a method of giving a chip address by hardware in the third embodiment of the present invention.

FIG. 17 is a schematic diagram illustrating a data transfer method according to a third embodiment of the present invention.

FIG. 18 is a timing chart showing a data transfer method according to a third embodiment of the present invention.

FIG. 19 is a timing chart showing a data transfer method according to a fourth embodiment of the present invention.

FIG. 20 is a timing chart showing a data transfer method according to a fifth embodiment of the present invention.

FIG. 21 is a table showing an addressing method in a data transfer method according to a fifth embodiment of the present invention.

FIG. 22 is a physical conceptual diagram showing a data transfer method according to a sixth embodiment of the present invention.

FIG. 23 is a conceptual diagram showing a method of giving a chip address in hardware according to the sixth embodiment of the present invention.

FIG. 24 is a schematic diagram illustrating a data transfer method according to a sixth embodiment of the present invention.

FIG. 25 is a timing chart showing a data transfer method of a common driver according to a sixth embodiment of the present invention.

FIG. 26 is a timing chart showing a data transfer method of a segment driver according to a sixth embodiment of the present invention.

FIG. 27 is a circuit diagram showing a configuration of a segment driver according to a sixth embodiment of the present invention.

FIG. 28 is a physical conceptual diagram showing a data transfer method according to a seventh embodiment of the present invention.

FIG. 29 is a physical conceptual diagram showing a display device driving circuit employing a data transfer method according to an eighth embodiment of the present invention.

30 is a schematic diagram showing a method of fixing the chip address of each driver in the circuit of FIG. 29 by hardware.

FIG. 31 is a schematic diagram showing a data transfer method in the circuit of FIG. 29;

32 is a diagram showing a data format of a scanning driver in the circuit of FIG. 29.

FIG. 33 is a diagram showing a data format of an information side driver in the circuit of FIG. 29.

FIG. 34 is a diagram showing a configuration of a data identification signal in the circuit of FIG. 29.

FIG. 35 is a block diagram showing a configuration of an information side driver in the circuit of FIG. 29;

FIG. 36 is a correspondence table showing a relationship between a combination of waveform information signals and an output voltage in a scanning driver of a conventional data transfer method.

FIG. 37 is a correspondence table showing a relationship between a combination of test mode signals and an output voltage in the information side driver of the conventional data transfer method.

FIG. 38 is a block diagram illustrating a configuration of a drive circuit according to a ninth embodiment of the present invention.

FIG. 39 is a block diagram showing a more specific configuration of the drive circuit of FIG. 38.

40 is a timing chart showing the operation of the drive circuit of FIG.

FIG. 41 is a block diagram corresponding to FIG. 2 and illustrating a configuration of a drive circuit according to a tenth embodiment of the present invention.

FIG. 42 is a diagram showing a display device employing the data transfer method of the present invention.

FIG. 43 is a diagram showing a display device employing the data transfer method of the present invention.

[Explanation of symbols]

1: display device (panel), 2: information line side driving integrated circuit (segment driver), 3: common bus, 4: chip select terminal, 5: segment bus board, 6: control signal,
7: data bus, 8: clock signal, 9: serial data input signal, 10: controller, 101: bus, 10
2: scan line side drive integrated circuit (common driver), 10
3: fixed chip address input pin, 104: common bus board, 105: controller, 106: control signal line, 1
07: clock signal line, 108: chip select signal line, 109: pin address signal bus, 110: display device (panel), 111: information line side driving integrated circuit (segment driver), 112: segment bus substrate, 201:
Display device (panel), 202: information line side driving integrated circuit (segment driver), 203: scanning line side driving integrated circuit (common driver), 204: common bus, 205: chip select terminal, 206: bus board, 207: Control signal line, 208: controller, 209: data bus, 210: clock signal line, 301: display device (panel), 302: information side (segment) driver,
303: scanning side (common) driver, 304: common bus, 305: chip select terminal, 306: bus board (printed board), 307: clock signal, 308: controller, 309: control signal, 401: display unit, 40
2: scan line drive circuit, 403, 403a to c: information line drive circuit, 404: scan line bus board, 40
5: information line bus board, 406: controller, 4
07, 408: cable, 409: data bus, 41
0: clock, 411: CS signal, 412: drive signal, 413: CS signal by hard pattern, 414:
Clock count number setting circuit, 415: clock counter section, 416: AND circuit, 417: first latch circuit,
418: Second latch circuit.

──────────────────────────────────────────────────続 き Continued on the front page (31) Priority claim number Japanese Patent Application No. 7-131183 (32) Priority date May 2, 1995 (5.2.1995) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 7-132643 (32) Priority date May 8, 1995 (5.8.1995) (33) Priority claim country Japan (JP) (72) Inventor Kenzo Ina 3-30-2 Shimomaruko, Ota-ku, Tokyo Within Canon Inc. (56) References JP-A-7-210121 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3 / 20 G09G 3/36 G06F 12/00-12/06

Claims (88)

(57) [Claims] 1. A data transfer method for driving a ferroelectric liquid crystal display element, comprising a chip address / video data identification circuit and a unit driver, to a plurality of information side driver circuits, wherein a chip address and video data are transmitted. In addition to the transfer via the common bus line, the chip address of each driver circuit and the chip address /
A data transfer method characterized by selectively inputting the video data to each driver circuit in response to a control signal for video data identification. 2. The data transfer system according to claim 1, wherein each of said driver circuits comprises an integrated circuit chip having said chip address / video data identification circuit and one unit driver, and each of said driver circuits has a plurality of pins. A data transfer method comprising a chip address terminal. 3. The data transfer method according to claim 1, wherein said unit driver has data latch means for holding previous data until receiving new data and outputting according to the data. Transfer method. 4. The data transfer method according to claim 1, wherein only the data of the unit driver whose video data has changed is transferred. 5. The data transfer method according to claim 4, wherein output pins of said unit driver are divided into a plurality of blocks, and only data of a block whose video data has changed is transferred. Transfer method. 6. The data transfer method according to claim 4, wherein only the data between the output pin block specified by the start block signal and the output pin block specified by the end block signal among the output pins of the unit driver. A data transfer method characterized by transferring. 7. A data transfer method for driving a ferroelectric liquid crystal display device, comprising a chip address / pin address identification circuit, and a plurality of scan-side drivers, wherein a chip address and a pin address are shared by a common bus line. And time-division transfer via the CPU, and selectively input a pin address to each driver circuit in accordance with a chip address of each driver circuit set by a hardware pattern and a control signal for identifying chip addresses / pin addresses. A data transfer method. 8. The data transfer method according to claim 7, wherein said driver circuit has a chip address terminal having a plurality of pins. 9. The data transfer method according to claim 7, wherein said chip address is sent in one clock. 10. The data transfer method according to claim 7, wherein
The chip address is transmitted in two clocks. 11. A data transfer method to a driver circuit for driving a ferroelectric liquid crystal display element, wherein data transfer to a scanning driver and an information driver is performed by transferring data to the scanning driver and data to the information driver. And a time-division transfer via a common bus line. 12. The data transfer method according to claim 11, wherein the scanning driver and the information driver are:
A data transfer method having a chip address set by a hard pattern. 13. The data transfer method according to claim 11, wherein the data to said scanning driver comprises a chip address and a pin address. 14. The data transfer method according to claim 11, wherein the data to said information side driver comprises a chip address and video data. 15. The data transfer method according to claim 11, wherein said scanning driver and said information driver have a plurality of pins of chip address terminals. 16. The data transfer method according to claim 11, wherein said information-side driver has data latch means for retaining previous data until receiving new data and outputting in accordance with the data. Data transfer method to use. 17. The data transfer method according to claim 11, wherein only data of a driver whose video data has changed is transferred. 18. The data transfer method according to claim 11, wherein the driver circuits are arranged on four sides of the display element, and the common bus is formed in a ring shape. 19. A controller for generating drive information,
And a scanning driver for driving a ferroelectric liquid crystal display element upon receiving the driving information from the controller, wherein the scanning is performed as driving data from the controller to the scanning driver. A data transfer method for a display device, wherein a chip address, an output pin address and control information of a side driver are transferred in a time-division manner. 20. The data transfer method according to claim 19, wherein said control information includes output waveform information. 21. The data transfer method according to claim 19, wherein said control information includes scanning mode information. 22. The data transfer method according to claim 19, wherein said scanning side driver has a chip address set by a hardware pattern. 23. The data according to claim 19, wherein said scanning side driver has latch means for holding previous output control information until receiving new output control information and outputting according to the output control information. Transfer method. 24. A controller for generating drive information,
In a data transfer method of a display device having an information side driver for driving a ferroelectric liquid crystal display element in response to the drive information from the controller, the information transfer method includes a step of driving data from the controller to the information side driver. A data transfer method for a display device, wherein a chip address, video data, and control information of a driver are transferred in a time-division manner using a bus line. 25. The data transfer method according to claim 24, wherein said control information includes output waveform information. 26. The data transfer method according to claim 24, wherein said control information includes test mode information. 27. The data transfer method according to claim 24, wherein the information-side driver has a chip address set by a hardware pattern. 28. The data according to claim 24, wherein the information-side driver has latch means for holding previous output control information until receiving new output control information and outputting in accordance with the output control information. Transfer method. 29. A display device data transfer method comprising the scanning driver according to claim 19 and the information driver according to claim 24. 30. A ferroelectric liquid crystal display, a plurality of drive circuits for driving the display, control means for generating power and control signals supplied to the drive circuit, and a control means for generating the control signal. And a bus board for supplying the supplied power and control signal to the drive circuit, wherein a start bit for declaring the start of transfer is added to the head of the image data transferred from the control means. A data transfer method for determining a timing at which image data is taken into each of the drive circuits according to a hardware pattern for recognizing a mounting position of the drive circuit provided on the bus board. 31. The data transfer method according to claim 30, wherein information for designating a drive circuit to start capturing image data is added to said start bit. 32. A liquid crystal display device comprising: a ferroelectric liquid crystal display element; and a plurality of drive circuits for driving the element, wherein the plurality of drive circuits select one of the plurality of drive circuits. A display device having a circuit for supplying a circuit selection signal through a common bus. 33. Each drive circuit has means for setting information on a position where the drive circuit is arranged.
2. The display device according to 2. 34. The device according to claim 3, wherein said means is a wiring pattern.
3. The display device according to 3. 35. The display device according to claim 33, wherein the means is provided outside the driving circuit. 36. The display device according to claim 33, wherein said means is provided on a common wiring board. 37. The display device according to claim 32, wherein the drive information signal is supplied via the bus. 38. The display device according to claim 37, wherein the drive information signal is video data. 39. The display device according to claim 37, wherein the driving information signal is a scanning line selection signal. 40. The display device according to claim 37, wherein a control signal for determining the drive information signal and the drive circuit selection signal is supplied from a line different from the bus. 41. The display device according to claim 40, wherein the line sends a 1-bit control signal. 42. The display device according to claim 40, wherein the bus has a bus width of 16 bits or more. 43. The display device according to claim 32, wherein a block selection signal is sent via the bus. 44. The display device according to claim 32, wherein scanning mode information is transmitted via the bus. 45. The display device according to claim 32, wherein the waveform data information is transmitted via the bus. 46. The display device according to claim 32, wherein test mode information is transmitted via said bus. 47. The display device according to claim 32, wherein a clock signal is sent to the drive circuit via another line. 48. The display device according to claim 32, wherein a drive signal is sent to the drive circuit via another line. 49. The display device according to claim 32, wherein each drive circuit is a one-chip IC. 50. The display device according to claim 32, wherein each drive circuit includes a latch circuit. 51. The display device according to claim 32, wherein each drive circuit includes a position information detection circuit. 52. The display device according to claim 51, wherein said position information detection circuit is a clock count number setting circuit. 53. The display device according to claim 51, wherein said position information detection circuit is a comparator. 54. Each drive circuit includes a decoder.
2. The display device according to 2. 55. Each driving circuit includes an AND circuit that receives an output of the bus and a control signal as inputs, a comparator that compares the output of the AND circuit with position information, and an output of the comparator. 33. An AND circuit for inputting an output of the bus.
The display device according to the above. 56. The display device according to claim 32, wherein the plurality of drive circuits are formed of two types of one-chip ICs. 57. The display device according to claim 56, wherein one of the plurality of driving circuits is a scanning driver and the other is an information driver. 58. The display device according to claim 57, wherein the video data and the scanning line selection signal are transmitted in time series via the bus. 59. A liquid crystal display device comprising: a ferroelectric liquid crystal display element; a plurality of drive circuits for driving the element; and a common wiring board connected to the plurality of drive circuits. And a circuit for supplying a drive circuit selection signal for selecting one of the plurality of drive circuits and a drive information signal to be supplied to the selected drive circuit to the plurality of drive circuits in a time series. apparatus. 60. The display device according to claim 59 , wherein the drive circuit has a circuit for detecting information on a position where the drive circuit is located. 61. The display device according to claim 59 , wherein any one of scan mode information, waveform data information, and test mode information is further supplied to said bus. 62. A ferroelectric liquid crystal display element, a plurality of drive circuits for driving the display element, and a common wiring board connected to the plurality of drive circuits, wherein a bus of the common wiring board is provided. Via, a scanning line information signal for selecting a scanning line, display data supplied to the information line,
A display device having a circuit for supplying a drive circuit selection signal for selecting a drive circuit to the plurality of drive circuits in time series. 63. A liquid crystal display device comprising: a ferroelectric liquid crystal display element; a plurality of drive circuits for driving the display element; and a common wiring board connected to the plurality of drive circuits. A circuit for emitting the arranged position information, wherein a scan line information signal for selecting a scan line and display data supplied to the information line are time-sequentially connected via a bus of the common wiring board. A display device having a circuit for supplying a plurality of driving circuits. 64. A liquid crystal display device comprising: a ferroelectric liquid crystal display element; a plurality of drive circuits for driving the element; and a common wiring board connected to the plurality of drive circuits. A display device provided with means for determining position information at which the drive circuit is arranged. 65. The means is a wiring pattern.
64. The display device according to 64 . 66. The display device according to claim 64 , wherein the drive circuit has a circuit for detecting a drive circuit selection signal. 67. The drive circuit processes a drive information signal based on a drive circuit selection signal and the position information.
64. The display device according to 64 . 68. plurality of driver circuits, the display device according to claim 59 or 64, wherein the information-side driver. 69. The display device according to claim 59 , wherein said drive information signal is video data. Wherein 70] said plurality of driver circuits, the display device according to claim 59 or 64, wherein comprising a decoder and a latch circuit. 71. the common the driving circuit via the one-bit line of the wiring board selection signal and the driving information signal and claim wherein the supplying control signals to determine to the drive circuit 59 or 6
5. The display device according to 4 . 72.] claim 59 or 64 having a circuit for comparing the position information of the driving circuit selection signal and the driving circuit
The display device according to the above. 73. the common wiring board to the drive Claim electric circuit is provided for determining the position information of the circuit 59 or
64. The display device according to 64 . 74.] plurality of drive circuits display device according to claim 59 or 64, wherein the scanning-side driver. 75. plurality of drive circuits display device according to claim 59 or 64, wherein the scanning-side and data-side driver. 76. The display device according to claim 59 , wherein the driving information signal is a scanning line information signal. 77. The display device according to claim 59, wherein said drive information signal is a scan line information signal and video data. 78. via line 1 bit the common wiring board, the driving circuit selection signal and wherein supplying a control signal for discriminating the scanning line information signal to the plurality of driving circuit 59.
64. The display device according to 64 . 79. A parallel with the driving circuit selection signal, the display device according to claim 59 or 64, wherein supplying a block selection information for selecting information line block in the drive circuit. Wherein 80] the common wiring board display device according to claim 59 or 64, wherein a multilayer wiring board. 81. The drive circuit 1 display device according to claim 59 or 64 wherein the chip IC. [82.] The drive circuit display device according to claim 59 or 64, wherein a one-chip IC which is a tape carrier package. 83.] The driving circuit includes at least claim 59 also <br/> are provided at two sides adjacent square display element display device 64 according. 84. The driving circuit includes a rectangular display element.
The display device of claim 59 or 64, wherein is provided on the sides. 85. A display device according to claim 59 or 64, wherein a wiring pattern to determine the position information of the drive circuit. 86. On the wiring pattern, the first reference potential or a different second display device according to claim 59 or 64, wherein the reference potential is given. 87. A plurality of integrated circuits each including the same drive circuit, and a common wiring board connected to the plurality of integrated circuits, wherein each of the integrated circuits is selected via a common bus of the common wiring board. A data transfer device for transferring data to be supplied to a ferroelectric liquid crystal display element in a time-series manner, wherein the common wiring board is provided with means for electrically determining information for identifying each integrated circuit. are provided, each integrated circuit in response to the information, the ferroelectric liquid crystal display, characterized by selectively input the data from the common bus
Data transfer device to the device. 88. ferroelectric of the means according to claim 87, wherein it is a different wiring patterns in each integrated circuit
For transferring data to a liquid crystal display element .