JP3941440B2 - Electro-optical device, manufacturing method thereof, and projection display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
According to the present invention, an electro-optical material is sandwiched between a pair of first and second substrates bonded together by a sealing material around an image display region, and provided on the side of the substrates facing the electro-optical material. The present invention belongs to the technical field of an electro-optical device such as a liquid crystal device having a pair of electrodes and a method for manufacturing the same.
[0002]
[Background]
In general, in this type of electro-optical device, a pixel electrode, a thin film transistor (hereinafter, referred to as a TFT (Thin Film Transistor)) that controls switching of the pixel electrode, a data line connected to the pixel electrode, an image signal and a scanning signal, a scanning line, etc. The TFT array substrate provided with the wiring and the like is provided. Further, the TFT array substrate is disposed opposite to the side on which the wiring or the like is disposed, and includes a counter substrate having a counter electrode provided on the entire surface in addition to a color filter, a light shielding film, and the like. These TFT array substrate and counter substrate are bonded together by a sealing material in a seal region located around the image display region, and an electro-optical material such as liquid crystal is sandwiched between the substrates. Further, a conductive vertical conductive material is sandwiched between vertical conductive regions (that is, regions such as vertical conductive pads and corners of the counter substrate) provided on both substrates outside the seal region. By this vertical conductive material, the wiring for supplying a fixed or inverted counter electrode potential provided on the TFT array substrate side and the counter electrode are electrically connected. In operation, each pixel corresponding to the pixel electrode generates a driving voltage between the pixel electrode and the counter electrode to drive each electro-optical material portion (for example, to change the alignment state of the liquid crystal), thereby displaying It is configured to perform operations.
[0003]
For example, in JP-A-62-89024, JP-A-11-64874, JP-A-11-202366, etc., a sealing material is provided in a sealing region surrounding the liquid crystal layer along the four sides of the substrate. The technology which provides a vertical conduction material in the vertical conduction area | region of four corners of this is disclosed. In general, the sealing material is made of a photo-curing resin having no electrical conductivity, and the vertical conduction material is made of a conductive material. Of these publications, Japanese Patent Laid-Open No. 62-89024 discloses. For example, the sealing material in the seal region and the vertical conduction material provided in the vertical conduction region are each formed from the same conductive material. Thereby, the sealing material and the vertical conduction material can be formed in the same process, and the manufacturing process can be simplified.
[0004]
On the other hand, when this type of electro-optical device has a large image display area having a diagonal of about 20 cm or more, for example, the gap between the two substrates is controlled in an electro-optical material such as liquid crystal disposed in the image display area. Bead-like or fiber-like gap material is dispersed (that is, there is no problem because the gap material is not visible in the image). On the other hand, for example, in the case of a small electro-optical device having an image display area with a diagonal of about 2 cm or less, a gap material for controlling the gap between both substrates is generally mixed in the sealing material. (Ie, the gap material is not visible in the image).
[0005]
[Problems to be solved by the invention]
However, if an attempt is made to reduce the size of the substrate or the size of the image display area by reducing the vertical conduction area, the reliability of the vertical conduction itself is lowered. Alternatively, if it is intended to reduce the size of the substrate or increase the size of the image display area by reducing the seal area, the reliability of the bonding between the two substrates and the reliability of the gap control between the substrates can be reduced. It will decline.
[0008]
The present invention has been made in view of the above problems, and it is possible to simplify the configuration related to the sealing material for bonding a pair of substrates and the configuration related to vertical conduction between the pair of substrates, and the vertical conduction. It is an object of the present invention to provide an electro-optical device and a method for manufacturing the same that can improve the reliability of the device.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the electro-optical device according to the present invention includes an electro-optical material sandwiched between a pair of first and second substrates, and the electro-optical device between the first and second substrates as viewed in a plan view. A sealing material that adheres the first and second substrates together in a sealing region along the periphery of the substrate, and is disposed on the first substrate in an image display region surrounded by the sealing region in plan view. A plurality of pixel electrodes, and a vertical conduction pad for vertical conduction with the counter electrode on the second substrate, and the vertical conduction pad is planarized together with an interlayer insulating film under the pixel electrode. The upper and lower electrodes are electrically connected to each other.
[0010]
One aspect of the electro-optical device of the present invention is characterized in that the vertical conduction pad is vertically conductive with the counter electrode through a conductive material included in the sealing material.
[0011]
One aspect of the electro-optical device of the present invention is characterized in that the upper and lower conductive pads are connected to a counter electrode signal line disposed under the interlayer insulating film.
[0012]
One aspect of the electro-optical device of the present invention is characterized in that the interlayer insulating film under the counter electrode signal line is planarized.
[0013]
One aspect of the electro-optical device of the present invention is characterized in that the counter electrode signal line is formed of the same film as a data line connected to a thin film transistor provided corresponding to a pixel electrode.
[0014]
In the method of manufacturing the electro-optical device according to the aspect of the invention, the first interlayer insulating film is formed on the first substrate, the first interlayer insulating film and the upper and lower conductive pads are formed, and the first interlayer insulating film and the upper and lower conductive pads are formed. Flattening the surfaces of the conductive pads together, forming the counter electrode on the second substrate, and bonding the first substrate and the second substrate with the sealing material, The vertical conductive pad and the counter electrode are electrically connected.
[0048]
In order to solve the above problems, the projection type display device of the present invention has a light source, a light valve composed of the electro-optical device of the present invention, and a light guide member that guides light generated from the light source to the light valve. And a projection optical member that projects light modulated by the light valve.
[0049]
Such an operation and other advantages of the present invention will become apparent from the embodiments described below.
[0050]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the electro-optical device of the invention is applied to a liquid crystal device.
[0051]
(Overall configuration of electro-optical device)
First, an overall configuration of an electro-optical device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3. Here, a TFT active matrix driving type liquid crystal device with a built-in driving circuit as an example of an electro-optical device is taken as an example.
[0052]
FIG. 1 is a plan view of a TFT array substrate as viewed from the counter substrate side together with the components formed thereon, and FIG. 2 is a cross-sectional view taken along line HH ′ of FIG. FIG. 3 is a plan view showing extracted vertical conductive pads and a sealing material formed on the TFT array substrate among the various components shown in FIG.
[0053]
1 and 2, in the electro-optical device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are disposed to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region positioned around the image display region 10a. Are bonded to each other.
[0054]
Particularly in the present embodiment, the sealing material 52 is made of, for example, a thermosetting resin, a heat and photo-curing resin, a photo-curing resin, an ultraviolet-curing resin, etc. in order to bond the two substrates as the original function of the sealing material. After being coated on the TFT array substrate 10, it is cured by heating, heating and light irradiation, light irradiation, ultraviolet irradiation or the like. Further, the sealing material 52 is sandwiched between the vertical conduction pad 106 provided in the sealing region on the TFT array substrate 10 and the vertical conduction part 21 a located at the edge of the counter electrode 21 provided on the counter substrate 20. As a result, it also functions as a vertical conduction material. That is, the sealing material 52 can establish electrical continuity between the TFT array substrate 10 and the counter substrate 20.
[0055]
In such a sealing material 52, a gap material such as glass fiber or glass beads for mixing the distance between the two substrates (inter-substrate gap) to a predetermined value is mixed. That is, the electro-optical device according to the present embodiment is suitable for a small and enlarged display for a projector light valve. However, such a gap material may be included in the liquid crystal layer 50 if the electro-optical device is a large-sized liquid crystal device such as a liquid crystal display or a liquid crystal television that performs the same size display. In the present embodiment, in particular, the gap material is made of conductive fine particles in a portion of the sealing material 52 that is disposed at least between the vertical conductive pad 106 and the vertical conductive portion 21a and functions as the vertical conductive material. More specifically, for example, bead-like or fiber-like SiO plated with nickel gold ₂ Consists of particles. The configuration and operational effects of the sealing material 52 and the vertical conduction pad 106 will be described in detail later with reference to FIGS. 3 to 5 and FIGS. 7 to 13.
[0056]
1 and 2, a light-shielding frame 53 that defines the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the seal material 52 is disposed. It goes without saying that the frame 53 may be provided on the TFT array substrate 10 side. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in an outer portion extending around the image display area and outside the seal area where the seal material 52 is disposed. The scanning line driving circuit 104 is provided along two sides adjacent to the one side. Further, on the remaining side of the TFT array substrate 10, a plurality of wirings 105 are provided for connecting between the scanning line driving circuits 104 provided on both sides of the image display region 10a.
[0057]
In FIG. 2, on the TFT array substrate 10, an alignment film is formed on the pixel electrode 9a after the pixel switching TFT, the scanning line, the data line and the like are formed. On the other hand, an alignment film is formed on the counter substrate 20 in the uppermost layer portion in addition to the counter electrode 21. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.
[0058]
In the present embodiment, a sampling circuit 301 is provided in a region on the TFT array substrate 10 below the frame 53. The sampling circuit 301 is configured to sample the image signal on the image signal line in accordance with the sampling circuit drive signal supplied from the data line drive circuit 101 and supply the sampled signal to the data line.
[0059]
Particularly in the present embodiment, as extracted and shown in FIGS. 1 and 3, three of the four sides of the sealing material 52 whose planar shape is substantially equal to the counter substrate 20 except the side where the liquid crystal injection port 108 is formed are excluded. The vertical conduction pad 106 is provided in the seal region facing the side, and the vertical conduction pad having a larger area than the traditional vertical conduction pad can provide more reliable vertical conduction. However, as shown in FIG. 4, the vertical conduction pads 106 ′ may be provided on both sides of the side where the liquid crystal inlet 108 is formed, or as shown in FIG. 5, the vertical conduction pads 106 ″. May be provided on one side opposite to the side where the liquid crystal injection port 108 is formed.
[0060]
Such a vertical conductive pad is formed of a low-resistance metal such as an Al (aluminum) film or Cr (chromium), but has a relatively large area in contact with the sealing material 52 as the vertical conductive material. It is also possible to form a metal or non-metal conductive material having a lower resistance than that of the Al film.
[0061]
(Circuit configuration and operation of electro-optical device)
Next, the circuit configuration and operation of the electro-optical device configured as described above will be described with reference to FIG. FIG. 6 is a block diagram showing equivalent circuits such as various elements and wirings and peripheral circuits in a plurality of pixels formed in a matrix that forms an image display area of the electro-optical device.
[0062]
In FIG. 6, a pixel electrode 9 a and a TFT 30 for switching control of the pixel electrode 9 a are formed in each of a plurality of pixels formed in a matrix that forms the image display region of the electro-optical device according to the present embodiment. The data line 6 a to which the image signal is supplied is electrically connected to the source of the TFT 30.
[0063]
In the peripheral area outside the image display area 10a, one end (the lower end in FIG. 6) of the data line 6a is connected to the drain of each switching element made of, for example, a TFT of the sampling circuit 301. On the other hand, the image signal line 115 is connected to the source of the TFT of the sampling circuit 301 via the lead wiring 116. The sampling circuit drive signal line 114 connected to the data line drive circuit 101 is connected to the gate of the TFT of the sampling circuit 301. The image signals S1, S2,..., Sn on the image signal line 115 are sampled in response to a sampling circuit drive signal supplied from the data line drive circuit 101 via the sampling circuit drive signal line 114. And is supplied to each data line 6a.
[0064]
In this way, the image signals S1, S2,..., Sn written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. Anyway.
[0065]
The scanning line 3a is electrically connected to the gate of the pixel switching TFT 30, and the scanning signals G1, G2,..., Gm are pulsed to the scanning line 3a at a predetermined timing. Thus, it is configured to apply the lines sequentially in this order. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the switch of the TFT 30 serving as a switching element for a certain period. Write at a predetermined timing. Image signals S1, S2,..., Sn written in a liquid crystal as an example of an electro-optical material via the pixel electrode 9a are held for a certain period with the counter electrode 21 formed on the counter substrate. . The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied potential level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to the image signal is emitted from the electro-optical device as a whole. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 a and the counter electrode 21. A capacitor line 300 including a fixed potential side capacitor electrode of the storage capacitor 70 and fixed at a constant potential is provided alongside the scanning line 3a.
[0066]
On the TFT array substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104, the sampling circuit 301 and the like, a precharge signal having a predetermined voltage level is applied to the plurality of data lines 6a before the image signal. In addition, a precharge circuit to be supplied, an inspection circuit for inspecting quality, defects, and the like of the electro-optical device during manufacture or shipment may be formed.
[0067]
(Details of sealing material and vertical conduction pad)
Next, the configuration and operational effects of the sealing material 52 and the vertical conductive pad 106 that also function as the vertical conductive material shown in FIGS. 1 to 5 will be further described with reference to FIGS. 7 to 9. FIG. 7 is an enlarged partial cross-sectional view showing a C1 portion in FIG. 2, FIG. 8 is an enlarged partial cross-sectional view showing a C2 portion in FIG. 2, and FIG. It is -B 'sectional drawing.
[0068]
In FIG. 7, a base insulating film 12, a first interlayer insulating film 41, a second interlayer insulating film, and a third interlayer insulating film that insulate the scanning lines 3a, data lines 6a, TFTs and the like formed in the pixel portion as will be described later. 43 and the fourth interlayer insulating film 44 are stacked on the TFT array substrate 10, and the pixel electrode 9 a and the alignment film 16 are formed on the fourth interlayer insulating film 44. A sampling circuit 301 (see FIG. 6) is formed on the first interlayer insulating film 41, and the same film as the data line 6a (for example, Al) is formed between the second interlayer insulating film 42 and the third interlayer insulating film 43. A lead wire 116 (see FIG. 3) made of a film is formed and connected to the sampling circuit 301. On the other hand, a frame 53 and a counter electrode 21 are formed on the counter substrate 20. Between the alignment film 16 that is the uppermost layer of the TFT array substrate 10 and the alignment film 22 that is the lowermost layer of the counter substrate 20, a sealing material 52 in which the gap material 201 is mixed in the resin 200 is disposed. .
[0069]
On the other hand, in FIG. 8, a gap material 202 is formed between the vertical conductive pad 106 which is the uppermost layer of the TFT array substrate 10 and the vertical conductive portion 21a which is the edge of the counter electrode 21 which is the lowermost layer of the counter substrate 20. The sealing material 52 mixed in 200 is arrange | positioned. Here, unlike the case of the seal region shown in FIG. 7, in the case of the seal region shown in FIG. 8, the gap material 202 has conductivity, and the seal material 52 also functions as a vertical conduction material. .
[0070]
On the other hand, in the case of FIG. 7, even if the gap material 201 does not have conductivity, even if the gap material 201 penetrates through the interlayer insulating films 44 and 43 to the lead-out wiring 116 formed below the gap material 201, This can reduce the possibility that the lead-out wiring 116 and the like are disconnected or short-circuited.
[0071]
As shown in FIG. 9, the vertical conductive pad 106 is a counter electrode for supplying a counter electrode potential signal that is fixed or inverted at a predetermined cycle to the counter electrode 21 at one or a plurality of locations on the TFT array substrate 10. The signal wiring 117 is connected to the signal wiring 117 (for example, wiring made of a low-resistance Al film or the like as in the case of the lead wiring 116) through the contact hole 118. Preferably, the upper and lower conductive pads 106 are flattened together with the fourth interlayer insulating film 44 as shown in FIG. Such planarization will be further described later in the manufacturing process.
[0072]
As shown in FIGS. 7 to 9, in this embodiment, the portion made of the conductive material by including the conductive gap material 202 in the sealing material 52 that adheres both substrates together in the sealing region is vertically moved. It arrange | positions between the conduction | electrical_connection pad 106 and the vertical conduction | electrical_connection part 21a, and functions as a vertical conduction | electrical_connection material between these. Therefore, the TFT array substrate 10 can be reduced in size by the amount that the vertical conduction region can be included in the seal region, or the image display region can be enlarged relative to the TFT array substrate. Conversely, a large seal area can be ensured by the amount that it is not necessary to prepare a vertical conduction area separately from the seal area. For this reason, both substrates can be bonded very reliably. Furthermore, by making at least a part of the sealing material 52 function as a vertical conduction material, it is possible to simplify the device configuration and the manufacturing process thereof.
[0073]
Next, various modifications of the above-described embodiment will be described with reference to FIGS. 10 to 13. FIG. 10 is a schematic cross-sectional view showing the state of the gap material in the vicinity of the boundary between the region where the vertical conductive pad is formed and the region where the vertical conductive pad is not formed in the seal region in the embodiment described above. FIG. 11 to FIG. 13 are schematic views showing the state of the gap material in the vicinity of the boundary between the region where the vertical conductive pad is formed and the region where the vertical conductive pad is not formed in the seal region in the modified embodiment. It is sectional drawing.
[0074]
First, as shown in FIG. 10, in the case of the above-described embodiment, the conductive gap material 202 is mixed in the resin 200 on the side where the upper and lower conductive pads 106 are formed across the boundary region. On the side where the sealing material 52 is made conductive and the upper and lower conductive pads 106 are not formed, an electrically insulating gap material 201 is mixed in the resin 200 so that the sealing material 52 becomes electrically insulating. Has been. The upper and lower conductive pads 106 are flattened, and the diameters of the gap members 201 and 202 are substantially the same. As a result, according to the embodiment described above, the sealing material 52 can be provided with a function as a vertical conduction material in addition to the original function of the sealing material, and at the same time, the inter-substrate gap can be controlled with high accuracy.
[0075]
In the case of the modification shown in FIG. 11, in addition to the conductive gap material 202 being mixed in the resin 200 on the side where the upper and lower conductive pads 106 are formed across the boundary region, the conductive The silver powder 203 is mixed. Thus, better conductivity can be given to the sealing material 52. Other configurations are the same as those of the embodiment shown in FIGS.
[0076]
In the case of the modification shown in FIG. 12, since the vertical conduction pad 106 is not flattened, the area where the vertical conduction pad 106 is formed in the seal area is more than the area where the vertical conduction pad 106 is not formed. Is also high. Therefore, if a gap material having the same diameter is mixed on both sides of the boundary, the gap material functions only on the upper and lower conductive pads 106, and the gap control becomes inaccurate. However, in the case of the modification shown in FIG. 12, the conductive gap material 202S having a small diameter and a small diameter is mixed on the upper and lower conductive pads 106, which are relatively high, and are relatively low. A gap material 201L having a large diameter and an electrically insulating property is mixed in a seal region where the vertical conductive pads 106 are not present. Preferably, the diameter D1 of the small gap material 202S is set smaller than the diameter D2 of the large gap material 201L by the height h1 of the vertical conductive pad 106 (that is, D1 = D2−h1). To do). As a result, according to the modification shown in FIG. 12, the inter-substrate gap can be accurately controlled without performing the planarization process on the upper and lower conductive pads 106. Other configurations are the same as those of the embodiment shown in FIGS.
[0077]
In the case of the modification shown in FIG. 13, since the vertical conduction pad 106 is not flattened, the region where the vertical conduction pad 106 is formed in the seal region is more than the region where the vertical conduction pad 106 is not formed. Is also low. Therefore, if a gap material having the same diameter is mixed on both sides of this boundary, the gap material functions only in a region where the upper and lower conductive pads 106 are not formed, and the reliability of the gap control is lowered. However, in the case of the modification shown in FIG. 13, a large gap and conductive gap material 202L is mixed on the upper and lower conductive pads 106, which are relatively low, and becomes relatively high. A gap region 201S having a small diameter and an electrically insulating property is mixed in the seal region where the upper and lower conductive pads 106 are not formed. Preferably, the diameter D3 of the large-diameter gap material 202L is set larger than the diameter D4 of the small-diameter gap material 201S by the height h2 of the upper and lower conductive pads 106 (that is, D3 = D4 + h2). . As a result, according to the modification shown in FIG. 13, the inter-substrate gap can be accurately controlled without performing the planarization process on the upper and lower conductive pads 106. Further, in the modification shown in FIG. 13, a sealing material 52 mixed with a small-diameter gap material 201 </ b> S is arranged in the boundary region where the gap between the substrates changes. An electrically insulating small-diameter gap material 201S enters the upper and lower conductive pads 106 having a wide gap. With this configuration, it is possible to reduce the possibility that the large-diameter gap material 202L enters the narrow side of the inter-substrate gap in the boundary region where the inter-substrate gap changes. That is, the possibility that the large-diameter gap material 202 </ b> L abuts locally at the narrow gap portion may cause a disconnection or a short circuit of the underlying wiring. Other configurations are the same as those of the embodiment shown in FIGS.
[0078]
As shown in FIGS. 10 to 13, without changing the sealing material 52 in the vicinity of the boundary, the sealing material 52 is made of the same material (that is, the same conductive gap material, the same material) over the entire sealing region. Resin or the same conductive resin). If comprised in this way, an apparatus structure and its manufacturing process can be simplified by making the sealing material 52 whole function also as a vertical conduction material.
[0079]
(Configuration of image display area of electro-optical device)
Next, the configuration of the image display area of the electro-optical device according to the embodiment of the invention will be described with reference to FIGS. 14 and 15. FIG. 14 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed. 15 is a cross-sectional view taken along line AA ′ of FIG. In FIG. 14, the scale of each layer and each member is different in order to make each layer and each member large enough to be recognized on the drawing.
[0080]
In FIG. 14, a plurality of transparent pixel electrodes 9a (outlined by dotted line portions 9a ′) are provided in a matrix on the TFT array substrate of the electro-optical device. A data line 6a and a scanning line 3a are provided along each boundary.
[0081]
In addition, the scanning line 3a is disposed so as to face the channel region 1a ′ indicated by the hatched region rising to the right in the drawing in the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode (particularly in the present embodiment). Then, the scanning line 3a is formed to be wide in the portion that becomes the gate electrode). As described above, the pixel switching TFT 30 in which the scanning line 3a is disposed as a gate electrode in the channel region 1a ′ is provided at each of the intersections of the scanning line 3a and the data line 6a.
[0082]
As shown in FIGS. 14 and 15, the storage capacitor 70 includes a relay layer 71 as a pixel potential side capacitor electrode connected to the high concentration drain region 1e (and the pixel electrode 9a) of the TFT 30, and a fixed potential side capacitor electrode. A part of the capacitor line 300 is formed so as to be opposed to each other through the dielectric film 75.
[0083]
The capacitor line 300 extends in a stripe shape along the scanning line 3a when seen in a plan view, and a portion overlapping the TFT 30 protrudes up and down in FIG. Such a capacitor line 300 preferably includes a first film made of a conductive polysilicon film having a thickness of about 50 nm and a second film made of a metal silicide film containing a refractory metal having a thickness of about 150 nm. It is configured to have a laminated multilayer structure. With this configuration, the second film functions not only as a fixed potential side capacitor electrode of the capacitor line 300 or the storage capacitor 70 but also as a light shielding layer that shields the TFT 30 from incident light above the TFT 30.
[0084]
On the other hand, below the TFT 30 on the TFT array substrate 10, a lower light-shielding film 11a is provided in a grid pattern. The lower light-shielding film 11a is made of, for example, at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum), and Pb (lead). Including a single metal, an alloy, a metal silicide, a polysilicide, and a laminate of these.
[0085]
Each data line 6a extending in the vertical direction in FIG. 14 and the capacitance line 300 extending in the horizontal direction in FIG. 14 are formed so as to cross each other, and the lower light-shielding film 11a formed in a lattice shape causes each pixel. The opening area is defined.
[0086]
As shown in FIGS. 14 and 15, the data line 6a is electrically connected to the high-concentration source region 1d in the semiconductor layer 1a made of, for example, a polysilicon film through the contact hole 81. Note that a relay layer made of the same film as the relay layer 71 described above may be formed, and the data line 6a and the high-concentration source region 1d may be electrically connected through the relay layer and the two contact holes.
[0087]
Further, the capacitor line 300 extends from the image display region where the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source to be a fixed potential. As such a constant potential source, a data line driving circuit for controlling a scanning line driving circuit for supplying a scanning signal for driving the TFT 30 to the scanning line 3a and a sampling circuit for supplying an image signal to the data line 6a ( A constant potential source such as a positive power source or a negative power source supplied to FIG. 1, FIG. 3 or FIG. 6 may be used, or a constant potential supplied to the counter electrode 21 of the counter substrate 20 may be used. Further, the lower light-shielding film 11 a provided on the lower side of the TFT 30 extends from the image display area to the periphery thereof in the same manner as the capacitor line 300 in order to avoid the potential fluctuation from adversely affecting the TFT 30. Then, it may be connected to a constant potential source.
[0088]
The pixel electrode 9a is electrically connected to the high-concentration drain region 1e in the semiconductor layer 1a through the contact holes 83 and 85 by relaying the relay layer 71.
[0089]
14 and 15, the electro-optical device includes a TFT array substrate 10 and a transparent counter substrate 20 disposed to face the TFT array substrate 10. The TFT array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate.
[0090]
As shown in FIG. 15, the TFT array substrate 10 is provided with a pixel electrode 9a, and an alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive film such as an ITO film. The alignment film 16 is made of an organic film such as a polyimide film.
[0091]
On the other hand, a counter electrode 21 is provided over the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. The counter electrode 21 is made of a transparent conductive film such as an ITO film. The alignment film 22 is made of an organic film such as a polyimide film.
[0092]
The counter substrate 20 may be provided with a lattice-shaped or stripe-shaped light-shielding film (a light-shielding film that is the same as or different from the frame 53). By adopting such a configuration, the incident light from the counter substrate 20 side is reduced to the channel region 1a ′ or the low level by the light shielding film on the counter substrate 20 together with the capacitor line 300 and the data line 6a constituting the light shield region as described above. Intrusion into the concentration source region 1b and the low concentration drain region 1c can be more reliably prevented. Further, such a light shielding film on the counter substrate 20 functions to prevent a temperature increase of the electro-optical device by forming at least a surface irradiated with incident light with a highly reflective film.
[0093]
The TFT array substrate 10 and the counter substrate 20 that are arranged in such a manner so that the pixel electrode 9a and the counter electrode 21 face each other are surrounded by a sealing material 52 (see FIGS. 1 to 5). Liquid crystal, which is an example of an electro-optical material, is sealed in the space, and a liquid crystal layer 50 is formed.
[0094]
Further, a base insulating film 12 is provided under the pixel switching TFT 30. The base insulating film 12 is formed on the entire surface of the TFT array substrate 10 in addition to the function of interlayer insulating the TFT 30 from the lower light-shielding film 11a, and thus remains rough after polishing the surface of the TFT array substrate 10 and after cleaning. It has a function of preventing changes in characteristics of the pixel switching TFT 30 due to dirt or the like.
[0095]
In FIG. 15, a pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and a scanning line 3a, a channel region 1a ′ of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, Insulating film 2 including a gate insulating film that insulates scanning line 3a from semiconductor layer 1a, low concentration source region 1b and low concentration drain region 1c of semiconductor layer 1a, high concentration source region 1d and high concentration drain region of semiconductor layer 1a 1e.
[0096]
On the scanning line 3a, a first interlayer insulating film 41 is formed in which a contact hole 81 leading to the high concentration source region 1d and a contact hole 83 leading to the high concentration drain region 1e are respectively opened.
[0097]
A relay layer 71 and a capacitor line 300 are formed on the first interlayer insulating film 41, and a contact hole 81 leading to the high-concentration source region 1d and a contact hole 85 leading to the relay layer 71 are opened on these, respectively. A holed second interlayer insulating film 42 is formed.
[0098]
A data line 6 a is formed on the second interlayer insulating film 42, and a flattened third interlayer insulating film 43 in which a contact hole 85 leading to the relay layer 71 is formed is formed thereon. .
[0099]
On the third interlayer insulating film 43, a fourth interlayer insulating film 44 for forming the upper and lower conductive pads 106 in the seal region is formed, and the pixel electrode 9a has the fourth interlayer insulating film thus configured. 44 is provided on the upper surface.
[0100]
In the present embodiment, at least one surface of the third interlayer insulating film 43 and the fourth interlayer insulating film 44 is planarized by a CMP (Chemical Mechanical Polishing) process or the like, and exists below the surface. The liquid crystal alignment defect in the liquid crystal layer 50 due to the steps due to various wirings and elements is reduced.
[0101]
In the embodiment described above, a plurality of conductive layers are stacked as shown in FIG. 15, whereby the data lines 6a and the scanning lines 3a on the lower ground of the pixel electrode 9a (that is, the surface of the third interlayer insulating film 43). The level difference in the region along the line is alleviated by flattening the surface of the third interlayer insulating film 43, but instead of or in addition to this, the TFT array substrate 10, the base insulating film 12, the first A planarization process may be performed by digging a groove in the first interlayer insulating film 41, the second interlayer insulating film 42, or the third interlayer insulating film 43 and embedding the wiring such as the data line 6a, the TFT 30, or the like. The planarization process may be performed by polishing a step on the upper surface of the interlayer insulating film 42 by CMP or the like, or by forming it flat using organic SOG (Spin On Glass).
[0102]
In the embodiment described above, the pixel switching TFT 30 preferably has an LDD structure as shown in FIG. 15, but does not implant impurities into the low concentration source region 1b and the low concentration drain region 1c. It may have a structure, or may be a self-aligned TFT in which a high concentration source and drain regions are formed in a self-aligned manner by implanting impurities at a high concentration using a gate electrode formed of a part of the scanning line 3a as a mask. . In this embodiment, only one gate electrode of the TFT 30 for pixel switching is arranged between the high concentration source region 1d and the high concentration drain region 1e. However, two or more gate electrodes are interposed between them. May be arranged. If the TFT is configured with dual gates or triple gates or more in this way, leakage current at the junction between the channel and the source and drain regions can be prevented, and the off-time current can be reduced.
[0103]
Through the same process as the pixel switching TFT 30, TFTs constituting the data line driving circuit 101, the sampling circuit 301, and the scanning line driving circuit 104 in FIG. 3 can be formed.
[0104]
(Manufacturing process)
Next, with reference to FIG. 16, the manufacturing process for manufacturing the above-described electro-optical device will be described with a focus on a vertical conductive pad forming process and a bonding process using a sealing material. FIG. 16 is a process chart sequentially showing the cross-sectional structure in each process at the location corresponding to the BB ′ cross section of FIG.
[0105]
First, in step (1) of FIG. 16, on the TFT array substrate 10, the lower light shielding film 11a, the semiconductor layer 1a, the scanning line 3a, the capacitance line 300, the data as shown in FIGS. In parallel with the sequential formation of the lines 6a and the like, the counter electrode signal wiring 117 is formed on the TFT array substrate 10 in the seal region using the same conductive film or from a dedicated conductive film. More specifically, here, the counter electrode signal wiring 117 is formed from the same film (that is, for example, an Al film) as the data line 6a (at this time, the extraction wiring 116 under the seal region shown in FIG. 7). Can be formed at the same time). The counter electrode signal wiring 117 (and the data line 6a and the lead wiring 116) is formed by, for example, forming an Al film on the entire surface of the second interlayer insulating film 42 by sputtering and then patterning it by photolithography processing and etching processing. Just do it. On the other hand, with respect to each interlayer insulating film including the second interlayer insulating film 42 and the third interlayer insulating film 43, for example, TEOS (tetra-ethyl ortho-silicate) gas, TEB (tetra- It may be formed from a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like using an ethyl boatrate) gas, TMOP (tetramethyloxyphosphorate) gas, or the like. .
[0106]
Next, in step (2), a contact hole 118 for electrically connecting the counter electrode signal wiring 117 and the vertical conduction pad 106 to the third interlayer insulating film 43 is opened by dry etching, wet etching, or a combination thereof. Make a hole. Thereafter, after forming an Al film or the like on the entire surface of the third interlayer insulating film 43, patterning is performed by photolithography processing and etching processing to form the upper and lower conductive pads 106.
[0107]
Next, in step (3), as with the second interlayer insulating film 42 and the third interlayer insulating film 43, the entire surface of the third interlayer insulating film 43 including the upper and lower conductive pads 106 is subjected to, for example, atmospheric pressure or reduced pressure CVD. An insulating film that forms the fourth interlayer insulating film 44 is formed from a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like. In particular, the thickness of this insulating film is set to be thicker than that of the upper and lower conductive pads 106.
[0108]
Next, in step (4), the insulating film formed in the above step (3) is polished by CMP to expose the upper and lower conductive pads 106, thereby flattening the sealing region including the upper and lower conductive pads 106. . More specifically, for example, by flowing a liquid chiller (chemical polishing liquid) containing silica particles on a polishing pad fixed on a polishing plate, the substrate surface fixed to the spindle is brought into rotational contact, Polish the surface of the insulating film. Then, the CMP process is stopped when the upper and lower conductive pads 106 are exposed. For example, the CMP process is stopped (stopped) by time management. Alternatively, the CMP process is stopped (stopped) by forming an appropriate stopper layer having a laminated structure similar to that of the upper and lower conductive pads 106 at a predetermined position on the TFT array substrate 10, for example. The surface of the stopper layer can be detected by, for example, a friction detection type that detects a change in the friction coefficient when the stopper layer is exposed, a vibration detection type that detects vibration that occurs when the stopper layer is exposed, or the stopper layer is exposed. What is necessary is just to carry out by the optical system which detects the change of the reflected light quantity at the time of doing.
[0109]
Next, in step (5), for the TFT array substrate 10, the pixel electrode 9a and the alignment film 16 as shown in FIGS. 14 and 15 are formed in the image display region. On the other hand, for the counter substrate 20, a light shielding film 53, a counter electrode 21, and an alignment film 22 are sequentially stacked.
[0110]
Then, the TFT array substrate 10 on which the respective layers are formed as described above and the counter substrate 20 are bonded together with a sealing material (see FIGS. 1 to 5) so that the alignment films 16 and 22 face each other. Immediately before this bonding, a seal region including the upper and lower conductive pads is drawn with a sealant 52 before curing (that is, the resin 200 before curing including the gap material 201 or the gap material 202) on one of the substrates by a dispenser. deep.
[0111]
At this time, in particular, a dispenser that outputs the uncured resin 200 including the electrically insulating gap material 201 and a dispenser that outputs the uncured resin 200 including the conductive gap material 202 are separately prepared, When the seal region excluding the vertical conduction pad 106 is drawn by the former and the seal region including the vertical conduction pad 106 is drawn by the latter, only the portion that should function as the vertical conduction material in the sealing material 52 is made conductive. The configuration (see FIGS. 7 to 13) can be obtained relatively easily.
[0112]
Furthermore, a dispenser that outputs the uncured resin 200 containing the small-diameter gap material 201S or 202S and a dispenser that outputs the uncured resin 200 containing the large-diameter gap material 201L or 202L are prepared separately, If the former draws a region having a narrow inter-substrate gap in the seal region and the latter draws a region having a wide inter-substrate gap in the seal region, the presence of the upper and lower conductive pads 106 causes a step in the seal region. However, a configuration (see FIGS. 12 and 13) that can accurately perform the gap between the substrates can be obtained relatively easily.
[0113]
Subsequently, the sealing material 52 (including the thermosetting resin or the resin 200 made of heat and photocurable resin) is cured by heat irradiation or light irradiation in a state where the two substrates are bonded with the sealing material 52. . In this embodiment, since the vertical conduction pad 106 exists, it is difficult to irradiate light from the TFT array substrate 10 side. Therefore, when a photo-curing resin or an ultraviolet-curing resin is used as the sealing material 52, light is emitted from the counter substrate 20 side. Irradiation is required. For this reason, it is advantageous from the viewpoint that the sealing material 52 made of thermosetting or heat and photo-curable resin can be cured well regardless of the presence of the upper and lower conductive pads 52. (However, by masking the image display area and irradiating light, it is possible to cure the photocurable resin by sufficient light irradiation from one side while avoiding deterioration of the electro-optical material or the like due to light irradiation. ).
[0114]
Subsequently, liquid crystal formed by mixing, for example, a plurality of types of nematic liquid crystals is sucked into the space between both substrates by vacuum suction or the like via the liquid crystal injection port 108 (see FIG. 1 and the like), and has a predetermined layer thickness. A liquid crystal layer is formed.
[0115]
According to the manufacturing process of the present invention described above, the above-described electro-optical device according to the present invention can be manufactured relatively easily. At this time, in particular, in the step (5) of FIG. 16, the TFT array substrate 10 on which the vertical conduction pad 106 is formed and the counter substrate 20 on which the counter electrode 21 having the vertical conduction portion 21a is formed are sealed by the sealing material 52. At the same time as the phase bonding, the vertical conductive material that vertically connects the vertical conductive pad 106 and the vertical conductive portion 21a can be formed from the portion of the sealing material 52 made of a conductive material. In addition, since the sealing region is flattened in the step (4) of FIG. 16, the gap between the substrates can be accurately controlled by the gap materials 201 and 202 mixed in the sealing material 52.
[0116]
The flattening of the seal region is performed by embedding the upper and lower conductive pads 106 in a trench dug in either the TFT array substrate 10 or the first to third interlayer insulating films instead of or in addition to the above-described CMP process. May be performed.
[0117]
Note that the vertical conductive pads in the various forms shown in FIGS. 3 to 5 can be formed by making a slight modification to the patterning in the step (2) of FIG. 16 (that is, without changing the other steps). Convenient because it can be formed).
[0118]
In the embodiment described above with reference to FIGS. 1 to 16, the data line driving circuit 101 and the scanning line driving circuit 104 are mounted on, for example, a TAB (Tape Automated Bonding) substrate instead of being provided on the TFT array substrate 10. The drive LSI may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. Further, for example, a TN mode, a VA (Vertically Aligned) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, and the like are respectively provided on the side on which the projection light of the counter substrate 20 enters and the side on which the emission light of the TFT array substrate 10 exits. A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to the operation mode and the normally white mode / normally black mode.
[0119]
(Application example of electro-optical device)
The electro-optical device in each embodiment described above can be applied to a projector. A projector using the above-described electro-optical device as a light valve will be described. FIG. 17 is a plan view showing the configuration of the projector. As shown in this figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by three mirrors 1106 and two dichroic mirrors 1108 disposed therein, and light valves 100R, 100G corresponding to the primary colors and 100B, respectively. Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the electro-optical device according to the above-described embodiment, and R, G, and B primary colors supplied from a processing circuit (not shown) that inputs an image signal. Each is driven by a signal. In addition, B light has a long optical path compared to other R colors and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124. Led.
[0120]
The light modulated by the light valves 100R, 100G, and 100B is incident on the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted by 90 degrees, while G light travels straight. Therefore, after the images of the respective colors are combined, a color image is projected on the screen 1120 by the projection lens 1114.
[0121]
Since light corresponding to the primary colors R, G, and B is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 1108, it is not necessary to provide a color filter as described above. Further, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 1112, whereas the transmission image of the light valve 100G is projected as it is, so that the display images of the light valves 100R and 100B are converted into the light valve. The display image is horizontally reversed with respect to the display image by 100G.
[0122]
In each embodiment, the counter substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the counter substrate 20 together with its protective film in a predetermined region facing the pixel electrode 9a. In this way, the electro-optical device in each embodiment can be applied to a direct-view type or reflective type color electro-optical device other than the projector. Further, micro lenses may be formed on the counter substrate 20 so as to correspond to one pixel. Alternatively, it is also possible to form a color filter layer with a color resist or the like under the pixel electrodes 9 a facing RGB on the TFT array substrate 10. In this way, a bright electro-optical device can be realized by improving the collection efficiency of incident light. Furthermore, a dichroic filter that produces RGB colors by using interference of light may be formed by depositing several layers of interference layers having different refractive indexes on the counter substrate 20. According to this counter substrate with a dichroic filter, a brighter color electro-optical device can be realized.
[0123]
The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. The manufacturing method is also included in the technical scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a plan view of a TFT array substrate in an electro-optical device according to an embodiment of the present invention, viewed from the side of a counter substrate together with each component formed thereon.
FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.
FIG. 3 is a plan view showing extracted vertical conductive pads and a sealing material formed on a TFT array substrate among various components shown in FIG. 1;
4 is a plan view showing another specific example of a vertical conductive pad and a seal material that can be employed in the present embodiment, similar to FIG.
FIG. 5 is a plan view showing another specific example of the vertical conduction pad and the sealing material that can be employed in the present embodiment, as in FIG. 3;
6 is a block diagram of an equivalent circuit and peripheral circuits such as various elements and wirings provided in a plurality of matrix-like pixels constituting an image display region in the electro-optical device according to the embodiment of the invention. FIG.
7 is an enlarged partial cross-sectional view showing a C1 portion of FIG. 2;
FIG. 8 is a partial cross-sectional view showing an enlarged C2 portion of FIG. 2;
9 is a cross-sectional view taken along the line BB ′ of FIG.
FIG. 10 is a schematic cross-sectional view showing a gap material in the vicinity of a boundary between a region where a vertical conductive pad is formed and a region where a vertical conductive pad is not formed in a seal region in the present embodiment.
11 is a schematic cross-sectional view showing a state of a gap material in the vicinity of a boundary between a region where a vertical conductive pad is formed and a region where a vertical conductive pad is not formed in a seal region in one modified embodiment. FIG.
FIG. 12 is a schematic cross-sectional view showing a state of a gap material in the vicinity of a boundary between a region where a vertical conductive pad is formed and a region where a vertical conductive pad is not formed in a seal region in another modified embodiment.
FIG. 13 is a schematic cross-sectional view showing a state of a gap material in the vicinity of a boundary between a region where a vertical conductive pad is formed and a region where a vertical conductive pad is not formed in a seal region in another modified embodiment.
14 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the electro-optical device of the embodiment. FIG.
15 is a cross-sectional view taken along the line AA ′ of FIG.
FIG. 16 is a process diagram showing a manufacturing process according to the embodiment.
FIG. 17 is a plan view showing a configuration of a projector.
[Explanation of symbols]
1a ... Semiconductor layer
1a '... channel region
1b ... low concentration source region
1c: low concentration drain region
1d ... High concentration source region
1e ... High concentration drain region
2… Insulating film
3a ... scan line
6a ... Data line
9a: Pixel electrode
10 ... TFT array substrate
11a: Lower light shielding film
12 ... Underlying insulating film
16 ... Alignment film
20 ... Counter substrate
21 ... Counter electrode
21a: vertical conduction part
22 ... Alignment film
30 ... TFT
50 ... Liquid crystal layer
52 ... Sealing material
70 ... Storage capacity
71 ... Relay layer
81, 83, 85 ... contact holes
101: Data line driving circuit
104: Scanning line driving circuit
106, 106 ', 106 "... vertical conductive pads
108 ... Liquid crystal injection port
114: Sampling circuit drive signal line
115: Image signal line
116 ... Lead-out wiring
117 ... Counter electrode signal wiring
118 ... Contact hole
200: Resin
201, 201S, 201L ... Gap material
202, 202S, 202L ... Gap material
203 ... Silver powder

Claims (7)

An electro-optic material is sandwiched between a pair of first and second substrates;
A sealing material is provided between the first and second substrates to bond the first and second substrates in a sealing region along a periphery thereof when viewed in plan.
A plurality of pixel electrodes disposed in an image display region surrounded by the seal region in plan view on the first substrate, and a vertical conduction pad for conducting vertical conduction with a counter electrode on the second substrate; With
The electro-optical device, wherein the vertical conductive pad is planarized together with an interlayer insulating film under the pixel electrode, and is vertically connected to the counter electrode.   The electro-optical device according to claim 1, wherein the vertical conduction pad is vertically conductive with the counter electrode through a conductive material included in the seal material.   The electro-optical device according to claim 1, wherein the upper and lower conductive pads are connected to a counter electrode signal line disposed below the interlayer insulating film.   4. The electro-optical device according to claim 3, wherein the interlayer insulating film under the counter electrode signal line is flattened.   5. The electro-optical device according to claim 3, wherein the counter electrode signal line is formed of the same film as a data line connected to a thin film transistor provided corresponding to the pixel electrode. An electro-optical device manufacturing method for manufacturing an electro-optical device, comprising:
Forming a first interlayer insulating film on the first substrate, forming the first interlayer insulating film and the upper and lower conductive pads, and planarizing both surfaces of the first interlayer insulating film and the upper and lower conductive pads; ,
Forming the counter electrode on the second substrate;
Adhering the first substrate and the second substrate with the sealing material,
A method of manufacturing an electro-optical device, wherein the vertical conductive pad and the counter electrode are electrically connected. A light source;
A light valve comprising the electro-optical device according to claim 1;
A light guide member that guides light generated from the light source to the light valve;
A projection type display device comprising: a projection optical member that projects light modulated by the light valve.

Images