JP3922950B2 - Frequency conversion circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a frequency conversion circuit, and more particularly to a circuit suitable for use in a semiconductor integrated circuit, which is used in a radio receiver or the like that handles high-frequency signals.
[0002]
[Prior art]
Conventionally, in a frequency conversion circuit for a high-frequency signal such as a quasi-microwave band, an integrated circuit is formed using, for example, a dual-gate field effect transistor (FET-Field Effect Transistor) made of a gallium arsenide compound semiconductor. For example, a semiconductor circuit for frequency conversion having a configuration as shown in FIG. 4 is publicly known.
The conventional circuit will be described below with reference to FIG.
In this circuit, the dual gate FET 51 is used for frequency conversion. First, the first gate G1 is externally connected to the first gate G1 via the first impedance matching circuit 52 and the first DC cut capacitor 55. A local oscillation signal is applied to the second gate G2, and a high-frequency signal is applied to the second gate G2 from the outside via the second impedance matching circuit 53 and the second DC cut capacitor 56, respectively.
[0003]
The source of the dual gate FET 51 is set to the ground potential via the self-bias resistor 59, and a bypass capacitor 58 is provided between the source and the ground potential. Here, the bypass capacitor 58 is provided in order to lower the impedance between the source of the dual gate FET 51 and the ground potential at a required frequency from the viewpoint of securing the gain of the circuit at the time of frequency conversion, that is, the conversion gain. is there.
The power supply voltage is applied to the drain of the dual gate FET 51 via the high frequency cutoff inductor 62, and the high frequency signal applied to the second gate G2 and the first gate G1. A high frequency signal having a frequency component that is the sum and difference of the local oscillation signal is obtained via the third impedance matching circuit 54 and the third DC cut capacitor 57.
[0004]
[Problems to be solved by the invention]
By the way, for example, in a frequency conversion circuit used in a receiving unit such as a portable wireless terminal, a high-frequency signal input to the frequency conversion circuit is usually weak, but it is assumed that the frequency conversion circuit is used under certain special conditions. In some cases, reception sensitivity suppression is defined when an interference wave signal having a strong electric field is input to the conversion circuit. However, in frequency conversion circuits that presuppose frequency conversion of high-frequency signals with weak electric fields, when such strong electric field interference wave signals are input, the circuit operation exceeds the linear operating region, and the conversion gain is suppressed. As a result, there is a problem that the reception sensitivity is significantly deteriorated.
In such a case, for example, by increasing the bias current of the frequency conversion circuit to increase the output, it is possible to reduce conversion gain suppression due to the input of a strong electric field disturbance wave signal. In a portable wireless terminal to be used, the amount of power consumed by the battery power supply increases with an increase in bias current during normal operation, leading to a problem that the operable time is shortened.
Further, for example, as disclosed in Japanese Unexamined Patent Publication No. 2000-91938, a buffer amplifier or the like is provided at the input stage of a frequency conversion circuit as an improvement in output characteristics when an interference signal of a strong electric field is input. There has been proposed a technique for providing a level detection circuit having the above and for controlling the bias current of the frequency conversion circuit in accordance with the level of the high-frequency signal detected thereby.
However, in such a conventional technique, the scale of the level detection circuit becomes large, and particularly in the case of an integrated circuit, there is a problem that the manufacturing cost increases due to the increase in the chip area.
[0005]
The present invention has been made in view of the above circumstances, and provides a frequency conversion circuit capable of reducing the conversion gain suppression by increasing the bias current only when a disturbance signal of a strong electric field is input. is there.
Another object of the present invention is to perform frequency conversion with a small conversion gain suppression when a strong electric field disturbance wave signal is input, without increasing the circuit scale and area when integrating the circuit as much as possible. It is to provide a circuit.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, a frequency conversion circuit according to the present invention includes:
In a frequency conversion circuit using a field effect transistor having a strong electric field gain adjusting means for suppressing an increase in conversion gain suppression when a high-frequency signal of a strong electric field is input,
The field effect transistor has a dual gate structure, and a self-bias resistor and a bypass capacitor connected in parallel are provided in series between the source of the dual gate field effect transistor and the ground potential. on the other hand,
The strong electric field gain adjusting means includes an enhancement type field effect transistor, and is configured so that a part of a high frequency signal is applied to the gate of the enhancement type field effect transistor, and the enhancement type electric field effect transistor. The effect transistor is connected in parallel with the self-bias resistor and the bypass capacitor.
[0007]
In such a configuration, when the input level of the high-frequency signal is increased, the strong electric field gain adjusting means suppresses an increase in conversion gain suppression. Therefore, unlike the conventional case, for example, when used in a receiving circuit, the strong electric field When a high-frequency signal is input, it is possible to prevent a conversion gain suppression from increasing and cause a significant deterioration in reception sensitivity, and to provide a frequency conversion circuit with stable operating characteristics.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a circuit configuration in the first configuration example will be described with reference to FIG.
In the first configuration example, a field effect transistor (hereinafter referred to as “dual gate FET”) 1 having a dual gate structure is used for frequency conversion.
That is, first, the second gate (denoted as “G2” in FIG. 1) of the dual gate FET 1 is connected to the ground potential via the first gate resistor 11 and the first DC cut capacitor. 25 and the first impedance matching circuit 21 are connected to the high frequency signal input terminal 35. An external high frequency signal is applied to the high frequency signal input terminal 35.
The first gate (denoted as “G1” in FIG. 1) of the dual gate FET 1 is connected to the ground potential via the second gate resistor 12, and the second DC cut capacitor 26 and The local signal input terminal 36 is connected via the second impedance matching circuit 22. The local signal input terminal 36 is applied with a local oscillation signal from the outside.
[0009]
On the other hand, the drain (denoted as “D1” in FIG. 1) of the dual gate FET 1 is connected to the output terminal 39 via the third impedance matching circuit 23 and the third DC cut capacitor 27. Yes. One end of a high frequency cutoff inductor 31 is connected to a connection point between the third impedance matching circuit 23 and the third DC cut capacitor 27. The other end of the high frequency cutoff inductor 31 is connected to a power supply application terminal 37 to which a power supply voltage is applied from the outside, and the high frequency cutoff inductor 31 and the third impedance matching circuit 23 are connected to the drain of the dual gate FET 1. A power supply voltage is applied via the.
Furthermore, the source of the dual gate FET 1 (denoted as “S1” in FIG. 1) is connected to one end of the self-bias resistor 14 and the bypass capacitor 29, and the other end of the self-bias resistor 14 and the bypass capacitor 29 is Are connected to the ground potential.
[0010]
In addition, the frequency converter circuit includes a second field effect transistor (hereinafter referred to as “second FET”) 2 as a main component, and includes a strong electric field gain adjusting means as described below. Yes.
That is, first, the second FET 2 is preferably an enhancement type, and its gate (indicated as “G3” in FIG. 1) is connected to the first first FET 2 via the fourth DC cut capacitor 28. It is connected to a connection point between the impedance matching circuit 21 and the first DC cut capacitor 25, and is connected to the ground potential via the third gate resistor 13.
Further, the drain of the second FET 2 (denoted as “D3” in FIG. 1) is connected to the source of the previous dual gate FET 1, while the source (denoted as “S3” in FIG. 1) is ground potential. Is connected to. Therefore, the second FET 2 is provided in a state of being connected in parallel to the self-bias resistor 14 and the bypass capacitor 29.
[0011]
In the above configuration, a part of the high-frequency signal applied to the high-frequency signal input terminal 35 is applied to the gate of the second FET 2 through the fourth DC cut capacitor 28. This is determined by the capacitance value of the fourth DC cut capacitor 28, the resistance value of the third gate resistor 13, and the gate width of the second FET 2.
More specifically, these circuit constants are set from the following viewpoints.
That is, first, when a high-frequency signal having a weak electric field is applied to the high-frequency signal input terminal 35, the drain-source current of the second FET 2 becomes substantially zero as compared with the current flowing through the self-bias resistor 14. On the other hand, when a high frequency signal of a strong electric field is applied to the high frequency signal input terminal 35, the sum of the drain-source current of the second FET 2 and the current flowing through the self-bias resistor 14 becomes a desired current value. As described above, the capacitance value of the fourth DC cut capacitor 28, the resistance value of the third gate resistor 13, and the gate width of the second FET 2 are set.
The circuit in the above configuration is preferably a semiconductor integrated circuit, but of course, it may be configured as a so-called discrete.
[0012]
Next, the operation in the above configuration will be described.
First, when a high-frequency signal of a weak electric field is applied to the high-frequency signal input terminal 35, the second FET 2 has almost no current (drain-source current) due to the operating conditions of the circuit described above. Therefore, the bias current in this frequency conversion circuit is only the current flowing through the self-bias resistor 14 connected between the source of the dual gate FET 1 and the ground potential, and the value is the desired frequency conversion. A low current value is set in consideration of the characteristics of the circuit.
On the other hand, when a high-frequency signal of a strong electric field is applied to the high-frequency signal input terminal 35, a current also flows between the drain and source of the second FET 2, and the current flowing through the self-bias resistor 14 As described above, the sum becomes a predetermined value by setting circuit constants. That is, more specifically, the current value is such that the linear operation region of the frequency conversion circuit becomes high. As a result, in a state where a strong electric field interference wave signal is input, the conversion gain suppression characteristic is greatly improved unlike the conventional case.
[0013]
Next, the operation characteristics in the above configuration example will be described in comparison with those of the conventional circuit with reference to FIG. 3 and FIG.
First, FIG. 3 shows a test result by simulation of the conversion gain with respect to the input power of the interference wave signal and the power supply current characteristic in the above configuration example, and FIG. 5 shows a similar characteristic example in the conventional circuit. Has been.
In any of the figures, the horizontal axis indicates the interference wave input power, and the vertical axis indicates the conversion gain and the power supply current. In any of the drawings, the alternate long and short dash line is a characteristic line indicating a change in the power supply current with respect to the disturbance wave input power change, and the solid line is a characteristic line indicating a change in conversion gain with respect to the disturbance wave input power change.
Comparing the interference wave input power, in the case of the conventional circuit, the interference wave input power when the conversion gain is compressed by 1 dB is −11.5 dBm (see FIG. 5). In the first configuration example of the embodiment, the interference wave input power is −7.3 dBm (see FIG. 3), and the conversion gain suppression characteristic at the time of the interference wave input signal is improved by about 4.2 dB compared to the conventional case. You can see that Note that the operating characteristics in the weak electric field are almost the same in both the circuit in the embodiment of the present invention and the conventional circuit (see FIGS. 3 and 5).
[0014]
Next, a second configuration example will be described with reference to FIG.
The same components as those shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below. In this second configuration example, the circuit portion configured around the second FET 2 in the previous first configuration example is configured around the second to fourth field effect transistors 2 to 4 connected in cascade. It has been replaced with the circuit.
Specifically, the second to fourth field effect transistors (hereinafter referred to as “second FET”, “third FET”, and “fourth FET”, respectively) 2 will be described in detail below. It is preferable that enhancement type field effect transistors are used for .about.4.
The second FET 2 has a gate connected to a connection point between the first impedance matching circuit 21 and the first DC cut capacitor 25 via a fourth DC cut capacitor 28, and a third FET 2. The gate resistor 13 is connected to the ground potential, while the source is directly connected to the ground potential, which is the same as the first configuration example shown in FIG. .
The drain of the second FET 2 is connected to the gate of the third FET 3 (denoted as “G4” in FIG. 2), and the drain of the second FET 2 and the gate of the third FET 3 are Both are connected to a second power supply application terminal 38 via a fourth resistor 15 as a first voltage application resistor, so that a power supply voltage is applied.
[0015]
The third FET 3 has a drain (denoted as “D4” in FIG. 2) and a gate of the fourth FET 4 (denoted as “G5” in FIG. 2) and a fifth resistor as a second voltage application terminal. The power supply voltage is applied to each of the second power supply application terminals 38 via the devices 16. The source of the third FET 3 (indicated as “S4” in FIG. 2) is connected to the ground potential together with the source of the fourth FET 4 (indicated as “S5” in FIG. 2) described below. It has become.
The drain of the fourth FET 4 (denoted as “D5” in FIG. 2) is connected to the source of the dual gate FET 1.
[0016]
Next, the operation in the above configuration will be described.
First, a case where a high-frequency signal having a weak electric field is applied to the high-frequency signal input terminal 35 will be described. A part of the high-frequency signal applied to the high-frequency signal input terminal 35 is passed through the fourth DC cut capacitor 28. 1 is applied to the gate of the second FET 2, and the applied voltage amplitude is equal to or smaller than a voltage (pinch-off voltage) that can make the second FET 2 conductive. Since the circuit constants are determined as described in the first configuration example shown in (2), the second FET 2 is in a non-conductive state.
Due to the non-conduction of the second FET 2, a power supply voltage equal to or higher than the pinch-off voltage is applied to the gate of the third FET 3 from the outside via the fourth resistor 15. It becomes a state.
Since the third FET 3 is conductive, the potential difference between the drain and the source becomes almost zero V. Therefore, the gate of the fourth FET 4 has a pinch-off voltage that is sufficient to bring the fourth FET 4 into a conductive state. No DC bias voltage is applied, and the fourth FET 4 becomes non-conductive.
That is, when a high-frequency signal having a weak electric field is applied to the high-frequency signal input terminal 35, the current flowing between the drain and source of the fourth FET 4 is substantially zero as compared with the current flowing through the self-bias resistor 14. It has become.
Therefore, in this case, a bias current flows only through the self-bias resistor 14, and the value thereof is a low current value set in view of the desired characteristics of the frequency conversion circuit.
[0017]
On the other hand, when a high-frequency signal of a strong electric field is applied to the high-frequency signal input terminal 35, the second FET 2 becomes conductive by the high-frequency signal applied via the fourth DC cut capacitor 28, thereby The third FET 3 is turned off. Therefore, as a result of the power supply voltage being applied to the gate of the fourth FET 4 via the fifth resistor 16, the fourth FET 4 becomes conductive.
In this case, the sum of the current flowing between the drain and source of the fourth FET 4 and the current flowing through the self-bias resistor 14 becomes a desired current value.
That is, as in the first configuration example shown in FIG. 1, when the high-frequency signal of the strong electric field is applied to the high-frequency signal input terminal 35 and the fourth FET 4 becomes conductive, The capacitance value of the DC cut capacitor 28, the resistance value of the third gate resistor 13, the gate widths of the second to fourth FETs 2 to 4, and the resistance values of the fourth and fifth resistors 15 and 16 are The sum of the current flowing between the drain and the source of the FET 4 and the current flowing through the self-bias resistor 14 is set to a suitable value that is a desired current value.
[0018]
In the above configuration example, a dual-gate field effect transistor is used to obtain a frequency conversion operation. However, the present invention is not limited to this. For example, a so-called single-gate field effect transistor has a stacked structure. Of course, they may be connected.
[0019]
【The invention's effect】
As described above, according to the present invention, the configuration is such that the increase in conversion gain suppression is prevented only when a high-frequency signal input with a strong electric field occurs. In addition, the increase in circuit size and area can be minimized as much as possible, and the bias current is adjusted only when a high-frequency signal with a strong electric field is input. In addition, the bias current can be reduced and the power consumption can be suppressed.
Further, when a high-frequency signal of a strong electric field is input, an effect is obtained that a frequency conversion circuit can be provided in which the bias current is efficiently increased to suppress conversion gain suppression.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first configuration example of a frequency conversion circuit according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a second configuration example of the frequency conversion circuit in the embodiment of the present invention.
FIG. 3 is a characteristic diagram showing conversion gain and power supply current change characteristics with respect to changes in interference wave input power in the first configuration example according to the embodiment of the present invention;
FIG. 4 is a circuit diagram showing an example of a conventional circuit.
FIG. 5 is a characteristic diagram showing a change characteristic of a conversion gain and a power supply current with respect to a change in interference wave input power of a conventional circuit.
[Explanation of symbols]
1 ... Dual gate FET
2 ... Enhancement-type second FET
3 ... Enhancement-type third FET
4 ... Enhancement-type fourth FET
14 ... Self-bias resistor 35 ... High-frequency signal input terminal 36 ... Local signal input terminal 39 ... Output terminal

Claims (3)

In a frequency conversion circuit using a field effect transistor having a strong electric field gain adjusting means for suppressing an increase in conversion gain suppression when a high-frequency signal of a strong electric field is input,
The field effect transistor has a dual gate structure, and a self-bias resistor and a bypass capacitor connected in parallel are provided in series between the source of the dual gate field effect transistor and the ground potential. on the other hand,
The strong electric field gain adjusting means includes an enhancement type field effect transistor, and is configured so that a part of a high frequency signal is applied to the gate of the enhancement type field effect transistor, and the enhancement type electric field effect transistor. The frequency conversion circuit according to claim 1, wherein the effect transistor is connected in parallel to the self-bias resistor and the bypass capacitor. In a frequency conversion circuit using a field effect transistor having a strong electric field gain adjusting means for suppressing an increase in conversion gain suppression when a high-frequency signal of a strong electric field is input,
The field effect transistor has a dual gate structure, and a self-bias resistor and a bypass capacitor connected in parallel are provided in series between the source of the dual gate field effect transistor and the ground potential. on the other hand,
The strong field gain adjusting means includes enhancement type first to third field effect transistors, and the enhancement type first field effect transistor is provided so that a part of a high frequency signal is applied to a gate thereof. The drain is connected to the gate of the enhancement type second field effect transistor, and the drain of the enhancement type first field effect transistor and the gate of the enhancement type second field effect transistor include A power supply voltage can be applied via the first voltage application resistor,
The drain of the enhancement type second field effect transistor is connected to the gate of the enhancement type third field effect transistor, and the drain of the enhancement type second field effect transistor and the enhancement type third field effect transistor. A power supply voltage can be applied to the gate of the gate via a second voltage application resistor,
The enhancement type first to third field effect transistors have a source connected to a ground potential,
The enhancement-type third field effect transistor is connected in parallel to the self-bias resistor and a bypass capacitor. 3. The frequency conversion circuit according to claim 1, wherein two field effect transistors having a single gate structure are connected in a stack structure instead of the dual gate field effect transistor.

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