JP3899236B2 - Manufacturing method of image sensor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
This invention relates to a method of manufacturing a CMOS image sensor using a submicron CMOS (complementary metal oxide semiconductor) technology.
[0002]
[Prior art]
In addition to the existing image sensor market, the demand for CMOS image sensors is growing rapidly in the fields of digital still cameras (DSC), mobile phones, personal computers (PCs), and personal digital assistants (PDAs). The importance is increasing.
[0003]
The CMOS image sensor has excellent features in terms of a single power source, low voltage drive, and low power consumption, as compared with a CCD (Charge Coupled Device) image sensor widely used as an image sensor at present. In addition, a simple and versatile scanning method can be put into practical use, and the signal processing circuit can be integrated on a single chip, so that the product can be reduced in size and weight. Further, since a CMOS technology similar to that of the logic process is used, a dedicated production line such as a CCD image sensor is not required even during production.
[0004]
The CMOS image sensor is also increasing in the number of pixels as in the CCD, and employs a configuration in which a photoelectric conversion element and a transistor are provided on the same substrate. Then, the potential of the signal charge accumulating portion is modulated by the signal charge generated by the photoelectric conversion element, and the amplification transistor inside the pixel is modulated by the potential, thereby giving the amplification function inside the pixel.
[0005]
As for the photodiode of the photoelectric conversion part of the CMOS image sensor, a structure embedded in the substrate and a structure in which the surface of the photodiode substrate is shielded by a P-type semiconductor layer has recently become mainstream, as in the CCD. It's getting on. FIG. 6 shows a cross section of a unit pixel portion in a conventional CMOS image sensor. In FIG. 6, the unit pixel portion includes four transistors 4 to 7 and a photodiode 8 formed in a region defined by the element isolation region 3 in the P-type epitaxial layer 2 on the P ⁺ silicon substrate 1. The The photodiode 8 includes a P-type semiconductor layer 9 on the substrate surface and an N ⁻ region 10 therebelow. Further, N ⁺ regions 11 and 12 as source / drain regions are formed in the respective transistors 4 to 7.
[0006]
In the CMOS image sensor having the above-described configuration, as described above, the surface of the photodiode 8 is shielded by the P-type semiconductor layer 9, so that a current generated from a defect level existing on the substrate surface of the photodiode 8 is photogenerated. It can be prevented from flowing into the diode 8, and as a result, defects such as white scratches can be greatly reduced.
[0007]
Note that 13 is a channel stopper region, 14 is a gate insulating film, 15 is a gate electrode, 16 is a CVD (chemical vapor deposition) oxide film, and 17 is a P ^- well.
[0008]
[Problems to be solved by the invention]
However, in the conventional CMOS image sensor, since the embedded photodiode 8 is formed in a certain region between the read transistor 4 and the element isolation region 3, the unit area of the embedded photodiode 8 can be increased. There is a problem that the integration degree must be reduced. In addition, since the area of the embedded photodiode 8 is reduced as the design rule is miniaturized, there is a problem that the sensitivity is significantly reduced as the design rule is miniaturized.
[0009]
In order to increase the unit area without reducing the degree of integration, a photodiode formed along the wall surface of a trench formed in a semiconductor substrate has been proposed (Japanese Patent Laid-Open No. 2000-31455). However, in this case, there is a concern that junction leakage current increases due to etching damage at the time of trench formation or stress due to an insulating film or the like filled in the trench. Furthermore, it is difficult to accurately form a P / N / P junction on an uneven portion, and there is a problem that when ion implantation from an oblique direction is used, throughput is increased and production efficiency is remarkably deteriorated.
[0010]
Accordingly, an object of the present invention is to provide a and manufacturing method of the photodiode CMOS image sensor capable of increasing the unit area of using a predetermined design rule without reducing the degree of integration.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the manufacturing method of the inventions image sensor of this is,
Forming an element isolation region made of an insulating film on a semiconductor substrate surface;
Forming a plurality of first channel regions on the semiconductor substrate;
Forming a first gate insulating film on the semiconductor substrate including the first channel region;
Forming a plurality of first gate electrodes on the first gate insulating film;
Forming a first high concentration impurity region in the semiconductor substrate adjacent to each of the first channel regions;
Forming a photoelectric conversion element between the isolation region and the first channel region in the surface of the semiconductor substrate,
Forming a semiconductor layer on the semiconductor substrate including the first gate electrode via an interlayer insulating film;
Forming a plurality of second channel regions in the semiconductor layer;
Forming a second gate insulating film on the semiconductor layer including the second channel region;
Forming a plurality of second gate electrodes on the second gate insulating film;
Forming a low-concentration impurity region in the semiconductor layer adjacent to both side edges in each of the second channel regions;
Forming a second high-concentration impurity region by converting a region to be a source region of the transistor later in the low-concentration impurity region into a high-concentration impurity region,
Signals generated by the photoelectric conversion element in the first channel, the first gate electrode and the first high concentration impurity region, and in the second channel, the second gate electrode, the second high concentration impurity region and the low concentration impurity region. An amplification transistor that performs charge amplification, a selection transistor that selects a signal amplified by the amplification transistor and outputs the selected signal to a signal line, and the signal remaining on the wiring between the photoelectric conversion element and the amplification transistor A reset transistor for discharging electric charge is formed.
[0012]
According to the above configuration, the transistor for selecting, amplifying, and resetting the signal charge generated by the photoelectric conversion element includes the lower layer transistor formed on the semiconductor substrate, and the upper layer transistor formed on the lower layer transistor. It has a two-layer structure. Therefore, if the same design rule as that of the conventional image sensor is applied, the occupied area of the transistor region is reduced, the occupied area of the photoelectric conversion element is increased, and the photosensitivity characteristics are improved. Alternatively, if the same photosensitivity characteristic as that of a conventional image sensor is obtained, the degree of integration is improved.
[0013]
At this time, the second channel region and the second high-concentration impurity region of the upper transistor are formed in the semiconductor layer stacked on the lower transistor via an interlayer insulating film. In this way, a two-layer transistor can be easily formed by conventional film formation techniques, doping techniques, photoetching techniques, and the like.
[0014]
Further, according to the first embodiment, in the method of manufacturing an image sensor of the present invention, the formation of the low concentration impurity region in the semiconductor layer in the step of forming the low concentration impurity region, and the second high concentration impurity. In the step of forming a region, the formation of the high concentration impurity region in the low concentration impurity region is performed in a self-aligned manner with respect to the second gate electrode.
[0015]
According to this embodiment, the second high concentration impurity region or the low concentration impurity region is formed in the semiconductor layer in a self-aligned manner with respect to the second gate electrode. Thus, by using a relatively simple method, it becomes possible to easily cope with miniaturization.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is a cross-sectional view showing a configuration of a unit pixel portion in a CMOS image sensor which is an image sensor of the present embodiment. FIG. 2 is a circuit diagram of the unit pixel portion.
[0017]
As shown in FIG. 1, the CMOS image sensor according to the present embodiment mainly includes an element isolation insulating film 32 formed on a semiconductor substrate 31, transistors 22 and 24 formed on the semiconductor substrate 31, A semiconductor layer 38 formed on the transistors 22 and 24 via an interlayer insulating film 37, thin film transistors 26 and 28 formed on the semiconductor layer 38, and at least a first conductivity type formed on the surface of the semiconductor substrate 31 And a photodiode 25 comprising a second conductivity type junction.
[0018]
The transistors 22 and 24 include a first channel region 33 formed on the semiconductor substrate 31, a first gate insulating film 34, and a first gate electrode 35 formed on the first gate insulating film 34. The first high-concentration impurity region 36 is formed on the surface of the semiconductor substrate 31 so as to be adjacent to the first channel region 33. The thin film transistors 26 and 28 include a second channel region 38a formed in the semiconductor layer 38, a second gate insulating film 39, a second gate electrode 40 formed on the second gate insulating film 39, The second high concentration impurity region 38b is formed in the semiconductor layer 38 so as to be adjacent to the second channel region 38a.
[0019]
The semiconductor substrate 31 is not particularly limited as long as it is a semiconductor substrate used in manufacturing a normal semiconductor device. For example, a semiconductor substrate such as silicon or germanium, or a compound such as SiC, GaAs, InGaAs, or the like. A semiconductor substrate etc. are mentioned. Of these, a silicon substrate is preferable, and an SOI (silicon-on-insulator) substrate, a bonded SOI, or SIMOX (separation by implanted oxygen) substrate may be used.
[0020]
The insulating film 32 formed on the semiconductor substrate 31 for element isolation may use either LOCOS (silicon selective oxidation) or a trench. However, when the LOCOS is used, the oxide film thickness is preferably about 250 nm to 400 nm. When the trench is used, the side wall may be formed to have a taper of about 75 to 85 degrees with respect to the substrate surface. The depth of the trench can be appropriately adjusted depending on the element isolation withstand voltage to be obtained, and is preferably about 250 nm to 500 nm, for example. Further, after the trench formation, it is desirable to oxidize about 10 nm to 30 nm for the purpose of rounding the corners of the surface and the bottom to suppress the influence of the electric field concentration and the generation of crystal defects.
[0021]
The first channel region 33 constitutes the read transistor 24 and the reset transistor 22 and is formed on the surface of the semiconductor substrate 31 on which the read transistor 24 and the reset transistor 22 are formed. The first channel region 33 can be appropriately set to a desired conductivity type by ion implantation or the like. In general, the read transistor 24 and the reset transistor 22 are configured by N type depletion transistors having a negative threshold value in order to increase charge conduction efficiency.
[0022]
The first gate insulating film 34 forms the read transistor 24 and the reset transistor 22 and is formed on the entire surface of the semiconductor substrate 31. Usually, it can be formed by depositing a material used as a gate insulating film with a desired film thickness by thermal oxidation or the like. The film thickness at that time is preferably about 3 nm to 10 nm, for example.
[0023]
The first gate electrode 35 constitutes the read transistor 24 and the reset transistor 22 and is formed on the first gate insulating film 34 on the surface of the semiconductor substrate 31. The first gate electrode 35 may be formed of any material as long as it functions as an electrode, but is preferably formed of polysilicon having an impurity concentration of the order of about 1E + 20 / cm ³ . The film thickness is not particularly limited as long as it can function as a gate electrode. However, it is necessary to adjust the film thickness appropriately in consideration of the capability, wiring resistance, and the like of the transistor to be obtained. The film thickness of the first gate electrode 35 is preferably about 100 nm to 200 nm, for example.
[0024]
A low concentration impurity region may be formed between the first channel region 33 and the first high concentration impurity region (source / drain region) 36 together with the formation of the sidewalls by the CVD oxide film.
[0025]
The first high-concentration impurity region 36 constitutes the read transistor 24, the reset transistor 22, and the photodiode 25, and is formed in each of the source / drain regions of the read transistor 24 and the reset transistor 22 and the region of the photodiode 25. Is done.
[0026]
The semiconductor layer 38 on which the amplification transistor 26 and the selection transistor 28 are formed is formed via an interlayer insulating film 37 so as to be located on the read transistor 24 and the reset transistor 22. The thickness of the interlayer insulating film 37 is preferably about 100 nm to 300 nm, for example. The semiconductor layer 38 may be formed of any material that functions as an active layer. For example, amorphous silicon is crystallized by annealing in nitrogen at 550 ° C. to 620 ° C. or laser annealing. A polysilicon layer is desirable. The film thickness of the semiconductor layer 38 is preferably about 30 nm to 70 nm. The semiconductor layer 38 is doped with impurities corresponding to the threshold value of the transistor in consideration of the performance of the transistor. For example, in addition to ion implantation, impurity doping may be performed in-situ during deposition of amorphous silicon. An impurity concentration of about 1E + 17 / cm ^{3 to} 5E + 17 / cm ³ is appropriate. In the semiconductor layer 38, a second channel region 38a and a second high-concentration impurity region 38b to be a source / drain region are formed.
[0027]
The second gate insulating film 39 constitutes the amplification transistor 26 and the selection transistor 28 and is formed so as to cover the surface of the semiconductor layer 38. The second gate insulating film 39 is usually a CVD silicon oxide film and is formed with a desired film thickness. The film thickness of the second gate insulating film 39 is preferably about 20 nm to 50 nm, for example. From the viewpoint of electrical characteristics, in order to suppress the leakage current, it is possible to increase the film density under conditions as high as possible within a range that does not affect the characteristics of the underlying transistors (the read transistor 24 and the reset transistor 22). desirable. The temperature in that case is, for example, about 700 ° C. to 800 ° C.
[0028]
The second gate electrode 40 constitutes the amplification transistor 26 and the selection transistor 28 and is formed on the second gate insulating film 39. The second gate electrode 40 may be any material as long as it functions as an electrode, but is preferably formed of polysilicon having an impurity concentration on the order of 1E + 20 / cm ³ . The film thickness is not particularly limited as long as it can function as a gate electrode, and is preferably about 100 nm to 150 nm, for example.
[0029]
The second high-concentration impurity regions 38b that serve as the source / drain regions of the amplification transistor 26 and the selection transistor 28 are formed in the semiconductor layer 38 using the second gate electrode 40 as a mask. In this case, the impurity concentration is not particularly limited as long as the impurity concentration functions as a source / drain region, and may be an impurity concentration of about 1E + 19 / cm ^{3 to} 1E + 20 / cm ³ .
[0030]
In the CMOS image sensor, the transistors 22, 24 formed on the semiconductor substrate 31 and the thin film transistors 26, 28 formed on the semiconductor layer 38 on the transistors 22, 24 are provided in advance in the first channel region 33 or the second channel. It is desirable that a low-concentration impurity region is formed adjacent to 38a. The impurity concentration in the low-concentration impurity region is not particularly limited as long as it can function as an offset region of the source / drain region, and an impurity concentration of about 1E + 18 / cm ^{3 to} 1E + 19 / cm ³ is desirable.
[0031]
Further, the thin film transistors 26 and 28 formed in the semiconductor layer 38 may be formed of a bottom gate structure or a double gate structure transistor in addition to the top gate structure transistor as described above.
[0032]
In general, an N ⁺ / P junction is widely used as the photodiode 25 serving as a photoelectric conversion unit, but the structure thereof can be appropriately changed according to the purpose and device specifications. For example, a P ⁺ / N ⁻ / P structure in which the surface portion of the semiconductor substrate 31 is shielded by a P-type semiconductor layer may be used. In this case, by shielding with the P-type semiconductor layer, it is possible to prevent a current generated from a defect level existing on the substrate surface of the photodiode from flowing into the photodiode, and to reduce defects such as white scratches. It can be done.
[0033]
Next, the operation of the CMOS image sensor having the above configuration will be described with reference to FIG. First, the voltage level of the reset line 21 is set to “H” to turn on the reset transistor 22, and the charge remaining on the wiring is discharged to the drain line 23. After that, the reset transistor 22 is turned off. Next, by turning on the read transistor 24, carriers generated by photoelectric conversion of the photodiode 25 flow into the gate of the amplification transistor 26. At this time, when the read transistor 24 is turned off, charges are accumulated in the gate of the amplification transistor 26 and the amplification transistor 26 is turned on. At the same time, when the level of the address line 27 is set to “H” and the selection transistor 28 is turned on, a signal is read out to the signal line 29.
[0034]
Here, the transistors 22 and 24 formed on the semiconductor substrate 31 in FIG. 1 correspond to the read transistor 24 and the reset transistor 22 in FIG. In FIG. 1, the thin film transistors 26 and 28 formed in the semiconductor layer 38 formed on the transistors 22 and 24 via the interlayer insulating film 37 correspond to the amplification transistor 26 and the selection transistor 28 in FIG. Further, the photodiode 25 formed on the surface of the semiconductor substrate 31 in FIG. 1 corresponds to the photodiode 25 in FIG.
[0035]
A method for manufacturing the CMOS image sensor having the above configuration will be described below. As shown in FIG. 3, the present CMOS image sensor is formed in a P-type epitaxial layer 52 formed on a P ⁺ silicon substrate 51 having a specific resistance of 0.01 Ωcm to 0.1 Ωcm. The specific resistance of the P-type epitaxial layer 52 is 10 Ωcm to 20 Ωcm, and the thickness is 5 μm to 10 μm. On the surface of the P-type epitaxial layer 52, an element isolation film 53 by LOCOS is formed with a film thickness of 200 nm to 400 nm. Thereafter, a silicon nitride film (not shown) and an insulating film (not shown) used as a mask for selective oxidation are sequentially removed.
[0036]
Next, a silicon oxide film (not shown) serving as a mask at the time of implantation is formed on the surface of the P-type epitaxial layer 52 with a thickness of 10 nm to 20 nm. Then, phosphorus ions of about 1E + 12 cm ^{−2 to} 1E + 13 cm ⁻² are implanted into regions where the read transistor 54 and the reset transistor 55 are to be formed, thereby forming first channel regions 56 and 56. Next, after forming the first gate insulating films 57, 57 on the first channel regions 56, 56, polysilicon to be the first gate electrodes 58, 58 is deposited by the CVD method. Then, phosphorus is ion-implanted into the polysilicon to perform doping to an impurity concentration of about 1E + 20 / cm ^{3 to} 5E + 20 / cm ³ . Thereafter, the polysilicon is processed to form the first gate electrodes 58 and 58 of the read transistor 54 and the reset transistor 55, and the first CVD silicon oxide film is formed around the first gate electrodes 58 and 58 by a known method. A side wall 59 is formed.
[0037]
Next, an abrasive of about 1E + 15 cm ^{−2 to} 5E + 15 cm ⁻² is ion-implanted at 40 keV to 90 keV into the formation region of the read transistor 54 and the reset transistor 55 in the P-type epitaxial layer 52 to form a first source / drain. High concentration impurity regions 60, 60 are formed. Thereafter, the formation region of the photodiode 61 between the first channel region 56 of the isolation layer 53 and the read transistor 54 on the surface of the P-type epitaxial layer 52, of about 1E + 12cm ^-2 ~1E + 14cm ^-2 in 100keV~200keV Phosphorus is ion implanted to form the N ⁻ region 62. Furthermore, the 1E + 13cm ^-2 ~1E + 15cm ^-2 about boron fluoride (BF ₂₎ is ion-implanted at 20keV~50keV, N ^- forming a ^{P +} region 63 in the surface of the region 62. Reference numeral 64 denotes a channel stopper region.
[0038]
Next, as shown in FIG. 4, a second CVD silicon oxide film having a thickness of about 100 nm to 300 nm is formed as an interlayer insulating film 65 on the entire surface. After that, as the semiconductor layer 68 serving as an active layer of the amplification transistor 66 and the selection transistor 67, amorphous silicon is deposited with a film thickness of about 30 nm to 70 nm by a CVD method, and nitrogen at 550 ° C. to 620 ° C. using a diffusion furnace. A polysilicon layer is formed by annealing inside or laser annealing. Then, the semiconductor layer (active layer) 68 is formed by removing the regions located above the read transistor 54 and the reset transistor 55 by photoetching. The semiconductor layer 68 is doped with an impurity corresponding to the threshold value of the transistor. In this case, the impurity doping is performed by ion implantation or by using in-situ doping at the time of depositing amorphous silicon. Then, the second channel region 68 a having an impurity concentration containing, for example, boron of about 1E + 17 / cm ^{3 to} 5E + 17 / cm ³ is formed in the semiconductor layer 68.
[0039]
Thereafter, a second CVD insulating film 69 is formed by depositing a third CVD silicon oxide film with a thickness of about 20 nm to 50 nm so as to cover the surface of the semiconductor layer 68 including the second channel region 68a. . At this time, for the purpose of reducing the interface state density between the second gate insulating film 69 and the polysilicon, before depositing the third CVD silicon oxide film, the surface of the semiconductor layer 68 made of polysilicon is set to 4 nm to 10 nm. The second gate insulating film 69 may be partially oxidized to be oxidized. Then, after depositing a second polysilicon to a thickness of about 100 nm to 150 nm, the second polysilicon above the phosphorus of about 1E + 15cm ^-2 ~1E + 16cm ^-2 by ion implantation 1E + 20 atoms / cm ³ ~5E + 20 pieces Doping is performed so that the impurity concentration is about / cm ³ . After that, photoetching is performed on the second polysilicon to form second gate electrodes 70 and 70.
[0040]
Next, phosphorus of about 1E + 13 cm ⁻² to 1E + 14 cm ⁻² is ion-implanted into the semiconductor layer 68 using the second gate electrodes 70 and 70 as a mask, so that the semiconductor layer 68 is adjacent to the second channel region 68a. Thus, a low concentration impurity region 68b is formed.
[0041]
Next, as shown in FIG. 5, after forming a mask (not shown) with a photoresist in the low concentration impurity region 68b on one side which becomes the drain region of the amplification transistor 66 and the selection transistor 67, the semiconductor layer Phosphorus of about 1E + 14 cm ⁻² to 1E + 15 cm ⁻² is ion-implanted into the semiconductor layer 68 to form a second high-concentration impurity region 68 c serving as a source region adjacent to the second channel region 68 a in the semiconductor layer 68. By doing so, the low concentration impurity region 68b can be formed in a self-aligned manner on the drain region side of the transistors 66 and 67. Note that, in forming the low concentration impurity region 68b and the second high concentration impurity region 68c, an impurity which becomes an N-type dopant such as arsenic may be used in place of the phosphorus. The low-concentration impurity region 68b may be formed as appropriate according to the characteristics of a desired transistor or the like.
[0042]
Next, a fourth CVD silicon oxide film 71 is laminated and planarized on the entire surface including the amplification transistor 66 and the selection transistor 67 with a thickness of about 500 nm to 1000 nm. After that, a contact hole 72 is opened in the silicon oxide film 71, a metal layer such as aluminum is laminated on the entire surface, and photoetching is performed to form a wiring 73.
[0043]
As described above, in the unit pixel portion, the CMOS image sensor having a structure in which the amplification transistor 66 and the selection transistor 67 are stacked on the readout transistor 54 and the reset transistor 55 with the interlayer insulating film 65 interposed therebetween. Is formed.
[0044]
As described above, in the present embodiment, in the unit pixel portion, the amplification transistors 26 and 66 and the selection transistors 28 and 67 are connected to the readout transistors 24 and 54 and the reset transistors 22 and 55 via the interlayer insulating films 37 and 65. They are stacked on top of each other. Therefore, when a predetermined design rule is applied, the region between the element isolation films 32 and 53 and the read transistors 24 and 54 is set to the read transistor 4, the reset transistor 7, the amplification transistor 5 and the selection as shown in FIG. It can be made wider than a conventional CMOS image sensor in which the transistor 6 is arranged in the same layer. As a result, the regions of the photodiodes 25 and 61 formed between the element isolation films 32 and 53 and the read transistors 24 and 54 can be widened, and the sensitivity can be improved.
[0045]
That is, according to the present embodiment, if the same design rule as that of a conventional CMOS image sensor is applied, the occupied area of the transistor region can be reduced and the occupied area of the photodiode can be increased, and the photosensitivity characteristics can be obtained. Can be improved. Further, if the same photosensitivity characteristic as that of the conventional CMOS image sensor is obtained, the degree of integration can be increased.
[0046]
In the present embodiment, the source / drain regions of the amplifying transistors 26 and 66 and the selection transistors 28 and 67 are interlayer insulating films generated by the presence of the readout transistors 24 and 54 and the reset transistors 22 and 55 located in the lower stage. It is formed in the inclined part in the level | step difference of 37,65. Therefore, there is an effect that the electrolytic concentration at the boundary between the source / drain region and the second channel regions 38a and 68a is easily relaxed.
[0047]
Note that the layout of the above four transistors can be freely set up and down or in combination as necessary. That is, the photodiodes 25 and 61 in the above embodiment are P / N / P junction type, but may be N / P junction type. In that case, the read transistors 24 and 54 can be omitted. That is, in the present invention, a structure in which at least three transistors are stacked in a unit pixel may be employed.
[0048]
In the said embodiment, although the preferable example of this invention was shown, this invention is not limited to the said embodiment, You may deform | transform suitably. For example, contact holes for connecting the upper and lower transistors, annealing in a hydrogen atmosphere for improving the switching characteristics of the thin film transistors 26, 66; 28, 67 having active layers 38, 68 made of polysilicon, Annealing or the like in a nitrogen atmosphere after ion implantation for suppressing junction leakage due to defects or the like can be added.
[0049]
【The invention's effect】
As is clear from the above, the production method of Lee Mejisensa of this invention, on a semiconductor substrate, a first channel region, a first gate insulating film, forming a first gate electrode and the first high concentration impurity region, the A photoelectric conversion element is formed on the surface of the semiconductor substrate, a semiconductor layer is formed on the semiconductor substrate including the first gate electrode via an interlayer insulating film, and a second channel region and a second gate insulation are formed on the semiconductor layer. The film, the second gate electrode, and the low concentration impurity are formed, and the second high concentration impurity region is formed by converting the low concentration impurity region into a region that will later become the source region of the transistor to form the second high concentration impurity region. A transistor for selecting, amplifying and resetting the signal charge generated by the transistor is formed on a lower transistor formed on the semiconductor substrate and on the lower transistor. It can be a two-layer structure of the transistor layer.
[0050]
Therefore, if the same design rule as that of the conventional image sensor is applied, the occupied area of the transistor region can be reduced and the occupied area of the photoelectric conversion element can be increased, and the photosensitivity characteristics can be improved. Alternatively, if the same light sensitivity characteristic as that of a conventional image sensor is obtained, the degree of integration can be improved.
[0051]
Further, since the second channel region and the second high-concentration impurity region of the upper layer transistor are formed in the semiconductor layer stacked on the lower layer transistor via an interlayer insulating film, a two-layer transistor is conventionally formed. The film can be easily formed by a film forming technique, a doping technique, a photo etching technique, and the like.
[0052]
Further, in the image sensor manufacturing method according to the first embodiment, the low concentration impurity region is formed in the semiconductor layer and the second high concentration impurity region is formed in the step of forming the low concentration impurity region. Since the low-concentration impurity region in the process is made to be a high-concentration impurity region in a self-aligned manner with respect to the second gate electrode, a relatively simple method for forming the second high-concentration impurity region and the low-concentration impurity region is used. By using it, it is possible to easily cope with miniaturization.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a unit pixel portion in a CMOS image sensor as an image sensor of the present invention.
FIG. 2 is a circuit diagram of a unit pixel unit shown in FIG.
FIG. 3 is a cross-sectional view of the CMOS image sensor shown in FIG. 1 in a certain manufacturing process.
4 is a sectional view in the manufacturing process, following FIG. 3; FIG.
FIG. 5 is a cross-sectional view in the manufacturing process, following FIG. 4;
FIG. 6 is a cross-sectional view of a unit pixel portion in a conventional CMOS image sensor.
[Explanation of symbols]
22, 55 ... reset transistor,
23 ... drain wire,
24, 54 ... Read transistor,
25, 61 ... Photodiode,
26, 66 ... amplification transistors,
28, 67 ... selection transistor,
29 ... Signal line,
31 ... Semiconductor substrate,
32. Insulating film for element isolation,
33, 56 ... first channel region,
34, 57 ... first gate insulating film,
35, 58 ... first gate electrode,
36, 60 ... first high concentration impurity region,
37, 65 ... interlayer insulating film,
38,68 ... semiconductor layer,
38a, 68a ... second channel region,
38b, 68c ... second high concentration impurity region,
39, 69 ... second gate insulating film,
40, 70 ... second gate electrode,
51 ... P ⁺ silicon substrate,
52 ... P-type epitaxial layer,
53. Element isolation film,
59… Sidewall,
62 ... N ^- region,
63 ... P ⁺ region,
68b ... low concentration impurity region,
71 ... Silicon oxide film,
72 ... contact hole,
73: Wiring.

Claims (5)

Forming an element isolation region made of an insulating film on a semiconductor substrate surface;
Forming a plurality of first channel regions on the semiconductor substrate ;
Forming a first gate insulating film on a semiconductor substrate comprising said first channel region,
Forming a plurality of first gate electrodes on the first gate insulating film;
Forming a first high-concentration impurity regions in the semiconductor substrate adjacent to the respective first channel area,
Forming a photoelectric conversion element between the element isolation region and the first channel region on the surface of the semiconductor substrate;
On the semiconductor substrate including the first gate electrode, and forming a semi-conductor layer through the interlayer insulating film,
Forming a plurality of second channel regions in the semiconductor layer;
Forming a second gate insulating film on the semiconductor layer including the second channel region,
Forming a plurality of second gate electrodes on the second gate insulating film;
Forming a low concentration impurity regions in the semiconductor layer adjacent to both side edges in each of the second channel region,
Forming a second high-concentration impurity region by converting a region that will later become a source region of the transistor from the low-concentration impurity region into a high-concentration impurity region;
Including
Signals generated by the photoelectric conversion element in the first channel , the first gate electrode and the first high concentration impurity region, and in the second channel , the second gate electrode , the second high concentration impurity region and the low concentration impurity region. An amplification transistor that performs charge amplification, a selection transistor that selects a signal amplified by the amplification transistor and outputs the selected signal to a signal line, and the signal remaining on the wiring between the photoelectric conversion element and the amplification transistor A method of manufacturing an image sensor , comprising forming a reset transistor for discharging electric charges . In the manufacturing method of the image sensor of Claim 1,
Forming the photoelectric conversion element step, the image sensor characterized by Rukoto comprise the step of forming a photodiode consisting of the junction of the at least a first conductivity type and the second conductivity type in said semiconductor substrate surface Manufacturing method . In the manufacturing method of the image sensor of Claim 1 ,
The step of forming the semiconductor layer includes a step of crystallizing by depositing an amorphous silicon layer on the interlayer insulating film and then solid-phase growth in a nitrogen atmosphere in a diffusion furnace. Manufacturing method . In the manufacturing method of the image sensor of Claim 1,
The method of manufacturing an image sensor , wherein the step of forming the semiconductor layer includes a step of crystallizing by laser annealing after depositing an amorphous silicon layer on the interlayer insulating film . In the manufacturing method of the image sensor of Claim 1 ,
The formation of the low concentration impurity region in the semiconductor layer in the step of forming the low concentration impurity region, and the high concentration impurity region of the low concentration impurity region in the step of forming the second high concentration impurity region are: A method of manufacturing an image sensor , which is performed in a self-aligned manner with respect to the second gate electrode .

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