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JP3870778B2 - Manufacturing method of element-embedded substrate and element-embedded substrate - Google Patents

Manufacturing method of element-embedded substrate and element-embedded substrate Download PDF

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Publication number
JP3870778B2
JP3870778B2 JP2001387428A JP2001387428A JP3870778B2 JP 3870778 B2 JP3870778 B2 JP 3870778B2 JP 2001387428 A JP2001387428 A JP 2001387428A JP 2001387428 A JP2001387428 A JP 2001387428A JP 3870778 B2 JP3870778 B2 JP 3870778B2
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resin
copper foil
semiconductor chip
layer
recess
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JP2003188314A (en
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睦禎 伊藤
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
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    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

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Description

【０００１】
【発明の属する技術分野】
本発明は、ＬＳＩ等の半導体チップをプリント配線板の内部に収容した素子内蔵基板の製造方法および素子内蔵基板に関する。
【０００２】
【従来の技術】
電子機器の小型化、多機能化に伴い、プリント配線板の高密度実装化や実装部品の小型化に対する要求が厳しくなっている。プリント配線板においては、従来、配線ルールの縮小により基板面内における高密度化が図られていたが、近年では、ビルドアップ工法等を採用してプリント配線板を多層化し、三次元的に配線を引き回して実装効率の向上が図られている。
【０００３】
一方、このようなビルドアップ多層プリント配線板の開発に並行して、実装効率の更なる向上を目的として、抵抗やコンデンサ等の受動素子、ＬＳＩ等の能動素子を内蔵した素子内蔵基板の開発が進められている。
【０００４】
例えば特開平６−４５７６３号公報には、図５に示すような構成の素子内蔵基板１０１が記載されている。素子内蔵基板１０１は、半導体チップ１０２を収容するためのキャビティ１０３が形成された内層基板１０４の両面に、外層基板１０５，１０６をそれぞれ積層した構造を有している。キャビティ１０３内の半導体チップ１０２は、外層基板１０５上の導体パターン１０７に対し、バンプ１０８を介して電気的に接続されている。なお、外層基板１０５，１０６の外面側には、半導体パッケージ部品１０９，１１０がそれぞれ実装されている。
【０００５】
導体パターン１０７に対する半導体チップ１０２の電気的接続は、いわゆるフリップチップ実装によって行われている。すなわち、半導体チップ１０２の電極パッド部上に形成したバンプ１０８を外部電極として、導体パターン１０７に対し熱圧着等の公知の接合技術を用いて実装されている。
【０００６】
【発明が解決しようとする課題】
上記のように、内蔵される半導体チップ１０２を導体パターン１０７に対してフリップチップ実装するためには、導体パターン１０７のチップ接続ランド部をバンプ１０８に対応した配列ピッチで形成する必要がある。このため、半導体チップ１０２の電極パッド部の配列ピッチが例えば６０μｍというようにファイン化されると、導体パターン１０７の接続ランド部を上記のパッドピッチに対応して形成することが困難となる。すなわち、電極パッド部のファインピッチ化に、導体パターン１０７が対応できないという問題がある。
【０００７】
この問題を解消するために、例えば特開２０００−２２８４５７号公報には、図６に示すように、半導体チップ１１２の能動面に対し、電極パッド部の配置を再配列するための再配線層１１３を設けて、バンプ１１４の配列ピッチを変換する方法が知られている。この方法によれば、電極パッド部の配列ピッチが６０μｍの場合、例えば１２０μｍにまでバンプピッチを拡張することができる。
【０００８】
しかしながら、再配線層１１３を形成することは、内蔵される半導体部品の製造コストの増大を招き、その製造工程の複雑化によるリードタイムの長大化や、歩留まりの低下といった種々の問題を包含することになる。
【０００９】
本発明は上述の問題に鑑みてなされ、ファインピッチの電極パッド部を有する半導体チップをピッチ変換することなく、基板上の導体パターンに接続することができる素子内蔵基板の製造方法および素子内蔵基板を提供することを課題とする。
【００１０】
【課題を解決するための手段】
以上の課題を解決するに当たり、本発明の素子内蔵基板の製造方法は、半導体チップを内部に収容した素子内蔵基板の製造方法であって、半導体チップを収容するための凹所を、樹脂付き銅箔の樹脂形成面側に積層された絶縁基材に形成する工程と、プリント配線板上の所定部位に能動面を上向きにして半導体チップを搭載し、上記能動面を凹所を介して樹脂形成面に密着させるとともに、プリント配線板を絶縁基材に積層する工程と、樹脂付き銅箔の銅箔側から、凹所内に収容された半導体チップの能動面上の電極パッド部に向けて、ダイレクトレーザ加工法により層間接続用の連絡孔を形成する工程と、連絡孔を介して銅箔と電極パッド部とを導通させる工程と、銅箔を所定形状にパターニングする工程とを有することを特徴としている。
【００１１】
本発明の素子内蔵基板の製造方法では、樹脂付き銅箔とプリント配線板との間の絶縁基材に内蔵された半導体チップの電極パッド部を樹脂付き銅箔の表面銅箔と電気的に接続するために、樹脂付き銅箔の表面銅箔と樹脂層とを同時に穿孔できるダイレクトレーザ加工法を採用している。そして、形成された連絡孔を介して、表面銅箔と電極パッド部とを導通させるようにしている。これにより、ファインピッチに形成された半導体チップ能動面上の電極パッド部をピッチ変換することなく、樹脂付き銅箔の銅箔層に接続することができる。
【００１２】
さらに、本発明の素子内蔵基板は、絶縁層と、絶縁層の一方の面に形成された導体層と、絶縁層の他方の面に形成され、半導体チップを収容可能な凹所と、絶縁層の他方の面に積層され、半導体チップをその能動面が凹所の底部に密着されるように搭載したプリント配線板と、導体層と能動面上の電極パッド部との間を導通させる層間接続部とを備え、絶縁層が、樹脂付き銅箔の樹脂層と、この樹脂層に積層され上記凹所が形成された絶縁基材とを含むことを特徴とする。
【００１３】
本発明の素子内蔵基板においては、絶縁層を介して対向する導体層と半導体チップの電極パッド部とが直接層間接続されている。これにより、電極パッド部のパッド配列を再配列することなく半導体チップを基板上の導体層へ接続することができる。
【００１４】
【発明の実施の形態】
以下、本発明の実施の形態について図面を参照して説明する。
【００１５】
図１は、本発明の実施の形態による素子内蔵基板を示している。本実施の形態の素子内蔵基板１は、半導体チップ２を搭載したプリント配線板３の上に絶縁層４が設けられ、更に絶縁層４の上に所定形状の導体パターン５が設けられている。半導体チップ２の能動面１４に配列された複数の電極パッド部６およびプリント配線板３の回路パターン（ランド）７はそれぞれ、導体パターン５に対して層間接続部８，９を介して導通されている。
【００１６】
半導体チップ２は、電極パッド部６が形成された能動面１４を上向きにして、プリント配線板３の回路形成面の所定部位に例えば接着剤（図示略）を介して搭載されている。半導体チップ２としては、例えばＤＲＡＭ等の半導体メモリやこれにロジック回路が混載されたシステムＬＳＩ、あるいはＭＰＵ、各種ハードウェアシステムを駆動するドライバ回路、電源回路、高周波信号処理回路等がそれぞれ組み込まれた、公知の半導体ベアチップ部品が適用される。
【００１７】
プリント配線板３は、本実施の形態では片面銅張積層板で構成され、絶縁基板１５と、この上に形成された所定形状の回路パターン７とで構成されている。絶縁基板１５の材質は特に限定されず、セラミック系材料あるいは有機系材料などの公知の材料が用いられる。セラミック系材料であれば、アルミナあるいはサファイア等が適用され、有機系材料であれば、ガラスエポキシ樹脂やポリイミド樹脂、ビスマレイミドトリアジン樹脂等が適用可能である。
【００１８】
プリント配線板３と絶縁層４との間には、絶縁性の接着シート１０が介装されている。接着シート１０は本発明の「絶縁基材」に対応し、本実施の形態では、熱硬化性樹脂に感光性を持たせたシート材で構成され、その厚さは半導体チップ２の厚さと同等もしくは、半導体チップ２の厚さよりも若干小さく形成されている。接着シート１０には、半導体チップ２を収容するための開口１１が形成されている。
【００１９】
絶縁層４および導体パターン５は、本実施の形態では、いわゆるＲＣＣ(Resin-Coated Copper) の呼称で知られる樹脂付き銅箔で構成されている。すなわち、絶縁層４および導体パターン５はそれぞれ、樹脂付き銅箔の合成樹脂層および表面銅箔に対応する。この樹脂付き銅箔の樹脂形成面側に接着シート１０を介してプリント配線板３が積層されている。
【００２０】
これら絶縁層４と接着シート１０の開口１１とによって、半導体チップ２が収容される凹所１２が形成されている。半導体チップ２は、その能動面１４が凹所１２の底部１３である絶縁層下面（樹脂形成面）に密着され、電極パッド部６が絶縁層４に没入している。
【００２１】
ここで、本実施の形態では、半導体チップ２の電極パッド部６はアルミニウムで構成されるが、その上にニッケルめっきおよび金めっきの複合層からなるバリア層１６が形成されている。このバリア層１６は、後述するように、層間接続部８を形成する際に適用されるレーザービームから、電極パッド部６を保護するために設けられている。バリア層１６は、ニッケル、金、パラジウム、白金等の金属めっきの単層またはこれらの複合層で構成することができる。なお、以下の説明では、特に断らない限り、電極パッド部６をバリア層１６も含む意味で用いるものとする。
【００２２】
プリント配線板３の回路形成面は、半導体チップ２の能動面１４を凹所１２の底部１３に密着させた状態で、接着シート１０に積層されている。また、半導体チップ２の側面と接着シート１０の開口１１との間の隙間には、プリント配線板３を積層する際に適用される加熱加圧プレスによって絶縁層４の構成樹脂が流入しており、これにより半導体チップ２が凹所１２内においてモールドされている。
【００２３】
半導体チップ２の各電極パッド部６およびプリント配線板３の回路パターン７の間は、層間接続部８，９および表層の導体パターン５を介して電気的に接続されている。層間接続部８，９は、後に詳述するように、例えば直径３０μｍの連絡孔に設けた導電材料で構成されている。
【００２４】
本実施の形態の素子内蔵基板１は、以上のようにして構成されている。本実施の形態の素子内蔵基板１によれば、絶縁層４を介して対向する導体パターン５と半導体チップ２の電極パッド部６とが直接、層間接続部８，９を介して導通されているので、電極パッド部６のパッド配列を再配列することなく半導体チップ２を導体パターン５へ接続することができる。
【００２５】
次に、以上のように構成される本実施の形態の素子内蔵基板の製造方法について、図２および図３を参照して説明する。
【００２６】
まず、図２（ａ）に示すように、銅箔（導体層）５Ａの厚さが３μｍ、絶縁層（樹脂層）４の厚さが２０μｍの樹脂付き銅箔２０を準備する。本実施の形態では、樹脂付き銅箔２０として、日立化成株式会社製の樹脂付き銅箔（Ｆ６０００Ｅ）が用いられる。
【００２７】
次に、図２（ｂ）に示すように、絶縁層４の下面に、接着シート１０を接着することによって、樹脂付き銅箔２０と接着シート１０との積層体２５を作製する。
【００２８】
接着シート１０は、本実施の形態では未硬化（半硬化状態）のエポキシ系熱硬化性樹脂に感光性を付与したシート材が用いられ、その厚さは、約３０μｍとした。なお、接着シート１０の厚さは、内蔵される半導体チップ２の厚さよりもやや小さくされるものとする。本実施の形態では、接着シート１０として、住友ベークライト株式会社製の感光性接着シート（ＣＦＰ２０３５）が用いられる。
【００２９】
続いて、図２（ｃ）に示すように、樹脂付き銅箔２０に積層した接着シート１０に対し、半導体チップ２を収容するための開口１１を形成する。これにより、樹脂付き銅箔２０の樹脂形成面側（絶縁層４側）に凹所１２が形成される。開口１１（凹所１２）は、接着シート１０の所定部位に対し、露光および現像の各処理を行うことによって形成される。開口１１は、内蔵すべき半導体チップ２の外形よりもやや大きく形成される。
【００３０】
ここで、接着シート１０がポジ型の感光性シートであれば、露光光が照射された領域が現像液中に溶解し、ネガ型の感光性シートであれば、露光光が照射されなかった領域が現像液中に溶解することによって開口１１が形成されるが、本発明では、何れのタイプの感光性シートでも用いることができる。
【００３１】
なお、以上の工程では、接着シート１０を絶縁層４に積層した後、接着シート１０の層のみ加工して開口１１（凹所１２）を形成するようにしたが、これに代えて、開口１１を形成した後に、接着シート１０を絶縁層４に積層するようにしてもよい。
【００３２】
なおまた、上記の工程では、フォトリソグラフィ技術を用いて開口１１を形成できる素材として感光性のある接着シート１０を用いたが、例えばプリプレグ等の未硬化の熱硬化性樹脂シートを上記接着シートとして適用し、これにプレス加工等を施して開口（凹所）を形成した後に絶縁層４へ積層するようにしてもよい。
【００３３】
さて、次に、図２（ｄ）に示すように、内蔵すべき半導体チップ２をフェイスアップ方式で（能動面１４を上方に向けて）搭載したプリント配線板３と、上述した樹脂付き銅箔２０および接着シート１０の積層体２５とを、互いに位置合わせする。
【００３４】
プリント配線板３には、あらかじめ回路パターン７が形成されている。本実施の形態では、回路パターン７の厚さは約２５μｍとされる。プリント配線板３と半導体チップ２の裏面（非能動面）との間は、例えば接着剤等によって接着されている。また、半導体チップ２の電極パッド部６のピッチは約６０μｍで、アルミニウムパッドの上に、厚さ１０μｍの無電解ニッケルめっきと、更にその上に形成される厚さ０．１μｍの無電解金めっきからなるバリア層１６が形成されている。
【００３５】
そして、図２（ｅ）に示すように、プリント配線板３と積層体２５とを真空中での加熱加圧プレスによって積層する。このとき、半導体チップ２の能動面１４が積層体２５の凹所１２の底部１３に密着されると同時に、プリント配線板３の回路形成面が積層体２５の接着シート１０に積層される。
【００３６】
この加熱加圧プレスにより、半導体チップ２の電極パッド部６は絶縁層４に没入するとともに、溶融した絶縁層４の構成樹脂が、開口１１（凹所１２）と半導体チップ２との間の隙間に流入する。冷却後、半導体チップ２はその流入した樹脂材料によってモールドされ、凹所１２内に保持される。
【００３７】
図３（ｆ）および（ｇ）は、表層の銅箔５Ａと、半導体チップ２の電極パッド部６およびプリント配線板３の回路パターン７との間の層間接続工程を示している。この工程は、銅箔５Ａの所定部位に対して紫外線レーザ（以下、ＵＶレーザという）Ｌを照射して、電極パッド部６および回路パターン７に到達する連絡孔１８，１９をそれぞれ形成する工程（図３（ｆ））と、これらの連絡孔１８，１９に導電性をもたせる工程（図３（ｇ））とを有する。
【００３８】
連絡孔１８，１９の形成は、ダイレクトレーザ加工法によって行われる。このダイレクトレーザ加工法は、銅箔５Ａおよび絶縁層４をＵＶレーザＬの照射によって一時に穿孔するレーザ加工法の一種である。このダイレクトレーザ加工法を用いることにより、表面の銅箔と絶縁層とを別々な工程で穿孔する方法に比べて、微細な孔を形成することができる。
【００３９】
すなわち、従来の樹脂付き銅箔の穿孔方法として、表面銅箔に孔径と同径のウィンド（窓）を形成した後、孔径よりも５０〜１００μｍ大きいＣＯ2 レーザで絶縁層を穿孔するコンフォーマルマスク法や、表面銅箔に孔径よりも約１００μｍ大きなウィンドを形成した後、絶縁層をＣＯ2 レーザで穿孔するラージウィンド法が用いられていた。これは、光沢のある銅表面のレーザビームの吸収率が絶縁層よりも低いため、前もって表面の銅箔をエッチングにより除去し、開口した銅箔を介して絶縁層をレーザ加工する必要があったからである。このため、従来のレーザ加工では、ファインピッチな孔を形成することが非常に困難で、かつ、工程が複雑であった。
【００４０】
一方、ダイレクトレーザ加工は、表面銅箔のレーザ吸収率を絶縁層の分解エネルギに近づけることによって、表面銅箔を絶縁層とともにレーザで同時に穿孔できるようにしたものである。本実施の形態では、このダイレクトレーザ加工に適した樹脂付き銅箔２０を採用しているために、微細孔をファインピッチで容易に形成することができる。本実施の形態では、層厚が最大５０μｍの絶縁層（４，１０）を紫外線レーザＬによって、３０μｍ程度の孔径の連絡孔１８，１９を形成している。
【００４１】
ＵＶレーザＬは、積層体２５を突き抜け、半導体チップ２の電極パッド部６に到達するが、バリア層１６によってＵＶレーザＬの進行が規制され、電極パッド部６に対する必要以上の加工が防止される。また、プリント配線板３上の回路パターン（ランド）７に到達したＵＶレーザＬも同様に、厚い銅箔層によって必要以上の加工が制限される。以上のようにして、電極パッド部６および回路パターン（ランド）７が開口される。
【００４２】
一方、連絡孔１８，１９に導電性をもたせる工程は、無電解めっき法と電解めっき法を併用して連絡孔１８，１９内に例えば銅めっきを析出させるか、あるいは、スクリーン印刷法等によって連絡孔１８，１９内に導電材料を充填することによって行われる。これにより、図３（ｇ）に示すように、半導体チップ２の電極パッド部６およびプリント配線板３の回路パターン７と、表面の銅箔５Ａとを電気的に接続する層間接続部８，９が形成される。
【００４３】
なお、上述のように、連絡孔１８，１９に対して導電材料を充填することによって層間接続部８，９を形成する場合には、導電材料として、φ３μｍの銀粒子を導電粒子とする導電ペーストを用いることによって、φ３０μｍという微細な連絡孔１８，１９に対して容易に導電ペーストを充填することができる。
【００４４】
次に、図３（ｈ）に示すように、銅箔５Ａを所定形状にパターニングすることによって導体パターン５を形成する。本実施の形態では、プリント配線板３の回路パターン７に対して半導体チップ２を電気的に接続するようにしている。
【００４５】
導体パターン５は、銅箔５Ａ上にフォトレジストを形成し、これに露光マスクを介して所定部位を感光させ、現像処理を施してレジストパターンを形成した後、エッチングによってレジストが形成されていない領域を除去することによって形成することができる。
【００４６】
以上のようにして、本実施の形態の素子内蔵基板１が製造される。本実施の形態によれば、ファインピッチに形成された電極パッド部６をピッチ変換することなく、導体パターン５に接続することができる。
【００４７】
また、電極パッド部６を半導体チップ２の能動面１４上でピッチ変換することなく、プリント配線板３の回路パターン７に接続することができるので、プリント配線板３上の回路パターン７を電極パッド部６の配列ピッチに対応して微細に形成せずとも、半導体チップ２と電気的に接続することができる。
【００４８】
また、以上の実施の形態によれば、ダイレクトレーザ加工が適用可能な樹脂付き銅箔２０を用いているので、製造工程を複雑化することなく低コストで高密度実装が可能な素子内蔵基板１を製造することができる。
【００４９】
以上、本発明の実施の形態について説明したが、勿論、本発明はこれに限定されることなく、本発明の技術的思想に基づいて種々の変形が可能である。
【００５０】
例えば以上の実施の形態では、層間接続用の連絡孔１８，１９をダイレクトレーザ加工法により形成するにあたって、ＵＶレーザＬを用いたが、勿論、これに限らない。すなわち、電極パッド部６のピッチに一定の余裕度があるならば、ＣＯ2 レーザやＹＡＧレーザ等の他のレーザ光源を用いることも可能である。
【００５１】
また、以上の実施の形態では、プリント配線板３として片面銅張積層板を用いたが、図４に示すように、これを両面銅張り積層板で構成するとともに、外面側の導体層５Ｂをベタ箔状態とすることによって、電磁ノイズの低減に寄与することができる。また、当該ベタ箔層５Ｂを接地回路へ接続すれば、静電放電（ＥＳＤ）対策にもなり得る。なお、図４において上述の実施の形態と対応する部分については同一の符号を付している。
【００５２】
さらに、上述の実施の形態において製造した素子内蔵基板１に対して、更にその上層または下層に他のプリント配線板を積層してビルドアップ化を図ることも可能である。この場合の各導体パターン間の層間接続を、上述のダイレクトレーザ加工法で行うようにすれば、ファインピッチな層間接続部を備えた多層プリント配線板を容易に製造することができる。
【００５３】
また、以上の実施の形態では、半導体チップ２を内蔵した素子内蔵基板１について説明したが、勿論、この半導体チップ２のみに限らず、他のＬＳＩを初めとする能動素子や、抵抗またはコンデンサ等の受動素子も内蔵されていてもよい。
【００５４】
【発明の効果】
以上述べたように、本発明の素子内蔵基板の製造方法によれば、ファインピッチに形成された半導体チップ能動面上の電極パッド部をピッチ変換することなく導体層に接続することができる。
【００５５】
また、ダイレクトレーザ加工が適用できる樹脂付き銅箔を用いて層間接続用の連絡孔を形成する本発明の素子内蔵基板の製造方法によれば、複雑な工程を要することなく容易に層間接続部を形成することができる。
【００５６】
上記銅箔と半導体チップの電極パッド部とを導通させる工程に、上記銅箔とプリント配線板の回路パターンとを導通させる工程を含めた本発明の素子内蔵基板の製造方法によれば、ファインピッチに形成された電極パッド部を半導体チップの能動面上で再配列することなく、プリント配線板上の回路パターンに接続することができる。
【００５７】
さらに、本発明の素子内蔵基板によれば、絶縁層を介して対向する導体層と半導体チップの電極パッド部とが直接、層間接続部を介して導通されているので、電極パッド部のパッド配列を再配列することなく半導体チップを導体層へ接続することができる。
【図面の簡単な説明】
【図１】 本発明の実施の形態による素子内蔵基板の構成を示す断面図である。
【図２】 （ａ）〜（ｅ）ともに、本発明の実施の形態による素子内蔵基板の製造方法を説明する工程断面図である。
【図３】 （ｆ）〜（ｈ）ともに、本発明の実施の形態による素子内蔵基板の製造工程を説明する図２に続く工程断面図である。
【図４】 本発明の実施の形態による素子内蔵基板の構成の変形例を示す断面図である。
【図５】 従来の素子内蔵基板の構成を示す断面図である。
【図６】 電極パッド部の再配線層１１３を能動面上に備えた従来の半導体部品の構成を示す斜視図である。
【符号の説明】
１…素子内蔵基板、２…半導体チップ、３…プリント配線板、４…絶縁層、５…導体パターン、５Ａ…銅箔（導体層）、６…電極パッド部、７…回路パターン、８，９…層間接続部、１０…接着シート（絶縁基材）、１１…開口、１２…凹所、１３…凹所の底部、１４…半導体チップの能動面、１６…バリア層、１８，１９…連絡孔、２０…樹脂付き銅箔、Ｌ…ＵＶレーザ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing an element-embedded substrate in which a semiconductor chip such as an LSI is accommodated inside a printed wiring board, and the element-embedded substrate.
[0002]
[Prior art]
With the downsizing and multi-functionalization of electronic devices, demands for high-density mounting of printed wiring boards and miniaturization of mounted parts are becoming strict. Conventionally, in printed wiring boards, high density in the substrate surface has been achieved by reducing the wiring rules, but in recent years, multilayered printed wiring boards have been adopted using a build-up method, etc., and wiring is performed three-dimensionally. As a result, the mounting efficiency is improved.
[0003]
On the other hand, in parallel with the development of such build-up multilayer printed wiring boards, development of device-embedded boards that incorporate passive elements such as resistors and capacitors, and active elements such as LSIs, is aimed at further improving mounting efficiency. It is being advanced.
[0004]
For example, Japanese Patent Laid-Open No. 6-45763, the element built-in substrate 101 configured as shown in FIG. 5 is described. The element-embedded substrate 101 has a structure in which outer layer substrates 105 and 106 are laminated on both surfaces of an inner layer substrate 104 in which a cavity 103 for accommodating a semiconductor chip 102 is formed. The semiconductor chip 102 in the cavity 103 is electrically connected to the conductor pattern 107 on the outer layer substrate 105 through bumps 108. Semiconductor package components 109 and 110 are mounted on the outer surface sides of the outer substrate 105 and 106, respectively.
[0005]
Electrical connection of the semiconductor chip 102 to the conductor pattern 107 is performed by so-called flip chip mounting. That is, the bump 108 formed on the electrode pad portion of the semiconductor chip 102 is used as an external electrode and is mounted on the conductor pattern 107 using a known bonding technique such as thermocompression bonding.
[0006]
[Problems to be solved by the invention]
As described above, in order to flip-chip mount the built-in semiconductor chip 102 on the conductor pattern 107, it is necessary to form the chip connection land portions of the conductor pattern 107 at an arrangement pitch corresponding to the bumps 108. For this reason, when the arrangement pitch of the electrode pad portions of the semiconductor chip 102 is made fine, for example, 60 μm, it becomes difficult to form the connection land portions of the conductor pattern 107 corresponding to the pad pitch. That is, there is a problem that the conductor pattern 107 cannot cope with the fine pitch of the electrode pad portion.
[0007]
To solve this problem, for example, JP-A-2000-228457 discloses, as shown in FIG. 6, the active surface of the semiconductor chip 112 to rewiring layer 113 for rearranging the arrangement of the electrode pad portion And a method of converting the arrangement pitch of the bumps 114 is known. According to this method, when the arrangement pitch of the electrode pad portions is 60 μm, the bump pitch can be expanded to, for example, 120 μm.
[0008]
However, the formation of the redistribution layer 113 leads to an increase in the manufacturing cost of a built-in semiconductor component, and includes various problems such as an increase in lead time due to a complicated manufacturing process and a decrease in yield. become.
[0009]
The present invention has been made in view of the above-described problems, and provides a method for manufacturing an element-embedded substrate and a device-embedded substrate that can be connected to a conductor pattern on the substrate without converting the pitch of a semiconductor chip having fine pitch electrode pad portions. The issue is to provide.
[0010]
[Means for Solving the Problems]
In solving the above problems, a method for manufacturing an element-embedded substrate according to the present invention is a method for manufacturing an element-embedded substrate in which a semiconductor chip is housed, and a recess for housing a semiconductor chip is formed with a resin-coated copper. A process of forming on an insulating base material laminated on the resin-forming surface side of the foil, and mounting a semiconductor chip with an active surface facing upward at a predetermined portion on the printed wiring board, and forming the resin on the active surface through a recess Directly from the copper foil side of the resin-coated copper foil toward the electrode pad on the active surface of the semiconductor chip housed in the recess A step of forming a connection hole for interlayer connection by a laser processing method, a step of conducting the copper foil and the electrode pad portion through the connection hole, and a step of patterning the copper foil into a predetermined shape Have
[0011]
In the manufacturing method of the element-embedded substrate of the present invention, the electrode pad portion of the semiconductor chip built in the insulating base material between the resin-coated copper foil and the printed wiring board is electrically connected to the surface copper foil of the resin-coated copper foil. In order to achieve this, a direct laser processing method capable of simultaneously perforating the surface copper foil and the resin layer of the resin-coated copper foil is employed. Then, the surface copper foil and the electrode pad portion are brought into conduction through the formed communication hole. Thereby, the electrode pad part on the active surface of the semiconductor chip formed in the fine pitch can be connected to the copper foil layer of the copper foil with resin without converting the pitch.
[0012]
Furthermore, the element-embedded substrate of the present invention includes an insulating layer, a conductor layer formed on one surface of the insulating layer, a recess formed on the other surface of the insulating layer and capable of accommodating a semiconductor chip, and an insulating layer Layered connection on the other side of the circuit board, and a conductive printed circuit board on which a semiconductor chip is mounted so that its active surface is in close contact with the bottom of the recess, and an interlayer connection for conducting between the conductor layer and the electrode pad on the active surface And the insulating layer includes a resin layer of a copper foil with resin and an insulating base material laminated on the resin layer and having the recess formed therein .
[0013]
In the element-embedded substrate of the present invention, the opposing conductor layer and the electrode pad portion of the semiconductor chip are directly connected to each other via an insulating layer. Thereby, the semiconductor chip can be connected to the conductor layer on the substrate without rearranging the pad arrangement of the electrode pad portion.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, will be described with reference to the drawings implementation of the present invention.
[0015]
Figure 1 shows a device embedded substrate according to the implementation of the embodiment of the present invention. In the element-embedded substrate 1 of this embodiment, an insulating layer 4 is provided on a printed wiring board 3 on which a semiconductor chip 2 is mounted, and a conductor pattern 5 having a predetermined shape is further provided on the insulating layer 4. The plurality of electrode pad portions 6 arranged on the active surface 14 of the semiconductor chip 2 and the circuit pattern (land) 7 of the printed wiring board 3 are respectively conducted to the conductor pattern 5 through the interlayer connection portions 8 and 9. Yes.
[0016]
The semiconductor chip 2 is mounted on a predetermined portion of the circuit forming surface of the printed wiring board 3 via an adhesive (not shown), for example, with the active surface 14 on which the electrode pad portion 6 is formed facing upward. As the semiconductor chip 2, for example, a semiconductor memory such as a DRAM, a system LSI in which a logic circuit is embedded in this, or an MPU, a driver circuit for driving various hardware systems, a power supply circuit, a high-frequency signal processing circuit, and the like are incorporated. A known semiconductor bare chip component is applied.
[0017]
In this embodiment, the printed wiring board 3 is composed of a single-sided copper clad laminate, and is composed of an insulating substrate 15 and a circuit pattern 7 having a predetermined shape formed thereon. The material of the insulating substrate 15 is not particularly limited, and a known material such as a ceramic material or an organic material is used. For ceramic materials, alumina, sapphire, or the like is applied, and for organic materials, glass epoxy resin, polyimide resin, bismaleimide triazine resin, or the like is applicable.
[0018]
An insulating adhesive sheet 10 is interposed between the printed wiring board 3 and the insulating layer 4. The adhesive sheet 10 corresponds to the “insulating base material” of the present invention. In the present embodiment, the adhesive sheet 10 is composed of a sheet material obtained by imparting photosensitivity to a thermosetting resin, and the thickness thereof is equal to the thickness of the semiconductor chip 2. Alternatively, it is formed slightly smaller than the thickness of the semiconductor chip 2. An opening 11 for accommodating the semiconductor chip 2 is formed in the adhesive sheet 10.
[0019]
In this embodiment, the insulating layer 4 and the conductor pattern 5 are made of a resin-coated copper foil known as a so-called RCC (Resin - Coated Copper). That is, the insulating layer 4 and the conductor pattern 5 correspond to the synthetic resin layer and the surface copper foil of the copper foil with resin, respectively. The printed wiring board 3 is laminated on the resin-formed surface side of the resin-coated copper foil with an adhesive sheet 10 interposed therebetween.
[0020]
The insulating layer 4 and the opening 11 of the adhesive sheet 10 form a recess 12 in which the semiconductor chip 2 is accommodated. The active surface 14 of the semiconductor chip 2 is in close contact with the lower surface of the insulating layer (resin forming surface) which is the bottom 13 of the recess 12, and the electrode pad portion 6 is immersed in the insulating layer 4.
[0021]
Here, in the present embodiment, the electrode pad portion 6 of the semiconductor chip 2 is made of aluminum, and a barrier layer 16 made of a composite layer of nickel plating and gold plating is formed thereon. As will be described later, the barrier layer 16 is provided to protect the electrode pad portion 6 from a laser beam applied when forming the interlayer connection portion 8. The barrier layer 16 can be composed of a single layer of metal plating such as nickel, gold, palladium, platinum or a composite layer thereof. In the following description, the electrode pad portion 6 is used to include the barrier layer 16 unless otherwise specified.
[0022]
The circuit forming surface of the printed wiring board 3 is laminated on the adhesive sheet 10 in a state where the active surface 14 of the semiconductor chip 2 is in close contact with the bottom 13 of the recess 12. In addition, the constituent resin of the insulating layer 4 flows into the gap between the side surface of the semiconductor chip 2 and the opening 11 of the adhesive sheet 10 by the heat and pressure press applied when the printed wiring board 3 is laminated. Thereby, the semiconductor chip 2 is molded in the recess 12.
[0023]
Each electrode pad portion 6 of the semiconductor chip 2 and the circuit pattern 7 of the printed wiring board 3 are electrically connected via interlayer connection portions 8 and 9 and a conductor pattern 5 on the surface layer. As will be described later in detail, the interlayer connection portions 8 and 9 are made of, for example, a conductive material provided in a communication hole having a diameter of 30 μm.
[0024]
The element built-in substrate 1 of the present embodiment is configured as described above. According to the element-embedded substrate 1 of the present embodiment, the conductive pattern 5 and the electrode pad portion 6 of the semiconductor chip 2 facing each other via the insulating layer 4 are directly connected via the interlayer connection portions 8 and 9. Therefore, the semiconductor chip 2 can be connected to the conductor pattern 5 without rearranging the pad arrangement of the electrode pad portion 6.
[0025]
Next, a method for manufacturing the element-embedded substrate of the present embodiment configured as described above will be described with reference to FIGS.
[0026]
First, as shown in FIG. 2A, a copper foil with resin 20 is prepared in which the thickness of the copper foil (conductor layer) 5A is 3 μm and the thickness of the insulating layer (resin layer) 4 is 20 μm. In the present embodiment, a copper foil with resin (F6000E) manufactured by Hitachi Chemical Co., Ltd. is used as the copper foil with resin 20.
[0027]
Next, as shown in FIG. 2 (b), the adhesive sheet 10 is adhered to the lower surface of the insulating layer 4 to produce a laminate 25 of the resin-coated copper foil 20 and the adhesive sheet 10.
[0028]
In the present embodiment, the adhesive sheet 10 is a sheet material obtained by imparting photosensitivity to an uncured (semi-cured) epoxy-based thermosetting resin, and the thickness thereof is about 30 μm. It is assumed that the thickness of the adhesive sheet 10 is slightly smaller than the thickness of the built-in semiconductor chip 2. In the present embodiment, a photosensitive adhesive sheet (CFP2035) manufactured by Sumitomo Bakelite Co., Ltd. is used as the adhesive sheet 10.
[0029]
Subsequently, as shown in FIG. 2C, an opening 11 for accommodating the semiconductor chip 2 is formed in the adhesive sheet 10 laminated on the copper foil with resin 20. Thereby, the recess 12 is formed on the resin forming surface side (insulating layer 4 side) of the resin-coated copper foil 20. The opening 11 (recess 12) is formed by performing each processing of exposure and development on a predetermined portion of the adhesive sheet 10. The opening 11 is formed to be slightly larger than the outer shape of the semiconductor chip 2 to be incorporated.
[0030]
Here, if the adhesive sheet 10 is a positive photosensitive sheet, the area irradiated with the exposure light is dissolved in the developer, and if the adhesive sheet 10 is a negative photosensitive sheet, the area not exposed to the exposure light. Is dissolved in the developer to form the opening 11, but in the present invention, any type of photosensitive sheet can be used.
[0031]
In the above process, after the adhesive sheet 10 is laminated on the insulating layer 4, only the layer of the adhesive sheet 10 is processed to form the opening 11 (recess 12). After forming, the adhesive sheet 10 may be laminated on the insulating layer 4.
[0032]
In the above process, the photosensitive adhesive sheet 10 is used as a material capable of forming the opening 11 using a photolithography technique, but an uncured thermosetting resin sheet such as a prepreg is used as the adhesive sheet. It may be applied to the insulating layer 4 after forming an opening (recessed portion) by press working or the like.
[0033]
Next, as shown in FIG. 2D, the printed wiring board 3 on which the semiconductor chip 2 to be incorporated is mounted in a face-up manner (with the active surface 14 facing upward), and the resin-coated copper foil described above. 20 and the laminated body 25 of the adhesive sheet 10 are aligned with each other.
[0034]
A circuit pattern 7 is formed on the printed wiring board 3 in advance. In the present embodiment, the thickness of the circuit pattern 7 is about 25 μm. The printed wiring board 3 and the back surface (inactive surface) of the semiconductor chip 2 are bonded with, for example, an adhesive. The pitch of the electrode pad portions 6 of the semiconductor chip 2 is about 60 μm, an electroless nickel plating having a thickness of 10 μm is formed on the aluminum pad, and an electroless gold plating having a thickness of 0.1 μm formed thereon. A barrier layer 16 made of is formed.
[0035]
And as shown in FIG.2 (e), the printed wiring board 3 and the laminated body 25 are laminated | stacked by the heating-pressing press in a vacuum. At this time, the active surface 14 of the semiconductor chip 2 is brought into close contact with the bottom 13 of the recess 12 of the laminated body 25, and the circuit forming surface of the printed wiring board 3 is laminated on the adhesive sheet 10 of the laminated body 25.
[0036]
By this heating and pressing, the electrode pad portion 6 of the semiconductor chip 2 is immersed in the insulating layer 4, and the molten constituent resin of the insulating layer 4 has a gap between the opening 11 (recess 12) and the semiconductor chip 2. Flow into. After cooling, the semiconductor chip 2 is molded by the inflowing resin material and held in the recess 12.
[0037]
3 (f) and 3 (g) show an interlayer connection process between the copper foil 5 </ b> A of the surface layer and the electrode pad portion 6 of the semiconductor chip 2 and the circuit pattern 7 of the printed wiring board 3. In this step, a predetermined portion of the copper foil 5A is irradiated with an ultraviolet laser (hereinafter referred to as a UV laser) L to form connection holes 18 and 19 reaching the electrode pad portion 6 and the circuit pattern 7, respectively ( 3 (f)) and a step (FIG. 3 (g)) for imparting conductivity to the communication holes 18 and 19.
[0038]
The connection holes 18 and 19 are formed by a direct laser processing method. This direct laser processing method is a kind of laser processing method in which the copper foil 5A and the insulating layer 4 are perforated at a time by irradiation with the UV laser L. By using this direct laser processing method, fine holes can be formed as compared with the method of perforating the surface copper foil and the insulating layer in separate steps.
[0039]
That is, as a conventional method for perforating a copper foil with resin, a conformal mask in which a window (window) having the same diameter as the hole diameter is formed on the surface copper foil and then the insulating layer is perforated with a CO 2 laser 50 to 100 μm larger than the hole diameter. Or a large window method in which a window about 100 μm larger than the hole diameter is formed on the surface copper foil and then the insulating layer is drilled with a CO 2 laser. This is because the absorption rate of the laser beam on the shiny copper surface is lower than that of the insulating layer, so it was necessary to remove the copper foil on the surface in advance by etching and laser processing the insulating layer through the opened copper foil. It is. For this reason, in conventional laser processing, it is very difficult to form fine pitch holes, and the process is complicated.
[0040]
On the other hand, in the direct laser processing, the surface copper foil can be simultaneously perforated by the laser together with the insulating layer by bringing the laser absorption rate of the surface copper foil close to the decomposition energy of the insulating layer. In this embodiment, since the resin-attached copper foil 20 suitable for the direct laser processing is employed, the fine holes can be easily formed with a fine pitch. In the present embodiment, the contact holes 18 and 19 having a hole diameter of about 30 μm are formed by the ultraviolet laser L in the insulating layer (4, 10) having a maximum thickness of 50 μm.
[0041]
The UV laser L penetrates the stacked body 25 and reaches the electrode pad portion 6 of the semiconductor chip 2, but the progress of the UV laser L is restricted by the barrier layer 16, and unnecessary processing on the electrode pad portion 6 is prevented. . Similarly, the UV laser L that has reached the circuit pattern (land) 7 on the printed wiring board 3 is also restricted from being processed more than necessary by the thick copper foil layer. As described above, the electrode pad portion 6 and the circuit pattern (land) 7 are opened.
[0042]
On the other hand, in the process of making the contact holes 18 and 19 conductive, for example, copper plating is deposited in the contact holes 18 and 19 by using both the electroless plating method and the electrolytic plating method, or the contact is made by screen printing or the like. This is done by filling the holes 18 and 19 with a conductive material. Thereby, as shown in FIG. 3G, the interlayer connection portions 8 and 9 for electrically connecting the electrode pad portion 6 of the semiconductor chip 2 and the circuit pattern 7 of the printed wiring board 3 and the copper foil 5A on the surface. Is formed.
[0043]
As described above, when the interlayer connection portions 8 and 9 are formed by filling the connection holes 18 and 19 with a conductive material, a conductive paste having silver particles having a diameter of 3 μm as the conductive particles is used as the conductive material. By using this, it is possible to easily fill the conductive holes 18 and 19 with a diameter of 30 μm with the conductive paste.
[0044]
Next, as shown in FIG. 3H, the conductor pattern 5 is formed by patterning the copper foil 5A into a predetermined shape. In the present embodiment, the semiconductor chip 2 is electrically connected to the circuit pattern 7 of the printed wiring board 3.
[0045]
The conductor pattern 5 is a region where a photoresist is formed on the copper foil 5A, a predetermined portion is exposed through an exposure mask, a resist pattern is formed by performing a development process, and a resist is not formed by etching. Can be formed by removing.
[0046]
As described above, the element-embedded substrate 1 of the present embodiment is manufactured. According to the present embodiment, the electrode pad portion 6 formed at a fine pitch can be connected to the conductor pattern 5 without changing the pitch.
[0047]
Further, since the electrode pad portion 6 can be connected to the circuit pattern 7 of the printed wiring board 3 without changing the pitch on the active surface 14 of the semiconductor chip 2, the circuit pattern 7 on the printed wiring board 3 is connected to the electrode pad. The semiconductor chip 2 can be electrically connected without being finely formed corresponding to the arrangement pitch of the portions 6.
[0048]
Moreover, according to the above embodiment, since the resin-coated copper foil 20 to which direct laser processing is applicable is used, the element-embedded substrate 1 capable of high-density mounting at low cost without complicating the manufacturing process. Can be manufactured.
[0049]
Having described the implementation of the present invention, of course, the present invention is not limited thereto, and various modifications are possible within the spirit of the invention.
[0050]
The example above implementation mode, the contact holes 18 and 19 for interlayer connection in forming by direct laser processing method, using UV laser L, of course, not limited to this. That is, if there is a certain margin in the pitch of the electrode pad portion 6, it is possible to use another laser light source such as a CO 2 laser or a YAG laser.
[0051]
Further, in the above implementation mode, it is used a single-sided copper-clad laminate as a printed wiring board 3, as shown in FIG. 4, as well as configure it with double-sided copper-clad laminate, the conductor of the outer surface side layer 5B Can be contributed to the reduction of electromagnetic noise. Further, if the solid foil layer 5B is connected to a ground circuit, it can be an electrostatic discharge (ESD) countermeasure. Are denoted by the same reference numerals corresponding to those of the implementation of embodiments described above in FIG.
[0052]
Furthermore, the element-containing substrate 1 manufactured in the form of implementation described above, it is further possible to reduce the build-up of by stacking another printed wiring board to the top or bottom layer. In this case, if the interlayer connection between the conductor patterns is performed by the above-described direct laser processing method, a multilayer printed wiring board having a fine pitch interlayer connection portion can be easily manufactured.
[0053]
Further, in the above implementation mode has described device embedded substrate 1 having a built-in semiconductor chip 2, of course, not limited to the semiconductor chip 2, and the active element including the other LSI, resistors or capacitors Such passive elements may also be incorporated.
[0054]
【The invention's effect】
As described above, according to the device-embedded substrate manufacturing method of the present invention, the electrode pad portion on the active surface of the semiconductor chip formed at a fine pitch can be connected to the conductor layer without changing the pitch.
[0055]
In addition, according to the method for manufacturing an element-embedded substrate of the present invention in which a contact hole for interlayer connection is formed using a resin-coated copper foil to which direct laser processing can be applied, an interlayer connection portion can be easily formed without requiring a complicated process. Can be formed.
[0056]
According to the method for manufacturing an element-embedded substrate of the present invention, the step of electrically connecting the copper foil and the electrode pad portion of the semiconductor chip includes the step of electrically connecting the copper foil and the circuit pattern of the printed wiring board. It is possible to connect the electrode pad portions formed on the circuit pattern on the printed wiring board without rearranging them on the active surface of the semiconductor chip.
[0057]
Furthermore, according to the element-embedded substrate of the present invention, since the conductive layer and the electrode pad portion of the semiconductor chip that are opposed to each other via the insulating layer are directly connected via the interlayer connection portion, the pad arrangement of the electrode pad portion The semiconductor chip can be connected to the conductor layer without rearranging.
[Brief description of the drawings]
Is a sectional view showing an element of the internal board arrangement according to the implementation of embodiment of the present invention; FIG.
Figure 2 (a) ~ (e) both are process sectional views explaining a manufacturing method for the device embedded substrate according to the implementation of the embodiment of the present invention.
[3] (f) ~ (h) both are process sectional views subsequent to FIG. 2 for explaining a manufacturing process of the element-embedded substrate according to the implementation of the embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a modification of the configuration of the element-embedded substrate according to the embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a configuration of a conventional element-embedded substrate.
FIG. 6 is a perspective view showing a configuration of a conventional semiconductor component having a rewiring layer 113 of an electrode pad portion on an active surface.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Device built-in board, 2 ... Semiconductor chip, 3 ... Printed wiring board, 4 ... Insulating layer, 5 ... Conductor pattern, 5A ... Copper foil (conductor layer), 6 ... Electrode pad part, 7 ... Circuit pattern, 8, 9 DESCRIPTION OF SYMBOLS Interlayer connection part, 10 ... Adhesive sheet (insulating base material) , 11 ... Opening, 12 ... Recess, 13 ... Bottom of recess, 14 ... Active surface of semiconductor chip, 16 ... Barrier layer, 18, 19 ... Communication hole 20 ... Copper foil with resin, L ... UV laser.

Claims (16)

半導体チップを内部に収容した素子内蔵基板の製造方法であって、
前記半導体チップを収容するための凹所を、樹脂付き銅箔の樹脂形成面側に積層された絶縁基材に形成する工程と、
プリント配線板上の所定部位に能動面を上向きにして前記半導体チップを搭載し、前記能動面を前記凹所を介して前記樹脂形成面に密着させるとともに、前記プリント配線板を前記絶縁基材に積層する工程と、
前記樹脂付き銅箔の銅箔側から、前記凹所内に収容された半導体チップの能動面上の電極パッド部に向けて、ダイレクトレーザ加工法により層間接続用の連絡孔を形成する工程と、
前記連絡孔を介して前記銅箔と前記電極パッド部とを導通させる工程と、
前記銅箔を所定形状にパターニングする工程とを有する
ことを特徴とする素子内蔵基板の製造方法。A method for manufacturing an element-embedded substrate containing a semiconductor chip therein,
Forming a recess for accommodating the semiconductor chip in an insulating base material laminated on the resin-formed surface side of the resin-coated copper foil;
A predetermined portion of the printed wiring board by the active side up mounting the semiconductor chip, with is adhered to the resin forming surface the active surface through the recess, said printed wiring board in the insulating substrate Laminating steps;
From the copper foil side of the resin-coated copper foil, to the electrode pad portion on the active surface of the semiconductor chip accommodated in the recess , forming a connection hole for interlayer connection by a direct laser processing method,
A step of conducting the copper foil and the electrode pad portion through the communication hole;
And a step of patterning the copper foil into a predetermined shape. 前記半導体チップを収容するための凹所を前記樹脂付き銅箔の樹脂形成面側に形成する工程が、前記樹脂付き銅箔の樹脂形成面側に前記絶縁基材として感光性の接着シートを接着した後、前記接着シートの所定部位に対し、露光および現像の各処理を行うことによって前記凹所を形成する
ことを特徴とする請求項１に記載の素子内蔵基板の製造方法。The step of forming a recess for housing the semiconductor chip on the resin-formed surface side of the resin-coated copper foil attaches a photosensitive adhesive sheet as the insulating substrate to the resin-formed surface side of the resin-coated copper foil. The manufacturing method of the element-embedded substrate according to claim 1 , wherein the recess is formed by performing exposure and development processes on a predetermined portion of the adhesive sheet. 前記半導体チップを収容するための凹所を前記樹脂付き銅箔の樹脂形成面側に形成する工程が、プレス加工によって前記凹所を形成した半硬化状態の熱硬化性樹脂シートを、前記絶縁基材として前記樹脂形成面に積層することによって行われる
ことを特徴とする請求項１に記載の素子内蔵基板の製造方法。The step of forming a recess for housing the semiconductor chip on the resin-formed surface side of the resin-coated copper foil comprises a semi-cured thermosetting resin sheet in which the recess is formed by pressing, the insulating base manufacturing method for the device-embedded board according to claim 1, characterized in that it is made by laminating the resin-forming surface as wood. 前記絶縁基材に前記プリント配線板を積層する工程が、加熱加圧プレスによって行われる
ことを特徴とする請求項１に記載の素子内蔵基板の製造方法。Wherein the step of laminating the printed wiring board in the insulating substrate, the manufacturing method of the head protection board according to claim 1, characterized in that it is carried out by the heat and pressure pressing. 前記銅箔と前記電極パッド部とを導通させる工程には、前記銅箔と前記プリント配線板上の回路パターンとを導通させる工程が含まれる
ことを特徴とする請求項１に記載の素子内蔵基板の製造方法。Wherein the step of a copper foil thereby turning on said electrode pad portions, the element built-in substrate according to claim 1, wherein the included step of electrically connecting the circuit pattern on the printed circuit board and the copper foil Manufacturing method. 前記銅箔と前記電極パッド部とを導通させる工程が、前記連絡孔の内壁面にめっき金属を析出させる工程である
ことを特徴とする請求項１に記載の素子内蔵基板の製造方法。Wherein the step of a copper foil thereby turning on said electrode pad portion, the manufacturing method of the head protection board according to claim 1, characterized in that the step of depositing a plating metal on the inner wall surface of the contact hole. 前記銅箔と前記電極パッド部とを導通させる工程が、前記連絡孔に対して導電材料を充填する工程である
ことを特徴とする請求項１に記載の素子内蔵基板の製造方法。Wherein the step of a copper foil thereby turning on said electrode pad portion, the manufacturing method of the head protection board according to claim 1, characterized in that the step of filling the conductive material with respect to the contact hole. 絶縁層と、
前記絶縁層の一方の面に形成された導体層と、
前記絶縁層の他方の面に形成され、半導体チップを収容可能な凹所と、
前記絶縁層の他方の面に積層され、前記半導体チップをその能動面が前記凹所の底部に密着されるように搭載したプリント配線板と、
前記導体層と、前記能動面上の電極パッド部との間を導通させる層間接続部とを備え、
前記絶縁層が、
樹脂付き銅箔の樹脂層と、
前記樹脂層に積層され前記凹所が形成された絶縁基材とを含む
ことを特徴とする素子内蔵基板。An insulating layer;
A conductor layer formed on one surface of the insulating layer;
A recess formed on the other surface of the insulating layer and capable of accommodating a semiconductor chip;
A printed wiring board that is stacked on the other surface of the insulating layer and on which the semiconductor chip is mounted so that its active surface is in close contact with the bottom of the recess;
With said conductor layer, and an interlayer connection portion for conduction between the electrode pad portions on the active surface,
The insulating layer is
A resin layer of copper foil with resin;
An element-embedded substrate comprising: an insulating base material laminated on the resin layer and having the recess formed therein . 前記絶縁基材が、熱硬化性樹脂からなる
ことを特徴とする請求項８に記載の素子内蔵基板。The element built-in substrate according to claim 8 , wherein the insulating base material is made of a thermosetting resin. 前記絶縁基材が、感光性を有する接着シートからなる
ことを特徴とする請求項８に記載の素子内蔵基板。The element built-in substrate according to claim 8 , wherein the insulating base material is made of a photosensitive adhesive sheet. 前記凹所の底部が樹脂付き銅箔の樹脂層でなり、
前記半導体チップが前記凹所内において、前記樹脂層の構成樹脂によってモールドされている
ことを特徴とする請求項８に記載の素子内蔵基板。The bottom of the recess is a resin layer of copper foil with resin,
The element built-in substrate according to claim 8 , wherein the semiconductor chip is molded with a constituent resin of the resin layer in the recess. 前記電極パッド部上には、前記導体層および前記絶縁層を同時に穿孔するレーザビームの進行を妨げるためのバリア層が設けられている
ことを特徴とする請求項８に記載の素子内蔵基板。The element built-in substrate according to claim 8 , wherein a barrier layer is provided on the electrode pad portion to prevent the progress of a laser beam that simultaneously drills the conductor layer and the insulating layer. 前記バリア層が、ニッケル、金、パラジウム、白金の単層またはこれらの複合層からなる
ことを特徴とする請求項１２に記載の素子内蔵基板。The element built-in substrate according to claim 12 , wherein the barrier layer is formed of a single layer of nickel, gold, palladium, platinum, or a composite layer thereof. 前記層間接続部が、前記導体層と前記電極パッド部との間を連絡する連絡孔の内部に充填された導電材料からなる
ことを特徴とする請求項８に記載の素子内蔵基板。The element built-in substrate according to claim 8 , wherein the interlayer connection portion is made of a conductive material filled in a communication hole that communicates between the conductor layer and the electrode pad portion. 前記層間接続部が、前記導体層と前記電極パッド部との間を連絡する連絡孔の内壁面に形成された金属めっきである
ことを特徴とする請求項８に記載の素子内蔵基板。The element built-in substrate according to claim 8 , wherein the interlayer connection portion is metal plating formed on an inner wall surface of a communication hole that communicates between the conductor layer and the electrode pad portion. 前記導体層と前記プリント配線板上の回路パターンとが、互いに層間接続されている
ことを特徴とする請求項８に記載の素子内蔵基板。The element built-in substrate according to claim 8 , wherein the conductor layer and the circuit pattern on the printed wiring board are interconnected to each other.
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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1636842B1 (en) 2003-06-03 2011-08-17 Casio Computer Co., Ltd. Stackable semiconductor device and method of manufacturing the same
FI20031341A (en) 2003-09-18 2005-03-19 Imbera Electronics Oy Method for manufacturing an electronic module
TWI278048B (en) 2003-11-10 2007-04-01 Casio Computer Co Ltd Semiconductor device and its manufacturing method
JP4321758B2 (en) * 2003-11-26 2009-08-26 カシオ計算機株式会社 Semiconductor device
JP4379693B2 (en) * 2003-11-10 2009-12-09 カシオ計算機株式会社 Semiconductor device and manufacturing method thereof
JP4324732B2 (en) * 2003-11-28 2009-09-02 カシオ計算機株式会社 Manufacturing method of semiconductor device
JP4298559B2 (en) 2004-03-29 2009-07-22 新光電気工業株式会社 Electronic component mounting structure and manufacturing method thereof
JP3925809B2 (en) 2004-03-31 2007-06-06 カシオ計算機株式会社 Semiconductor device and manufacturing method thereof
FI117814B (en) * 2004-06-15 2007-02-28 Imbera Electronics Oy A method for manufacturing an electronic module
JP4622449B2 (en) * 2004-10-21 2011-02-02 パナソニック株式会社 Electronic component built-in substrate and manufacturing method thereof
DE112006001506T5 (en) 2005-06-16 2008-04-30 Imbera Electronics Oy Board structure and method for its production
FI119714B (en) 2005-06-16 2009-02-13 Imbera Electronics Oy Circuit board structure and method for manufacturing a circuit board structure
FI122128B (en) 2005-06-16 2011-08-31 Imbera Electronics Oy Process for manufacturing circuit board design
JP4636090B2 (en) * 2008-01-31 2011-02-23 カシオ計算機株式会社 Semiconductor device and manufacturing method thereof
JP4840373B2 (en) * 2008-01-31 2011-12-21 カシオ計算機株式会社 Semiconductor device and manufacturing method thereof
KR101046379B1 (en) 2008-02-14 2011-07-05 주식회사 하이닉스반도체 Semiconductor package and manufacturing method thereof
CN106601699A (en) * 2016-12-22 2017-04-26 深圳中科四合科技有限公司 Discrete device packaging method and discrete device
DE102019214996A1 (en) * 2019-09-06 2021-03-11 Siemens Aktiengesellschaft Semi-finished product for component assembly, method for component assembly and use of the semi-finished product
TWI750838B (en) * 2020-10-08 2021-12-21 友達光電股份有限公司 Display panel and method for manufacturing the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06275739A (en) * 1993-03-23 1994-09-30 Sony Corp Adaptor made of ceramics, and ceramic package
JP3003510B2 (en) * 1994-07-19 2000-01-31 凸版印刷株式会社 Method for forming electrode part of wiring board
JP2001119147A (en) * 1999-10-14 2001-04-27 Sony Corp Multilayer board incorporating electronic device and production method therefor
JP3813402B2 (en) * 2000-01-31 2006-08-23 新光電気工業株式会社 Manufacturing method of semiconductor device
JP2001274203A (en) * 2000-03-24 2001-10-05 Hitachi Cable Ltd Bimetal substrate and bga structure

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