[go: up one dir, main page]

JP3840166B2 - Semiconductor element storage package and semiconductor device - Google Patents

Semiconductor element storage package and semiconductor device Download PDF

Info

Publication number
JP3840166B2
JP3840166B2 JP2002267160A JP2002267160A JP3840166B2 JP 3840166 B2 JP3840166 B2 JP 3840166B2 JP 2002267160 A JP2002267160 A JP 2002267160A JP 2002267160 A JP2002267160 A JP 2002267160A JP 3840166 B2 JP3840166 B2 JP 3840166B2
Authority
JP
Japan
Prior art keywords
base
semiconductor element
frame body
frame
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002267160A
Other languages
Japanese (ja)
Other versions
JP2004056063A (en
Inventor
民男 草野
晃子 松崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2002267160A priority Critical patent/JP3840166B2/en
Publication of JP2004056063A publication Critical patent/JP2004056063A/en
Application granted granted Critical
Publication of JP3840166B2 publication Critical patent/JP3840166B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、半導体素子を収納するための半導体素子収納用パッケージおよび半導体装置に関する。
【0002】
【従来の技術】
従来の半導体素子を収納するための半導体素子収納用パッケージ(以下、半導体パッケージともいう)を図7に示す。図7は半導体パッケージの平面図、図8は図7の半導体パッケージの側面図、図9は図7の半導体パッケージの底面図である。これらの図において、21は略四角形の基体、22は枠体を示し、これら基体21、枠体22とで、内部空間に半導体素子25を収容する容器が基本的に構成される。
【0003】
基体21は、鉄(Fe)−ニッケル(Ni)−コバルト(Co)合金等の金属や銅(Cu)−タングステン(W)等の焼結材から成り、その上側主面の中央部には、半導体レーザ(LD),フォトダイオード(PD)等の半導体素子25を載置するための載置部21dが設けられるとともに、基体21の四隅部に外側に延出して設けられた張出部に円弧状の切欠き部21cが形成されて成るネジ止め部21aが設けられている。なお、図7に示すように、ネジ止め部21aは基体21の四隅部で一辺側にのみつながるように形成されており、ネジ止め部21a内に円弧状の切欠き部21cが形成されている。また、ネジ止め部21aの円弧状の切欠き部21cは、基体21の隣接する二辺の延長線および枠体22の隣接する二側部の外側面の延長面に挟まれる領域の外側に位置する。この基体21は、円弧状の切欠き部21cにネジを挿入し外部電気回路基板にネジ止め固定される。
【0004】
基体21の上側主面の外周部には、載置部21dを囲繞するようにして接合された枠体22が立設されている。この枠体22は、アルミナ(Al23)セラミックス等のセラミックスから成り、基体21に銀(Ag)ロウ等のロウ材を介してロウ付けされる。
【0005】
枠体22には、内外を導通する線路導体(図示せず)が設けられており、枠体22外面側の線路導体にはFe−Ni−Co合金等の金属から成るリード端子24がAgロウ等のロウ材を介して電気的に接続されることによって半導体パッケージが製作される(例えば、下記の特許文献1参照)。
【0006】
このような構成の半導体パッケージの載置部21dに半導体素子25を載置固定した後、半導体素子25の電極と枠体22内面側に設けられた線路導体とをボンディングワイヤで電気的に接続し、蓋体26により半導体素子25を気密に封止する。また、枠体22の上面にFe−Ni−Co合金等から成るシールリング23をロウ付けし、シールリング23の上面にFe−Ni−Co合金等から成る蓋体26をシーム溶接法等の溶接法により接合することによって、製品としての半導体装置となる。そして、ネジ止め部21aの円弧状の切欠き部21cにネジを挿入し、基体21を外部電気回路基板にネジ止め固定する。この半導体装置は、リード端子24が外部電気回路に接続され、半導体素子25が外部電気回路に電気的に接続されることによって、半導体素子25が高周波信号で作動することとなる。
【0007】
【特許文献1】
特開平11−54657号公報
【0008】
【発明が解決しようとする課題】
しかしながら、枠体22と基体21の各外形寸法が略同じ大きさとなっているため、枠体22を基体21にロウ付けする際に、枠体22と基体21の間に良好なロウ材のメニスカスを形成できず、枠体22を基体21に強固に接合するのが困難であるという問題があった。
【0009】
また、上記従来の構成において、基体21をネジ止めして外部電気回路基板に固定した際、ネジ止めにより発生した歪みが原因で、枠体22と基体21の外周端の接合部において、基体21の接合がはがれ、枠体22にクラック等の破損が生じ、主に基体21と枠体22とから構成される半導体パッケージ内部を気密に保持できなくなるという問題があった。
【0010】
さらに、半導体素子25が作動して発熱した場合に、基体21が熱膨張を起こし、ネジ止めにより拘束されている基体21に反りが生じ、基体21が外部電気回路基板から浮き上がり、半導体素子25の熱を外部に効率良く放熱できなくなるという問題があった。
【0011】
また、基体21のネジ止め部21aは4箇所あるため、外部電気回路基板に実装する際に必要となる面積が大きくなるという問題点、ネジ止めの際に基体21に歪みが加わりやすいという問題点もあった。
【0012】
従って、本発明は上記従来の問題点に鑑み完成されたものであり、その目的は、半導体パッケージ内部を気密に保持するとともに、半導体素子の熱を効率良く外部に放散し得るものとすることにある。
【0013】
【課題を解決するための手段】
本発明の半導体素子収納用パッケージは、上側主面に半導体素子を載置するための載置部が設けられた略四角形の金属製の基体と、該基体の前記上側主面の外周部に前記載置部を囲繞するように接合されたセラミック製の枠体と、前記基体の対角位置の2隅部で前記基体の隣接する2辺の延長線に挟まれる領域の外側に突出してネジ孔が前記枠体の外側に位置するように設けられた、付け根がくびれているネジ止め部とを具備しており、前記基体は、前記上側主面の外形寸法が前記枠体の下面の外周寸法よりも小さくかつ前記枠体の下面の内周寸法よりも大きいことを特徴とする。
【0014】
本発明の半導体素子収納用パッケージは、基体の上側主面の外形寸法が枠体の下面の外周寸法よりも小さくかつ枠体の下面の内周寸法よりも大きいことにより、枠体と基体とをロウ付けした際に、枠体と基体の外周端の接合部に良好なロウ材のメニスカスを形成することができ、それらの接合が強固になる。また、基体を外部電気回路基板にネジ止め固定することにより発生した基体の歪みを、ネジ止め部の付け根のくびれ部で吸収できる。また、半導体素子が作動し発熱した場合に基体が熱膨張を起こしても、ネジ止め部の付け根のくびれ部で熱膨張による歪みを吸収できる。さらに、基体のネジ止め部を対角位置の2隅部に設けたことにより、半導体装置の実装面積を小さくでき、またネジ止め時に基体に加わる歪みを最小限に抑えることができる。
【0015】
本発明の半導体素子収納用パッケージにおいて、好ましくは、前記基体と前記枠体とは、ロウ材を介して接合されており、前記ネジ止め部は、前記付け根の上面に前記付け根の両側面間にわたって前記ロウ材を導入するための溝が、その開口の前記基体の中心側の開口縁を前記枠体の内面の下端と外面の下端との間に位置させて形成されていることを特徴とする。
【0016】
本発明の半導体素子収納用パッケージは、基体と枠体とがロウ材を介して接合されており、ネジ止め部の付け根の上面に付け根の両側面間にわたってロウ材を導入するための溝が、その開口の基体の中心側の開口縁を枠体の内面の下端と外面の下端との間に位置させて形成されていることから、基体と枠体とをロウ付けした際に、ネジ止め部の付け根においてロウ材が溝に入り込んで枠体とロウ材との接着面積およびネジ止め部の付け根とロウ材との接着面積を大きくすることができるとともに、基体と枠体との接合部に全周にわたって良好なロウ材のメニスカスを形成することができ、それらの接合を著しく強固にできる。
【0017】
本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、前記載置部に載置固定された半導体素子と、前記枠体の上面に接合された蓋体とを具備したことを特徴とする。
【0018】
本発明の半導体装置は、上記の構成により、上記本発明の半導体素子収納用パッケージを用いた信頼性の高いものとなる。
【0019】
【発明の実施の形態】
本発明の半導体素子収納用パッケージについて以下に詳細に説明する。図1は本発明の半導体パッケージについて実施の形態の一例を示す平面図、図2は図1の半導体パッケージの側面図、図3は図1の半導体パッケージの底面図である。また、図4は本発明の半導体パッケージについて他の例を示す平面図、図5は図4の半導体パッケージの側面図、図6は図4の半導体パッケージの底面図である。これらの図において、1は基体、2は枠体、3はシールリング、4はリード端子を示し、基体1と枠体2とで半導体素子5を収納する容器が基本的に構成される。
【0020】
本発明の基体1は、Fe−Ni−Co合金等の金属やCu−Wの焼結材等から成り、そのインゴットに圧延加工や打ち抜き加工等の従来周知の金属加工法を施したり、射出成形と切削加工等を施すことによって、所定形状に製作される。基体1の上側主面には、半導体素子5を載置する載置部1dが設けられる。この基体1は、半導体素子5が作動時に発する熱を外部に放熱させる放熱板の役割をも果たす。基体1の表面には、酸化腐食の防止や半導体素子5の載置固定を良好にするために、厚さ0.5〜9μmのNi層や厚さ0.5〜5μmの金(Au)層からなる金属層をメッキ法により被着させておくとよい。また、半導体素子5の熱を効率よく外部へ放熱させるために、半導体素子5がペルチェ素子等の熱電冷却素子に搭載された状態で載置部1dに載置固定されていてもよい。
【0021】
基体1の上側主面の外周部には、載置部1dを囲繞するようにして接合された枠体2が立設されており、枠体2は基体1とともにその内側に半導体素子5を収容する空所を形成する。枠体2は、Al23や窒化アルミニウム(AlN)等のセラミックスから成る平面視形状が略四角形の枠状体であり、セラミックグリーンシートを打ち抜き加工し、セラミックグリーンシートを多層積層し焼成することによって形成され、基体1にAgロウ等のロウ材を介してロウ付けされる。
【0022】
枠体2には、内外を導通する線路導体(図示せず)が設けられており、枠体2にはFe−Ni−Co合金等の金属から成るリード端子4がAgロウ等のロウ材を介して電気的に接続される。
【0023】
本発明の半導体パッケージは、図2,図3,図5,図6(a),(b)に示すように、基体1は上側主面の外形寸法が枠体2の下面の外周寸法よりも小さくかつ枠体2の下面の内周寸法よりも大きいことにより、基体1と枠体2との外周端の接合部にAgロウ等のロウ材のメニスカスを良好に形成できる。これにより、ロウ付けにより基体1を枠体2に強固に接合できるとともに、熱膨張差により基体1から枠体2に加わる歪みを軽減することができる。
【0024】
基体1の外周端と枠体2の外周端との間隔D、即ち基体1の上側主面の外形寸法と枠体2の下面の外周寸法との差は、0.1mm以上であるのがよい。この構成により、基体1と枠体2との外周端の接合部に良好なメニスカスを形成できる。D<0.1mmの場合、基体1と枠体2との外周端の接合部に良好なメニスカスを形成できなくなり、基体1を枠体2に強固に接合できなくなるとともに、熱膨張差によって基体1から枠体2に加わる歪みを軽減できなくなる。また、Dは枠体2の枠部の幅方向の厚さ(1mm程度)以下であり、Dが枠体2の厚さを超えると枠体2を基体1の上側主面に接合できなくなる。
【0025】
また、図1,図3,図4,図6(a),(b)に示すように、ネジ止め部1aは、基体1の隣接する二辺の延長線に挟まれる領域の外側に突出してネジ孔が枠体2の外側に位置するように設けられ、ネジ止め部1aの付け根にくびれ部1bを有している。ネジ止め部1aにはネジ孔としての円弧状の切欠き部1cが形成されている。この構成により、切欠き部1cにネジを挿入して外部電気回路基板にネジ止め固定する際に、枠体2内側の載置部1dに載置固定された半導体素子5が載置部1dから剥がれず、かつ基体1の下側主面が外部電気回路基板から浮き上がらないように、基体1の反りを適度に矯正することができる。その結果、基体1と外部電気回路基板とを十分密着させて、半導体素子5の熱を無駄なく放熱させることができる。
【0026】
なお、ネジ孔は円弧状の切欠き部1cに限らず、円形状の貫通孔であってもよい。
【0027】
また、ネジ止め部1aの円弧状の切欠き部1cが、基体1の隣接する二辺の延長線に挟まれる領域、また枠体2の隣接する二側部の外側面の延長面に挟まれる領域の外側に位置するように設けられており、かつネジ止め部1aの付け根にくびれ部1bが形成されていることにより、切欠き部1cにネジを挿入して外部電気回路基板にネジ止め固定する際に、基体1を介して枠体2に伝わる歪みをくびれ部1bで分散するとともに、基体1がくびれ部1bで適度に変形することにより歪みを緩和して、枠体2にクラック等の破損が発生することを防止できる。
【0028】
図3,図6(a),(b)に示すように、ネジ止め部1aのくびれ部1bの幅W1は、0.5mm以上で、かつネジ止め部1aの幅W2の0.9倍以下であるのがよい。W1<0.5mmの場合、切欠き部1cにネジを挿入して外部電気回路基板にネジ止め固定する際に、くびれ部1bが大きく変形し易くなり、ネジ止め部1aがくびれ部1bで破断され、基体1を外部電気回路基板に固定できなくなる場合がある。また、W1>0.9×W2の場合、切欠き部1cにネジを挿入して外部電気回路基板にネジ止め固定しても基体1の反りをほとんど矯正することができず、枠体2にクラックが入り易くなり、また枠体2内側に位置する基体1の下側主面を外部電気回路基板に十分密着させることができず、半導体素子5の熱を十分に放熱できなくなる。
【0029】
さらに、W1はネジ止め部1aが設けられる基体1の辺の長さの0.1〜0.3倍がよい。0.1倍未満では、ネジ止め固定する際にくびれ部1bが大きく変形し易くなり、ネジ止め部1aがくびれ部1bで破断され、基体1を外部電気回路基板に固定できなくなる場合がある。0.3倍を超えると、ネジ止め固定した際に基体1に大きな歪が加わってその反りが大きく矯正され、枠体2に大きな歪みが加わって枠体2内側に位置する基体1の下側主面を外部電気回路基板に十分密着させることができず、半導体素子5の熱を十分に放熱できなくなる。
【0030】
また、本発明において、基体1と枠体2とは、ロウ材を介して接合されており、ネジ止め部1aは、付け根の上面に付け根の両側面間にわたってロウ材を導入するための溝1eが、その開口の基体1の中心側の開口縁を枠体2の内面の下端と外面の下端との間に位置させて形成されていることが好ましい。この構成により、基体1と枠体2とをロウ付けした際に、ネジ止め部1aの付け根においてロウ材が溝1eに入り込んで枠体2とロウ材との接着面積およびネジ止め部1aの付け根とロウ材との接着面積を大きくすることができるとともに、基体1と枠体2との接合部に全周にわたって良好なロウ材のメニスカスを形成することができ、それらの接合を著しく強固にできる。
【0031】
溝1eは、図5,図6(a),(b)に示すように、枠体2の外面の下端の下方に設けられるのがよい。つまり、溝1eの基体1の中心側の開口縁は枠体2の外面の下端よりも内側に設けられ、切欠き部1c側の開口縁は枠体2の外面の下端よりも外側に設けられるのがよい。これにより、ネジ止め部1aの付け根を含んで、基体1と枠体2との接合部に全周にわたってロウ材のメニスカスが形成され、基体1と枠体2との接合強度が向上する。
【0032】
溝1eの幅W3は0.1〜2mmとするのがよい。W3が0.1mm未満の場合、ロウ材が溝1eに入り込み難くなりネジ止め部1aにおける接合部(以下、接合部Aという)に良好なロウ材のメニスカスを形成し難くなるとともに、接合部Aで枠体2とロウ材との接着面積およびネジ止め部1aの付け根とロウ材との接着面積が小さくなって、接合部Aで基体1と枠体2との接合が弱くなり易い。また、W3が2mmを超える場合、ネジ止め部1aの強度が付け根で低下して付け根が反り易くなり、基体1を外部電気回路基板に固定し難くなる。
【0033】
また、溝1eの深さは、基体1の厚さの1/5〜3/4(0.1〜0.4mm程度)とするのがよい。溝1eの深さが基体1の厚さの1/5より小さい場合、ネジ止め部1aの付け根でロウ材が枠体2の下面に入り込み難くなり接合部Aに良好なロウ材のメニスカスを形成し難くなるとともに、接合部Aで枠体2とロウ材との接着面積およびネジ止め部1aの付け根とロウ材との接着面積が小さくなって、接合部Aで基体1と枠体2との接合が弱くなり易い。また、溝1eの深さが基体1の厚さの3/4より大きい場合、ネジ止め部1aの付け根の強度が小さくなって大きく反ったりして変形し易くなり、基体1を外部電気回路基板に固定し難くなる。
【0034】
なお、溝1eは、図6(a)に示すように、基体1の中心側の開口縁が基体1の側面と略面一とされるのがよい。これにより、基体1と枠体2との接合部に全周にわたって均一なロウ材のメニスカスを形成できる。また、溝1eの基体1の中心側の開口縁が基体1の側面と枠体2の外面の下端との間に位置していてもよい。これにより、ネジ止め部1aの付け根の強度が向上するとともに接合部Aにもロウ材のメニスカスを形成できる。より好ましくは、図6(b)に示すように、溝1eの基体1の中心側の開口縁が基体1の側面よりも内側に位置し、かつ枠体2の内面の下端よりも外側に設けられるのがよい。これにより、ネジ止め部1aの付け根により大きなロウ材のメニスカスを形成して接合部Aにおける接合強度が向上するとともに、ネジ止め部1aの付け根の強度が低下するのを大きなロウ材のメニスカスによってカバーすることができる。
【0035】
そして、溝1eの基体1の中心側の開口縁が基体1の側面よりも内側に位置し、かつ枠体2の内面の下端よりも外側に設けられている場合、W3=0.5〜2mmとするのがよい。W3が0.5mm未満の場合、溝1eの幅が狭いため、溝1eが枠体2の下面に覆われてネジ止め部1aの適度な変形により歪を緩和する効果が阻害され易くなる。また、2mmを超えると半導体素子5から発生する熱により、あるいはネジ止め部1aの付け根の強度が低下することによりネジ止め部1aの付け根が変形し易くなる。またこの場合、溝1eの長さW4はW2〜1.5×W2とするのがよい。W4がW2未満の場合、溝1eでネジ止め部1aの強度が低下しネジ止め部1aに折れ等の破損が生じ易くなる。また、W4が1.5×W2を超えるとネジ止め部1aの付け根の強度の低下をロウ材のメニスカスでカバーするのが難しくなり、ネジ止め部1aが変形し易くなる。
【0036】
また、ネジ止め部1aにおいて、円弧状の切欠き部1cの曲率半径は1mm程度で曲率中心の位置はネジの中心位置と略同じであるが、切欠き部1cの曲率中心とくびれ部1bの最幅狭部との距離は0.2〜2mmが好ましい。0.2mm未満では、ネジ止め固定した際に基体1に大きな歪が加わってその反りが大きく矯正され、枠体2に大きな歪みが加わって枠体2内側に位置する基体1の下側主面を外部電気回路基板に十分密着させることができず、半導体素子5の熱を十分に放熱できなくなる。2mmを超えると、ネジ止め固定する際にくびれ部1bが大きく変形し易くなり、ネジ止め部1aがくびれ部1bで破断され、基体1を外部電気回路基板に固定できなくなる場合がある。
【0037】
また、図1,図3,図4,図6(a),(b)に示すように、ネジ止め部1aは基体1の辺に略直交するようにしてその辺から外側に伸びるように形成されているが、ネジ止め部1aは基体1の辺の中心側に傾くようにその辺に対して斜めに設けられていてもよい。この場合、ネジ止めによる歪みをより緩和することができ、その結果、半導体パッケージ内部の気密性を保持できるとともに半導体素子5の熱を外部に効率よく放熱できる。
【0038】
また、基体1のネジ止め部1aを2箇所にしたことにより、外部電気回路基板に実装する際に必要とする面積を小さくでき、かつネジ止め時に基体1に加わる歪みを最小限に抑えることができる。
【0039】
このような構成の半導体パッケージの載置部1dに半導体素子5を載置固定した後、半導体素子5の電極と線路導体の枠体2内面側の部位とを、ボンディングワイヤで電気的に接続し、枠体2の上面にFe−Ni−Co合金等から成るシールリング3をロウ付けし、シールリング3の上面にFe−Ni−Co合金等から成る蓋体6をシーム溶接法等の溶接法により接合し、半導体素子5を気密に封止することにより、製品としての半導体装置となる。
【0040】
そして、ネジ止め部1aの切欠き部1cにネジを挿入し基体1を外部電気回路基板にネジ止め固定し、リード端子4を外部電気回路に接続することにより、半導体装置内部に収納した半導体素子5が外部電気回路に電気的に接続され、半導体素子5が高周波信号で作動することとなる。
【0041】
本発明の半導体装置は、図1,図3,図4,図6(a),(b)に示すように、ネジ止め部1aの切欠き部1cにネジを挿入し、ネジ止め固定して外部電気回路基板に実装した際に、基体1をほとんど変形させることなく、ネジ止め部1aが主に変形する。また、半導体素子5の熱により、熱膨張を起こしても、くびれ部1bが優先的に変形する。これらによって、枠体2内側に位置する基体1の下側主面を外部電気回路基板に密着させることができ、内部に収容した半導体素子5から基体1と外部電気回路基板とを介して外部に熱を効率良く放熱することができる。
【0042】
なお、本発明は上記実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲内で種々の変更を施すことは可能である。
【0043】
【発明の効果】
本発明の半導体素子収納用パッケージは、上側主面に半導体素子を載置するための載置部が設けられた略四角形の金属製の基体と、基体の上側主面の外周部に載置部を囲繞するように接合されたセラミック製の枠体と、基体の対角位置の2隅部で基体の隣接する2辺の延長線に挟まれる領域の外側に突出してネジ孔が枠体の外側に位置するように設けられた、付け根がくびれているネジ止め部とを具備しており、基体は、上側主面の外形寸法が枠体の下面の外周寸法よりも小さくかつ枠体の下面の内周寸法よりも大きいことにより、枠体と基体とをロウ付けした際に、枠体と基体の外周端の接合部に良好なロウ材のメニスカスを形成することができ、それらの接合が強固になる。また、基体を外部電気回路基板にネジ止め固定することにより発生した基体の歪みを、ネジ止め部の付け根のくびれ部で吸収できる。また、半導体素子が作動し発熱した場合に基体が熱膨張を起こしても、ネジ止め部の付け根のくびれ部で熱膨張による歪みを吸収できる。さらに、基体のネジ止め部を対角位置の2隅部に設けたことにより、半導体装置の実装面積を小さくでき、またネジ止め時に基体に加わる歪みを最小限に抑えることができる。
【0044】
また、本発明の半導体素子収納用パッケージは、基体と枠体とがロウ材を介して接合されており、ネジ止め部の付け根の上面に付け根の両側面間にわたってロウ材を導入するための溝が、その開口の基体の中心側の開口縁を枠体の内面の下端と外面の下端との間に位置させて形成されていることから、基体と枠体とをロウ付けした際に、ネジ止め部の付け根においてロウ材が溝に入り込んで枠体とロウ材との接着面積およびネジ止め部の付け根とロウ材との接着面積を大きくすることができるとともに、基体と枠体との接合部に全周にわたって良好なロウ材のメニスカスを形成することができ、それらの接合を著しく強固にできる。
【0045】
本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、載置部に載置固定された半導体素子と、枠体の上面に接合された蓋体とを具備したことにより、上記本発明の半導体素子収納用パッケージを用いた信頼性の高いものとなる。
【図面の簡単な説明】
【図1】本発明の半導体素子収納用パッケージについて実施の形態の例を示す平面図である。
【図2】図1の半導体素子収納用パッケージの側面図である。
【図3】図1の半導体素子収納用パッケージの底面図である。
【図4】本発明の半導体素子収納用パッケージについて実施の形態の他の例を示す半導体素子収納用パッケージの平面図である。
【図5】図4の半導体素子収納用パッケージの側面図である。
【図6】(a)は図4の半導体素子収納用パッケージの底面図、(b)は図4の半導体素子収納用パッケージについて実施の形態の他の例を示す半導体素子収納用パッケージの底面図である。
【図7】従来の半導体素子収納用パッケージの平面図である。
【図8】図7の半導体素子収納用パッケージの側面図である。
【図9】図7の半導体素子収納用パッケージの底面図である。
【符号の説明】
1:基体
1a:ネジ止め部
1b:くびれ部
1c:切欠き部
1d:載置部
1e:溝
2:枠体
5:半導体素子
6:蓋体
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element housing package and a semiconductor device for housing semiconductor elements.
[0002]
[Prior art]
A conventional semiconductor element storage package (hereinafter also referred to as a semiconductor package) for storing a conventional semiconductor element is shown in FIG. 7 is a plan view of the semiconductor package, FIG. 8 is a side view of the semiconductor package of FIG. 7, and FIG. 9 is a bottom view of the semiconductor package of FIG. In these drawings, reference numeral 21 denotes a substantially rectangular base body, and 22 denotes a frame body. The base body 21 and the frame body 22 basically constitute a container for housing the semiconductor element 25 in the internal space.
[0003]
The base body 21 is made of a metal such as an iron (Fe) -nickel (Ni) -cobalt (Co) alloy or a sintered material such as copper (Cu) -tungsten (W). A mounting portion 21d for mounting a semiconductor element 25 such as a semiconductor laser (LD), a photodiode (PD) or the like is provided, and a circular portion is provided on the protruding portion provided at the four corners of the base 21 so as to extend outward. A screwing portion 21a formed with an arc-shaped cutout portion 21c is provided. As shown in FIG. 7, the screwing portion 21a is formed so as to be connected only to one side at the four corners of the base 21, and an arcuate cutout portion 21c is formed in the screwing portion 21a. . Further, the arc-shaped cutout portion 21c of the screwing portion 21a is positioned outside the region sandwiched between the extension lines of the two adjacent sides of the base body 21 and the extension surface of the two adjacent side portions of the frame body 22. To do. The base body 21 is fixed to the external electric circuit board with screws by inserting screws into the arc-shaped cutout portions 21c.
[0004]
On the outer peripheral portion of the upper main surface of the base body 21, a frame body 22 joined so as to surround the mounting portion 21d is erected. The frame 22 is made of ceramics such as alumina (Al 2 O 3 ) ceramics, and is brazed to the base 21 via a brazing material such as silver (Ag) brazing.
[0005]
The frame body 22 is provided with a line conductor (not shown) that conducts both inside and outside. The line conductor on the outer surface side of the frame body 22 is provided with a lead terminal 24 made of a metal such as Fe-Ni-Co alloy. A semiconductor package is manufactured by being electrically connected via a brazing material such as the above (for example, see Patent Document 1 below).
[0006]
After the semiconductor element 25 is mounted and fixed on the mounting portion 21d of the semiconductor package having such a configuration, the electrode of the semiconductor element 25 and the line conductor provided on the inner surface side of the frame body 22 are electrically connected by a bonding wire. Then, the semiconductor element 25 is hermetically sealed by the lid body 26. Also, a seal ring 23 made of Fe-Ni-Co alloy or the like is brazed to the upper surface of the frame body 22, and a lid body 26 made of Fe-Ni-Co alloy or the like is welded to the upper surface of the seal ring 23 by a seam welding method or the like. By joining by a method, a semiconductor device as a product is obtained. Then, a screw is inserted into the arc-shaped cutout portion 21c of the screwing portion 21a, and the base 21 is fixed to the external electric circuit board with screws. In this semiconductor device, the lead terminal 24 is connected to an external electric circuit, and the semiconductor element 25 is electrically connected to the external electric circuit, whereby the semiconductor element 25 operates with a high-frequency signal.
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-54657
[Problems to be solved by the invention]
However, since the outer dimensions of the frame body 22 and the base body 21 are substantially the same size, when brazing the frame body 22 to the base body 21, a good meniscus of brazing material is provided between the frame body 22 and the base body 21. There is a problem that it is difficult to form a frame 22 and it is difficult to firmly bond the frame 22 to the base 21.
[0009]
Further, in the above conventional configuration, when the base body 21 is screwed and fixed to the external electric circuit board, the base body 21 is bonded to the outer peripheral end of the frame body 22 and the base body 21 due to distortion generated by screwing. As a result, the frame body 22 is peeled off, and the frame body 22 is damaged, such as cracks, so that the inside of the semiconductor package mainly composed of the base body 21 and the frame body 22 cannot be kept airtight.
[0010]
Further, when the semiconductor element 25 is activated to generate heat, the base 21 undergoes thermal expansion, warping occurs in the base 21 that is restrained by screwing, and the base 21 is lifted from the external electric circuit board. There was a problem that heat could not be efficiently radiated to the outside.
[0011]
In addition, since there are four screwing portions 21a of the base 21, there are problems that the area required for mounting on the external electric circuit board increases, and that the base 21 tends to be distorted when screwing. There was also.
[0012]
Accordingly, the present invention has been completed in view of the above-mentioned conventional problems, and an object of the present invention is to keep the inside of the semiconductor package airtight and to efficiently dissipate the heat of the semiconductor element to the outside. is there.
[0013]
[Means for Solving the Problems]
The package for housing a semiconductor element of the present invention includes a substantially rectangular metal base provided with a mounting portion for mounting a semiconductor element on an upper main surface, and an outer peripheral portion of the upper main surface of the base. A ceramic frame joined so as to surround the mounting portion, and a screw hole projecting outside a region sandwiched between two extension lines adjacent to the base at two diagonal portions of the base And a screwing portion having a constricted base, provided so that the outer peripheral dimension of the upper main surface is the outer peripheral dimension of the lower surface of the frame body. Smaller and larger than the inner circumference of the lower surface of the frame.
[0014]
The package for housing a semiconductor element of the present invention is such that the outer dimension of the upper main surface of the base body is smaller than the outer peripheral dimension of the lower surface of the frame body and larger than the inner peripheral dimension of the lower surface of the frame body. When brazed, a good meniscus of brazing material can be formed at the joint between the frame body and the outer peripheral edge of the substrate, and the joint between them becomes strong. Further, the distortion of the base generated by fixing the base to the external electric circuit board with screws can be absorbed by the constriction at the base of the screw fixing portion. Further, even when the semiconductor element is activated and generates heat, even if the base causes thermal expansion, distortion due to thermal expansion can be absorbed by the constriction at the base of the screwing portion. Furthermore, the mounting area of the semiconductor device can be reduced by providing the screwing portions of the base at the two corners of the diagonal position, and the distortion applied to the base at the time of screwing can be minimized.
[0015]
In the package for housing a semiconductor element according to the present invention, preferably, the base body and the frame body are joined via a brazing material, and the screwing portion extends between both side surfaces of the base. The groove for introducing the brazing material is formed such that the opening edge of the opening on the center side of the base is located between the lower end of the inner surface of the frame body and the lower end of the outer surface. .
[0016]
In the package for housing a semiconductor element of the present invention, the base body and the frame body are joined via a brazing material, and a groove for introducing the brazing material across the both side surfaces of the base is formed on the upper surface of the base of the screwing portion. Since the opening edge on the center side of the base of the opening is formed between the lower end of the inner surface of the frame body and the lower end of the outer surface, when the base body and the frame body are brazed, the screwing portion The brazing material can enter the groove at the base of the solder to increase the bonding area between the frame body and the brazing material and the bonding area between the base of the screwing portion and the brazing material, and at the joint between the base and the frame body. A good brazing meniscus can be formed over the circumference, and the bonding can be remarkably strengthened.
[0017]
A semiconductor device of the present invention comprises the above-described package for housing a semiconductor element of the present invention, a semiconductor element mounted and fixed on the mounting portion, and a lid body joined to the upper surface of the frame body. And
[0018]
The semiconductor device of the present invention has high reliability using the semiconductor element storage package of the present invention due to the above-described configuration.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor element storage package of the present invention will be described in detail below. 1 is a plan view showing an example of an embodiment of the semiconductor package of the present invention, FIG. 2 is a side view of the semiconductor package of FIG. 1, and FIG. 3 is a bottom view of the semiconductor package of FIG. 4 is a plan view showing another example of the semiconductor package of the present invention, FIG. 5 is a side view of the semiconductor package of FIG. 4, and FIG. 6 is a bottom view of the semiconductor package of FIG. In these drawings, reference numeral 1 denotes a base body, 2 denotes a frame body, 3 denotes a seal ring, 4 denotes a lead terminal, and the base body 1 and the frame body 2 basically constitute a container for housing the semiconductor element 5.
[0020]
The substrate 1 of the present invention is made of a metal such as an Fe-Ni-Co alloy, a sintered material of Cu-W, or the like, and the ingot is subjected to a conventionally known metal processing method such as rolling or punching or injection molding. By cutting and the like, it is manufactured in a predetermined shape. On the upper main surface of the base body 1, a mounting portion 1 d for mounting the semiconductor element 5 is provided. The base body 1 also serves as a heat radiating plate that radiates heat generated when the semiconductor element 5 is activated. On the surface of the substrate 1, a metal layer composed of a Ni layer having a thickness of 0.5 to 9 μm or a gold (Au) layer having a thickness of 0.5 to 5 μm in order to prevent oxidative corrosion and to make the semiconductor element 5 well fixed. Is preferably deposited by a plating method. Further, in order to efficiently dissipate the heat of the semiconductor element 5 to the outside, the semiconductor element 5 may be mounted and fixed on the mounting portion 1d while being mounted on a thermoelectric cooling element such as a Peltier element.
[0021]
A frame body 2 joined so as to surround the mounting portion 1d is erected on the outer peripheral portion of the upper main surface of the base body 1. The frame body 2 accommodates the semiconductor element 5 inside the base body 1 together with the base body 1. A void is formed. The frame body 2 is a frame body having a substantially square shape in plan view made of ceramics such as Al 2 O 3 and aluminum nitride (AlN). The ceramic green sheet is punched and laminated, and the ceramic green sheets are laminated and fired. And is brazed to the substrate 1 via a brazing material such as Ag brazing.
[0022]
The frame body 2 is provided with a line conductor (not shown) that conducts the inside and outside. The lead body 4 made of a metal such as an Fe-Ni-Co alloy is provided with a brazing material such as Ag brazing. Electrically connected.
[0023]
As shown in FIGS. 2, 3, 5, 6 (a) and 6 (b), the semiconductor package of the present invention is such that the outer dimension of the upper main surface of the substrate 1 is larger than the outer peripheral dimension of the lower surface of the frame 2. By being small and larger than the inner peripheral dimension of the lower surface of the frame body 2, a meniscus of a brazing material such as Ag brazing can be satisfactorily formed at the joint portion between the outer peripheral ends of the base body 1 and the frame body 2. As a result, the base body 1 can be firmly joined to the frame body 2 by brazing, and distortion applied to the frame body 2 from the base body 1 due to a difference in thermal expansion can be reduced.
[0024]
The distance D between the outer peripheral edge of the base body 1 and the outer peripheral edge of the frame body 2, that is, the difference between the outer dimension of the upper main surface of the base body 1 and the outer peripheral dimension of the lower surface of the frame body 2 is preferably 0.1 mm or more. With this configuration, a good meniscus can be formed at the joint between the outer peripheral ends of the base 1 and the frame 2. In the case of D <0.1 mm, a good meniscus cannot be formed at the joint between the outer peripheral ends of the base body 1 and the frame body 2, the base body 1 cannot be firmly joined to the frame body 2, and from the base body 1 due to a difference in thermal expansion. The distortion applied to the frame 2 cannot be reduced. Further, D is equal to or less than the thickness (about 1 mm) in the width direction of the frame portion of the frame body 2, and when D exceeds the thickness of the frame body 2, the frame body 2 cannot be joined to the upper main surface of the base body 1.
[0025]
As shown in FIGS. 1, 3, 4, and 6 (a) and 6 (b), the screwing portion 1 a protrudes outside a region sandwiched between two adjacent extension lines of the base 1. The screw hole is provided so as to be located outside the frame body 2 and has a constricted portion 1b at the base of the screwing portion 1a. An arc-shaped notch 1c as a screw hole is formed in the screwing portion 1a. With this configuration, when a screw is inserted into the cutout portion 1c and fixed to the external electric circuit board by screws, the semiconductor element 5 placed and fixed on the placement portion 1d inside the frame 2 is removed from the placement portion 1d. The warp of the base body 1 can be appropriately corrected so that it does not peel off and the lower main surface of the base body 1 does not float from the external electric circuit board. As a result, the substrate 1 and the external electric circuit board can be sufficiently adhered to dissipate the heat of the semiconductor element 5 without waste.
[0026]
The screw hole is not limited to the arcuate cutout 1c, but may be a circular through hole.
[0027]
Further, the arc-shaped cutout portion 1c of the screwing portion 1a is sandwiched between the extension surface of the two adjacent sides of the base body 1 and the extension surface of the outer side surface of the two adjacent side portions of the frame body 2. Since it is provided so as to be located outside the region and the constricted portion 1b is formed at the base of the screwing portion 1a, the screw is fixed to the external electric circuit board by inserting a screw into the notch portion 1c. In this case, the strain transmitted to the frame body 2 through the base body 1 is dispersed by the constricted portion 1b, and the base body 1 is moderately deformed by the constricted portion 1b, so that the strain is relieved and the frame body 2 is free of cracks and the like. Damage can be prevented from occurring.
[0028]
As shown in FIGS. 3, 6A and 6B, the width W1 of the constricted portion 1b of the screwing portion 1a is not less than 0.5 mm and not more than 0.9 times the width W2 of the screwing portion 1a. Is good. When W1 <0.5 mm, when the screw is inserted into the notch portion 1c and fixed to the external electric circuit board by screwing, the constricted portion 1b is easily deformed greatly, and the screwed portion 1a is broken at the constricted portion 1b. In some cases, the substrate 1 cannot be fixed to the external electric circuit board. Further, when W1> 0.9 × W2, even if a screw is inserted into the notch 1c and fixed to the external electric circuit board, the warp of the base body 1 can hardly be corrected, and the frame 2 is cracked. In addition, the lower main surface of the base body 1 located inside the frame 2 cannot be sufficiently adhered to the external electric circuit board, and the heat of the semiconductor element 5 cannot be sufficiently dissipated.
[0029]
Further, W1 is preferably 0.1 to 0.3 times the length of the side of the base 1 on which the screwing portion 1a is provided. If it is less than 0.1 times, the constricted portion 1b is likely to be greatly deformed when screwed and fixed, and the screwed portion 1a may be broken at the constricted portion 1b, and the base 1 may not be fixed to the external electric circuit board. If it exceeds 0.3 times, a large distortion is applied to the base body 1 when the screw is fixed, and the warpage is greatly corrected. A large distortion is applied to the frame body 2 and the lower main surface of the base body 1 located inside the frame body 2 Cannot be sufficiently adhered to the external electric circuit board, and the heat of the semiconductor element 5 cannot be sufficiently dissipated.
[0030]
Further, in the present invention, the base body 1 and the frame body 2 are joined via a brazing material, and the screwing portion 1a is a groove 1e for introducing the brazing material to the upper surface of the base between both side surfaces of the base. However, it is preferable that the opening edge on the center side of the base body 1 of the opening is formed between the lower end of the inner surface of the frame body 2 and the lower end of the outer surface. With this configuration, when the base body 1 and the frame body 2 are brazed, the brazing material enters the groove 1e at the root of the screwing portion 1a, the bonding area between the frame body 2 and the brazing material, and the root of the screwing portion 1a. The bonding area between the base material 1 and the frame 2 can be increased, and a good braid meniscus can be formed over the entire periphery of the base member 1 and the frame body 2. .
[0031]
The groove 1e is preferably provided below the lower end of the outer surface of the frame 2 as shown in FIGS. 5 and 6A, 6B. That is, the opening edge on the center side of the base body 1 of the groove 1 e is provided inside the lower end of the outer surface of the frame body 2, and the opening edge on the notch portion 1 c side is provided outside the lower end of the outer surface of the frame body 2. It is good. As a result, a braided meniscus is formed over the entire circumference at the joint between the base body 1 and the frame body 2 including the root of the screwing portion 1a, and the joint strength between the base body 1 and the frame body 2 is improved.
[0032]
The width W3 of the groove 1e is preferably 0.1 to 2 mm. When W3 is less than 0.1 mm, it is difficult for the brazing material to enter the groove 1e, and it becomes difficult to form a good meniscus of the brazing material at the joint portion (hereinafter referred to as the joint portion A) in the screwing portion 1a. The bonding area between the frame 2 and the brazing material and the bonding area between the root of the screwing portion 1a and the brazing material are reduced, and the bonding between the base 1 and the frame 2 is likely to be weak at the bonding portion A. On the other hand, if W3 exceeds 2 mm, the strength of the screwing portion 1a is lowered at the root, and the root tends to warp, and it is difficult to fix the base 1 to the external electric circuit board.
[0033]
The depth of the groove 1e is preferably set to 1/5 to 3/4 (about 0.1 to 0.4 mm) of the thickness of the substrate 1. When the depth of the groove 1e is smaller than 1/5 of the thickness of the base 1, the brazing material does not easily enter the lower surface of the frame 2 at the base of the screwing portion 1a, and a favorable brazing material meniscus is formed at the joint A. In addition, the bonding area between the frame 2 and the brazing material and the bonding area between the root of the screwing portion 1a and the brazing material are reduced at the joint A, and the base 1 and the frame 2 are bonded at the joint A. Bonding tends to be weak. Further, when the depth of the groove 1e is larger than 3/4 of the thickness of the base body 1, the strength of the base of the screwing portion 1a is reduced, and the base 1 is easily warped and deformed. It becomes difficult to fix to.
[0034]
As shown in FIG. 6A, the groove 1 e is preferably such that the opening edge on the center side of the substrate 1 is substantially flush with the side surface of the substrate 1. Thereby, a uniform meniscus of the brazing material can be formed at the joint portion of the base body 1 and the frame body 2 over the entire circumference. Further, the opening edge of the groove 1 e on the center side of the base body 1 may be located between the side surface of the base body 1 and the lower end of the outer surface of the frame body 2. As a result, the strength of the base of the screwing portion 1a is improved, and a braided meniscus can also be formed at the joint A. More preferably, as shown in FIG. 6B, the opening edge of the groove 1e on the center side of the base body 1 is located on the inner side of the side face of the base body 1 and provided outside the lower end of the inner face of the frame body 2. It is good to be done. As a result, a large brazing meniscus is formed at the base of the screwing portion 1a to improve the joint strength at the joint A, and the strength of the base of the screwing portion 1a is reduced by the large brazing meniscus. can do.
[0035]
And when the opening edge of the center side of the base | substrate 1 of the groove | channel 1e is located inside the side surface of the base | substrate 1, and is provided outside the lower end of the inner surface of the frame 2, it is set to W3 = 0.5-2 mm. It is good. When W3 is less than 0.5 mm, since the width of the groove 1e is narrow, the groove 1e is covered by the lower surface of the frame body 2, and the effect of alleviating the distortion by appropriate deformation of the screwing portion 1a is likely to be hindered. If it exceeds 2 mm, the base of the screwing portion 1a is likely to be deformed by the heat generated from the semiconductor element 5 or the strength of the base of the screwing portion 1a is reduced. In this case, the length W4 of the groove 1e is preferably W2 to 1.5 × W2. When W4 is less than W2, the strength of the screwing portion 1a is reduced by the groove 1e, and the screwing portion 1a is likely to be broken or broken. On the other hand, if W4 exceeds 1.5 × W2, it is difficult to cover the lowering of the strength of the base of the screwing portion 1a with the meniscus of the brazing material, and the screwing portion 1a is easily deformed.
[0036]
Further, in the screw fastening portion 1a, the radius of curvature of the arc-shaped cutout portion 1c is about 1 mm and the position of the center of curvature is substantially the same as the center position of the screw, but the center of curvature of the cutout portion 1c and the constricted portion 1b. The distance from the narrowest part is preferably 0.2 to 2 mm. If it is less than 0.2 mm, a large distortion is applied to the base body 1 when screwed and fixed, and the warpage is greatly corrected, and a large distortion is applied to the frame body 2 so that the lower main surface of the base body 1 located inside the frame body 2 is covered. It is not possible to sufficiently adhere to the external electric circuit board, and the heat of the semiconductor element 5 cannot be sufficiently dissipated. If it exceeds 2 mm, the constricted portion 1b is likely to be greatly deformed when screwed and fixed, and the screwed portion 1a may be broken at the constricted portion 1b, and the base 1 may not be fixed to the external electric circuit board.
[0037]
Further, as shown in FIGS. 1, 3, 4, 4, and 6A and 6B, the screwing portion 1a is formed so as to extend outward from the side so as to be substantially orthogonal to the side of the base 1. However, the screwing portion 1a may be provided obliquely to the side so as to be inclined toward the center of the side of the base 1. In this case, distortion due to screwing can be further relaxed, and as a result, airtightness inside the semiconductor package can be maintained and heat of the semiconductor element 5 can be efficiently radiated to the outside.
[0038]
In addition, since the screw fixing portions 1a of the base body 1 are provided at two locations, the area required for mounting on the external electric circuit board can be reduced, and distortion applied to the base body 1 when screwing can be minimized. it can.
[0039]
After the semiconductor element 5 is mounted and fixed on the mounting portion 1d of the semiconductor package having such a configuration, the electrode of the semiconductor element 5 and the portion of the line conductor on the inner surface side of the frame body 2 are electrically connected by a bonding wire. The seal ring 3 made of Fe—Ni—Co alloy or the like is brazed on the upper surface of the frame body 2, and the lid body 6 made of Fe—Ni—Co alloy or the like is brazed on the upper surface of the seal ring 3. The semiconductor element 5 is hermetically sealed, and the semiconductor element 5 is hermetically sealed, so that a semiconductor device as a product is obtained.
[0040]
Then, a screw is inserted into the notch 1c of the screwing portion 1a, the base body 1 is screwed and fixed to the external electric circuit board, and the lead terminal 4 is connected to the external electric circuit, whereby the semiconductor element housed in the semiconductor device is stored. 5 is electrically connected to an external electric circuit, and the semiconductor element 5 operates with a high-frequency signal.
[0041]
As shown in FIGS. 1, 3, 4, 4, 6A, and 6B, the semiconductor device of the present invention inserts a screw into the notch 1c of the screwing portion 1a and fixes the screw. When mounted on the external electric circuit board, the screwing portion 1a is mainly deformed with almost no deformation of the base body 1. Further, even if thermal expansion occurs due to the heat of the semiconductor element 5, the constricted portion 1b is preferentially deformed. By these, the lower main surface of the base body 1 located inside the frame body 2 can be brought into close contact with the external electric circuit board, and the semiconductor element 5 housed inside can be brought outside through the base body 1 and the external electric circuit board. Heat can be radiated efficiently.
[0042]
The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.
[0043]
【The invention's effect】
The semiconductor element storage package of the present invention includes a substantially rectangular metal base provided with a mounting portion for mounting a semiconductor element on the upper main surface, and a mounting portion on the outer peripheral portion of the upper main surface of the base. And a ceramic frame joined so as to surround the outer periphery of the substrate, and a screw hole projecting outside the region sandwiched between the extension lines of two adjacent sides of the substrate at the two corners of the substrate diagonally. The base is provided with a screwed portion with a constricted base, and the base has an outer dimension of the upper main surface smaller than an outer peripheral dimension of the lower surface of the frame and a lower surface of the frame. By being larger than the inner peripheral dimension, when the frame body and the base are brazed, a good brazing meniscus can be formed at the joint between the outer edge of the frame and the base, and the bonding between them is strong. become. Further, the distortion of the base generated by fixing the base to the external electric circuit board with screws can be absorbed by the constriction at the base of the screw fixing portion. Further, even when the semiconductor element is activated and generates heat, even if the base causes thermal expansion, distortion due to thermal expansion can be absorbed by the constriction at the base of the screwing portion. Furthermore, the mounting area of the semiconductor device can be reduced by providing the screwing portions of the base at the two corners of the diagonal position, and the distortion applied to the base at the time of screwing can be minimized.
[0044]
In the package for housing a semiconductor element of the present invention, the base body and the frame body are joined via the brazing material, and the groove for introducing the brazing material between the both side surfaces of the base on the upper surface of the base of the screwing portion. However, since the opening edge of the opening on the center side of the base is positioned between the lower end of the inner surface of the frame body and the lower end of the outer surface, when the base body and the frame body are brazed, The brazing material enters the groove at the base of the stop portion, and the bonding area between the frame body and the brazing material and the bonding area between the base portion of the screw fastening portion and the brazing material can be increased, and the joint portion between the base and the frame body In addition, a good braid meniscus can be formed over the entire circumference, and the bonding can be remarkably strengthened.
[0045]
The semiconductor device of the present invention includes the semiconductor element storage package of the present invention, the semiconductor element mounted and fixed on the mounting portion, and the lid bonded to the upper surface of the frame. The semiconductor device housing package of the invention is highly reliable.
[Brief description of the drawings]
FIG. 1 is a plan view showing an example of an embodiment of a package for housing a semiconductor element of the present invention.
2 is a side view of the semiconductor element storage package of FIG. 1; FIG.
3 is a bottom view of the semiconductor element storage package of FIG. 1; FIG.
FIG. 4 is a plan view of a semiconductor element storage package showing another example of the embodiment of the semiconductor element storage package of the present invention.
5 is a side view of the semiconductor element storage package of FIG. 4; FIG.
6A is a bottom view of the semiconductor element storage package of FIG. 4, and FIG. 6B is a bottom view of the semiconductor element storage package showing another example of the embodiment of the semiconductor element storage package of FIG. 4; It is.
FIG. 7 is a plan view of a conventional package for housing semiconductor elements.
8 is a side view of the semiconductor element storage package of FIG. 7;
9 is a bottom view of the semiconductor element storage package of FIG. 7; FIG.
[Explanation of symbols]
1: Base 1a: Screw fixing portion 1b: Constricted portion 1c: Notch portion 1d: Placement portion 1e: Groove 2: Frame body 5: Semiconductor element 6: Lid

Claims (3)

上側主面に半導体素子を載置するための載置部が設けられた略四角形の金属製の基体と、該基体の前記上側主面の外周部に前記載置部を囲繞するように接合されたセラミック製の枠体と、前記基体の対角位置の2隅部で前記基体の隣接する2辺の延長線に挟まれる領域の外側に突出してネジ孔が前記枠体の外側に位置するように設けられた、付け根がくびれているネジ止め部とを具備しており、前記基体は、前記上側主面の外形寸法が前記枠体の下面の外周寸法よりも小さくかつ前記枠体の下面の内周寸法よりも大きいことを特徴とする半導体素子収納用パッケージ。A substantially rectangular metal base provided with a mounting portion for mounting a semiconductor element on the upper main surface is bonded to the outer peripheral portion of the upper main surface of the base so as to surround the mounting portion. The screw hole is positioned outside the frame so that it protrudes outside the region sandwiched between the extension lines of the two adjacent sides of the base at the two diagonal corners of the base. The base has a constricted screwing portion, and the base has an outer dimension of the upper main surface smaller than an outer peripheral dimension of the lower surface of the frame body and a lower surface of the frame body. A package for housing a semiconductor element, wherein the package is larger than an inner peripheral dimension. 前記基体と前記枠体とは、ロウ材を介して接合されており、前記ネジ止め部は、前記付け根の上面に前記付け根の両側面間にわたって前記ロウ材を導入するための溝が、その開口の前記基体の中心側の開口縁を前記枠体の内面の下端と外面の下端との間に位置させて形成されていることを特徴とする請求項1記載の半導体素子収納用パッケージ。The base body and the frame body are joined via a brazing material, and the screwing portion has a groove for introducing the brazing material between both side surfaces of the base on the top surface of the base. 2. The package for housing a semiconductor element according to claim 1, wherein the opening edge on the center side of the base is positioned between the lower end of the inner surface of the frame body and the lower end of the outer surface. 請求項1または請求項2記載の半導体素子収納用パッケージと、前記載置部に載置固定された前記半導体素子と、前記枠体の上面に接合された蓋体とを具備したことを特徴とする半導体装置。A package for housing a semiconductor element according to claim 1, comprising: the semiconductor element placed and fixed on the placement part; and a lid joined to an upper surface of the frame. Semiconductor device.
JP2002267160A 2002-05-27 2002-09-12 Semiconductor element storage package and semiconductor device Expired - Fee Related JP3840166B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002267160A JP3840166B2 (en) 2002-05-27 2002-09-12 Semiconductor element storage package and semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002152892 2002-05-27
JP2002267160A JP3840166B2 (en) 2002-05-27 2002-09-12 Semiconductor element storage package and semiconductor device

Publications (2)

Publication Number Publication Date
JP2004056063A JP2004056063A (en) 2004-02-19
JP3840166B2 true JP3840166B2 (en) 2006-11-01

Family

ID=31948940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002267160A Expired - Fee Related JP3840166B2 (en) 2002-05-27 2002-09-12 Semiconductor element storage package and semiconductor device

Country Status (1)

Country Link
JP (1) JP3840166B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5357133B2 (en) * 2010-11-24 2013-12-04 日本電信電話株式会社 V-groove composite substrate for fiber alignment
KR101684829B1 (en) * 2016-04-21 2016-12-08 (주)스마트시스텍 Rotation angle sensor and rotary motor using it
US11372043B2 (en) * 2019-08-21 2022-06-28 Micron Technology, Inc. Heat spreaders for use in semiconductor device testing, such as burn-in testing

Also Published As

Publication number Publication date
JP2004056063A (en) 2004-02-19

Similar Documents

Publication Publication Date Title
JP4036694B2 (en) Multilayer semiconductor device
JP2007059875A (en) Heat dissipation member, electronic component storage package and electronic device using the same
JP3840166B2 (en) Semiconductor element storage package and semiconductor device
JP4822820B2 (en) Semiconductor element storage package and semiconductor device
JP2001035977A (en) Container for semiconductor device
JP4514598B2 (en) Electronic component storage package and electronic device
KR102197642B1 (en) Semiconductor device package with improved heat characteristic and method for forming the same
JP4057883B2 (en) Semiconductor element storage package and semiconductor device
JP5004837B2 (en) Structure and electronic device
JP4377769B2 (en) Electronic component storage package and electronic device
JP4608409B2 (en) High heat dissipation type electronic component storage package
US20080303127A1 (en) Cap-less package and manufacturing method thereof
JP3784346B2 (en) I / O terminal and semiconductor element storage package and semiconductor device
JP2007012718A (en) Electronic component storage package and electronic device
JP2005159251A (en) Electronic component storage package and electronic device
JP3762261B2 (en) Optical semiconductor element storage package and optical semiconductor device
JP2005056933A (en) Heat dissipation component, circuit board, and semiconductor device
JP4430477B2 (en) High heat dissipation type electronic component storage package
JP2777212B2 (en) Package for electronic components
JP4070181B2 (en) Semiconductor element storage package and semiconductor device
JP2004221327A (en) Semiconductor element storage package and semiconductor device
JP4377748B2 (en) Electronic component storage package and electronic device
JP3652255B2 (en) Package for storing semiconductor elements
JP2002246494A (en) Package for storing semiconductor elements
JP2006041287A (en) Electronic component storage package and electronic device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050309

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060718

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060725

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060804

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090811

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100811

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100811

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110811

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110811

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120811

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees