JP3834436B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit provided with a protective element for preventing electrostatic breakdown, and more particularly to a circuit capable of protecting an element when a wiring having a large stray capacitance exists inside.
[0002]
[Prior art]
The miniaturization of semiconductor integrated circuits continues to advance, and the number of integrated gates is becoming enormous. On the other hand, countermeasures against damage due to static electricity or the like become more difficult as the size becomes smaller. Since the conventional MM method (machine model) and HBM method (human body model) have insufficient correlation with the occurrence of defects on the automatic production line or in the field, devices represented by the CDM (Charged Device Model) method are used. A method of charging and discharging from each pin and testing has been proposed, and a good correlation result has been reported. Many improvements have been proposed for both the ESD protection circuit and the protection element, and it can be said that the countermeasures are almost fixed in ordinary input circuits and output circuits.
[0003]
FIG. 4 is an explanatory diagram of the CDM method. In this figure, 1 is an IC, 2 is a metal electrode, 3 is a lead (discharge terminal), 4 is an applied voltage source, SW is a switch for discharge, and Z is an equivalent impedance of an object in the discharge path.
[0004]
First, the package is charged by the applied voltage source 4 at several thousand to several tens of thousands volts, and then one lead 3 is short-circuited to the external ground potential via the switch SW and discharged. When the charging energy, that is, the charging voltage is gradually increased, eventually destruction occurs. The ESD withstand voltage is measured by the magnitude of the charging energy. In the CDM method, it is generally assumed that charging is performed on an integrated circuit board and discharged therefrom.
[0005]
Conventionally, an ESD protection element has not been added to an internal bus line or a common signal line. This is because there is no possibility that static electricity is applied to the wiring that is not connected to the external terminal, so that it is not necessary.
[0006]
[Problems to be solved by the invention]
However, it has been found that there is a structure in which the internal wiring is charged in the CDM method. That is, if there is a wiring that is indirectly connected to the substrate, there may be a discharge from the wiring. Conventionally, even with such a structure, if the discharge capability of the FET or the like in the connected actual circuit is large, the problem has not become apparent. However, when the degree of integration is increased and the number of terminals is increased, the element dimensions are inevitably reduced, and the electrostatic discharge capability and withstand voltage are lowered and the CDM method is used for destruction.
[0007]
At the same time, when the degree of integration is increased and the number of output terminals is increased, the wiring for controlling the terminals in common also becomes longer, and the stray capacitance of the wiring also increases in proportion to the area of the wiring. Incidentally, a capacitance of about 10 pF is added to a wiring having a width of 10 microns and a length of 10 mm. This is one million times as large as the gate capacitance of 0.01 × 10 ⁻³ pF of a standard 10 micron wide FET inside the integrated circuit, and is easily destroyed when discharged to this one FET. Can be done.
[0008]
In addition, in the MM method and the HBM method, static electricity is applied to two terminals and discharge occurs between the terminals, so that the discharge path can be uniquely determined. In the CDM method, however, the discharge is performed to an external ground potential that is not a part of the integrated circuit. Therefore, the discharge path is complicated and cannot be specified. If the discharge path cannot be specified, no improvement measures can be determined when there is a problem.
[0009]
As pointed out in many reports, the CDM method has excellent correlation in reproducing static electricity problems in an actual automated production line. In the case of a general input structure or output structure, the discharge path in the CDM method can be uniquely determined, and therefore measures for improving the breakdown strength can be easily considered. That is, a discharge path from the power supply wiring may be considered.
[0010]
However, when there is a wiring having a large stray capacitance in addition to the power supply, the discharge path may become an undesirable path. That is, it discharges through the elements in the actual circuit. If the discharge capacity and breakdown voltage of the element are sufficient, destruction can be avoided. However, as the degree of integration increases, the FET size of the output circuit must be optimized and minimized, and the fact that such a real circuit transistor is included in the discharge path reduces the ESD tolerance. This can lead to a decline and expose the market to vulnerabilities.
[0011]
For example, there is an example as shown in FIG. This figure is one of the conventional example in which an example LCD driver _{output, C VD, C OFD, C} OND, C P is the parasitic _{capacitance, D NS1, D ND1, D} ND2, D NS2, D PS1, D PD1, D _PD2 and D _PS2 are parasitic diodes, R _P1 is a protective resistor, P ₁ is a protective element, MN1 and MN2 are N-type MOSFETs, MP1 and MP2 are P-type MOSFETs, _PIN is a discharge terminal, and SW is a discharge switch. Show.
[0012]
V _ON is a signal for turning on the dots of the LCD and is simultaneously connected to several tens to several hundreds of MOSFETs depending on the size of the LCD panel. Therefore, a large stray capacitance is added as compared with a normal signal line. In the CDM method and the actual automated production line, after such a large internal capacity is charged, the electric discharge is instantaneously performed.
[0013]
In FIG. 2, the positive discharge path and the negative discharge path are (1) and (2), respectively, and both are discharged through MN1. At this time, if the voltage of MN1 exceeds the breakdown voltage of the gate, MN1 or MP1 is destroyed. However, although the protective element P1 is conventionally attached for the purpose of protecting the internal elements, it is a protective element for HBM and other ESD countermeasures and does not protect MN1 or MP1.
[0014]
Since MN1 and MP1 have a high breakdown voltage to drive the LCD, it is difficult to set a gate breakdown voltage (hereinafter abbreviated as a breakdown voltage) lower than the gate breakdown voltage. Incidentally, the breakdown voltage of MN1 is 30V, MP1 is 35V, the gate breakdown voltage of MN1 is 29V, and MP1 is 27V in the CMOS of 15V high breakdown voltage portion with a gate length of 2 microns. .
[0015]
As a countermeasure, it is conceivable to add a protection element between the pad and V _{ON and} between the pad and V _OFF. However, adding a protection element to all of several hundred pads increases the pad area and reduces the chip area. It is not realistic because it is very large.
[0016]
An object of the present invention is to solve the above problems and to improve the ESD withstand voltage by the CDM method.
[0017]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor integrated circuit according to the present invention is a part of an integrated circuit formed on a semiconductor substrate, and is connected to a plurality of elements in common without being connected to an external terminal. A common line connecting another terminal of the element connected to a terminal led to the outside, and an element that discharges a current between the common line and a power line or other discharge dedicated line, A breakdown voltage of an element that discharges the current is lower than a breakdown voltage of a plurality of elements connected to the common line.
[0018]
The plurality of elements are preferably MOSFETs, the common line is a bus line, and the element that discharges the current is GGNMOS.
[0019]
With such a configuration, a discharge path that does not pass through the transistor of the actual circuit is determined, and the discharge tolerance is improved.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing an embodiment of the present invention. In this figure, the same or corresponding elements as those in FIG. 2 are denoted by the same reference numerals, and P2 to P5 indicate protective elements. As shown in the figure, a protection element P2 is added between the V _ON line and the V ₅ power source, and P4 is added between the V _ON and Vdd power sources.
[0021]
P2 and P4 are, for example, low breakdown voltage GGNMOS (Gate Grounded NMOS FET), the gate length is 1.6 microns, the gate film thickness is 250 angstroms, and the breakdown voltage is about 18V.
[0022]
FIG. 3 shows an example of discharge characteristics of GGNMOS. Vsb is a snapback voltage, and a breakdown state occurs between the source and the drain. V1 becomes a voltage lower than Vsb in a state where the primary breakdown is stable. Because such a phenomenon can be utilized, GGNMOS is exclusively employed for electrostatic discharge and surge discharge and protection.
[0023]
As shown in FIG. 1, in the present embodiment, the positive discharge follows the route (1), and the V _ON line does not exceed 18V. On the other hand, the negative discharge becomes the path (2), and the voltage between Vdd and V _ON is clamped at 18 V, and the gate breakdown voltage is not exceeded.
[0024]
On the other hand, P3 and P5 are elements equivalent to P2 and P4, and P2 and P4 create a discharge path from the V _ON line, whereas they form a discharge path from the V _OFF line. That is, the alternate long and short dash line discharge paths (3) and (4) are formed in which the stray capacitance generated in the V _OFF line is released to the power supply line Vdd without passing through the transistors MN1, 2, MP1, and MP2. The case where V _OFF is positively charged is the discharge path (3), and the case where it is negatively charged is the discharge path (4).
[0025]
Although the embodiment has been described above, the present invention is not limited to this, and various modifications can be made without departing from the spirit of the invention. For example, in the above embodiment, GGNMOS is used as an element for discharging current, but any element that conducts at a specific threshold may be used, and other protective elements such as a Zener diode may be used. However, GGNMOS is more suitable for electrostatic discharge and surge electrical discharge and protection.
[0026]
In the above embodiment, an element for discharging one current is added to one bus wiring (common line). However, in the case of a particularly long wiring, not only one element but also a plurality of discharging elements are added in a distributed manner. You may do it. However, it is important to make the number sufficiently smaller than the number of terminals so as not to seriously affect the increase in chip area.
[0027]
In the above embodiment, an element for discharging current is added between the common line and the power supply line. However, a discharge wiring (discharge dedicated line) is newly provided, and this is replaced with the power supply line. You may use for.
[0028]
【The invention's effect】
The ESD withstand voltage can be improved by adding one or two or more discharge elements to a common line such as an internal bus wiring without adding an ESD protection element to all the many terminals. In the case of a long wiring, if a plurality of discharge elements are added in a dispersed manner, a further effect can be obtained.
[Brief description of the drawings]
FIG. 1 shows a circuit and a discharge path when a discharge element is added to an internal bus wiring in an embodiment of the present invention.
FIG. 2 shows a circuit, a discharge path, and a breakage point in a conventional example.
FIG. 3 shows the snapback characteristics of GGNmos.
FIG. 4 is a principle diagram of a test circuit of the CDM method.
[Explanation of symbols]
Vdd: positive power supply, V _5: negative supply, V _ON: bus signal line, V _OFF: another bus signal line, P1: protection elements are conventional, P2-P5: protection element newly provided, MN1, MN2 : NMOSFET, MP1, MP2: PMOSFET, C _VD , C _OFD , C _OND , C _P : Parasitic capacitance of MOSFET, D _NS1 , D _ND1 , D _ND2 , D _NS2 , D _PS1 , D _PD1 , D _PD2 , D _PS2 : MOSFET parasitic diode, R _P1 : Protection resistance, P _IN : Discharge terminal, SW: Switch for discharge

Claims (2)

A part of an integrated circuit formed on a semiconductor substrate, which is connected to a plurality of elements without being connected to an external terminal, and another terminal of the connected element is connected to a terminal led to the outside A common line that is connected, and an element that discharges current between the common line and a power supply line or other discharge dedicated line, and the gate breakdown voltage of the plurality of elements connected to the common line A semiconductor integrated circuit, wherein a gate breakdown voltage of an element for discharging current is lower. 2. The semiconductor integrated circuit according to claim 1, wherein the plurality of elements are MOSFETs, the common line is a bus line, and the element for discharging the current is GGNMOS.

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