JP3811164B2 - Plasma display panel - Google Patents

Description

  The present invention relates to a plasma display panel.

  FIG. 22 is a plan view schematically showing a conventional cell structure of this surface discharge type AC plasma display panel, FIG. 23 is a cross-sectional view taken along the line VV of FIG. 22, and FIG. It is sectional drawing in the WW line.

  22 to 24, on the front glass substrate 1 side serving as a display surface of a plasma display panel (hereinafter referred to as PDP), a plurality of row electrode pairs (X ′, Y ′) and a plurality of row electrode pairs are arranged on the rear surface. A dielectric layer 2 covering (X ′, Y ′) and a protective layer 3 made of MgO covering the back surface of the dielectric layer 2 are sequentially provided.

  The row electrodes X ′ and Y ′ are respectively transparent electrodes Xa ′ and Ya ′ made of a transparent conductive film such as wide ITO, and bus electrodes Xb ′ and Yb ′ made of a narrow metal film that supplements the conductivity. It consists of and.

  The row electrodes X ′ and Y ′ are alternately arranged in the column direction so as to face each other across the discharge gap g ′, and one display line for matrix display is provided by each row electrode pair (X ′, Y ′). (Row) L is configured.

  On the other hand, on the rear glass substrate 4 facing the front glass substrate 1 through the discharge space S ′ filled with a rare gas, a plurality of arrays arranged to extend in a direction perpendicular to the row electrode pairs X ′ and Y ′. The color is divided into a column electrode D ′, a strip-shaped partition wall 5 formed so as to extend in parallel between the column electrodes D ′, and R, G, B respectively covering the side surface of the partition wall 5 and the column electrode D ′. The phosphor layer 6 is provided.

  In each display line L, the column electrode D ′ and the row electrode pair (X ′, Y ′) intersect, and a discharge cell is formed in a unit light emitting region formed by dividing the discharge space S ′ by the barrier rib 5. C ′ is defined respectively.

  The display of an image in the surface discharge AC type PDP is performed as follows. That is, first, by an address operation, a discharge is selectively performed between the row electrode pair (X ′, Y ′) and the column electrode D ′ in each discharge cell C ′, and a lighting cell (dielectric layer 2 has a wall). Discharge cells C ′) in which electric charges are formed and extinguishing cells (discharge cells C ′ in which no wall charges are formed in the dielectric layer 2) are distributed on the panel corresponding to the image to be displayed.

  After this address operation, a discharge sustaining pulse is alternately applied to the row electrode pair (X ′, Y ′) all at once in all the display lines L. A surface discharge is generated.

  As described above, ultraviolet rays are generated by the surface discharge in the lighting cell, and the phosphor layers 6 of R, G, and B in the discharge space S ′ are excited to emit light, thereby forming a display screen. .

  In the plasma display panel as described above, as shown in FIG. 24, the phosphor layer 6 is also formed on the side surface of the strip-shaped partition wall 5 to increase the light emitting area in the discharge cell C ′, thereby displaying the display screen. The brightness is increased.

  However, in the above-described conventional PDP structure, when the size of each discharge cell C ′ is reduced to increase the definition of the screen, the surface area of the phosphor layer 6 is reduced accordingly, and the luminance is lowered. Problem arises.

  Furthermore, if the pitch of the row electrode pair (X ′, Y ′) is narrowed in order to cope with the high definition of the screen, discharge interference occurs in the discharge cell C ′ adjacent in the vertical direction, resulting in erroneous discharge. The problem that it becomes easy to generate | occur | produce occurs.

  Therefore, the applicant of the present invention has previously proposed a novel PDP cell structure and electrode structure as shown in FIGS. In this PDP, a plurality of row electrode pairs (X, Y) extend in the row direction of the front glass substrate 10 (left-right direction in FIG. 25) on the back surface of the front glass substrate 10 as a display surface in FIGS. Are arranged in parallel.

  The row electrode X includes a transparent electrode Xa made of a transparent conductive film such as ITO formed in a T shape, and a metal film extending in the row direction of the front glass substrate 10 and connected to a narrow base end portion of the transparent electrode Xa. It is comprised by the bus electrode Xb which consists of.

  Similarly, the row electrode Y is connected to the transparent electrode Ya made of a transparent conductive film such as ITO formed in a T-shape and the narrow base end portion of the transparent electrode Ya extending in the row direction of the front glass substrate 10. The bus electrode Yb is made of a metal film.

  The row electrodes X and Y are alternately arranged in the column direction (vertical direction in FIG. 25) of the front glass substrate 10, and the transparent electrodes Xa and Ya arranged in parallel along the bus electrodes Xb and Yb are respectively Extending to the paired row electrode side, the tops of the wide portions of the transparent electrodes Xa and Ya are opposed to each other via a discharge gap g having a required width.

  The bus electrodes Xb and Yb are respectively formed in a two-layer structure of black conductive layers Xb ′ and Yb ′ on the display surface side and main conductive layers Xb ″ and Yb ″ on the back surface side. A dielectric layer 11 is further formed on the back surface of the front glass substrate 10 so as to cover the row electrode pair (X, Y). The row electrode pairs adjacent to each other are formed on the back surface of the dielectric layer 11. A raised dielectric that protrudes on the back side of the dielectric layer 11 at a position facing the adjacent bus electrodes Xb and Yb of (X, Y) and a position facing the region between the adjacent bus electrodes Xb and Yb. The layer 11A is formed to extend in parallel with the bus electrodes Xb and Yb.

  A protective layer 12 made of MgO is formed on the back side of the dielectric layer 11 and the raised dielectric layer 11A. On the other hand, on the display side surface of the rear glass substrate 13 arranged in parallel with the front glass substrate 10, the column electrode D is connected to the transparent electrodes Xa and Ya that are paired with each other in each row electrode pair (X, Y). They are arranged in parallel at predetermined intervals so as to extend in a direction (column direction) orthogonal to the row electrode pair (X, Y) at the opposing positions.

  A white dielectric layer 14 that covers the column electrode D is further formed on the display side surface of the rear glass substrate 13, and a partition wall 15 is formed on the dielectric layer 14. The partition wall 15 is formed in a cross-like shape by a vertical wall 15a extending in the column direction at a position between the column electrodes D arranged in parallel to each other and a horizontal wall 15b extending in the row direction at a position facing the raised dielectric layer 11A. Is formed.

  And by this grid-like partition 15, the space between the front glass substrate 10 and the rear glass substrate 13 is partitioned for each portion facing the transparent electrodes Xa and Ya paired in each row electrode pair (X, Y). Thus, a rectangular discharge space S is formed.

  The partition wall 15 is formed on the display surface side, but has a two-layer structure of a black layer (light absorption layer) 15 ′ and a white layer (light reflection layer) 15 ″ on the back side. The side wall surface that faces is substantially white (that is, a light reflection layer).

  The display side surface of the vertical wall 15a of the partition wall 15 is not in contact with the protective layer 12 (see FIG. 28), and a gap r is formed between them, but the display side surface of the horizontal wall 15b is the protective layer. 12 are in contact with the portion covering the raised dielectric layer 11A (see FIGS. 26 and 27), and are shielded from the adjacent discharge spaces S in the column direction.

  On the side surfaces of the vertical wall 15a and the horizontal wall 15b of the partition wall 15 facing the discharge space S and the surface of the dielectric layer 14, the phosphor layers 16 are sequentially formed so as to cover all five surfaces. The color of the phosphor layer 16 is set so that the colors of R, G, and B are arranged in order in the row direction for each discharge space S. And in the discharge space S, rare gas is enclosed.

  In this PDP, each row electrode pair (X, Y) constitutes one display line (row) L of the matrix display screen, and each discharge space S partitioned by the grid-like barrier ribs 15 is one discharge cell. C is defined. In the image display in this PDP, as in the PDP in FIGS. 22 to 24, first, all display lines L are turned on by selective discharge between the row electrode pair (X, Y) and the column electrode D by the address operation. The cells and the unlit cells are distributed on the panel corresponding to the image to be displayed, and thereafter, the discharge sustaining pulse is alternately applied to the row electrode pair (X, Y) simultaneously in all the display lines L. Thus, a surface discharge is generated in each lighting cell.

  Then, ultraviolet rays are generated by the surface discharge in the lighting cell, and the R, G, B phosphor layers 16 in the discharge space S are excited to emit light, thereby forming a display screen.

  In the PDP, in each discharge cell C, the phosphor layer 16 is formed on the four side walls of the partition wall 15 facing the discharge space S and the display side surface of the dielectric layer 14 covering the column electrode D. As a result, the surface area, that is, the light emitting area of the phosphor layer 16 is enlarged as compared with the PDP shown in FIGS. 22 to 24. Therefore, the luminance per discharge cell C is increased, and the luminance of the display screen is increased. On the other hand, it has a feature that the brightness of the display screen does not decrease compared with the conventional one even if the size of each discharge cell C is reduced in order to increase the definition of the screen. Yes.

  Further, the transparent electrodes Xa and Ya of the row electrodes X and Y extend from the bus electrodes Xb and Yb to the paired row electrode side, and are configured to be island-like for each discharge cell C. Therefore, even if the size of each discharge cell C is reduced in order to increase the definition of the screen, there is no possibility that interference of discharge to the adjacent discharge cells C in the display line L direction (horizontal direction) occurs. It has.

  Furthermore, a raised dielectric layer 11A is formed on the dielectric layer 11, and the protective layer 12 covering the raised dielectric layer 11A is brought into contact with the display side surface of the lateral wall 15b of the partition wall 15 so as to be arranged in the column direction (vertical direction). ), The discharge spaces S of adjacent discharge cells C are shielded from each other (see FIGS. 26 and 27), thereby preventing discharge interference between adjacent discharge cells C in the column direction. Thus, the display side surface of the vertical wall 15a of the partition wall 15 is opposed to the portion of the dielectric layer 11 where the raised dielectric layer 11A is not formed, and the display side surface of the vertical wall 15a and the protective layer 12 are provided. (See FIGS. 28 and 29), the discharge spaces S of the discharge cells C adjacent to each other in the row direction (display line direction) are slightly connected via the gap r. Discharge Priming effect to cause a chain reaction occurs, and a feature that can be stabilized in the discharge operation.

  Further, this PDP has black conductive layers Xb ′ and Yb ′ provided on the display surface side of the bus electrodes Xb and Yb, respectively, and a black layer 15 ′ formed on the display side surface of the partition wall 15. The liquid crystal display device has various features such as preventing reflection of external light incident through the front glass substrate 10 and improving the contrast of the display screen.

  However, as can be seen from FIG. 25, the vertical wall 15a of the partition wall 15 defining the discharge space S is formed so that its width becomes as small as possible in order to increase the area of the discharge space S, whereas the horizontal wall The width of 15b must be wider than the width of the vertical wall 15a in order to secure the installation space for the bus electrodes Xb and Yb.

  For this reason, due to the difference in the width between the vertical wall 15a and the horizontal wall 15b of the partition wall 15, the shrinkage at the time of firing occurs, thereby causing warpage of the front glass substrate 10 and the back glass substrate 13, damage to the partition wall 15, etc. There is a new problem that causes deformation of the discharge cell shape.

  As described above, an object of the present invention is to solve a problem peculiar to a plasma display panel proposed to cope with high definition without causing a decrease in luminance in each unit light emitting region.

  That is, the present invention provides a cross beam that divides a discharge space in a row direction and a column direction for each unit light emitting region by a vertical wall portion that is disposed between a front substrate and a back substrate and extends in a column direction and a horizontal wall portion that extends in a row direction The phosphor layer is formed on the side surfaces of the vertical wall portion and the horizontal wall portion and the surface of the dielectric layer corresponding to the bottom surface of the discharge space partitioned by the vertical wall portion and the horizontal wall portion. The purpose of the plasma display panel is to prevent the shape of the discharge cell from being deformed due to warpage of the substrate or damage to the barrier ribs.

  In order to achieve such an object, the plasma display panel according to the present invention comprises at least the configuration according to the following independent claims.

[Claim 1] A plurality of row electrode pairs that extend in the row direction and are arranged in parallel in the column direction to form display lines, respectively, and a first dielectric layer that covers the row electrode pairs are provided on the back side of the front substrate. A plurality of unit light-emitting regions are formed in the discharge space at positions where the back substrate extends in the column direction and is juxtaposed in the row direction and intersects the row electrode pairs on the side facing the front substrate through the discharge space. In a plasma display panel provided with a column electrode and a second dielectric layer covering the column electrode, a vertical wall portion and a row are arranged between the front substrate and the back substrate and extend in the column direction. A partition wall that divides the discharge space in a row direction and a column direction for each unit light emitting region by a lateral wall portion extending in a direction, and the unit light emitting region is between and between the row electrode pair and the column electrode. No discharge between row electrodes In addition, a phosphor layer is formed on the side surfaces of the vertical wall portion and the horizontal wall portion constituting the unit light emitting region and on the surface of the second dielectric layer, and the pair of row electrodes are respectively arranged in the row direction. Between the unit light emitting areas arranged in rows adjacent to each other, and a main body extending in the column direction and projecting in the column direction and facing each other through a discharge gap for each unit light emitting area The plasma display panel is characterized in that the horizontal wall portions of the plasma display panel are separated by a gap parallel to the row direction, and discharge occurs only in the unit light emitting region in the discharge space .

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments that are considered to be most suitable for the present invention will be described in detail below with reference to the drawings.

  1 to 5 show a first example of an embodiment of a plasma display panel (hereinafter referred to as PDP) according to the present invention, and FIG. 1 is a plan view schematically showing the PDP in the first example. 2 is a sectional view taken along line V3-V3 in FIG. 1, FIG. 3 is a sectional view taken along line V4-V4 in FIG. 1, FIG. 4 is a sectional view taken along line W3-W3 in FIG. It is sectional drawing in line W4-W4.

  In the PDP shown in FIGS. 1 to 5, a plurality of row electrode pairs (X, Y) are arranged in the row direction of the front glass substrate 10 (left and right direction in FIG. 1) on the back surface of the front glass substrate 10 which is a display surface. They are arranged in parallel so as to extend. The row electrode X includes a transparent electrode Xa made of a transparent conductive film such as ITO formed in a T shape, and a metal film extending in the row direction of the front glass substrate 10 and connected to a narrow base end portion of the transparent electrode Xa. It is comprised by the bus electrode Xb which consists of.

  Similarly, the row electrode Y is connected to the transparent electrode Ya made of a transparent conductive film such as ITO formed in a T-shape and the narrow base end portion of the transparent electrode Ya extending in the row direction of the front glass substrate 10. The bus electrode Yb is made of a metal film.

  The row electrodes X and Y are alternately arranged in the column direction (vertical direction in FIG. 1) of the front glass substrate 10, and the transparent electrodes Xa and Ya arranged in parallel along the bus electrodes Xb and Yb are respectively Extending to the paired row electrode side, the tops of the wide portions of the transparent electrodes Xa and Ya are opposed to each other via a discharge gap g having a required width.

  The bus electrodes Xb and Yb are respectively formed in a two-layer structure of black conductive layers Xb ′ and Yb ′ on the display surface side and main conductive layers Xb ″ and Yb ″ on the back surface side. On the back surface of the front glass substrate 10, a row direction along the bus electrodes Xb and Yb is provided between the bus electrodes Xb and Yb of the row electrode pairs (X, Y) adjacent to each other in the column direction. A black light absorption layer (light-shielding layer) 30 extending in the direction is formed, and a light absorption layer (light-shielding layer) 31 is formed in a portion facing the vertical wall 35 a of the partition wall 35.

  A dielectric layer 11 (first dielectric layer) is further formed on the back surface of the front glass substrate 10 so as to cover the row electrode pair (X, Y). Of the dielectric layer 11 at a position facing the adjacent bus electrodes Xb and Yb of the adjacent row electrode pair (X, Y) and a position facing the region between the adjacent bus electrodes Xb and the bus electrodes Yb. A raised dielectric layer 11A protruding to the back side is formed so as to extend in parallel with the bus electrodes Xb and Yb.

  A protective layer 12 made of MgO is formed on the back side of the dielectric layer 11 and the raised dielectric layer 11A. On the other hand, on the display side surface of the rear glass substrate 13 arranged in parallel with the front glass substrate 10, the column electrode D is connected to the transparent electrodes Xa and Ya that are paired with each other in each row electrode pair (X, Y). They are arranged in parallel at predetermined intervals so as to extend in a direction (column direction) orthogonal to the row electrode pair (X, Y) at the opposing positions. A white dielectric layer 14 (second dielectric layer) covering the column electrode D is further formed on the display side surface of the rear glass substrate 13, and a partition wall 35 is formed on the dielectric layer 14. Is formed.

  The partition wall 35 is formed in a ladder shape by a vertical wall 35a extending in the column direction at a position between the column electrodes D arranged in parallel with each other and a horizontal wall 35b extending in the row direction at a position facing the raised dielectric layer 11A. Has been. And by this ladder-shaped partition wall 35, the space between the front glass substrate 10 and the rear glass substrate 13 is divided for each portion facing the transparent electrodes Xa and Ya paired in each row electrode pair (X, Y). Thus, a rectangular discharge space S is formed.

  The display side surface of the vertical wall 35a of the partition wall 35 is not in contact with the protective layer 12 (see FIG. 4), and a gap r is formed between them, but the display side surface of the horizontal wall 35b is the protective layer. 12 are in contact with the portion covering the raised dielectric layer 11A (see FIGS. 2 and 5), and are shielded from the adjacent discharge spaces S in the column direction.

  On the side surfaces of the vertical and horizontal walls 35a and 35b of the partition wall 35 facing the discharge space S and the surface of the dielectric layer 14, the phosphor layers 16 are formed in order so as to cover all five surfaces.

  The color of the phosphor layer 16 is set so that the colors of R, G, and B are sequentially arranged in the row direction for each discharge space S (see FIG. 4). And in the discharge space S, rare gas is enclosed. The horizontal wall 35b of the partition wall 35 that partitions the discharge space S is separated in the column direction by a gap SL provided at a position overlapping the light absorption layer 30 between the display lines.

  That is, the partition walls 35 are formed in a ladder shape along the display line (row) L direction, and are arranged so as to be parallel to each other via a gap SL extending along the display line L in the column direction. The width of the gap SL is set so that the width of each portion 35b ′ of the horizontal wall 35b divided by the gap SL provided between the display lines L is substantially the same as the width of the vertical wall 35a.

  In the above PDP, each row electrode pair (X, Y) constitutes one display line (row) L of the matrix display screen, and each discharge space S partitioned by the ladder-shaped partition walls 35 has one discharge. Cell C is defined.

  In the image display in this PDP, first, discharge is selectively performed between the row electrode pair (X, Y) and the column electrode D in each discharge cell C by an address operation, and the lighted cells ( Discharge cells C in which wall charges are formed on the dielectric layer 11) and extinguishing cells (discharge cells C in which wall charges are not formed on the dielectric layer 11) are distributed on the panel corresponding to the image to be displayed. Is done.

  After this address operation, discharge sustain pulses are alternately applied to the row electrode pairs (X, Y) simultaneously on all the display lines L. Each time this discharge sustain pulse is applied, the surface of each lighting cell is turned on. A discharge is generated.

  As described above, ultraviolet rays are generated by the surface discharge in the lighting cell, and the phosphor layers 16 of R, G, and B in the discharge space S are excited to emit light, thereby forming a display screen. The PDP separates the horizontal wall 35b of the partition wall 35 partitioning the discharge space S in the column direction by the gap SL provided between the display lines L, and the width of each of the separated portions 35b ′ is respectively set to the vertical wall 35a. By setting it to be substantially the same as the width, variation in shrinkage during firing of the barrier ribs 35 is reduced, and thereby the discharge cell shape due to warpage of the front glass substrate 10 and the rear glass substrate 13 and breakage of the barrier ribs 35, etc. There is no risk of deformation.

  Further, in the PDP, the portions other than the portion facing the discharge space S on the back surface of the front glass substrate 10 are the light absorbing layers 30 and 31 and the black conductive layer Xb ′ of the bus electrodes Xb and Yb formed in a two-layer structure. , Yb ′ can prevent external light incident through the front glass substrate 10 from being reflected and improve the contrast of the display screen.

In this example, only one of the light absorption layers 30 and 31 may be formed. Further, a color filter layer (not shown) of a color corresponding to the color (R, G, B) of the phosphor layer 16 in the opposing discharge space S is provided on the back surface of the front glass substrate 10 for each discharge cell C. It can also be formed.
In this case, the light absorption layers 30 and 31 are formed in gaps between the color filter layers formed in an island shape so as to face the respective discharge spaces S or at positions corresponding to the gaps.

    Next, a second example in the embodiment of the present invention will be described with reference to FIGS. 6 is a plan view schematically showing the PDP of the second example, FIG. 7 is a cross-sectional view taken along line V5-V5 in FIG. 6, and FIG. 8 is a cross-sectional view taken along line V6-V6 in FIG.

  In the PDP shown in FIGS. 6 to 8, row electrode pairs (Xo, Yo) are arranged on the back surface of the front glass substrate 10 in the same manner as the PDP of the first example of FIGS. Further, on the back surface of the front glass substrate 10, a black light absorption layer (light-shielding layer) 40 is formed on all of the portions facing the display side surface of the ladder-shaped partition walls 35 and the gap SL.

  The bus electrodes Xob and Yob of the row electrodes Xo and Yo are formed in a single-layer structure having only the main conductive layer, and are arranged so as to be positioned on the back surface of the light absorption layer (light shielding layer) 40. The other structure is the same as that of the first embodiment shown in FIGS. 1 to 5, and the horizontal wall 35b of the partition wall 35 that partitions the discharge space S is separated in the column direction by the gap SL provided between the display lines L. The width of each portion 35b ′ of the separated horizontal wall 35b is substantially the same as the width of the vertical wall 35a.

  In the PDP as well, as in the example of FIGS. 1 to 5, the width of each portion 35b ′ separated in the column direction by the gap SL is substantially the same as the width of the vertical wall 35a. Thus, there is no possibility that the discharge cell shape is deformed due to warpage of the front glass substrate 10 and the rear glass substrate 13 and damage to the partition walls 35.

  Furthermore, this PDP is covered with a light absorbing layer (light-shielding layer) 40 except for the portion facing the discharge space S on the back surface of the front glass substrate 10, so It is possible to improve the contrast of the display screen by preventing light from being reflected.

  Next, the 3rd example in embodiment of this invention is demonstrated based on FIG. FIG. 9 is a plan view schematically showing the relationship between the row electrode pairs of the PDP and the partition walls in the third example.

  In the PDP of the third example, the display electrodes Li-1 ′, Li ′, Li + 1 ′... Arranged in the column direction have row electrodes (Yi-1 ′, Xi-1 ″), ( Xi ′, Yi ′), (Yi + 1 ′, Xi + 1 ′)... Are alternately arranged for each display line, and are back to back in adjacent display lines. The base electrodes of the transparent electrodes Xai-1 ′ and Xai ′ of the row electrodes Xi-1 ′ and Xi ′ arranged in the same are connected and formed integrally, and the row electrodes Yi ′ and Yi + 1 ′ are further formed. The base ends of the transparent electrodes Yai ′ and Yai + 1 ′ are connected and integrally formed.

  With the above arrangement, the transparent electrodes Xai-1 ′ and Xai ′ of the row electrodes Xi-1 ′ and Xi ′ arranged back to back in the display lines adjacent in the column direction are connected to the common bus electrode Xbj. Further, in the display lines adjacent to each other in the column direction, the transparent electrodes Yai ′ and Yai + 1 ′ of the row electrodes Yi ′ and Yi + 1 ′ arranged back to back with each other are connected to a common bus. It is connected to the electrode Ybj ′.

  Also in this example, as in the first and second examples described above, the horizontal wall 35b of the partition wall 35 partitioning the discharge space S is separated in the column direction by a gap provided between the display lines L. The width of each portion 35b ′ of the horizontal wall 35b is substantially the same as the width of the vertical wall 35a.

  Also in the PDP, since the width of each portion 35b 'separated in the column direction by the gap SL is the same as the width of the vertical wall 35a, there is less variation in shrinkage during firing of the partition wall 35, thereby There is no possibility of deformation of the discharge cell shape due to warpage of the front glass substrate or the rear glass substrate and damage to the partition walls 35.

  Further, in this PDP, row electrodes Xi ′ and Xi + 1 ′ arranged back to back in adjacent display lines share the bus electrode Xbj ′, and further, row electrodes Yi arranged back to back with each other. '' And Yi + 1 ′ share the bus electrode Ybj ′, so that the installation area of the bus electrodes Xbj ′ and Ybj ′ is further smaller than the installation area of the bus electrode of the PDP of FIGS. Become.

  Accordingly, the width of the horizontal wall 25b ′ of the partition wall 25 ′ facing the bus electrodes Xbj ′ and Ybj ′ can be further reduced as compared with the PDP of FIGS. 1 to 5, respectively, and the volume of the discharge space S1 ′ is increased accordingly. Since the surface area of the phosphor layer formed in the discharge space S1 ′ can be further increased, the luminance of the display screen is increased.

  Further, the discharge current can be reduced by sharing the bus electrodes Xbj ′ and Ybj ′. Here, each of the bus electrodes Xbj ′ and Ybj ′ has two layers of a black conductive layer and a main conductive layer, or the bus electrodes Xbj ′ and Ybj ′ have a single layer structure, and the bus electrodes Xbj ′ and Ybj ′ By forming a black light absorption layer so as to be located on the front side of the bus electrodes Xbj ′ and Ybj ′ between the front glass substrate and the outside light incident through the front glass substrate is prevented from being reflected. Thus, the contrast of the display screen can be improved.

  Next, a fourth example in the embodiment of the present invention will be described with reference to FIG. FIG. 10 is a plan view schematically showing the relationship between the row electrode pairs of the PDP and the partition walls in the fourth example. In the PDP of the fourth example, the row electrodes X and Y of the PDP in the first example of FIGS. 1 to 5 are alternately arranged in the column direction, whereas the display lines Li, In Li + 1..., The row electrodes are arranged in such a manner that their arrangement is alternately changed for each display line, such as (Yi, Xi), (Xi + 1, Yi + 1).

  With the arrangement described above, the row electrodes Xi arranged back-to-back with the row electrode pairs (Yi, Xi) and (Xi + 1, Yi + 1) in the display lines Li, Li + 1 adjacent in the column direction. Each transparent electrode Xai and Xai + 1 of Xi + 1 is connected to a common bus electrode Xbj.

  Also in this example, similarly to the above-described examples, the horizontal walls 45b1 and 45b2 of the partition wall 45 that divides the discharge space S are separated in the column direction by the gaps SL1 and SL2 provided between the display lines L, and this gap SL1. The widths of the portions 45b1 ′ and 45b2 ′ of the horizontal walls 45b1 and 45b2 separated by SL2 are substantially the same as the width of the vertical wall 45a.

  Also in the PDP, the widths of the portions 45b1 ′ and 45b2 ′ of the horizontal walls 45b1 and 45b2 separated in the column direction by the gaps SL1 and SL2 are substantially the same as the width of the vertical wall 45a. There is less variation in the shrinkage at the time, and there is no risk of deformation of the discharge cell shape due to warpage of the front glass substrate or the back glass substrate and damage to the partition walls 45.

  Further, in the PDP in the fourth example, the row electrodes Xi and Xi + 1 arranged back to back in the adjacent display lines share the bus electrode Xbj, and the installation area of the bus electrode Xbj is small. Become. Therefore, the width of the horizontal wall 45b1 of the partition wall 45 facing the bus electrode Xbj can be reduced, and the volume of the discharge space S1 is increased correspondingly to increase the surface area of the phosphor layer formed in the discharge space S1. The brightness of the display screen is increased. Further, the discharge current can be reduced by sharing the bus electrode Xbj.

  Next, a fifth example of the embodiment of the present invention will be described with reference to FIGS. 11 is a plan view schematically showing the PDP in the fifth example, FIG. 12 is a cross-sectional view taken along the line V7-V7 in FIG. 11, and FIG. 13 is a cross-sectional view taken along the line V8-V8 in FIG. 14 is a cross-sectional view taken along line W7-W7 in FIG. 11, and FIG. 15 is a cross-sectional view taken along line W8-W8 in FIG.

  In the PDP shown in FIGS. 11 to 15, a plurality of row electrode pairs (X, Y) are arranged in the row direction of the front glass substrate 10 (left and right direction in FIG. 11) on the back surface of the front glass substrate 10 which is a display surface. They are arranged in parallel so as to extend. The row electrode X includes a transparent electrode Xa made of a transparent conductive film such as ITO formed in a T shape, and a metal film extending in the row direction of the front glass substrate 10 and connected to a narrow base end portion of the transparent electrode Xa. It is comprised by the bus electrode Xb which consists of.

  Similarly, the row electrode Y is connected to the transparent electrode Ya made of a transparent conductive film such as ITO formed in a T-shape and the narrow base end portion of the transparent electrode Ya extending in the row direction of the front glass substrate 10. The bus electrode Yb is made of a metal film. The row electrodes X and Y are alternately arranged in the column direction (vertical direction in FIG. 11) of the front glass substrate 10, and the transparent electrodes Xa and Ya arranged in parallel along the bus electrodes Xb and Yb are respectively Extending to the paired row electrode side, the tops of the wide portions of the transparent electrodes Xa and Ya are opposed to each other via a discharge gap g having a required width.

  The bus electrodes Xb and Yb are respectively formed in a two-layer structure of black conductive layers Xb ′ and Yb ′ on the display surface side and main conductive layers Xb ″ and Yb ″ on the back surface side. On the back surface of the front glass substrate 10, a row direction along the bus electrodes Xb and Yb is provided between the bus electrodes Xb and Yb of the row electrode pairs (X, Y) adjacent to each other in the column direction. A black light absorption layer (light-shielding layer) 30 is formed, and a light absorption layer (light-shielding layer) 31 is formed at a portion facing the vertical wall 35a of the ladder-shaped partition wall 35. The above configuration is substantially the same as the structure of the PDP in the first example.

  A dielectric layer 61 is further formed on the back surface of the front glass substrate 10 so as to cover the row electrode pair (X, Y). The dielectric layer 61 does not have a configuration corresponding to the raised dielectric layer of the first example. On the back side of the dielectric layer 61, a protective layer 62 made of MgO is formed.

  On the other hand, on the display side surface of the rear glass substrate 13 arranged in parallel with the front glass substrate 10, the column electrode D is connected to the transparent electrodes Xa and Ya that are paired with each other in each row electrode pair (X, Y). They are arranged in parallel at predetermined intervals so as to extend in a direction (column direction) orthogonal to the row electrode pair (X, Y) at the opposing positions. A white dielectric layer 14 that covers the column electrodes D is further formed on the display side surface of the rear glass substrate 13, and a partition wall 65 is formed on the dielectric layer 14.

  The partition wall 65 is formed in a ladder shape by a vertical wall 65a extending in the column direction and a horizontal wall 65b extending in the row direction at positions between the column electrodes D arranged in parallel to each other, and the surface thereof is a protective layer. 62 is in contact with the back side.

  And by this ladder-shaped partition wall 65, the space between the front glass substrate 10 and the rear glass substrate 13 is divided for each portion facing the transparent electrodes Xa and Ya paired in each row electrode pair (X, Y). Thus, a rectangular discharge space S is formed.

  A slit sl that allows the adjacent discharge space S to communicate is formed in the vertical wall 65a of the partition wall 65 that partitions the discharge space S. Further, the horizontal wall 65b of the partition wall 65 is separated in the column direction by a gap SL provided at a position facing the light absorption layer 30 between the display lines L. The width of the slit SL is set so that the width of each portion 65b ′ of the horizontal wall 65b separated by the gap SL is substantially the same as the width of the vertical wall 65a.

  On the side surfaces of the vertical wall 65a and the horizontal wall 65b of the partition wall 65 facing the discharge space S and the surface of the dielectric layer 14, the phosphor layers 16 are sequentially formed so as to cover all five surfaces.

  The color of the phosphor layer 16 is set so that the colors of R, G, and B are sequentially arranged in the row direction for each discharge space S (see FIG. 14). A discharge gas is sealed in the discharge space S. In the above PDP, each row electrode pair (X, Y) constitutes one display line (row) L of the matrix display screen, and each discharge space S partitioned by the ladder-shaped partition walls 35 has one discharge. Cell C is defined.

  In the image display in this PDP, first, discharge is selectively performed between the row electrode pair (X, Y) and the column electrode D in each discharge cell C by an address operation, and the lighted cells ( Discharge cells C in which wall charges are formed on the dielectric layer 11) and extinguishing cells (discharge cells C in which wall charges are not formed on the dielectric layer 11) are distributed on the panel corresponding to the image to be displayed. Is done.

  After this address operation, discharge sustain pulses are alternately applied to the row electrode pairs (X, Y) simultaneously on all the display lines L. Each time this discharge sustain pulse is applied, the surface of each lighting cell is turned on. A discharge is generated.

As described above, ultraviolet rays are generated by the surface discharge in the lighting cell, and the phosphor layers 16 of R, G, and B in the discharge space S are excited to emit light, thereby forming a display screen.

  In the PDP, the surface of the partition wall 65 is in contact with the back surface of the protective layer 62 to shield the discharge space S. However, the discharge spaces S adjacent to each other are communicated by the slits sl formed in the vertical wall 65a. Thus, the enclosed discharge gas and priming particles can be moved to the adjacent discharge space S, whereby discharge is performed in a chain between adjacent discharge cells C.

  Further, the horizontal wall 65b of the partition wall 65 partitioning the discharge space S is separated in the column direction by the gap SL, and the width of each separated portion 65b ′ is set to be substantially the same as the width of the vertical wall 65a. Therefore, there is less variation in the shrinkage during firing of the barrier ribs 65, and there is no possibility of deformation of the discharge cell shape due to warpage of the front glass substrate 10 or the rear glass substrate 13 and damage of the barrier ribs 65.

  Next, a sixth example of the embodiment of the present invention will be described with reference to FIG. In the PDP according to the sixth example, the slits communicating with the discharge spaces S adjacent to each other in the PDP of the fifth example are formed in the vertical wall of the partition wall, whereas the transparent electrode Xa on the horizontal wall 65b of the partition wall 65 is used. , Ya and the bus electrodes Xb, Yb are formed at a position different from the position where the bus electrodes Xb, Yb are overlapped, and the discharge spaces S adjacent to each other in the column direction are communicated with each other. Other configurations are the same as those of the PDP of the fifth example.

  The slit sl ′ is provided at a position different from the position where the transparent electrodes Xa, Ya and the bus electrodes Xb, Yb overlap each other on the horizontal wall 65b of the partition wall 65, and is spread by the horizontal wall 65b of the partition wall 65. It is because it is suppressing. In each of the first to sixth examples, an example in which the ladder-shaped partition wall has a white single layer structure is shown, but at least the vertical wall portion has a two-layer structure in which the front side is a black layer and the back side is a white layer. May be. Furthermore, in each example, the black conductive layer and the light absorbing layer of the bus electrode having a two-layer structure may be colored in a dark color that absorbs light such as dark brown in addition to black.

  Next, a seventh example of the embodiment of the present invention will be described with reference to FIG. FIG. 17 is a plan view schematically showing a configuration of a pixel constituted by three discharge cells C color-coded into three colors of RGB in the seventh example PDP. In FIG. 17, the discharge cells C partitioned by the ladder-shaped barrier ribs 15A are arranged linearly in the column direction, and the column electrodes DA are formed linearly.

  The color of the phosphor layer of each discharge cell C is set so as to be arranged in the order of R, G, B in the display line L direction (row direction), and further, a direction perpendicular to the display line L direction. The discharge cells C of the same color are arranged in the (column direction).

  In the PDP in this example, as shown in the figure, one pixel GA is constituted by three discharge cells C of R, G, and B arranged in the display line L direction. Therefore, the pixel GA is linear on the column direction. Arranged.

  The horizontal wall 15Ab of the partition wall 15A is separated by a gap SL provided between the display lines L, and the width of each separated portion 15Ab ′ is set to be substantially the same as the width of the vertical wall 15Aa. Therefore, there is less variation in shrinkage during firing of the barrier ribs 15A, and there is no risk of deformation of the discharge cell shape due to warpage of the front glass substrate and rear glass substrate constituting the PDP and damage to the barrier ribs 15A. .

  Next, an eighth example of the embodiment of the present invention will be described with reference to FIG. FIG. 18 is a plan view schematically showing the configuration of a pixel constituted by three discharge cells C color-coded into three colors of RGB in the PDP of the eighth example. In FIG. 18, discharge cells C are partitioned by ladder-shaped barrier ribs 15B and arranged linearly in the column direction as in the case of the seventh example described above, and column electrodes DB are also formed linearly. However, the colors of R, G, and B of the phosphor layers of each discharge cell C are set so that the two adjacent display lines L in the column direction are shifted one by one in the display line L direction.

  As shown in the figure, one pixel GB is constituted by three discharge cells C of R, G, and B arranged in the display line L direction. Therefore, the pixel GB is composed of two display lines adjacent in the column direction. In L, the discharge cells C are arranged so as to be shifted one by one in the display line L direction.

  The PDP in this example can improve the resolution of the display screen by arranging the pixels GB so that the discharge cells C are shifted one by one for each display line L as described above. The horizontal wall 15Bb of the partition wall 15B is separated in the column direction by the gap SL provided between the display lines L, and the width of each of the separated portions 15Bb ′ is substantially the same as the width of the vertical wall 15Ba. Therefore, there is less variation in shrinkage during firing of the barrier ribs 15B, and this causes deformation of the discharge cell shape due to warpage of the front glass substrate and the rear glass substrate constituting the PDP and damage to the barrier ribs 15B. There is no fear.

  Next, a ninth example of the embodiment of the present invention will be described with reference to FIG. FIG. 19 is a plan view schematically showing a configuration of a pixel constituted by three discharge cells C that are color-coded into three colors of RGB in the ninth example PDP. In FIG. 19, the discharge cells C arranged in two display lines L adjacent in the column direction are shifted from each other in the display line L direction by a half of the dimension in the width direction of the discharge cells C by a ladder-shaped partition wall 15C. It is divided into.

  The colors of R, G, and B of the phosphor layers of each discharge cell C are the same in the discharge cells C arranged so as to be shifted in the display line L direction by half each of the two adjacent display lines L in the column direction. It is set to be. For this reason, the column electrode DC is formed in a zigzag-shaped shape corresponding to the discharge cells C arranged so as to be shifted by half in the two display lines L adjacent in the column direction in the display line L direction. .

  As shown in the figure, one pixel GC is constituted by three discharge cells C of R, G, and B arranged in the display line L direction. Therefore, the pixel GC is composed of two display lines adjacent in the column direction. In L, the discharge cells C are arranged so as to be shifted from each other in the direction of the display line L by half.

  In the PDP in this example, the resolution of the display screen can be improved by arranging the pixels GC such that the discharge cells C are shifted by half for each display line L as described above. Then, the ladder-like partition wall 15C is separated in the column direction by the gap SL provided between the display lines L, and the width of each of the separated portions 15Cb ′ is substantially the same as the width of the vertical wall 15Ca. Therefore, there is less variation in shrinkage during firing of the barrier ribs 15C, and this causes deformation of the discharge cell shape due to warpage of the front glass substrate and the rear glass substrate constituting the PDP and damage to the barrier ribs 15C. There is no fear.

  Next, a tenth example of the embodiment of the present invention will be described with reference to FIG. FIG. 20 is a plan view schematically showing the configuration of a pixel constituted by three discharge cells C color-coded into three colors of RGB in the PDP of the tenth example. In FIG. 20, the discharge cells C arranged in two display lines L adjacent in the column direction are separated from each other by half of the widthwise dimension of the discharge cells C by the barrier ribs 15D, as in the ninth example. It is partitioned so as to be shifted in the display line L direction.

  The colors of R, G, and B of the phosphor layers of each discharge cell C are 1.5 times larger than the width of the discharge cell C in the display line L adjacent in the column direction. It is set to shift to For this reason, the column electrode DD has a shape that bends in a zigzag manner corresponding to the discharge cells C arranged so as to be shifted in the display line L direction by half of the width direction in two display lines L adjacent in the column direction. Is formed.

  As shown in the figure, one pixel GD is constituted by three discharge cells C of R, G, and B positioned in a delta shape across two display lines L adjacent in the column direction.

  The PDP in this example can improve the resolution of the display screen by including three discharge cells C in which one pixel GD is positioned in a delta shape as described above. Ladder-shaped partition walls 15D are arranged so as to be parallel to each other via a gap SL provided between the display lines L. The width of each portion 15Db ′ of each horizontal wall 15Db is equal to the width of each vertical wall 15Da. Since they are set so as to be substantially the same, there is less variation in shrinkage during firing of the barrier ribs 15D, thereby causing discharge cells due to warpage of the front glass substrate and rear glass substrate constituting the PDP and damage to the barrier ribs 15D. There is no risk of shape deformation.

  FIG. 21 shows the shape and arrangement of the partition walls in the examples of FIGS. The partition walls 15A partition discharge spaces so that the discharge cells C are arranged in a row by vertical walls 15Aa and horizontal walls 15Ab each formed in a ladder shape. The partition walls 15A are arranged in the column direction so that the partition walls 15A extend in parallel with each other along the display line L, and the side walls 15Ab of the partition walls 15A adjacent to each other face each other with the gap SL therebetween.

  The discharge cells C ′ located at the right end and the left end of the partition wall 15A are dummy cells. Then, chamfers 15Ac are applied to the outer corners of the partition wall 15A partitioning the dummy cell C ′. The chamfer 15Ac may be linear as shown in the figure or may be curved.

  The chamfer 15Ac is for preventing the corner of the partition wall 15A from rising. That is, if the corner portion of the partition wall 15A is raised, when the front substrate and the rear substrate are overlapped, the front substrate contacts only the raised portion (that is, the peripheral portion of the substrate) and the other portion (center portion) is Since the substrate is in a floating state, vibration is generated in the substrate when the plasma display panel is driven, and vibration noise is generated. However, the chamfer 15Ac provided at the corner of the partition wall 15A prevents the swell, thereby preventing the substrate and the partition wall 15A. Are uniformly in contact with each other, and the occurrence of vibration as described above is prevented.

  The characteristics of the invention according to the embodiment of the present invention are summarized as follows.

  For example, a plurality of row electrode pairs X and Y that extend in the row direction and are arranged in parallel in the column direction on the back side of the front substrate (front glass substrate 10) to form display lines, respectively, and the row electrode pairs are covered. The first dielectric layer 11 is disposed on the side of the rear substrate (rear glass substrate 13) facing the front substrate through the discharge space S. The first dielectric layer 11 extends in the column direction and is arranged in parallel in the row direction. In the plasma display panel provided with a plurality of column electrodes D constituting unit light-emitting regions in the discharge space at positions intersecting with the pair, and a second dielectric layer 14 covering the column electrodes, A partition that is disposed between the rear substrate and the vertical wall 35a extending in the column direction and the horizontal wall 35b extending in the row direction partition the discharge space in the row direction and the column direction for each unit light emitting region, Vertical wall and front A phosphor layer is formed on a side surface of the lateral wall portion and on the surface of the second dielectric layer, and the pair of row electrodes are respectively extended to the main body portions Xb and Yb extending in the row direction and from the main body portion. Each of the unit light emitting regions has a protruding portion Xa, Ya facing each other through a discharge gap g, and a horizontal wall portion between the unit light emitting regions arranged along adjacent rows is a row direction. They are separated by parallel gaps SL.

  In this plasma display panel, a discharge space between a front substrate and a rear substrate is partitioned for each unit light emitting region by a partition wall having a vertical wall portion extending in the column direction and a horizontal wall portion extending in the row direction. Then, the horizontal wall portions between the unit light emitting regions arranged along adjacent rows are separated by a gap parallel to the row direction, whereby the width in the column direction of each separated horizontal wall portion is reduced.

  According to this, since the discharge space between the front substrate and the rear substrate is partitioned in the row direction and the column direction for each light emitting region by the barrier ribs, there is no discharge interference between the adjacent unit light emitting regions in the column direction. It is possible to prevent the occurrence of erroneous discharge, thereby making it possible to achieve a high-definition screen, and the horizontal wall of the partition wall is separated in the vertical direction by a gap, so that it is separated. Since the width in the column direction of each horizontal wall portion is reduced, the difference between the respective width and the width of the vertical wall portion of the partition wall is reduced, thereby reducing variation in shrinkage during firing of the partition wall, There is no possibility that the shape of the discharge space of the unit light emitting region is deformed due to warpage of the front substrate or the rear substrate and damage to the partition walls.

  In addition, in the plasma display panel described above, the discharge spaces defined by the vertical wall portion and the horizontal wall portion each form a discharge cell C, and the row electrode pair and the column electrode in the discharge cell. A selective discharge for selecting a lighted cell and a non-lighted cell is performed, a discharge sustain pulse is applied to the row electrode pair, and a surface discharge is generated in the lighted cell selected by the selective discharge. It is characterized by.

  According to this, first, by the address operation, discharge is selectively performed between the row electrode pair (X, Y) and the column electrode D in each discharge cell C, and lighting cells (dielectric layers) are displayed on all display lines L. 11 are distributed on the panel corresponding to the image to be displayed. Discharge cells C in which wall charges are formed on the discharge cells C) and extinguishing cells (discharge cells C in which no wall charges are formed on the dielectric layer 11). After this address operation, discharge sustain pulses are alternately applied to the row electrode pairs (X, Y) simultaneously on all the display lines L. Each time this discharge sustain pulse is applied, the surface of each lighting cell is turned on. A discharge is generated. Thus, each discharge cell C is configured to perform a preliminary discharge at the time of address operation and a sustain discharge at the time of applying a discharge sustain pulse.

  Further, in addition to the above-described configuration, the width in the column direction of each portion of the horizontal wall portion of the partition wall divided vertically by the gap is the width in the row direction of the vertical wall portion extending in the column direction of the partition wall. It is characterized by almost the same. That is, the width of each part of the partition walls separated by the gap is set to be the same as the width of the vertical wall part.

  According to this, since there is almost no variation in shrinkage during firing of the barrier ribs, deformation of the shape of the discharge space of the unit light emitting region due to warpage of the front substrate and the rear substrate and damage of the barrier ribs can be prevented more reliably.

  In addition, in addition to the above-described configuration, one of the first dielectric layers is formed so as to project to the side of the horizontal wall at a portion facing the horizontal wall of the partition wall. It is characterized in that a closed raised portion 11A is formed. That is, a discharge that is partitioned by the barrier ribs into unit light-emitting regions and arranged in the column direction by a raised portion formed so as to project to the side of the horizontal wall portion at a portion facing the horizontal wall portion of the barrier ribs of the first dielectric layer The space is shielded between the opposing side walls of the partition wall.

  According to this, since the space between the discharge spaces arranged in the column direction is shielded by the raised portion of the dielectric layer, discharge interference occurs between adjacent unit light emitting regions in the column direction, and erroneous discharge occurs. Can be prevented, and this makes it possible to increase the definition of the screen.

  One feature is that, in addition to the above-described configuration, a slit sl is formed in a part of the partition so as to communicate the discharge spaces of the adjacent unit light emitting regions with each other. That is, when the surface of the barrier rib is in contact with the front substrate side and shields the discharge space, the unit light emitting regions adjacent to each other in the row direction or the column direction through the slit formed in a part of the barrier rib. The discharge space is communicated.

  According to this, the discharge gas and the priming particles sealed in the discharge space can be moved to the adjacent discharge space, and thereby, the discharge is chain-connected between the discharge spaces of the adjacent unit light emitting regions. Will be done.

  In addition, in addition to the above-described configuration, the slit is formed in a vertical wall portion of the partition wall. That is, when the surface of the barrier rib is in contact with the front substrate side to shield the discharge space, the discharge space for each unit light emitting region adjacent to each other in the row direction via the slit formed in the vertical wall portion of the barrier rib Is communicated.

  According to this, the discharge gas and the priming particles sealed in the discharge space can be moved to the adjacent discharge space, and thus, the discharge space of each unit light emitting region adjacent in the row direction is chained. The electric discharge is started.

  In addition, in addition to the above-described configuration, the slit is formed in a lateral wall portion of the partition wall. That is, when the surface of the barrier rib is in contact with the front substrate side to shield the discharge space, the discharge space for each unit light emitting region adjacent to each other in the column direction is formed through the slit formed in the horizontal wall portion of the barrier rib. Communicated.

  According to this, the discharge gas and the priming particles sealed in the discharge space can be moved to the adjacent discharge space, and thereby, the discharge space for each unit light emitting region adjacent in the column direction is chained. The electric discharge is started.

  In addition, in addition to the above-described configuration, first light absorption layers 30 and 31 are provided in a portion of the front substrate facing the gap. That is, a light-absorbing layer colored in a dark color that absorbs light such as black or dark brown is formed on a portion of the front substrate facing the horizontal wall portion of the partition wall, and further, on the front substrate side of the electrode body portion of the row electrode The surface is covered by this light absorbing layer.

  According to this, external light that enters the portion of the front substrate facing the gap between the lateral walls of the front substrate through the front substrate is absorbed by the light absorption layer, so that reflection is prevented and the display screen contrast is increased. Can be improved.

  In addition, in addition to the above-described configuration, a second light absorption layer 40 is provided in a portion facing the vertical wall portion of the partition wall on the back side of the front substrate. That is, a light-absorbing layer colored in a dark color that absorbs light such as black or dark brown is formed in a portion facing the vertical wall portion of the partition wall on the back side of the front substrate, and further, the electrode main body portion of the row electrode is formed. The surface on the front substrate side is covered with this light absorption layer.

  According to this, since the external light incident on the portion of the front substrate facing the horizontal wall portion of the front substrate through the front substrate is absorbed by the light absorption layer, reflection is prevented and the display screen contrast is improved. be able to.

  In addition, in addition to the above-described configuration, at least the vertical wall portion of the partition wall has a two-layer structure of a light absorption layer formed on the display surface side and a light reflection layer formed on the back side. It is characterized by having. In other words, a light-absorbing layer colored in a dark color that absorbs light such as black or dark brown is formed on the surface of the partition wall defining the discharge space that faces at least the front substrate of the vertical wall, and other portions reflect light. It is layered.

  According to this, the external light incident through the front substrate is absorbed by the light absorption layer formed on at least the vertical wall portion of the partition wall and reflection is prevented, so that the contrast of the display screen can be improved. And since the other part is a light reflection layer, the light emission at the time of discharge in the discharge space can be reflected, and the luminance of the screen can be increased.

  Further, in addition to the above-described configuration, the main body portion of the pair of row electrodes is formed of a metal film, and the projecting portion has a base end portion connected to the main body portion and the unit light emitting region. The feature is that each island is provided independently. That is, each row electrode constituting the row electrode pair projects from the main body portion formed by the metal film of the electrode extending in the row direction to the direction of the other row electrode that forms a pair for each unit light emitting region, and a required discharge gap The projections are formed by transparent conductive films that face each other via each other, and each unit light emitting region is configured to be independent in an island shape.

  According to this, since each row electrode constituting the row electrode pair is configured to be island-like independently for each unit light emitting region, the size of each unit light emitting region is set to increase the definition of the screen. Even if it is made small, there is no possibility that interference of discharge to the adjacent unit light emitting region in the row direction occurs.

  In addition, in addition to the above-described configuration, a light absorption layer is provided on the display surface side of the main body. That is, a light absorbing layer colored in a dark color that absorbs light such as black or dark brown is formed on the surface of the main body of the row electrode facing the front substrate.

  According to this, external light incident through the front substrate is absorbed by the light absorption layer formed in the main body portion of the row electrode, thereby preventing reflection, thereby improving the contrast of the display screen. it can.

  One feature is that, in addition to the above-described configuration, at least one of the pair of row electrodes shares the main body portion between display lines adjacent to each other. That is, a pair of row electrodes constituting a row electrode pair are alternately replaced for each display line, and row electrodes having at least one pole are arranged back to back in adjacent display lines. Share the same body.

  According to this, the row electrodes arranged back to back in adjacent display lines share the same main body portion, so that the installation area of the main body portion can be reduced. Since the width of the horizontal wall of the opposing partition can be reduced, the size of the unit light emitting region can be increased accordingly, and the surface area of the phosphor layer formed in this unit light emitting region can be increased, and the brightness of the display screen can be increased. Is increased. Furthermore, the discharge current can be reduced by sharing the main body.

  In addition, in addition to the above-described configuration, the unit light-emitting regions partitioned by the partition walls are linearly arranged in the column direction, and a phosphor layer is formed in each unit light-emitting region. The color of the body layer is set in the order of red, green, and blue in the row direction, and the unit light emitting areas having the same color phosphor layer are arranged in a straight line in the column direction, and are arranged in the row direction. One pixel is composed of three unit light-emitting areas that are color-coded. That is, unit light-emitting regions partitioned by barrier ribs are arranged in a matrix, and the color of each unit light-emitting region is set in the order of red, green, and blue in the row direction, and the unit light-emitting region having the same color phosphor layer Are arranged in a straight line in the column direction. Then, the pixels constituting the display screen are configured in units of three unit light emitting areas that are color-coded red, green, and blue arranged in the row direction.

  In addition, in addition to the above-described configuration, the unit light-emitting regions partitioned by the partition walls are linearly arranged in the column direction, and a phosphor layer is formed in each unit light-emitting region. The color of the body layer is set in the order of red, green, and blue in the row direction, and the color of the phosphor layer is the same in the unit light-emitting region where two adjacent display lines are shifted from each other in the row direction by one. Thus, one pixel is constituted by three unit light-emitting areas which are set as described above and are color-coded red, green and blue arranged in the row direction. That is, the unit light emitting areas partitioned by the barrier ribs are arranged in a matrix, and the color of each unit light emitting area is set in the order of red, green, and blue in the row direction, and the color of the phosphor layer is red in the row direction. The unit light emission areas are set in the order of green and blue, and the unit light emitting areas of the same color are set to be shifted one by one in the row direction from each other in two adjacent display lines. Then, the pixels constituting the display screen are configured in units of three unit light emitting areas that are color-coded red, green, and blue arranged in the row direction.

  According to this, the resolution of the display screen can be improved by arranging the pixels so as to be shifted by one unit light emitting area discharge in the row direction for each display line.

  For example, in addition to the above-described configuration, the unit light-emitting region defined by the partition wall may be shifted by half of the width of the unit light-emitting region in the row direction from each other in two adjacent display lines. The phosphor layers are formed in each unit light emitting region, and the colors of the phosphor layers are set in the order of red, green, and blue in the row direction, and the colors of the phosphor layers are adjacent to each other. One pixel is formed by three unit light-emitting areas that are set to be the same in unit light-emitting areas that are shifted from each other by half of the dimension in the width direction in the row direction, and that are color-coded red, green, and blue in the row direction. It is characterized by being composed. That is, the unit light emitting areas defined by the partition walls are arranged so as to be shifted from each other by half in the row direction in the two adjacent display lines, and the colors of the unit light emitting areas are set in the order of red, green, and blue in the row direction. At the same time, the unit light-emitting areas of the same color are set so as to be located at positions shifted by half in the row direction from each other in two adjacent display lines. Then, the pixels constituting the display screen are configured in units of three unit light emitting areas that are color-coded red, green, and blue arranged in the row direction.

  According to this, the resolution of the display screen can be improved by arranging the pixels so as to be shifted by half of the unit light emitting area discharge in the row direction for each display line.

  For example, in addition to the above-described configuration, the unit light-emitting region defined by the partition wall may be shifted by half of the width of the unit light-emitting region in the row direction from each other in two adjacent display lines. The phosphor layers are formed in each unit light emitting region, and the colors of the phosphor layers are set in the order of red, green, and blue in the row direction, and the colors of the phosphor layers are adjacent to each other. Red and green that are set to be the same in unit light-emitting regions that are shifted by 1.5 times the width dimension in the row direction of the display lines, and are arranged in a delta pattern across the two adjacent display line row directions , One pixel is composed of three unit light emitting areas color-coded in blue. That is, the unit light emitting areas defined by the partition walls are arranged so as to be shifted from each other by half in the row direction in the two adjacent display lines, and the colors of the unit light emitting areas are set in the order of red, green, and blue in the row direction. At the same time, the unit light-emitting areas of the same color are set so as to be located at positions shifted from each other in the row direction by one and a half in two adjacent display lines.

  Then, the pixels constituting the display screen are configured in units of three unit light-emitting areas that are color-coded red, green, and blue that are positioned in a delta shape across two display lines adjacent in the column direction.

  According to this, the resolution of the display screen can be improved by arranging the three unit light emitting regions constituting one pixel in a delta shape.

  In addition, in addition to the above-described configuration, the outer corners of the partition walls that divide the unit light emitting regions located on the outermost side of the unit light emitting regions arranged in the row direction are chamfered. It is a feature. That is, the corners of the barrier ribs are raised by chamfering the outer corners of the barrier ribs that divide the unit light emitting regions located on the outermost sides of the unit light emitting regions arranged in a line in the row direction. Is prevented.

  As a result, the corners of the partition wall are raised, and in some cases, when the front substrate and the rear substrate are overlapped, the front substrate contacts only the raised portion (that is, the peripheral portion of the substrate) and other parts (the central part) ) In a floating state and vibration occurs in the substrate when the plasma display panel is driven, and vibration noise is generated. By preventing chamfering on the corners of the partition walls, Are uniformly in contact with each other, and the occurrence of vibration as described above is prevented.

It is a top view which represents typically the 1st example of this invention. It is sectional drawing in the V3-V3 line | wire of FIG. It is sectional drawing in the V4-V4 line | wire of FIG. It is sectional drawing in the W3-W3 line | wire of FIG. It is sectional drawing in the W4-W4 line | wire of FIG. It is a top view which represents typically the 2nd example of this invention. It is sectional drawing in the V5-V5 line | wire of FIG. It is sectional drawing in the V6-V6 line | wire of FIG. It is a top view which represents typically the relationship between the row electrode pair of PDP and the partition in the 3rd example of this invention. It is a top view which represents typically the 4th example of this invention. It is a top view which represents typically the 5th example of this invention. It is sectional drawing in the V7-V7 line | wire of FIG. It is sectional drawing in the V8-V8 line | wire of FIG. It is sectional drawing in the W7-W7 line | wire of FIG. It is sectional drawing in the W8-W8 line | wire of FIG. It is a top view which represents typically the 6th example of this invention. It is a top view which represents typically the 7th example of this invention. It is a top view which represents typically the 8th example of this invention. It is a top view which represents typically the 9th example of this invention. It is a top view which represents typically the 10th example of this invention. It is a top view which shows the shape and arrangement | positioning of the partition in this invention. It is a top view which represents typically the structure of the conventional PDP. It is sectional drawing in the VV line | wire of FIG. It is sectional drawing in the WW line of FIG. It is a top view which represents typically PDP concerning an applicant's proposal. It is sectional drawing in the V1-V1 line | wire of FIG. It is sectional drawing in the V2-V2 line | wire of FIG. It is sectional drawing in the W1-W1 line | wire of FIG. It is sectional drawing in the W2-W2 line | wire of FIG.

Explanation of symbols

10 Front glass substrate (front substrate)
11 Dielectric layer (first dielectric layer)
11A Raised dielectric layer (raised part)
12 Protective layer 13 Back glass substrate (back substrate)
14 Dielectric layer (second dielectric layer)
15, 35, 45, 65, 15A Partition 15a, 35a, 45a, 65a, 15Aa Vertical wall (vertical wall)
15b, 35b, 45b, 65b, 15Ab Horizontal wall (horizontal wall part)
15b, 35b, 45b, 65b Divided portions 15A, 15B, 15C, 15D Partition 15Aa, 15Ba, 15Ca, 15Da Vertical wall 15Ab, 15Bb, 15Cb, 15Db Horizontal wall 15Ac Chamfer 16 Phosphor layer 30 Light absorption layer 31 Light absorption layer 40 Light Absorption layer X row electrode Y row electrode Xa transparent electrode Ya transparent electrode Xb bus electrode (main body)
Yb bus electrode (main part)
Xb ′, Yb ′ Black layer (light absorption layer)
Xb ″, Yb ″ White layer (light reflection layer)
D, DA, DB, DC, DD Column electrode S Discharge space SL, SL1, SL2 Gap sl, sl 'Slit C Discharge cell (unit emission region)
C 'dummy cell GA, GB, GC, GD pixel L display line g gap r gap

Claims (21)

On the back side of the front substrate, a plurality of row electrode pairs extending in the row direction and juxtaposed in the column direction to form display lines and a first dielectric layer covering the row electrode pairs are provided. A plurality of column electrodes that form unit light-emitting regions in the discharge space at positions that extend in the column direction and are arranged in parallel in the row direction and intersect the row electrode pairs on the side facing the front substrate through the discharge space in In the plasma display panel provided with the second dielectric layer covering the column electrode,
A partition wall is provided between the front substrate and the rear substrate and partitions the discharge space in the row direction and the column direction for each unit light emitting region by a vertical wall portion extending in the column direction and a horizontal wall portion extending in the row direction. ,
In the unit light emitting region, a discharge is made between the row electrode pair and the column electrode, and between the pair of row electrodes,
A phosphor layer is formed on the side surfaces of the vertical wall portion and the horizontal wall portion constituting the unit light emitting region, and on the surface of the second dielectric layer,
Each of the pair of row electrodes has a main body portion extending in the row direction, and a protrusion portion protruding from the main body portion in the column direction and facing each other via a discharge gap for each unit light emitting region,
The lateral wall portions between the unit light emitting regions arranged along adjacent rows are separated by a gap parallel to the row direction ,
A plasma display panel , wherein discharge occurs only in the unit light emitting region in the discharge space .   The discharge spaces defined by the vertical wall portion and the horizontal wall portion each form a discharge cell, and in the discharge cell, a selective discharge for selecting a lighted cell and a light-off cell between the row electrode pair and the column electrode is performed. 2. The plasma display panel according to claim 1, wherein a discharge sustain pulse is applied to the pair of row electrodes to generate a surface discharge in the lighting cell selected by the selective discharge.   The plasma display panel according to claim 1, wherein the width of the horizontal wall portion of the partition walls separated by the gap is substantially the same as the width of the vertical wall portion extending in the column direction of the partition walls in the row direction.   The raised part which is formed so that it may protrude in the side wall part side in the part which opposes the side wall part of the said partition of the said 1st dielectric material layer, and closes between a side wall part is formed. Plasma display panel.   The plasma display panel according to claim 1, wherein a slit is formed in a part of the partition wall to communicate discharge spaces of the adjacent unit light emitting regions with each other.   The plasma display panel according to claim 5, wherein the slit is formed in a vertical wall portion of the partition wall.   The plasma display panel according to claim 5, wherein the slit is formed in a lateral wall portion of the partition wall.   The plasma display panel according to claim 1, wherein a first light absorption layer is provided in a portion of the front substrate facing the gap.   2. The plasma display panel according to claim 1, wherein a second light absorption layer is provided in a portion facing the vertical wall portion of the partition wall on the back side of the front substrate.   The plasma display panel according to claim 1, wherein at least the vertical wall portion of the partition wall has a two-layer structure of a light absorption layer formed on the display surface side and a light reflection layer formed on the back surface side.   The main body portion of the pair of row electrodes is formed of a metal film, the projecting portion is formed of a transparent conductive film, and the projecting portion is connected to the main body portion and has a base end portion for each unit light emitting region. The plasma display panel according to claim 1, wherein the plasma display panel is independently provided in an island shape.   The plasma display panel according to claim 11, wherein a light absorption layer is provided on a display surface side of the main body.   The plasma display panel according to claim 11, wherein at least one of the pair of row electrodes shares the main body between display lines adjacent to each other.   The unit light emitting areas partitioned by the barrier ribs are linearly arranged in the column direction, and a phosphor layer is formed in each unit light emitting area, and the color of the phosphor layer is red, green, blue in the row direction. The unit light emitting regions having the same color phosphor layer are arranged in a straight line in the column direction, and one pixel is formed by three unit light emitting regions colored in red, green, and blue arranged in the row direction. The plasma display panel according to claim 1 configured.   The unit light emitting areas partitioned by the barrier ribs are linearly arranged in the column direction, and the colors of the phosphor layers in each unit light emitting area are set in the order of red, green, and blue in the row direction. Three units that are set to be the same in the unit light-emitting area where the color of the phosphor layer is shifted by one in the row direction between two adjacent display lines and are color-coded red, green, and blue in the row direction The plasma display panel according to claim 1, wherein one pixel is constituted by a light emitting region.   The unit light-emitting regions partitioned by the barrier ribs are arranged so as to be shifted by half of the width direction of the unit light-emitting region in the row direction in two adjacent display lines, and the phosphor layer in each unit light-emitting region Are set in the order of red, green, and blue in the row direction, and the color of the phosphor layer is the same in a unit light emitting region in which two adjacent display lines are shifted from each other by half in the width direction in the row direction. The plasma display panel according to claim 1, wherein one pixel is constituted by three unit light-emitting areas which are set so as to be color-separated into red, green and blue arranged in the row direction.   The unit light-emitting regions partitioned by the barrier ribs are arranged so as to be shifted by half of the width direction of the unit light-emitting region in the row direction in two adjacent display lines, and the phosphor layer in each unit light-emitting region Are set in the order of red, green, and blue in the row direction, and the unit light emitting region in which the color of the phosphor layer is shifted by 1.5 times the width direction dimension in the row direction between two adjacent display lines. A pixel is composed of three unit light-emitting regions that are set to be the same in the above and are arranged in a delta shape across two adjacent display line row directions and are color-coded red, green, and blue 2. The plasma display panel according to 1.   2. The plasma display panel according to claim 1, wherein chamfering is performed on an outer corner of a partition wall that divides a unit light emitting region located on the outermost side of the unit light emitting regions arranged in a row direction.   The plasma display panel according to claim 1, wherein the gap is not included in the unit light emitting region.   The plasma display panel according to claim 1, wherein the vertical wall portion is separated for each unit light emitting region by the gap.   The width of the base end side connected to the main body part is narrower than the width of the front end side, and the wide part of the front end side is opposed to each other through the discharge gap. 1. The plasma display panel described in 1.

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