JP3781240B2 - Nonvolatile semiconductor memory and semiconductor integrated circuit incorporating the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique effective when applied to a write verify method in an electrically writable nonvolatile semiconductor memory. For example, the present invention relates to a microcomputer incorporating a flash memory chip capable of erasing data in a block unit. It is related to effective technology.
[0002]
[Prior art]
A flash memory uses a nonvolatile memory element having a control gate and a floating gate as a memory cell, and the memory cell can be configured by one transistor. In such a flash memory, in the write operation, as shown in FIG. 14B, the voltage of the drain region D of the nonvolatile memory element is set to, for example, 6.0 V (volt), and the word line to which the control gate C-GATE is connected. For example, by setting the voltage to −10.0 V, the charge is extracted from the floating gate F-GATE to the drain region D, and the threshold voltage is lowered (logic “0”). In the erase operation, as shown in FIG. 14C, the source region S and the base P-SUB are set to -10.0 V, for example, and the control gate C-GATE is set to a high voltage such as 10.0 V to form a floating gate. Negative charge is injected into F-GATE to bring the threshold value to a high state (logic “1”). Thereby, 1-bit data is stored in one storage element.
[0003]
In a flash memory, writing is generally performed simultaneously on, for example, a sector unit, that is, a memory cell for one row sharing a word line, and erasing is performed on a plurality of sectors sharing a block unit, that is, a well region. In the embodiment of the present invention, it is assumed that it is configured as such unless otherwise specified.
[0004]
[Problems to be solved by the invention]
In the flash memory, as described above, the writing operation and the erasing operation for changing the threshold value are performed by injecting charges to the floating gate or discharging the charges from the floating gate. When excessive writing is performed in such an operation, a bit called a depletion failure (bit in which current flows in a non-selected state) having a threshold value of 0 V or less occurs. Therefore, according to the flow shown in FIG. 16, a relatively short write pulse having a high voltage is applied to the word line in a plurality of times, so that the threshold value is gradually changed as shown in FIG. Then, a read operation for verifying is performed after the application of the write pulse, and control is performed so that no more write pulses are applied to bits that have reached a predetermined threshold value (for example, 2.0 V). It is.
[0005]
However, since the verify read operation in the flash memory detects a minute threshold value change of the memory element by the sense amplifier, it is necessary to use a sense amplifier having a high amplification factor. As a result, the sensitivity of the sense amplifier to noise increases. When the threshold value of the storage element is close to the verify voltage, the apparent threshold value may shift as shown by the dotted line in FIG. It is easy to make a mistake. For this reason, even if it is determined that writing has been completed once, it may be determined that writing has not been completed at the time of the next verify operation, and as a result, the total number of times of writing increases and the time required for writing increases. It became clear that there was.
[0006]
An object of the present invention is to provide a non-volatile semiconductor memory capable of shortening the time required for writing and a semiconductor integrated circuit such as a microcomputer incorporating the non-volatile semiconductor memory.
[0007]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0009]
That is, in the nonvolatile semiconductor memory configured to control and change the voltage applied to the threshold value of the memory element to store data, or the number of times the write voltage is applied to the same memory element in the semiconductor integrated circuit incorporating the same Accordingly, the end of the writing is determined by performing the reading with the voltage with the relaxed verify condition.
[0010]
According to the above means, since reading is performed with a voltage that relaxes the verification condition, erroneous determination of read data can be avoided even if noise enters the read circuit (sense amplifier), so the total number of write operations is reduced. Writing time can be reduced.
[0011]
As a means for counting the number of times of writing, for example, a counter that counts the number of times of application of the writing voltage to the word line to which the gate of the memory element is connected can be considered. The counter is preferably a soft counter that is updated by a program that performs write control, but may be a counter circuit that operates in response to a signal. However, the software configuration has the advantage that the amount of hardware can be reduced and the chip size can be reduced.
[0012]
Instead of reading at a voltage with relaxed verification conditions after application of the write voltage, the sensitivity of the read circuit (sense amplifier) may be lowered.
[0013]
In addition, a differential amplifier circuit in which a reference voltage is applied to the non-inverting input terminal, a resistor ladder connected in series between the output terminal of the differential amplifier circuit and the ground point, and the resistor ladder And a pair of switch means connected in parallel between the node of the differential amplifier circuit and the inverting input terminal of the differential amplifier circuit, and a verify voltage switching signal is applied to the control terminals of these switch means A voltage switching circuit is provided. Thereby, a circuit for switching the verify voltage can be configured relatively easily.
[0014]
Further, a means for counting the number of times of application of the write voltage is provided, and the verify voltage switching circuit is switched by the verify voltage switching signal when the count value of the counting means reaches a predetermined number. As a result, the verify voltage can be switched relatively accurately, and the number of write voltage application times for switching the verify voltage can be changed according to the memory.
[0015]
A switching control register for controlling the verify voltage switching circuit is provided, and the verify voltage switching signal is generated by setting the register. As a result, the verify voltage can be switched by setting the register from an external control device or the like without providing a circuit for counting the number of times the write voltage is applied to the memory itself, thereby reducing the load on the memory. There are advantages.
[0016]
Furthermore, a semiconductor integrated circuit is built in which the nonvolatile semiconductor memory configured as described above and a control circuit that controls the nonvolatile semiconductor memory to perform write and verify operations are built. This simplifies the system configuration and reduces the burden on the user.
[0017]
In this case, it is desirable that the control circuit is configured by a program control system circuit and that the control circuit is configured to count the number of write pulse applications to the storage element according to the program. Thereby, the amount of hardware, that is, the circuit scale can be reduced.
[0018]
The control circuit is provided with a switching control register for controlling the verify voltage switching circuit, and the control circuit rewrites the register when the number of write pulse application times to the storage element reaches a predetermined number, and A verify voltage switching signal is generated. As a result, the generation of the verify voltage switching signal can be performed by software, and the flexibility of the system is improved.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention applied to a microcomputer having a built-in flash memory (hereinafter referred to as a flash microcomputer) will be described with reference to the drawings. FIG. 1 shows a schematic configuration of a flash microcomputer to which the present invention is applied. Although not particularly limited, each circuit block shown in FIG. 1 is formed on one semiconductor chip such as single crystal silicon.
[0020]
In FIG. 1, FLASH is a memory array in which memory cells as nonvolatile memory elements made of MOSFETs having floating gates as shown in FIG. 14 are arranged in a matrix, an address decoder for selecting memory cells, addresses and A flash memory circuit including peripheral circuits such as a data latch circuit, a sense amplifier for data amplification, a power supply circuit for generating a voltage required for data writing, erasing, and reading, FLC is used for writing to the flash memory circuit FLASH A flash controller that performs control such as erasing and reading (including verify reading), a CPU is a central processing unit that controls the entire chip, and a RAM is a high-speed random storage that temporarily stores data and provides a work area for the central processing unit CPU Access memory, BUS Serial central processing unit CPU and the flash memory circuit FLASH, a flash controller FLC, buses connecting between the high-speed memory RAM, BSC is a bus controller for performing control of exclusive right of the bus.
[0021]
Although not shown in FIG. 1, in the case of a microcomputer such as a single chip microcomputer, in addition to the above circuit blocks, DMA (direct memory access) between an internal memory and an external memory, etc. DMA transfer control circuit for controlling transfer, interrupt control circuit for determining the generation and priority of interrupt requests to the CPU and making an interrupt, serial communication interface circuit for serial communication with external devices, various timer circuits, analog An A / D conversion circuit for converting a signal and a digital signal, a watchdog timer for system monitoring, an oscillator for generating a clock signal necessary for system operation, and the like are provided as necessary.
[0022]
FIG. 2 shows a schematic configuration of the flash memory circuit FLASH. In FIG. 2, 11 is a memory array in which memory cells as non-volatile storage elements made of MOSFETs having floating gates as shown in FIG. 14 are arranged in a matrix, and 12 is write data input from the outside. A data register 13 is a write circuit for writing to the memory array 11 based on the data held in the data register 12.
[0023]
14 is an address register for holding an address signal, 15 is an X decoder for selecting one word line corresponding to the X address taken into the address register 14 from the word lines in the memory array 11, and 16 is A Y decoder that decodes the Y address fetched into the address register 14 and selects 1 byte (or 1 word) of data in one sector, and 17 is an erase control circuit that selects a block (mat) at the time of erasure. , 18 are sense amplifiers that amplify and output data read from the memory cell array 11.
[0024]
Further, in the flash memory circuit of this embodiment, in addition to the above circuit blocks, a control circuit 27 for converting a control signal from the outside into a control signal for each circuit of the flash memory, and input / output of address signals and data signals. The I / O buffer circuit 23 is provided with step-up and step-down means such as a charge pump, and the write voltage Vw, erase voltage Ve, read voltage Vr, verify voltage Vwv, Ver, etc. are provided inside the chip based on the power supply voltage Vcc supplied from the outside. A power supply circuit 25 that generates a required voltage, a power supply switching circuit 26 that selects a desired voltage from these voltages according to the operation state of the memory, and supplies the selected voltage to the memory array 11 are provided.
[0025]
Although not particularly limited, in the flash memory circuit of this embodiment, the control gate C-GATE, the source S, the drain D, and the substrate (substrate or well region) P-SUB of the storage element are shown in FIG. A read operation (A), a write operation (B), an erase operation (C), a write verify operation (D), and an erase verify operation (E) are performed by applying voltages as shown in FIG. It is. As shown in FIGS. 14A and 14D, the voltage Vr applied to the gate (word line) during the normal read operation is 3.8 V, whereas the gate (word line) during the verify operation. The verify voltage Vwv applied to the capacitor is 2.0V lower than Vr.
[0026]
Although a detailed description of the configuration of the flash controller FLC is omitted, the flash controller FLC of this embodiment includes a plurality of control registers. When the CPU writes to the control register according to a program stored in the RAM, the flash controller FLC The controller FLC is configured to generate a control signal for the flash memory circuit FLASH in accordance with the bit state of the control register to perform operations such as writing, erasing, reading and verifying.
[0027]
FIG. 3 shows a configuration example of the control register CNTR for writing and erasing control among the control registers. In the register of this embodiment, the bit FWE for protecting the writing and erasing operations from being performed carelessly, the bit SWE for instructing the power supply to the power supply circuit 25, the polarity of the decoder output, the power supply switching, etc. A write setup bit PSU for setting the memory array and its peripheral circuit to a write ready state, a bit P for instructing to provide a write pulse, an erase setup bit ESU for setting the memory array and its peripheral circuit to an erase ready state, and an erase pulse Bit E for instructing bit, bit EV for instructing to perform erase verify, bit PV for instructing to perform write verify, and the like.
[0028]
The flash controller FLC includes, in addition to the control register CNTR for write / erase control, an erase selection register for selecting an erase block among a plurality of blocks in the memory array at the time of erasure, and a memory including defective bits in the memory array A register for holding relief information for replacing the column with a spare memory column is provided.
[0029]
In a general memory, a control signal for each circuit in the memory is sequentially formed to decode a command given from an external CPU or the like and execute processing corresponding to the command based on the decoding result. A control circuit (sequencer) for output is provided, and the control circuit is a ROM that stores a series of microinstructions necessary for executing commands (instructions), for example, like a control unit of a microprogram CPU. In this embodiment, the flash controller FLC includes the control register CNTR as described above. When the CPU writes to the control register in accordance with the program stored in the RAM, the flash controller FLC is flashed. Controller FLC is in bit state of control register CNTR Accordingly, a control signal for the flash memory circuit FLASH is formed to perform operations such as writing, erasing, reading, and verifying. Therefore, the hardware scale is reduced compared to a general command-type controller. There is an advantage that you can.
[0030]
FIG. 4 shows a procedure of one embodiment of writing and verify control by the flash controller FLC in the microcomputer with built-in flash memory to which the present invention is applied. In this embodiment, as the write verify voltage applied to the word line, in addition to the verify voltage Vwv1 of a predetermined level (for example, 2.0 V) set in advance based on the design value, this voltage is given a marginal value. A circuit capable of generating a verify voltage Vwv2 (for example, 2.05V) set to a high level and a circuit capable of switching these voltages are provided in the flash memory FLASH, and a write pulse is applied as software of the flash controller FLC. A counter for counting the number of times is prepared in the working memory RAM. Note that the margin value of the verify voltage Vwv2 with respect to Vwv1 is desirably as small as possible within a range in which malfunction due to noise of the sense amplifier 18 can be avoided.
[0031]
In writing, first, the value n of the counter is set to “0” (step S1), and then the write data is loaded from the memory RAM and stored in the data latch 12 in the flash memory FLASH (step S2). . Next, a write pulse is generated by the write circuit 13 in accordance with the write data stored in the data latch 12 and applied to the selected memory cell (step S3), and the write pulse application number counter is incremented (+1) ( Step S4).
[0032]
Then, the value of this counter is examined to determine whether it is an even number (step S5). When the number is even, the switching circuit is controlled to select a predetermined level of verify voltage Vwv1 (step S6), and the verify voltage is applied to the word line for reading (step S8). On the other hand, when the value of the write pulse application number counter is an odd number, the switching circuit is controlled to select a verify voltage Vwv2 slightly higher than a predetermined level (step S7), and the verify voltage is applied to the word line. Reading is performed (step S8).
[0033]
Subsequently, the read data and the write data stored in the memory RAM are compared to determine whether all the bits corresponding to the data “0” have been brought into a low threshold state, for example. Is determined (steps S9 and S10). Then, based on the read data and the write data, rewrite data set to “0” is generated only for the bits for which writing has not been completed (step S11), and the process returns to step S2 and the rewritten data is changed to this rewritten data. Repeat writing based on.
[0034]
FIG. 6A shows how the verify voltage is switched and the distribution of the threshold value is changed when the write verify control is performed according to the flowchart of this embodiment. According to this example, according to this embodiment, the verify voltage Vwv2 performed after the odd-numbered application of the write pulse is higher than the verify voltage Vwv1 performed after the even-numbered application. In the case of reading only with the verify voltage, if the writing is completed on the average five times, the application of this embodiment will apply five write pulses in most cases even if noise enters the sense amplifier. The writing can be terminated with. However, the even-numbered verify voltage may be set slightly higher than the odd-numbered verify voltage.
[0035]
The counter that counts the number of write pulse applications may be a counter circuit that counts the write control signal as well as the soft counter as described above. Further, instead of the counter, it is also possible to use a circuit such as a flip-flop that distinguishes between the odd-numbered times and the even-numbered times and generates and outputs a verify voltage switching signal. In this case, the write verify control by the flash controller can be performed according to the same flowchart as the write verify control flow in the general flash memory shown in FIG. 16, and there is an advantage that the program change is unnecessary.
[0036]
FIG. 5 shows the procedure of the second embodiment of writing and verify control by the flash controller FLC in the microcomputer with built-in flash memory to which the present invention is applied. Also in this embodiment, as a write verify voltage applied to the word line, a margin value is given to this voltage in addition to a verify voltage Vwv1 of a predetermined level (for example, 2.0 V) set in advance based on a design value. A circuit capable of generating a verify voltage Vwv2 (for example, 2.05V) set to a slightly high level and a circuit capable of switching these voltages are provided in the flash memory FLASH, and a write pulse is used as software of the flash controller FLC. A counter for counting the number of times of application is prepared in the working memory RAM.
[0037]
This embodiment differs from the embodiment of FIG. 4 in that a write pulse application number N (for example, 5 times) at which writing is desired to be completed is preset and stored in the memory RAM as a predetermined number of times, and step S5. Thus, it is determined whether or not the value of the counter for counting the number of pulse applications has reached a predetermined number or more, and the verify voltage is switched from Vwv1 to Vwv2.
[0038]
FIG. 6B shows how the verify voltage is switched and the distribution of the threshold value is changed when the write verify control is performed according to the flowchart of the second embodiment. According to this embodiment, according to the present embodiment, the verify voltage Vwv2 performed after the predetermined number of times (fifth) application of the write pulse is higher than the verify voltage Vwv1 so far. ) Can be terminated by application of the address pulse. However, the number of application times of the write pulse for switching the verify voltage is not limited to 5 times, and it is desirable to determine the average number of pulse application times of all the memory elements in advance by testing.
[0039]
7 and 8 show a specific example of a circuit for generating a verify voltage switching signal and an operation timing chart thereof. The verify voltage switching signal generation circuit of this embodiment is composed of the latch read circuits VR1 and LT2 using the verify read signal VR output from the control circuit 27 in FIG. 2 and its inverted signal as a clock, and the output of the latch circuit LT1 is the latch circuit. The output is supplied to the input terminal of LT2, and the output of the latch circuit LT2 is connected to the input terminal of the latch circuit LT1 via the inverter INV1, so that the output is changed from high to low every time the verify read signal VR is input. Alternatively, it operates as a flip-flop that changes from low to high. The output is supplied as a verify voltage switching signal VC to a verify voltage switching circuit described later.
[0040]
As shown in FIG. 8, the verify voltage switching signal generation circuit according to this embodiment is configured such that the verify voltage switching signal VC, which is an output, is set to the high level every time the verify read signal VR is set to the high level after the application of the write pulse Pw. Changed to low level. When this verify voltage switching signal VC is supplied to the verify voltage switching circuit, a predetermined verify voltage Vwv is applied to the selected word line WL when the verify voltage switching signal VC is at a low level, and when VC is at a high level, A voltage higher than the verify voltage Vwv by a margin value is applied.
[0041]
Although not particularly limited, NOR gates G1 and NAND gates G2 are provided at the output portions of the latch circuits LT1 and LT2 of this embodiment, respectively, and a mode control signal MD is applied to one input terminal of these gates G1 and G2. When the signal is inverted by the inverter INV2, the circuit is activated only when the mode control signal MD is set to the low level, and the mode control signal MD is set to the high level. The circuit does not operate regardless of whether the verify read signal VR is input. That is, the verify voltage switching signal VC that is an output is not changed. As a result, the functions of the present invention can be exhibited or prohibited as necessary, and the flexibility of the system is increased. If the function of the present invention is disabled, the threshold time distribution after writing can be controlled with higher accuracy, although the time required for writing becomes somewhat longer.
[0042]
FIG. 9 shows a specific example of the verify voltage switching circuit. In the verify voltage switching circuit of this embodiment, an operational amplifier OP in which a reference voltage Vref generated by a reference voltage generation circuit (not shown) is applied to a non-inverting input terminal, and an output terminal of the operational amplifier OP and a ground point are connected in series. A resistor ladder RLD connected in the form and a pair of switch MOSFETs Q1 and Q2 connected in parallel between appropriate nodes n1 and n2 in the resistor ladder RLD and the inverting input terminal of the operational amplifier OP. Then, a verify voltage switching signal VC and a signal / VC obtained by inverting it with an inverter INV3 are applied to the gate terminals of Q1 and Q2.
[0043]
In the circuit of this embodiment, the resistor ladder RLD divides the output voltage of the operational amplifier OP by resistance, and the operational amplifier OP is connected via the one where the potential of the node n1 or n2 divided by the resistance is turned on either of the switch MOSFETs Q1 and Q2. When fed back to the inverting input terminal, the operational amplifier OP outputs a voltage such that the potential of the node n1 or n2 becomes equal to the reference voltage Vref of the non-inverting input terminal.
[0044]
Specifically, when the verify voltage switching signal VC is set to the low level, the MOSFET Q1 is turned on, the potential of the node n1 is fed back to the inverting input terminal of the operational amplifier OP, and the output voltage Vout of the operational amplifier OP is 2. The potential is set to 0V, and this is supplied to the selected word line as the verify voltage Vwv1. When the verify voltage switching signal VC is set to the high level, the MOSFET Q2 is turned on, the potential of the node n2 is fed back to the inverting input terminal of the operational amplifier OP, and the output voltage Vout of the operational amplifier OP is 2.05V. This potential is supplied to the selected word line as the verify voltage Vwv2.
[0045]
Conversely, when the MOSFET Q1 is turned on and the potential of the node n1 is fed back to the inverting input terminal of the operational amplifier OP, the output voltage Vout of the operational amplifier OP becomes a potential such as 2.0 V, and the MOSFET Q2 Each resistor constituting the resistor ladder RLD is set so that the output voltage Vout of the operational amplifier OP becomes a potential such as 2.05 V when the potential of the node n2 is fed back to the inverting input terminal of the operational amplifier OP. The ratio of is determined.
[0046]
FIG. 10 shows another specific example of the verify voltage switching circuit. As in the circuit of the embodiment of FIG. 9, the verify voltage switching circuit of this embodiment includes an operational amplifier OP in which a reference voltage Vref generated by a reference voltage generation circuit (not shown) is applied to a non-inverting input terminal, and the operational amplifier OP. The resistor ladder RLD is connected in series between the output terminal and the ground point. However, unlike FIG. 9, in this embodiment, the potential of an appropriate node n1 in the resistor ladder RLD is fed back to the inverting input terminal of the operational amplifier OP, and any one or more resistors in the resistor ladder RLD are used. The switch MOSFET Q1 is connected in parallel to the MOSFET Q1, and a verify voltage switching signal VC is applied to the gate terminal of the MOSFET Q1.
[0047]
In the circuit of this embodiment, the resistor ladder RLD divides the output voltage of the operational amplifier OP by resistance, and when the potential of the node n1 obtained by the resistance division is fed back to the inverting input terminal of the operational amplifier OP, the operational amplifier OP becomes the potential of the node n1. Outputs a voltage such that becomes equal to the reference voltage Vref of the non-inverting input terminal.
[0048]
Specifically, when the verify voltage switching signal VC is at a low level, the MOSFET Q1 is turned off, the potential of the node n1 is relatively increased and fed back to the inverting input terminal of the operational amplifier OP, and the operational amplifier OP Is set to a potential such as 2.0 V, and this is supplied to the selected word line as a verify voltage Vwv1. On the other hand, when the verify voltage switching signal VC is set to the high level, the MOSFET Q1 is turned on, the potential of the node n1 is relatively lowered and fed back to the inverting input terminal of the operational amplifier OP, and the output voltage Vout of the operational amplifier OP. Is set to a potential such as 2.05 V, and this is supplied to the selected word line as a verify voltage Vwv2.
[0049]
FIG. 11 shows another specific example of the verify voltage switching circuit. In the verify voltage switching circuit of this embodiment, a switch MOSFET is provided in a resistor ladder RLD provided on the output terminal side of the operational amplifier OP, and a voltage generated by switching a feedback voltage by a verify voltage switching signal VC is switched. Instead, a resistor ladder RLD0 for resistance-dividing the reference voltage Vref supplied from the reference voltage generation circuit is provided in front of the operational amplifier OP, and the potentials of appropriate nodes n11 and n12 in the resistor ladder RLD0 are set to switch MOSFETs Q11 and Q12. The voltage generated by selectively supplying to the non-inverting input terminal of the operational amplifier OP is switched.
[0050]
Similarly to the circuit of FIG. 10, the resistor ladder RLD also divides the output voltage of the operational amplifier OP by the resistor ladder RLD, and the potential of the node n1 divided by the resistor is fed back to the inverting input terminal of the operational amplifier OP. The operational amplifier OP outputs a voltage such that the potential of the node n1 is equal to the reference voltage Vref of the non-inverting input terminal.
[0051]
However, in this embodiment, when the verify voltage switching signal VC is at the low level, the MOSFET Q11 is turned on, the potential of the node n11 is supplied to the non-inverting input terminal of the operational amplifier OP, and the output voltage of the operational amplifier OP. Vout is set to a potential such as 2.0 V, and this is supplied to the selected word line as a verify voltage Vwv1. When the verify voltage switching signal VC is set to the high level, the MOSFET Q12 is turned on, and the potential of the node n12 higher than the potential of the node n11 is supplied to the non-inverting input terminal of the operational amplifier OP, and the output of the operational amplifier OP The voltage Vout is set to a potential such as 2.05 V, and this is supplied to the selected word line as the verify voltage Vwv2.
[0052]
That is, when the MOSFET Q11 is turned on and the low potential of the node n11 is supplied to the non-inverting input terminal of the operational amplifier OP, the output voltage Vout of the operational amplifier OP becomes a potential such as 2.0 V, and the MOSFET Q12 is The resistor ladder RLD0 is configured so that the output voltage Vout of the operational amplifier OP becomes a potential such as 2.05 V when turned on and the high potential of the node n12 is supplied to the non-inverting input terminal of the operational amplifier OP. The resistance ratio has been determined.
[0053]
FIG. 12 shows another specific example of a circuit that generates a verify voltage switching signal. The verify voltage switching signal generation circuit of the embodiment of FIG. 7 is a complete hardware system that forms a verify voltage switching signal in which the level of the write pulse is changed between odd and even times based on the verify read signal. Whereas the circuit is provided, this embodiment is provided with a register CCR for setting the switching state of the verify voltage, and controls the verify voltage switching circuit configured similarly to FIG. 9 by the bit signal of this register CCR. The flash controller FLC sets which verify voltage is supplied to the word line according to the write control program. The verify voltage switching control register CCR can be provided in the flash controller FLC.
[0054]
The verify voltage switching signal generation circuit of the embodiment of FIG. 7 is effective only when performing control according to the flow of FIG. 4 in which the number of application of the write pulse is switched between the odd number and the even number. The embodiment circuit of FIG. 12 can be used not only for such control but also for performing control according to the flow of FIG. 5 for switching the verify voltage when the number of application times of the write pulse reaches a predetermined number. It is.
[0055]
FIG. 13 shows another embodiment in which the sensitivity of the sense amplifier is switched by a switching signal in accordance with the number of application of the write pulse, instead of switching the verify voltage in accordance with the number of application of the write pulse.
[0056]
That is, in this embodiment, two p-channel MOSFETs Q21 and Q22 are connected in parallel between the input terminal of the inverter SA as a sense amplifier and the power supply voltage terminal Vcc, and the sense amplifier is connected to the gate of one MOSFET Q21. The sensitivity switching signal SC is applied to the gate of Q22 and the signal / SC obtained by inverting it with the inverter INV4. Specifically, the gate width of each MOSFET so that W1 / L1 (ratio of gate width W to gate length L) of MOSFET Q21 is larger than W2 / L2 of Q22 (W1 / L1> W2 / L2). And the gate length is designed.
[0057]
Therefore, in the circuit of this embodiment, when the sense amplifier sensitivity switching signal SC is at the low level, the MOSFET Q21 having a relatively small on-resistance is turned on, whereas the sense amplifier sensitivity switching signal SC is at the high level. When changed, Q21 is turned off and MOSFET Q22 having a larger on-resistance is turned on. Therefore, the sensitivity of the inverter SA as a sense amplifier is increased when the MOSFET Q22 is turned on, and operates in the same manner as when the verify voltage of the word line is increased in the above embodiment.
[0058]
The sense amplifier sensitivity switching signal SC for controlling the circuit of this embodiment is supplied from a signal formed by a circuit similar to the verify voltage switching signal generation circuit of the embodiment of FIG. 7 or from the register CCR shown in FIG. Can be used.
[0059]
In FIG. 13, MC1 and MC2 are memory elements as memory cells, BL is a bit line to which the drains of the elements constituting the memory cells are connected, WL is connected to a control gate of the elements constituting the memory cells, and a verify voltage C-SW is a column switch circuit that selectively connects an arbitrary bit line in the memory array to the sense amplifier SA based on a decode signal from a column decoder (not shown).
[0060]
The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment, the flash memory of the type in which the threshold value of the memory element is increased by the erasing operation and the threshold value of the memory element is decreased by the writing is described. The present invention can be similarly applied to a flash memory of a type in which the threshold value of the memory element is increased by lowering the threshold value and writing and a semiconductor integrated circuit incorporating the same.
[0061]
In the embodiment, the write pulse application count is counted by the program to switch the write verify voltage. However, a counter circuit for counting the write pulse application count is provided, and the program applies the write pulse by referring to the counter. The write verify voltage may be switched by determining the number of times. The verify voltage to be switched may be three or more stages instead of two stages as in the embodiment.
[0062]
Furthermore, in the above-described embodiment, the case where the write verify voltage is switched by counting the number of write pulse applications has been described. However, the erase verify voltage is counted and the erase verify voltage is switched in a direction that gives a margin according to the number of erases. It can also be applied to.
[0063]
In addition, the configuration has been described in which the voltage is determined by switching the verification condition to a relaxed voltage with respect to the predetermined voltage, but on the contrary, the verification is performed at a voltage stricter than the predetermined voltage and the condition is restored to the predetermined voltage. A configuration in which the determination is made by switching may be used.
[0064]
In the above description, the case where the invention made by the present inventor is applied to a microcomputer having a built-in flash memory, which is a field of use as a background, has been described. However, the present invention is not limited thereto, and FIG. 1 can be widely used for a nonvolatile memory having the same configuration as the flash memory circuit FLASH and the flash controller FLC shown in FIG. 1 and a semiconductor integrated circuit incorporating the nonvolatile memory.
[0065]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0066]
That is, according to the present invention, it is possible to reduce the time required for writing in a semiconductor integrated circuit such as a nonvolatile semiconductor memory and a microcomputer incorporating the nonvolatile semiconductor memory.
[Brief description of the drawings]
FIG. 1 is an overall block diagram showing an outline of an embodiment of a microcomputer incorporating a flash memory to which the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration example of a flash memory circuit unit.
FIG. 3 is an explanatory diagram showing a configuration example of a control register in the flash controller.
FIG. 4 is a flowchart showing a procedure of an embodiment of writing by a flash controller and its verify control.
FIG. 5 is a flowchart showing a procedure of a second embodiment of writing by the flash controller and its verify control.
FIG. 6 is an explanatory diagram showing how the verify voltage is switched and the distribution of the threshold value is changed when the write verify control is performed according to the write verify operation procedure of the embodiment;
FIG. 7 is a circuit configuration diagram showing one embodiment of a circuit for generating a verify voltage switching signal.
8 is a timing chart showing the operation timing of the verify voltage switching signal generation circuit of FIG.
FIG. 9 is a circuit configuration diagram showing one embodiment of a verify voltage switching circuit;
FIG. 10 is a circuit configuration diagram showing another embodiment of the verify voltage switching circuit.
FIG. 11 is a circuit configuration diagram showing another method of the verify voltage switching circuit.
FIG. 12 is a circuit configuration diagram showing another method of the verify voltage switching circuit.
FIG. 13 is a circuit configuration diagram showing an embodiment in which the sense-up sensitivity is changed instead of the verify voltage switching.
FIG. 14 is a cross-sectional explanatory view showing a typical structure of a memory element of a flash memory and an example of an applied voltage in each operation mode.
FIG. 15 is an explanatory diagram showing how a verify voltage is switched and a distribution of threshold values is changed when a write verify control is performed in accordance with a general write verify operation procedure;
FIG. 16 is a flowchart showing a write operation procedure in a general flash memory.
[Explanation of symbols]
11 Memory array
12 Data register
13 Writing circuit
14 Address register
15 X decoder
16 Y decoder
25 Power supply circuit
26 Power supply switching circuit
FLC flash controller
CNTR control register
CCR switching control register

Claims (8)

In a non-volatile semiconductor memory configured to store data by changing the threshold value of the memory element by controlling the voltage to be applied, a voltage that relaxes the verification condition according to the number of times of application of the write voltage to the same memory element A non-volatile semiconductor memory configured to read the data and determine the end of the writing. A differential amplifier circuit in which a reference voltage is applied to a non-inverting input terminal, a resistor ladder connected in series between the output terminal of the differential amplifier circuit and a ground point, and a node in the resistor ladder And a plurality of switching means connected in parallel between the differential amplifier circuit and the inverting input terminal of the differential amplifier circuit, and a verify voltage switching signal obtained by applying a verify voltage switching signal to the control terminals of these switch means The nonvolatile semiconductor memory according to claim 1, further comprising a circuit. And a means for counting the number of times of application of the write voltage, wherein the verify voltage switching circuit is switched by the verify voltage switching signal when the count value of the counting means reaches a predetermined number. The nonvolatile semiconductor memory according to claim 2. 4. The nonvolatile semiconductor memory according to claim 3, further comprising a switching control register for controlling the verify voltage switching circuit, wherein the verify voltage switching signal is generated by setting of the register. . 3. A semiconductor integrated circuit comprising the nonvolatile semiconductor memory according to claim 1 and a control circuit for controlling the nonvolatile semiconductor memory to perform writing and verifying operations. 6. The control circuit according to claim 5, wherein the control circuit is configured by a circuit of a program control system, and the control circuit is configured to count the number of write pulse applications to the storage element according to a program. Semiconductor integrated circuit. The control circuit includes a switching control register for controlling the verify voltage switching circuit, and the control circuit rewrites the register when the number of write pulse application times to the storage element reaches a predetermined number to switch the verify voltage. The semiconductor integrated circuit according to claim 6, wherein the semiconductor integrated circuit is configured to generate a signal. In a nonvolatile semiconductor memory configured to store data by changing a threshold value of a memory element by controlling a voltage to be applied, the sensitivity of an amplifier circuit for a read signal according to the number of times of applying a write voltage to the same memory element A non-volatile semiconductor memory configured to determine the end of writing by performing a read operation with a loosening of the memory.

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