JP3213434B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Documents describing the prior art relating to a nonvolatile semiconductor memory device to which the present invention is directed are listed below.

Reference 1: A 16Kb Electrically Erasable N
onvolatile Memory 1980 IEEEE ISSCC Dig.Tech.Pap. pp.152-153 271 1980 Reference 2; Analysis and Modeling of Floating-Gate EEP
ROM Cells IEEE Trans. Electron Devices 1986 June ED-33 No.6 pp.835-844 Literature 3: Semiconductor MOS memory and how to use it pp.96-101 Published by Nikkan Kogyo Shimbun, 1990 Literature 4; A NOVEL CELL STRUCTURE SUITABLE FOR A 3 VO
LT OPERATION, SECTOR ERASE FLASH MEMORY IEDM 92 pp.599-602 (1992) Reference 5; FLASH EEPROM MEMORY SYSTEMS HAVING MULTIST
ATE STORAGE CELLS UNITED STATES PATENT NO. 5043940 (1991)

A non-volatile semiconductor memory device (P
ROM) has been developed and put to practical use since the early 1970s. Further, since the 1980's, a semiconductor memory device (hereinafter referred to as an EEPROM) capable of electrically rewriting stored information and having non-volatility has been put into practical use (see Document 1). As a method of storing the memory cell of the EEPROM, the threshold voltage of the transistor is controlled by injecting and discharging charges through a thin oxide insulating film through a thin oxide insulating film into a memory cell having a transistor structure having a floating gate. Is known (see Documents 1 and 2). In this case, the threshold voltage of the memory cell increases by injecting electrons into the floating gate, and decreases by injecting holes by emitting electrons.

[0005] The functional circuit block of this EEPROM is as follows.
For example, as shown in FIG. 2 of Reference 3, a circuit block of a conventional EEPROM is shown in FIG. 5 for comparison with the present invention. FIG. 5 shows 144 memory cells in 4 columns and 36 rows that can simultaneously read and program 9-bit data. This circuit block includes a decoder circuit, a multiplexer, an address buffer, a chip control circuit, and a high voltage generator / decoder for selectively performing programming, erasing, and reading for 144 memory cells.
It has a control circuit, a program circuit, a sense circuit, a data input buffer, and a data output buffer.

In FIG. 5, reference numerals 501 to 504 denote address input terminals for inputting addresses of memory cells selected by column lines and row lines, and 505 to 507 input control signals for controlling the operation mode of the EEPROM. 505, a chip selection signal, 506, an output selection signal, and 507, a write signal. 508
Numerals 516 denote data input / output terminals for outputting data stored in the selected memory cell in the read mode and inputting data to be stored in the memory cell in the write mode.

Address buffers 517 to 520 have a function of buffering an address input and a function of receiving a power down signal to reduce the current consumption of the input section. There is also known a conventional technique in which a function of receiving a latch signal and latching an address input in a write mode is added to an address buffer (see Reference 3).

Reference numeral 521 denotes a chip control circuit which generates a read mode, a write mode, a power down mode (or a standby mode), and an output non-select mode in accordance with control inputs from control input terminals 505 to 507.
The chip control circuit 521 also has a function of automatically terminating the erase mode or the program mode using an internal timer. Note that the write mode is divided into two modes: an erase mode and a program mode. Here, the erase mode is
In order to rewrite the storage data of the memory cell, the memory cells of the byte, column line, and memory block to which the selected memory cell belongs are erased (the threshold voltage of the memory cell is higher (or lower) than the gate voltage at the time of reading). The program mode is to bring the selected memory cell into a programmed state (a state in which the threshold voltage of the memory cell is lower (or higher) than the gate voltage at the time of reading) according to the input data. It is. When rewriting data in a memory cell, first, the memory cell is set to an erased state in an erase mode, and then the memory cell is set to a program state according to input data. That is, the write mode has an erase mode and a program mode.

A column decoder 522 decodes the outputs of the address buffers 517 and 518, applies a high (H) voltage only to a column line (word line) of a selected memory cell, and outputs a column of a non-selected memory cell. A low voltage is applied to the line. The high voltage at the time of selection is close to the power supply voltage at the time of reading, but is high at the time of writing.

Reference numeral 523 denotes a row decoder which decodes the output of the address buffer and applies a high voltage to a selected row line (bit line), a low voltage to a non-selected row line, and a multiplexer 5
29 to 537.

Reference numeral 524 denotes a high voltage generation / control circuit which boosts the power supply voltage of the EEPROM at the time of writing to 10 to 2
It has a circuit (charge pump circuit) that generates a high voltage of about 5 V, and a control circuit that supplies a desired high voltage to each circuit in the EEPROM according to an erase mode or a program mode.

Reference numeral 525 denotes a sense circuit which transmits data of a memory cell selected in a read mode to a data line 614 via a row line and multiplexers 529 to 537. Alternatively, the magnitude of the current value is detected and amplified, and the data output buffer 52
7 is output.

A program circuit 526 receives a program mode signal and a high voltage, and outputs a high voltage to a low voltage by data input to the data line 614. On this occasion,
A conventional EEPROM can output only one high voltage value and one low voltage (normally 0 V).

The data output buffer 527 outputs data from the sense circuit 525 to an output terminal in a read mode. Further, it has a function of inhibiting output in the power down mode and the output non-selection mode.

Reference numeral 528 denotes a data input buffer which buffers data input from the input / output terminal 516 and outputs data to the program circuit 526 in the write mode. There is also a data input buffer having a function of receiving a latch signal in a write mode and latching data input.

The multiplexers 529 to 537 are connected to the row line and the data line 6 selected according to the signal of the row decoder 523.
14, 629-636. The high voltage of the output of the row decoder 523 is near the power supply voltage at the time of reading, and is a high voltage at the time of writing.

617 to 620 are column lines;
72 is a row line, 625 to 628 are memory sense program lines, and 542 to 557 are memory cells (the memory cells 542 to 557 are shown in FIGS.
It is connected to the structure shown in In the memory cell of FIG. 3 of Document 1, the column line is connected to the gate of the select transistor,
The row line is connected to the drain of the select transistor, and the memory sense program line is connected to the gate of the memory transistor. ).

Each of MARY1 to MARY3 includes four rows and four columns of memory cell arrays MARY01 to MARY03 having the same transistor and connection, and includes column lines 617 to 620 of each of the memory cell arrays MARY01 to MARY03, memory sense program lines 625 to 628, and memory. This is a 12-row, 4-column memory cell array in which ground lines 610 are connected to each other.

The DIO 1 is a circuit composed of a program circuit, a sense circuit, a data input buffer, and a data output buffer. The data line is 614, and the input / output terminal is 516. 615 is an output of the data input buffer 528 and an input of the program circuit 526, and 616 is an output of the sense circuit 525 and an input of the data output buffer 527. And DIO2 ... DI
O9 is also a circuit having the same configuration as DIO1, the data lines are 629 to 636, and the input / output terminals are 508 to 636.
515.

601 is an output of the address buffer 517 and an input of the column decoder 522, 602 is an output of the address buffer 518 and an input of the column decoder 522, and 603 is an output of the address buffer 519 and an input of the row decoder 523. , 604 is the address buffer 5
20 and the input of the row decoder 523;
624 are the outputs of the row decoder 523 and the inputs of the multiplexers 529-537.

A power down signal 605 of the chip control circuit 521 is connected to each of the inputs of the address buffers 517 to 520. Reference numeral 606 denotes a read enable signal, which is a sense circuit 5 for DIO1 to DIO9.
Activate or deactivate 25. Reference numeral 607 denotes a program signal.
The program circuit 526 of the IO 9 is activated, the high voltage generation / control circuit 524 outputs a high voltage to the high voltage lines 608 and 609, and the memory sense line 611 is set to 0V.
Reference numeral 673 denotes an erasing signal which generates a high voltage in the erasing mode.
A high voltage is output from the outputs 608 and 611 of the control circuit 524. A data input enable signal 612 activates the data input buffers 528 of DIO1 to DIO9 in the write mode. Reference numeral 613 denotes a data output enable signal, which is DIO1 to DI0 in the read mode.
The O9 data output buffer 527 is activated.

Reference numeral 608 of the high voltage generation / control circuit 524 is a first high voltage signal.
22 and a high voltage to the row decoder 523. 61
1 is a memory sense signal, which is 0 V during programming,
At the time of erasing, the voltage is high and at the time of reading, the voltage is between 0 V and the power supply voltage. 609 is a second high voltage signal;
High voltage during programming.

538 to 541 transmit the memory sense signal 611 of the high voltage generation / control circuit 524 to the column lines 617 to 620.
And outputs the signals from the memory sense program lines 625 to 628.

Next, the write operation and read operation of the conventional EEPROM will be briefly described. At the time of reading, first, the control signals of the control signal input terminals 505 to 507 are set to the read mode, and the address input terminals 501 are set.
Enter the selected address in 〜504. Input addresses are buffered in address buffers 517-520,
The data is decoded by the column decoder 522 and the row decoder 523.

There are four output signals from the column decoder 522, which are connected to column lines 617 to 620, respectively. One selected column line is at a high voltage (near normal power supply voltage) and the other three The book is at low voltage. Furthermore, row decoder 5
23, one of the row lines 637 to 640 is selected by the outputs 621 to 624 and the multiplexer 529.
Only one selected row line is electrically connected to data line 614 with low impedance.

Similarly, the output 62 of the row decoder 523
1 to 624 and the multiplexer 530,
By 21 to 624 and 531, also 621
624 and 537 electrically connect the selected row line to the data lines 629 to 636 with low impedance. At this time, a voltage for detecting the threshold value of the memory cell, for example, 2 to 4 V is output to the memory sense line 611, and the memory sense program line selection circuits 538 to 541 are output.
, The threshold detection voltage is applied only to the selected memory sense program line. Memory ground line 6
10 is a ground state.

A voltage is supplied to the row line of the selected memory cell from a corresponding sense circuit (for example, 525 in DIO1). If the threshold voltage of the memory cell is lower than the threshold detection voltage, Then, the memory cell transistor becomes conductive, and current flows from the row line to the memory ground line 610. When the threshold voltage of the memory cell is also high, the memory cell transistor is off, and no current flows from the row line to the memory ground line 610. The voltage of the row line is set by the sense circuit, and the current to the row line at the time of reading is supplied from the sense circuit. By detecting and amplifying the presence or absence of the current, the data stored in the memory cell is output as a high voltage or a low voltage to 616 in DIO1, for example, via a data input buffer 527. Read outside. For example, a high voltage is output to the input / output terminal 516 when the threshold value of the memory cell is as high as 6 V, and a low voltage is output when the threshold value of the memory cell is as low as 0 V. The function of the sense circuit and data input buffer is DIO2
The same applies to DIO9.

In the case of a write operation, first, a memory cell is erased. In the case of this conventional example, erasing is performed in units of column lines, but may be performed in units of bytes or blocks, and there is no particular limitation. In the case of this conventional example, the input of the erasing mode is based on the control inputs 505 to 507.
There is also a technique for enabling the erase mode by input data to the data input buffer 528 in addition to the control input. When the erase mode is input, a column line is selected by the address inputs 501 and 502. The high voltage line 608 becomes high voltage, the selected column line becomes high voltage, and the other column lines become 0V. The memory sense line 611 also has a high voltage, and the memory sense program lines of the column lines selected by the memory sense program line selection circuits 538 to 541 also have a high voltage.

The sense circuits and program circuits of DIO1 to DIO9 (for example, 525 and 526 in DIO1)
Are inactivated at the time of erasing, and each data line 614, 6
29 to 636 are 0 V or floating. The memory ground line 610 is in a ground state at the time of erasing.
Therefore, a high voltage (for example, 20 V) is applied to the gate of the memory cell on the selected column line, and the drain and the source are grounded. At this time, the Farrner-Heim tunnel phenomenon occurs, electrons are injected from the drain to the floating gate, and the threshold value of the memory cell transistor becomes high (for example, 5 to 8 V).

When programming an erased memory cell, a program mode is input and an address input terminal 50 is set.
Enter the address to be programmed in 1 to 504. During programming, high voltage line 608 is high voltage,
11 is 0 V, the high voltage line 609 is high voltage, and the memory ground line 610 is floating. In addition, the column decoder 522, the row decoder 523, each program circuit and each data input buffer of DIO1 to DIO9 are activated, and each sense circuit and each data output buffer are inactivated. For example, when a low voltage is input to the input / output terminal 516 as a data input, the program circuit 526 outputs a high voltage (for example, 20 V) to the data line 614, and when a high voltage is input to the input / output terminal 516, the data line 6
0V is output to 14. When the data line 614 is at a high voltage, the selected signal among the signals 621 to 624 is also at a high voltage.
V). Since the selected column line is also at a high voltage and the memory sense program line is at 0 V, 0 V is applied to the gate of the memory cell transistor and a high voltage (for example, 20 V) is applied to the drain. At this time, electrons are emitted from the floating gate to the drain and holes are injected from the drain to the floating gate due to the Faraday-Heim tunnel phenomenon, so that the threshold voltage of the memory cell transistor falls, for example, from 0V to -3V.

In order to improve the reliability of data of the semiconductor memory device, for example, the input / output terminals 508 to 51 shown in FIG.
There is also a technique in which one of the six bits is used as a parity bit to detect the presence or absence of an error in information stored in a memory cell.

[0032]

As described above, the conventional EEPR
Although the circuit function of the OM has been described, the Farrer-Nheim tunnel current as a storage principle is proportional to the electric field applied to both ends of the insulating film (see Reference 2), and the threshold voltage of the memory cell transistor changes due to this. Changes linearly depending on the high voltage value at the time of erasing or programming (see Document 2). In a conventional EEPROM,
Only one high voltage value is used at the time of erasing or programming, and the threshold value is high or low at the time of reading.
Only values could be detected.

In view of the above-mentioned drawbacks of the prior art, a main object of the present invention is to provide a nonvolatile semiconductor memory device capable of realizing an increase in memory capacity and an improvement in data reliability. .

[0034]

In order to achieve the above object, according to the present invention, two or more data are inputted into an EEPROM at the time of programming, and the data is inputted in accordance with a combination of two or more data. A program high voltage of four or more values is generated, a threshold of four or more values is stored in a memory cell, and information of two bits or more is stored. Further, in order to detect two or more bits of information from memory cells having four or more threshold values, three or more reference memory cells having a plurality of threshold values are provided, and the selected memory cell is compared with the plurality of reference memory cells. And a sense circuit. In addition, a method of storing parity bits together with data in a semiconductor memory device that stores two or more bits of information in a memory cell is provided. For example, when three bits of information are stored in one memory cell, one bit per byte (eight bits) is set by setting one bit of the nine bits of information that can be stored in three memory cells to a parity bit. Is provided. Further, when the correspondence between the threshold voltage and the input / output information at the time of storing in the memory cell is shifted to the next higher or lower threshold voltage, the input / output information becomes 1
The association is performed so that only the bits change.

[0035]

According to the present invention, a multi-value program high voltage is generated, and a predetermined high voltage is applied to a memory cell in accordance with input data, thereby providing not only a binary threshold but also a plurality of threshold values for the memory cell. Can be. For example, when there is a 3-bit data input, by providing eight high voltage values, combinations of data inputs (001), (000),
(010), (011), (111), (101),
(100) and (110). Thereby, the threshold value of the memory cell is changed in proportion to the program voltage value. For example, the program voltage is set to 22V for the input of (001), 20V for (000), and so on.
..., there is a proportional relationship between the program voltage and the threshold value of the memory cell.
The threshold value can be set to -1.5 V for V, -0.5 V for 20 V, and so on.

In order to perform reading in accordance with the threshold value of the memory cell, a reference memory cell corresponding to the threshold value of the memory cell is provided. For example, three-bit data is restored. Further, by providing the parity, it is possible to realize improvement in data reliability in a semiconductor memory device capable of storing information of 2 bits or more in a memory cell.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is an EEPROM of the present invention, and FIG.
FIG. 3 shows a sense circuit in FIG. In FIG. 1, 101 to 106 are address input terminals, 107 to 109 are control input terminals, 111 to 119 are data input / output terminals, 120 to 125 are address buffers, 126 is a chip control circuit, and 127 is a high voltage generation / Control circuit, 128 is a column decoder, 129 is a row decoder, 1
47 to 162 are memory cells, MARY01 to MARY03 are memory cell arrays of 4 rows and 4 columns, MARY1 to MARY3
Is a line connecting the MARY01 to MARY03 column lines, the memory sense program lines, and the memory ground lines to each other.
Memory cell array of 2 rows and 4 columns, 143 to 146 are memory sense program line selection circuits, 131 to 133 are multiplexers, 141 is a program circuit, 142 is a sense circuit, 134 to 136 are data input buffers, 137 to 1
39 is a data output buffer, and DIO1 to DIO3 are circuits composed of a program circuit, a sense circuit, three data input buffers, and three data output buffers. Note that the memory cell is for injecting charge into the floating gate through a thin insulating film, but the shape is not particularly limited.

In the connection relationship shown in FIG. 1, reference numeral 201 denotes an output of the address buffer 120 and an input of the column decoder 128,
2 is the output of the address buffer 121 and the column decoder 128
203, the output of the address buffer 122 and the input of the row decoder 129; 204, the output of the address buffer 123 and the input of the row decoder 129;
Is connected between the output of the address buffer 124 and the input of the row decoder 129, and 206 is connected between the output of the address buffer 125 and the input of the row decoder 129.

Numerals 222 to 225 denote column lines (word lines), each of which is a memory cell array MARY01 to MARY.
The selection gate of Y03 and the memory sense program line selection circuits 143 to 146 are connected as outputs of the column decoder 128. Reference numerals 226 to 237 connect the output of the row decoder 129 and the inputs of the multiplexers 131 to 133. 24
6 to 281 are row lines (bit lines) that connect the drains of the memory cell arrays MARY01 to MARY03 and the multiplexers 131 to 133.

Reference numeral 207 denotes a power down signal, which is an output of the chip control circuit 126 and each of the address buffers 120-1.
25 inputs. Reference numeral 208 denotes a read enable signal, which is an output of the chip control circuit 126 and DIO1 to DIO1.
The input of each sense circuit of DIO3 is connected. Reference numeral 209 denotes a program enable signal.
6 is connected to the input of each of the program circuits DIO1 to DIO3 and the high-current generation / control circuit 127. 210
Is an erase signal, which connects the output of the chip control circuit 126 and the input of the high-voltage generation / control circuit 127. Reference numeral 211 denotes a data input enable signal, and the chip control circuit 126
Are connected to the inputs of the data input buffers DIO1 to DIO3. Reference numeral 212 denotes a data output enable signal, which is an output of the chip control circuit 126 and DIO1 to DI
Connect the input of each data output buffer of O3.

Numerals 215, 244 and 245 denote data lines.
To DIO3 input / output. In the DIO 1, 216 to 218 connect the outputs of the data input buffers 134 to 138 and the input of the program circuit 141, and 219 to 221 connect the output of the sense circuit 142 and the data output buffers 137 to 139. Connect to input.

A high voltage line 238 connects the output of the high voltage generation / control circuit 127 with the inputs of the column decoder 128 and the row decoder 129. A memory sense voltage line 214 connects the output of the high voltage generation / control circuit 127 to the inputs of the memory sense program line selection circuits 143 to 146. A program high voltage line 213 connects the output of the high voltage generation / control circuit 127 to the input of each of the program circuits DIO1 to DIO3. A memory ground line 239 connects the output of the high voltage generation / control circuit 127 to the source terminals of the memory cell arrays MARY1 to MARY3. Address input terminals 101 to 10
6 is connected to the input of each address buffer 120-125, the control input terminals 107-109 are connected to the input of the chip control circuit 126, and the data input / output terminals 117-1
19 is a data input buffer 134 of DIO1
136 to 136 input and data output buffers 137 to 139
Data input / output terminals 114 to 116
Are connected to a data input buffer and a data output buffer of DIO2.
Connected to the data input buffer and data output buffer of O3.

The EEPROM of FIG. 1 has at least a read mode, a write mode, a power down mode (or a standby mode), and an output non-select mode as operation modes. The write mode is further divided into an erase mode and a program mode.

In the operation of the present EEPROM in the read mode, first, the inputs of the control input terminals 107 to 109 are set to the read mode, and the address to be read is input to the address input terminals 101 to 106. Input addresses are buffered by address buffers 120-125,
The outputs of the two address buffers 120 and 121 are decoded by the column decoder 128 into four of the column lines 222 to 225, one of these four being a high voltage and the other three being a low voltage. And four address buffers 122
To 125 are supplied to the row line 22 by the row decoder 129.
6 to 237, and the multiplexer 1
31 to 133, one out of twelve row lines is brought into conduction with the data lines 215, 244, 245, respectively. By decoding column lines and row lines, three of the memory cells
(For example, the memory cell 150 at the intersection of 222 and 246 in MARY 1 and the M in MARY 2 and MARY 3
The memory cell corresponding to the position of the memory cell 150 of ARY1 is selected.

The control signals 207 to 212 deactivate the high voltage generation / control circuit 127 and each of the program circuits DIO1 to DIO3 and the data input buffer, 238 becomes near the power supply voltage, and 214 becomes 3V, for example. 213 becomes a low voltage, for example, and 239
Is the ground voltage, the output of each data input buffer in DIO1 to DIO3 and the input of each program circuit is a low voltage. Here, each of the sense circuits DIO1 to DIO3 is activated when 208 of the chip control circuit 126 becomes, for example, a high voltage, and performs amplification, comparison detection and data restoration of the voltage of the row line appearing on the data line. Output to each data output buffer. The data output buffer buffers the output of the sense circuit, and the data input / output terminal 1
The data stored in the memory cell is output to 11 to 119.

In the erase mode, first, the control input terminal 107
To 109, the erase mode is set.
The column line address to be erased is input to 1, 102. The output signal of the chip control circuit 126 is, for example, 207 becomes a low voltage, 208 becomes a low voltage, 209 becomes a low voltage, 210 becomes a high voltage, 211 becomes a low voltage, and 212 becomes a low voltage. And 127 is activated,
The program circuits, sense circuits, and data output buffers of DIO1 to DIO3 are deactivated. High voltage generation /
The output 238 of the control circuit 127 is a high voltage (for example, 20 V)
And 214 becomes a high voltage (for example, 20 V), and 21
Reference numeral 3 indicates a low voltage or a power supply voltage, and reference numeral 239 indicates a ground voltage. As a result, the output 222 of the column decoder 128
225 becomes high voltage (for example, 20 V). Also, the memory sense program line 240
243 (for example, 240) also becomes a high voltage (for example, 20 V). Therefore, the gate of the memory cell transistor having the floating gate of the selected column line becomes 20 V, the source becomes the ground voltage, and the drain becomes the ground voltage (since the memory cell transistor becomes conductive by the gate voltage), The Farrner-Nheim tunnel phenomenon occurs, and the threshold voltage increases to, for example, 4V.

In the program mode, first, the program mode is set at the control input terminals 107 to 109, and an address to be programmed is input to the address input terminals 101 to 106. The output signals of the chip control circuit 126 are, for example, 207 and 208 at low voltage, 209 at high voltage, 210 at low voltage, 211 at high voltage, 212 at low voltage, and high voltage generation. / Control circuit 127 and the program circuits of DIO1 to DIO3 and the data input buffer are activated, and the sense circuits of DIO1 to DIO3 and the data output buffer are deactivated. Then, the output 238 of the high voltage generation / control circuit 127 becomes a high voltage (for example, 23 V), 214 becomes the ground voltage, and 2
13 becomes a high voltage (for example, 23 V), and 239 becomes a high impedance state. As a result, the column decoder 128
Of the outputs 222 to 225 of the row decoder 129 have a high voltage (for example, 23 V), and one of the outputs 226 to 237 of the row decoder 129 have a high voltage (for example, 23 V). The portion of the multiplexer is strongly turned on, and makes the row line and the data line conductive.

Input data at the time of programming is inputted from the data input / output terminals 111 to 119 substantially simultaneously with the address, buffered by the data input buffer, and sent to the program circuit. In the program circuit, the input data is converted into a program voltage, and a predetermined program voltage corresponding to the predetermined input data is output to the data line. In the case of the present embodiment, one of eight different voltage values (for example, 22 V, 21 V, 20 V,..., 15 V) is selected as the program voltage value. The program voltage value may be four or eight or more. For example, when the column line 222 and the row line 246 are selected, the row line 246 is connected to the program voltage (for example, 20
V). 214 is a ground voltage, 222 is 23V
Therefore, the memory sense program line 240 goes to the ground voltage via the memory sense program line selection circuit 143. Therefore, 20V is applied to the drain of the memory cell 150.
Is applied and the ground voltage is applied to the gate, so that the threshold value of the memory cell is, for example, −0.0.
It becomes as low as 5V. The threshold value of the memory cell changes in proportion to the program voltage value.

In the present embodiment, the erasing mode, the program mode, and other modes are set only by inputting the control input terminals 107 to 109. However, the present invention is not limited to this. Further, the unit of selection of the memory cell at the time of erasing is the column line unit, but may be the byte unit or the block unit, and is not particularly limited.

FIG. 2 shows the program circuit of FIG. 1 in more detail. In FIG. 2, DI1 is the first
DI2 is a second data input, DI3 is a third data input, VPPX is a high voltage input, PRG is an input and a program enable signal, and VPRG is an output and a program voltage. IV1 to IV3 are inverter circuits, HVSW is a high voltage switch, C1 to C5 are capacitances, MN20 to MN25 are N-channel enhancement type MOS transistors, and MP20 to MP23 are P-channel enhancement type MOS transistors. AND1 to AND9 are two-input or three-input AND circuits (AND) constituted by MOS transistors.
Circuit), and OR1 to OR3 are three-input OR circuits (OR circuits) formed of MOS transistors.

N1 is the output of the OR circuit OR1 and is connected to the gates of the transistors MP20 and MN20. N2 is an output of the OR circuit OR2, and is connected to the gates of the transistors MP21 and MN21. N3
Is the output of the OR circuit OR3, and the transistor MP22
And the gate of MN22. N5 is a ground node, which is connected to the ground potential of the inverter circuit, one end of the capacitance C2, and the sources of the transistors MN20 to MN23. N7 is a transistor MN2
3 and the drains of MP20 to MP23 and the gates of the transistors MP23 and MN23. N
8 is one end of the capacitance C3 and the transistor MP20.
N9 is connected to one end of the capacitance C4, the source of the transistor MP21, and the drain of the transistor MN21. N10 is one end of the capacitance C5, the source of the transistor MP22 and the transistor M
It is connected to the drain of N22. N6 is connected to one end of the capacitance C1, the other ends of the capacitances C2 to C5, and the gate of the transistor MN25. N11 is connected to the source of the transistor MN24 and the drain of the transistor MN25. N12 is the output of the high voltage switch HVSW, and the transistor M
It is connected to the gate of N24. N4 is a power supply node, which is connected to the source of the transistor MP23 and the power supplies of the inverter circuit, the AND circuit, and the OR circuit. The high voltage input VPPX is connected to the other end of the capacitance C1,
The drain of the transistor MN24 and the high-voltage switch H
VSW, the program enable signal PRG is applied to the control input of the high voltage switch HVSW, and each data input DI
1 to DI3 are each inverter circuit IV1 to IV3 and each A
The outputs of the AND circuits AND1 to AND9 are connected to the inputs of the respective OR circuits OR1 to OR3, and the program voltage VPRG is connected to the source of the transistor MN25.

The first data input DI1 in FIG.
1, the second data input DI2 is also denoted by 216, and the third data input DI3 is also denoted by 217.
218, the high voltage input VPPX is 213, the program enable signal PRG is 209, and the program voltage VPRG is 2 of DIO1 in FIG.
15 respectively.

The circuit shown in FIG. 2 is a conversion circuit for converting 3-bit digital data into analog data. When a high voltage (for example, 24 V) is applied to the high voltage input VPPX and the program enable signal PRG becomes a high voltage. , N
6, the voltage values of the capacitances C1 to C5 are as follows.
And N7. N6 voltage = (VPPX voltage · C1 value + N8 voltage · C3 value + N9 voltage · C4 value + N10 voltage · C
5) / CT where CT = C1 + C2 + C3 + C4 + C5

In this circuit, the voltages of N8, N9, and N10 are switched between the ground voltage and the voltage of N7 (for example, a low voltage of about 3 V) according to the input data value, so that N
The voltage of No. 6 can be varied by the values of the data inputs DI1, DI2, DI3. Further, the capacitance C
3, C4, and C5 are different from each other (for example, C3 <
C4 <C5), the data is weighted, and the voltage value of N6 can have a proportional relationship with eight values.

When the voltage of the program enable signal PRG is high, the output N12 of the high voltage switch HVSW becomes a high voltage, the transistor MN24 is turned on,
The program voltage VPRG has a value obtained by subtracting the threshold value of the transistor MN25 from the voltage of N6. When the voltage of N6 is, for example, 21V, the program voltage VPRG is, for example, 20V.
Becomes In the case of the embodiment of FIG. 2, the first and second data inputs DI1 and DI2 are at high voltage and the third data input DI3 is high.
Is a low voltage, the program voltage VPRG becomes the lowest (for example, 15 V), and the first and second data inputs DI
1, when the third data input DI3 is at a high voltage while DI2 is at a low voltage, the program voltage VPRG becomes the highest (for example, 22V). When the program enable signal PRG is at a low voltage, N12 is also at a low voltage, the transistor MN24 is turned off, and the program voltage VPRG becomes floating.

FIG. 3 is a detailed diagram of the sense circuit in FIG. In FIG. 3, RD is a read signal, DO1 is a first data output, DO2 is a second data output, DO3 is a third data output, and DBUS is a memory read data input. IV01 to IV09 are inverter circuits composed of MOS transistors, AND01 to AND04 are 5-input and 7-input logical product circuits (AND circuits) composed of MOS transistors, and OR01 and OR02 are 2-input logical circuits composed of MOS transistors. It is a logical sum circuit (OR circuit).
MP01 to MP06 are P-channel enhancement type MO
SN transistors; MN01 to MN10 are N-channel enhancement type MOS transistors;
L1 to RCEL7 are reference memory cells.

N20 denotes transistors MP01, MN01, M
N21 is connected to the drain of N02 and the gate of MN03.
Is the drain and gate of the transistor MP02 and MN03
N23 is connected to the drain of the transistor MP03, the drain of MN05, and the input of the inverter circuit IV02.
Is the drain and gate of the transistor MP05 and MN07
N26 is connected to the drain of the transistor MP06, the drains of MN09 and MN10, and the gate of MN07, N27 is connected to the source of the transistor MP07, the drain of MP08,
It is connected to the gate of MN09.

DAMP1 is composed of transistors MP03 to MN.
10 and an inverter circuit IV02.
P2 to DAMP7 are circuits having the same transistors and connections as DAMP1.

The read signal RD is output from the inverter circuit IV.
01 is connected to the position corresponding to the gate of the transistor MN04 in DAMP1 to DAMP7, and the output RDV of the inverter circuit IV01 corresponds to the gates of the transistors MP01 and MN01 and the gates of the transistors MN06 and MN10 in DAMP1 to DAMP7. Connected to

The memory read data input DBUS is connected to the gate of the transistor MN02 and the source of MN03, the first data output DO1 is connected to SO1, and the second data output DO1 is connected to SO2.
Is connected to the output of the OR circuit OR01, and the third data output DO3 is connected to the output of the OR circuit OR02. SO1 is the output of the inverter circuit IV02 of DAMP01, and the inverter circuit IV03 and AND
It is an input of the circuit, and SO2 to SO7 are DAMP2
ＤＡDAMP7 are outputs corresponding to the inverter circuit IV02, and are inputs to the inverter circuit and the AND circuit as in the case of SO1.

The output of inverter circuits IV03 to IV09 is A
ND circuit, and the output of the AND circuit is OR circuit OR
01, OR02. REF1 is connected to the source of the transistor MN08 of DAMP1 and the drain of the reference memory cell RCELL1.
REF7 is connected to a portion corresponding to the source of the transistor MN08 in DAMP2 to DAMP7 and to a drain portion of the reference memory cells RCEL2 to RCEL7.

N30 is a ground node, the ground nodes of the inverter circuit, the AND circuit, and the OR circuit, the source terminals of the transistors MN01, MN02, MN04, MN09 and MN10, and the reference memory cells RCEL1 to RCEL.
It is connected to the source part of L7. N31 is a power supply node, which is connected to the power supply nodes of the inverter circuit, the AND circuit, and the OR circuit, the sources of the transistors MP01 to MP06, and the gate of MN08.

The read signal RD in FIG.
08, the memory read data input DBUS is also connected to, for example, 215 of DIO1 in FIG.
1, DO2 and DO3 are, for example, 117 of DIO1 in FIG.
118, 119 respectively.

In the read mode, the read signal RD
Becomes a high voltage and the memory read data input DBUS
Becomes the same potential as the row line of the selected memory cell. Output R
Since DV becomes a low voltage, the transistor MP01 is turned on, MN01 is turned off, and the voltage of N20 rises from 0V. When the voltage of N20 rises, the transistor MN03 is turned on, and the memory read data input DBUS becomes a voltage obtained by subtracting the threshold value of MN03 from N20. However, the memory read data input DBUS
Is higher than the threshold value of the transistor MN02, MN
02 is turned on, and the rise in the potential of DBUS is suppressed.
Therefore, when the read signal RD becomes high, the memory read data input DBUS becomes close to an intermediate value between 0 V and the power supply voltage (for example, 2 V). At this time, if the memory cell to be read is on, a current flows from the memory read data input DBUS to the source of the memory cell, and the potential of DBUS slightly decreases (for example, 1.8 V).
Since the current supply for this is performed via the transistor MP02, by appropriately selecting the transistor size of MP02, the voltage of N21 is greatly reduced as compared with the memory read data input DBUS (for example, from 4.2V to 3.5V). become). Since the voltage of N21 is naturally proportional to the amount of current flowing through the memory cell, the transistors MP01, MP02, MN02, and MN03 amplify the potential fluctuation of the memory read data input DBUS. . Transistors MP03, MP04, MN04, MN0
5. MN06 is a differential amplifier, and N21 and N22 are differential inputs. MP05, MP06, MN07, MN09,
MN10 is a circuit similar to MP01, MP02, MN01, MN02, and MN03, and performs the same operation as REF1 with respect to REF1.

The threshold value of the memory cell to be read is, for example, 4 V, and the reference memory cells RCEL1 to RCEL are used.
7 are, for example, 4.5V, 3.5V, 2.5V,.
Assuming that the voltages are 5 V, 0.5 V, -0.5 V, and -1.5 V, the relationship between the voltages is as follows.
The voltage of F2 <the voltage of DBUS <the voltage of REF1,
SO1 becomes a low voltage, and SO2 to SO7 become a high voltage. The threshold value of the reference memory cell is set in advance in a test mode or the like, and will not be described in detail in this embodiment. As a result, DO1 becomes a high voltage, DO2 and DO2 become high voltage.
3 becomes a low voltage. As described above, the storage information of the memory cell can be read successfully.

FIG. 4 shows input / output terminals (eg, D in FIG. 1) for storing 3-bit information in one memory cell.
3-bit data (D1 to D3 or D11 to D13) to be read and written from IO1 117 to 119), and
It shows the correspondence between bit data and a threshold voltage stored in a memory cell. The upper one corresponds to a higher threshold, and the lower one corresponds to a lower threshold.
With reference to this figure, a description will be given of a change in data due to a change in the threshold voltage of a memory cell and detection of a data error due to parity.

In the program circuit and the sense circuit in the present embodiment, the correspondence between the input / output data and the threshold value of the memory cell is set to a pattern of D11, D12 and D13 (see FIG. 4A). This is to ensure that only one bit of D11 to D13 changes the data when the threshold value shifts to the next higher or lower level. Therefore, FIG.
In the example of -a, the presence or absence of an error in data in which the threshold voltage of the memory cell shifts to the next higher or lower level can be detected by providing a parity bit.

For example, (D11, D12, D13) is
The threshold of the memory cell decreases due to the discharge of the charge, and (11)
When the level changes from 0) to (100),
Since the number of “1” changes from two to one, a parity error occurs, and it is possible to detect a data error. Conversely, when data changes from (100) to (110), an error can be detected in the same manner. (100) and (10
1), data changes between (101) and (111),..., (000) and (001) can also be detected as errors.

On the other hand, when the input / output data and the threshold value of the memory cell correspond to each other as (D1, D2, D3),
For example, (110) and (101), (010) and (00)
Since a change in data between 1) does not result in a parity error, an error cannot be detected (see the portion marked * in FIG. 4B).

From the above, in the present embodiment, the correspondence between the threshold value of the memory cell and the input / output data when storing the data in the memory cell is represented by (D11, D12, D13). An error in which at least the threshold value of the memory cell changes to the next higher or lower level can be detected as a parity error.

While one embodiment of the present invention has been described in detail, other embodiments can be easily considered without departing from the gist of the present invention. For example, in the present embodiment, the program voltage value at the time of programming is generated by the program circuit, but this may be included in the high voltage / generation control circuit and other circuits.

In this embodiment, the program voltage value is changed at the time of programming. However, if the memory cell can have a threshold value corresponding to the input / output information, the program voltage value may be changed. The width or the number of application of the program voltage may be changed.

In the present embodiment, the reference memory cell is included in the sense circuit. However, there is no problem if the reference memory cell is included in the memory cell array.

In the present embodiment, the memory cells are given an eight-valued threshold value for convenience of explanation, but may be of course more than eight.

Although the function of the EEPROM in this embodiment has been simplified for convenience of explanation, the effectiveness of the present invention is not lost even if other functions are added thereto. For example, a verify mode after programming or the like can be easily added.

The memory cell in this embodiment includes a transistor having a floating gate and a select transistor. However, the present invention is not limited to this. The threshold voltage of the memory cell is proportionally controlled by a program voltage during programming. Any configuration can be used as long as it is variable (see memory cells described in References 4 and 5).

Further, in the semiconductor memory device of this embodiment,
Although one bit is provided for one byte (8 bits), the ratio of the number of data and the number of parity bits may be more or less.

In this embodiment, data and parity bits are stored together in one memory cell. However, a memory cell for storing data and a memory cell for storing parity bits are separately provided. It may be provided.

[0080]

As described above, the effect of the present invention is clear by comparing the conventional example shown in FIG. 5 with the embodiment of the present invention shown in FIG. In the conventional example of FIG.
Although there are four address inputs and nine outputs for four, in the embodiment of the present invention of FIG.
There are six address inputs and nine outputs for each. That is, according to the present invention, it is possible to store and read out data twice or more (three times in this embodiment) with respect to the same number of memory cells as in the prior art, and to reduce the capacity of the semiconductor memory device. Can be increased dramatically. In other words, when compared with the same storage amount, the number of memory cells of the present invention can be reduced to half or less as compared with the conventional technology, so that the chip area when integrated is reduced to about half, and cost reduction is achieved. The effect is remarkable. In addition, by storing parity bits together with data in the semiconductor memory device of the present invention, the presence or absence of a data error can be detected, and the reliability of data can be improved. For example, when 1-bit parity is provided for 8-bit data,
Conventionally, 8-bit data and 1-bit parity are stored in one memory cell each. However, according to the present invention, 8-bit data and 1-bit parity bit are stored in three memory cells. Since data is stored in the cell, data reliability can be improved without impairing the increase in memory capacity.

Further, in the present invention, the relationship between the value of data to be written in a memory cell and the threshold voltage of the memory cell, or the relationship between the threshold voltage of the memory cell and the value of data read from the memory cell is determined. By determining that the difference between the values of the write data or read data corresponding to the threshold voltage values adjacent to each other is 1 bit, an error in which the threshold value of the memory cell changes to an adjacent level can be detected as a parity error. Data reliability can be improved.

Further, in the present invention, while achieving the above effects,
The external connection terminal is compatible with the conventional EEPROM, and has the advantage that it is not necessary to reduce the functions of the conventional technology and to add a new terminal for incorporating the present invention. This is because, in the present invention, the program circuit and the sense circuit are configured so that data can be accessed in parallel from a plurality of data input / output terminals.

In addition, the sense circuit of the present invention includes a plurality of reference memory cells having different thresholds,
By comparing the reference memory cell and the memory cell to be read, highly accurate reading can be realized. For example, as another sensing method, a method of detecting the absolute value of the current flowing in the memory cell with a load transistor or the like can be considered. In this method, when the current of the memory cell becomes unstable due to manufacturing variation, it is possible to use the method. It is expected that it cannot be detected. On the other hand, the sense circuit of the present invention does not perform the comparison based on the absolute value of the current, but performs the comparison based on the relative value with respect to the reference memory cell.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a program circuit according to an embodiment of the present invention.

FIG. 3 is a sense circuit according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of an error check method.

FIG. 5 is a circuit diagram showing a conventional technique.

[Explanation of symbols]

 101-106 Address input 107-109 Control input 111-119 Data input / output 120-125 Address buffer 126 Chip control input 127 High voltage generation / control circuit 128 Column decoder 129 Row decoder 222-225 Column line 226-237 Row line 147- 162 memory cell 131-133 multiplexer 141 program circuit 142 sense circuit 134-136 data input buffer 137-139 data output buffer

Continuation of the front page (51) Int.Cl. ⁷ identification code FI H01L 29/788 29/792 (58) Investigated field (Int.Cl. ⁷ , DB name) G11C 16/02 G11C 29/00 631 H01L 27 / 10 421 H01L 29/792

Claims (1)

(57) [Claims] 1. A plurality of electrically programmable memory cells connected in a matrix to a plurality of column lines and a plurality of row lines, and a program data value of 2 bits or more inputted to the semiconductor memory device at the time of programming. And a program circuit capable of applying four or more types of voltages to selected memory cells among the plurality of memory cells in response to the application of the four or more types of voltages to the selected memory cells. Provided four or more different threshold voltages, and two at the time of reading the four or more different threshold voltages.
A sense circuit that takes out the data as bits or more of read data, and stores the parity information of the data together with the data to be written to the memory cell at the time of programming in the memory cell. Integrated to read
A volatile semiconductor memory device, wherein data to be written to the memory cell at the time of programming
And the output voltage value of the program circuit.
The relationship between the threshold voltage of the memory cell and the read time
The threshold voltage of the memory cell and the memory cell
The relationship with the value of the data read from the
Supports adjacent threshold voltages with different threshold voltages
Values of the write data and the read data
Wherein the difference is 1 bit .