JP3767602B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a thin film semiconductor device provided with a CMOS circuit composed of a thin film transistor (hereinafter abbreviated as TFT), a liquid crystal display device including the same, and an electronic apparatus. More specifically, the present invention relates to a technique for individually optimizing the electrical characteristics of each thin film transistor.

A thin film semiconductor device conventionally used for an active matrix substrate of a liquid crystal display device has a structure in which a source / drain region containing a high concentration of a donor element or an acceptor element is formed in a self-aligned manner with respect to a gate electrode. It is common.
(In the present application, this structure is hereinafter abbreviated as S / A.) For example, when a drive circuit such as a shift register is incorporated in a TFT on an active matrix substrate (these TFTs are abbreviated as Dr TFT in the present application), these. However, the CMOS TFT is normally formed as an S / A structure, although the Dr TFT is composed of an N-type TFT and a P-type TFT in a complementary manner (this is abbreviated as a CMOS TFT in the present application). A TFT is also formed as a switching element for each pixel electrode in the pixel region of the active matrix substrate (this is abbreviated as Pi TFT in the present application), and this Pi TFT also has many field S / A structures.

  Thus, in the prior art, all TFTs have an S / A structure. On the other hand, since the impurity concentration in the TFT channel region (acceptor ion concentration for N-type TFTs and donor ion concentration for P-type TFTs) is usually low, the scaling law found in LSIs works. Therefore, in the conventional S / A TFT, the channel length could not be taken as long as about 5 μm or more. As a result, the on-current of the TFT cannot be increased, and there has been a problem that, for example, the drive circuit cannot increase the operation speed. In addition, since the channel length of the TFT cannot be shortened, the gate capacity cannot be reduced. From this point of view, there is a problem that the speeding up of the driving circuit operation is hindered. Furthermore, in the circuit composed of the conventional S / A TFT, the circuit operation deteriorates with time, and the problem is that the circuit operation is stopped in a few minutes. Abbreviated). The reliability of this circuit becomes more serious as the circuit scale becomes larger, the circuit configuration becomes more complicated, and the operation speed becomes faster. Therefore, there is a problem that a high-performance circuit that performs the above cannot be built in the TFT.

  On the other hand, there is a problem that flicker and display unevenness are likely to occur in the pixel region because the off current of the S / A TFT is large.

  Accordingly, the present invention aims to solve the above-mentioned problems, and the object of the present invention is to provide a thin film semiconductor device capable of constructing a circuit capable of operating at high speed by increasing the on-current of the TFT and reducing the gate capacitance. It is in providing. Another object of the present invention is to provide a thin film semiconductor device capable of constituting a highly functional high-performance circuit. Furthermore, another object of the present invention is to provide a liquid crystal display device having a high-performance and high-functional circuit incorporated in a TFT and having excellent display quality and a method for manufacturing the same.

  In order to solve the above problems, in the present application, in a thin film semiconductor device (CMOS TFT) having a CMOS configuration with N-type and P-type TFTs, the N-type and P-type TFTs are included in the source / drain regions. A structure having a low-concentration source / drain region in a portion facing the end portion of the gate electrode through a gate insulating film is taken (hereinafter, this structure is abbreviated as LDD, and the low-concentration source / drain region is referred to as a low concentration source / drain region). The TFT having the LDD structure is referred to as an LDD TFT.) The size and impurity concentration of the LDD region, the channel length and channel width of each TFT, and the source / drain region and channel region of the TFT are configured. It is characterized in that the relationship between the film thickness of a semiconductor film such as silicon and the impurity concentration in the LDD region is optimized. In a liquid crystal display device using a so-called active matrix substrate in which a driving circuit composed of a CMOS TFT is incorporated on a substrate and a TFT is used as a switching element in a pixel region, both a Pi TFT and a Dr TFT are LDD TFTs. The above relationship is optimized between these TFTs. Further, such a CMOS TFT or a liquid crystal display device is used for an electronic device.

  When the CMOS circuit is assembled with the LDD TFT of the present invention, the above-described optimization is performed, so the sheet resistance of the LDD region (parasitic resistance due to the LDD region when viewed in the entire TFT) is minimized, At the same time, both the breakdown voltage between the source and the drain (this is abbreviated as S / D breakdown voltage in this application) and the breakdown voltage between the source and gate (this is abbreviated as S / G breakdown voltage in this application) can be increased. Yes. As a result, it becomes possible to adapt the TFT to a scaling rule that shortens the channel length or thins the gate insulating film, increasing the on-current (low parasitic resistance, short channel, thin gate insulating film) and gate capacitance. This is because a circuit that operates at high speed can be obtained. Further, since the LDD structure relaxes the electric field strength at the drain end, the transistor deterioration due to impact ionization is minimized when the transistor is in an on state, thus improving the reliability of the circuit. Further, in order to minimize the off-leakage current in the off state, it is possible to reduce the current consumption of the entire circuit as well as to suppress the occurrence of circuit malfunction. In addition, in the CMOS TFT of the present invention, as a result of the above optimization, the element sizes of N-type TFT and P-type TFT (channel length when channel area and channel width are equal) are almost equal and It is possible to make both the on-current values equal. That is, in the present invention, the difference in mobility between electrons and holes is offset by the difference in sheet resistance in the LDD region, and the on-current is made equal. Therefore, the N-type TFT and the P-type TFT have almost the same gate capacitance, and the on-currents of the two can be made uniform. Therefore, the CMOS circuit according to the present invention can balance PN (balance of gate capacitance and balance of on-resistance). It works because it gives up and works stably with maximum performance.

  Now, the operation purpose of the Dr TFT and the Pi TFT of the liquid crystal display device are different. As described above, the Dr TFT is desired to operate stably and at high speed without causing malfunction of the high-function circuit and further to have low current consumption. On the other hand, Pi TFT is not required to have a large on-current value compared to Dr TFT, but it is strongly required to reduce off-leak current more reliably. Therefore, in view of such circumstances, the present invention is characterized in that the above-mentioned parameters are optimized independently for the Dr TFT and the Pi TFT. In this way, a liquid crystal display device that incorporates a high-performance and high-performance circuit and displays beautiful image quality can be obtained.

  Such optimization of the LDD structure usually results in a redundant manufacturing process. Therefore, in the present application, when there are two types of LDD TFTs having different LDD region concentrations in the first conductivity type TFT, the second conductivity type impurity is introduced into the LDD region of one LDD TFT to obtain a substantial first conductivity type impurity concentration. It is characterized by lowering. Thus, for example, in a liquid crystal display device, the electric characteristics different from those of the first conductivity type driving circuit TFT while using the manufacturing process of the first conductivity type and second conductivity type driving circuit TFT. It is possible to form a first conductivity type pixel TFT having the following. That is, the electrical characteristics of the TFT can be optimized for each pixel region and drive circuit portion without increasing the number of manufacturing steps. Therefore, the pixel portion does not cause display unevenness or flicker, and a liquid crystal display device incorporating a highly reliable high-speed operation driving circuit can be easily manufactured.

The present invention specifically has the following characteristics.
(First embodiment of the present invention)
The present invention relates to a thin film semiconductor device in which a CMOS circuit is constituted by N-type and P-type thin film transistors, wherein the N-type and P-type thin film transistors have the gate insulation with respect to an end of a gate electrode in a source / drain region. A low-concentration source / drain region is provided in a portion facing the film, and the impurity concentration of the low-concentration / drain region in the P-type thin film transistor is the impurity concentration in the low-concentration source / drain region in the N-type thin film transistor. It is characterized by being higher than the concentration. The impurity concentration of the low-concentration source / drain region in the P-type thin film transistor is in the range of 6 to 8 times the impurity concentration of the low-concentration source / drain region in the N-type thin film transistor. And Furthermore, the impurity concentration of the low-concentration source / drain region in the P-type thin film transistor is in a range from about 1.5 × 10 ¹⁸ cm ⁻³ to about 3.0 × 10 ¹⁸ cm ⁻³ , and the N-type The impurity concentration of the low-concentration source / drain region in the thin film transistor is about 0.2 × 10 ¹⁸ cm ⁻³ to about 0.5 × 10 ¹⁸ cm ⁻³ .

The N-type and P-type thin film transistors are manufactured by a low-temperature process, and the thickness of the semiconductor film constituting the low-concentration source / drain region of the N-type and P-type thin film transistors is t. When the impurity concentration of the low-concentration source / drain region is C _DrPLDD , t and C _{DrPLDD satisfy} the following formula: 1.2 × 10 ¹² cm ⁻² ≦ C _DrPLDD · t ≦ 1.8 × 10 ¹³ cm ⁻² It is in the range to satisfy. At this time, t is the following formula: 1 × 10 ⁻⁶ cm ≦ t ≦ 4.5 × 10 ⁻⁶ cm
It is in the range which satisfy | fills.

The N-type and P-type thin film transistors are manufactured by a low-temperature process, and the thickness of the semiconductor film constituting the low-concentration source / drain regions of the N-type and P-type thin film transistors is t. When the impurity concentration of the low-concentration source / drain region is C _DrNLDD , t and C _{DrNLDD satisfy} the following formula: 2.4 × 10 ¹¹ cm ⁻² ≦ C _DrNLDD · t ≦ 6.0 × 10 ¹² cm ⁻² It is in the range to satisfy. At this time, t is the following formula: 1 × 10 ⁻⁶ cm ≦ t ≦ 4.5 × 10 ⁻⁶ cm
It is in the range which satisfy | fills.

The N-type and P-type thin film transistors are manufactured by a low-temperature process, and the impurity concentration of the low-concentration source / drain region in the N-type thin film transistor and the impurity concentration of the low-concentration source / drain region in the P-type thin film transistor are manufactured. the when expressed in C _DrNLDD and C _DrPLDD respectively, C _DrNLDD and C _DrPLDD the following formula _{3 ≦ C DrPLDD / C DrNLDD ≦} 5
It is in the range which satisfy | fills. At this time, when the film thickness of the semiconductor film constituting the low-concentration source / drain regions of the N-type and P-type thin film transistors is t, t is expressed by the following formula: 1 × 10 ⁻⁶ cm ≦ t ≦ 4.5 × 10 ^-6 cm
It is in the range which satisfy | fills.

The N-type and P-type thin film transistors are manufactured by a low-temperature process, and the thickness of the semiconductor film constituting the low-concentration source / drain regions of the N-type and P-type thin film transistors is t. When the impurity concentration of the low-concentration source / drain region and the impurity concentration of the low-concentration source / drain region in the P-type thin film transistor are expressed by C _DrNLDD and C _DrPLDD , respectively, t, C _DrNLDD and C _DrPLDD are Formula 1.2 × 10 ¹² cm ⁻² ≦ C _DrPLDD · t ≦ 1.8 × 10 ¹³ cm ⁻² 2.4 × 10 ¹¹ cm ⁻² ≦ C _DrNLDD · t ≦ 6.0 × 10 ¹² cm ⁻² 3 ≦ C _DrPLDD / C _DrNLDD ≦ 5
It is in the range which satisfy | fills. At this time, t is the following formula: 1 × 10 ⁻⁶ cm ≦ t ≦ 4.5 × 10 ⁻⁶ cm
It is in the range which satisfy | fills.

The present invention is an electronic device having a substrate on which a thin film semiconductor device is formed as a component, and the thin film semiconductor device has the above-described characteristics.
(Second embodiment of the present invention)
A liquid crystal display device according to the present invention includes a first conductive type and a second conductive type thin film transistor for a driving circuit that constitute a CMOS circuit in a driving circuit portion on an active matrix substrate, and a first conductive type pixel formed in a pixel region. In the liquid crystal display device, the driver circuit thin film transistor and the pixel thin film transistor have a low concentration source in a portion of the source / drain region facing the end of the gate electrode through the gate insulating film. An LDD structure having a drain region, and the impurity concentration of the low-concentration source / drain region in the first-conductivity-type pixel thin-film transistor is the low-concentration source-drain in the first-conduction-type driver circuit thin-film transistor It is characterized by being lower than the impurity concentration of the region. At this time, the first conductivity type is an N type, and the second conductivity type is a P type. Alternatively, the first conductivity type is P-type, and the second conductivity type is N-type.

The impurity concentration of the low-concentration source / drain region in the P-type driver circuit thin film transistor is higher than the impurity concentration of the low-concentration source / drain region in the N-type driver circuit thin film transistor. . At this time, the impurity concentration of the low concentration source / drain region in the P-type driving circuit thin film transistor is 6 to 8 times the impurity concentration of the low concentration source / drain region in the N-type driving circuit thin film transistor. It is characterized by being in the range up to.

When the channel length and channel width of the N-type driving circuit thin film transistor are L _DrN and W _DrN , respectively, and the channel length and channel width of the P-type driving circuit thin film transistor are L _DrP and W _DrP , respectively, _DrN , W _DrN , L _DrP , and W _{DrP satisfy} the following formula 0.8 ≦ (L _DrN · W _DrN ) / (L _DrP · W _DrP ) ≦ 1.25.
(Third embodiment of the present invention)
A method of manufacturing a liquid crystal display device according to the present invention includes a first conductive type and a second conductive type thin film transistor for a driving circuit constituting a CMOS circuit in a driving circuit portion on an active matrix substrate, and a first conductive type formed in a pixel region. In the liquid crystal display device having a thin film transistor for a pixel, the thin film transistor for a driving circuit and the thin film transistor for a pixel are located in a portion of a source / drain region facing a gate electrode end portion through a gate insulating film. It has an LDD structure including a low concentration source / drain region, and the low concentration source / drain region of the pixel thin film transistor has the same amount of first light source / drain region as the low concentration source / drain region of the first conductivity type driving circuit thin film transistor. Conductive type impurity and less than the impurity dose amount for the second conductive type drive circuit By introducing the same amount of the second conductivity type impurity as the low concentration source / drain region of the film transistor, it is substantially more effective than the low concentration source / drain region of the first conductivity type driving circuit thin film transistor. It is characterized by being a low-concentration first conductivity type region. At this time, the first conductivity type is an N type, and the second conductivity type is a P type. Alternatively, the first conductivity type is P-type, and the second conductivity type is N-type.

The first conductivity type impurity concentration in the low concentration source / drain region of the first conductivity type thin film transistor for driver circuit and the first conductivity type pixel thin film transistor is N _I cm ^−3, and the second conductivity type When the impurity concentration of the second conductivity type in the low-concentration source / drain region of the thin film transistor for driving circuit is N _II cm ⁻³ , N _I and N _II are expressed by the following equations 0 <N _II <N _I < 10 × 10 ¹⁸ is satisfied. At this time, (N _I −N _II ) ≦ 3 × 10 ¹⁸
It is characterized by satisfying. Further, N _I and N _II are the following formulas: 0 <N _II ≦ (4 × 10 ¹⁸ )
N _II <N _I ≦ (N _II + 3 × 10 ¹⁸ ) is satisfied. Further, N _I and N _II are the following formulas: 0 <N _II <N _I ≦ (N _II + 3 × 10 ¹⁸ ) N _I ≦ (4 × 10 ¹⁸ )
It is characterized by satisfying. Further, N _I and N _II satisfy the following formulas 0 <N _II <N _I ≦ (4 × 10 ¹⁸ ) (N _I −3 × 10 ¹⁸ ) ≦ N _II ≦ (3 × 10 ¹⁸ ) And Further, when the channel length L _Dr1 of the first conductive type driving circuit thin film transistor is x (μm), x, N _I , and N _II are expressed by the following equations: 0 <N _II <N _I ≦ (x × 10 ¹⁸ ) Is satisfied.

  According to the present invention, in the above-described method for manufacturing a liquid crystal display device, in the low-concentration second conductivity type impurity introduction step for forming the low-concentration source / drain region of the thin film transistor for the second conductivity type drive circuit, A low-concentration second conductivity type impurity is introduced into a region where the low-concentration source / drain region of the pixel thin film transistor is to be formed in addition to the region where the region is scheduled to be formed. In the low-concentration first conductivity type impurity introduction step for forming the low-concentration source / drain region, the low-concentration source / drain region formation region of the pixel thin film transistor in addition to the source / drain region formation region In addition, the first conductivity is larger than the dose of the second conductivity type impurity in the low concentration second conductivity type impurity introduction step. In this step, the region where the low concentration source / drain region of the pixel thin film transistor formed as the second conductivity type is formed in the low concentration second conductivity type impurity introduction step is inverted to the first conductivity type. A low-concentration source / drain region of the pixel thin film transistor is formed. Alternatively, in the low-concentration first conductivity type impurity introduction step for forming the low-concentration source / drain region of the first-conductivity-type driving circuit thin-film transistor, the pixel thin-film transistor in addition to the region where the source / drain region is to be formed In order to form the low concentration source / drain regions of the second conductivity type thin film transistor for a driver circuit, a low concentration first conductivity type impurity is also introduced into the regions where the low concentration source / drain regions are to be formed. In the low concentration second conductivity type impurity introduction step, the low concentration first conductivity type impurity introduction step is performed not only in the source / drain region formation scheduled region but also in the low concentration source / drain region formation scheduled region of the pixel thin film transistor. And introducing a second conductivity type impurity having a dose smaller than the dose of the first conductivity type impurity in the first conductivity type impurity. The low concentration source / drain region of the pixel thin film transistor is formed by substantially reducing the impurity concentration in the region where the low concentration source / drain region of the pixel thin film transistor formed in the material introduction step is to be formed. It is characterized by that.

  According to the present invention, in addition to the effect of the LDD structure, the off current of the pixel TFT is further reduced, the on current of the drive circuit TFT is further increased, and the on current and gate capacitance balance of the drive circuit TFT are reduced. Securement can be achieved. Therefore, it is possible to realize a liquid crystal display device in which display unevenness does not occur and the operation speed of the drive circuit unit is higher.

(4th form of this invention)
A liquid crystal display device according to the present invention includes a first conductive type and a second conductive type thin film transistor for a driving circuit which are formed in a driving circuit portion and constitute a CMOS circuit on an active matrix substrate, and a first conductive type which is formed in a pixel region. The first conductive type pixel thin film transistor, the first conductive type drive circuit thin film transistor, and the second conductive type drive circuit thin film transistor include a source / drain region. The LDD structure having a low concentration source / drain region in a portion facing the end portion of the gate electrode through the gate insulating film, and the low concentration source / drain of the first conductivity type pixel thin film transistor. The length of the drain region is the low-concentration source / drain of the thin film transistor for the drive circuit of the first conductivity type. Wherein the longer than the length of the band. At this time, the first conductivity type is an N type, and the second conductivity type is a P type. Alternatively, the first conductivity type is P-type, and the second conductivity type is N-type.

The length of the low concentration source / drain region of the P-type driving circuit thin film transistor is shorter than the length of the low concentration source / drain region of the N-type driving circuit thin film transistor. 1 relative to the length of the said low concentrations the length of the source and drain regions of the N type driving circuit TFT, the low concentration source and drain regions of the P type driving circuit thin film transistor. It is characterized by being in the range of 5 to 3 times.

The length and width of the low concentration source / drain region of the N-type driving circuit thin film transistor are L _DrNLDD and W _DrNLDD , respectively, and the length and width of the low concentration source / drain region of the P type driving circuit thin film transistor are When L _DrPLDD and W _DrPLDD are used, L _DrNLDD , W _DrNLDD , L _DrPLDD and W _DrPLDD are expressed as follows: 1.5 <(L _DrNLDD / W _DrNLDD ) / (L _DrPLDD / W _DrPLDD ) <3.0 It is characterized by satisfying.

In these liquid crystal display devices, the channel length and channel width of the N-type driving circuit thin film transistor are set to L _DrN and W _DrN , respectively, and the channel length and channel width of the P-type driving circuit thin film transistor are set to L _DrP , respectively _. , W _DrP , L _DrN , W _DrN , L _DrP , W _{DrP satisfy} the following formula 0.8 ≦ (L _DrN · W _DrN ) / (L _DrP · W _DrP ) ≦ 1.25 It is characterized by.
(Fifth embodiment of the present invention)
A liquid crystal display device according to the present invention includes a first conductive type and a second conductive type thin film transistor for a driving circuit which are formed in a driving circuit portion and constitute a CMOS circuit on an active matrix substrate, and a first conductive type which is formed in a pixel region. The first conductive type pixel thin film transistor, the first conductive type drive circuit thin film transistor, and the second conductive type drive circuit thin film transistor include a source / drain region. The LDD structure having a low concentration source / drain region in a portion facing the end portion of the gate electrode through the gate insulating film, and the low concentration source / drain of the first conductivity type pixel thin film transistor. The length of the drain region is the low-concentration source / drain of the thin film transistor for the drive circuit of the first conductivity type. The impurity concentration of the low-concentration source / drain region in the first conductivity type pixel thin film transistor is longer than the length of the region, and the impurity concentration of the low-concentration source / drain region in the first conductivity type driver circuit thin film transistor It is characterized by being low compared. At this time, the first conductivity type is an N type, and the second conductivity type is a P type. Alternatively, the first conductivity type is P-type, and the second conductivity type is N-type.

The length of the low concentration source / drain region of the P-type driving circuit thin film transistor is shorter than the length of the low concentration source / drain region of the N-type driving circuit thin film transistor. The low concentration the length of the source and drain regions of this time the N type driving circuit TFT is 1 relative to the length of the low-concentration source and drain regions of the P type driving circuit thin film transistor. It is characterized by being in the range of 5 to 3 times.

The impurity concentration of the low-concentration source / drain region in the P-type driver circuit thin film transistor is higher than the impurity concentration of the low-concentration source / drain region in the N-type driver circuit thin film transistor. . At this time, the impurity concentration of the low concentration source / drain region in the P-type driving circuit thin film transistor is 6 to 8 times the impurity concentration of the low concentration source / drain region in the N-type driving circuit thin film transistor. It is characterized by being in the range up to.

The length and width of the low concentration source / drain region of the N-type driving circuit thin film transistor are L _DrNLDD and W _DrNLDD , respectively, and the length and width of the low concentration source / drain region of the P type driving circuit thin film transistor are When L _DrPLDD and W _DrPLDD are used, L _DrNLDD , W _DrNLDD , L _DrPLDD and W _DrPLDD are expressed as follows: 1.5 <(L _DrNLDD / W _DrNLDD ) / (L _DrPLDD / W _DrPLDD ) <3.0 It is characterized by satisfying.

When the channel length and channel width of the N-type driving circuit thin film transistor are L _DrN and W _DrN , respectively, and the channel length and channel width of the P-type driving circuit thin film transistor are L _DrP and W _DrP , respectively, _DrN , W _DrN , L _DrP , and W _{DrP satisfy} the following formula 0.8 ≦ (L _DrN · W _DrN ) / (L _DrP · W _DrP ) ≦ 1.25.
(Sixth embodiment of the present invention)
According to the present invention, in a thin film semiconductor device in which a CMOS circuit is constituted by N-type and P-type thin film transistors, the length and width of the low-concentration source / drain region of the N-type thin film transistor are L _DrNLDD and W _DrNLDD , respectively. the type of the low-concentration source and drain regions of the thin film transistor length and width L _DrPLDD respectively, when the _{W DrPLDD, L DrNLDD, W DrNLDD} , L DrPLDD, W DrPLDD has the following formula (L _DrNLDD / W _DrNLDD) It is characterized by satisfying ≧ (L _DrPLDD / W _DrPLDD ). Alternatively, in an electronic device having a substrate on which a thin film semiconductor device is formed as a component, the thin film semiconductor device is a thing described above.

A liquid crystal display device according to the present invention includes a first conductive type and a second conductive type thin film transistor for a driving circuit that constitute a CMOS circuit in a driving circuit portion on an active matrix substrate, and a first conductive type pixel formed in a pixel region. In the liquid crystal display device, the driver circuit thin film transistor and the pixel thin film transistor have a low concentration source in a portion of the source / drain region facing the end of the gate electrode through the gate insulating film. A LDD structure having a drain region, and the length and width of the low-concentration source / drain region of the first conductive type pixel thin film transistor are L _PiILDD and W _PiILDD , respectively, for the drive circuit of the first conductive type the length and width of the low concentration source and drain regions of the thin film transistors each L _DrILDD, was W _DrILDD To _{come, L PiILDD, W PiILDD, L} DrILDD, W DrILDD is characterized by satisfying the following formula _{(L PiILDD / W PiILDD) ≧} (L DrILDD / W DrILDD).

  An electronic apparatus according to the present invention is characterized by including the liquid crystal display device according to (second embodiment of the present invention) to (sixth embodiment of the present invention).

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, the present invention will be described in detail with reference to the drawings.

The following (the fourth embodiment of the present invention) mainly relates to claims 1 to 2 .

  The fifth aspect of the present invention mainly relates to claims 3 to 6.

  However, the present invention is not limited to the configurations described in the embodiments of the invention, and it is needless to say that the configurations described in the embodiments of the invention may be appropriately combined.

  Since many of the embodiments described below relate to a liquid crystal display device using an active matrix substrate with a built-in drive circuit, the configuration of the active matrix substrate will be briefly described before describing each embodiment in detail. Keep it.

  First, a basic configuration of an active matrix substrate with a built-in drive circuit will be described with reference to FIG. A drive circuit built-in type active matrix substrate basically includes a display pixel region 81 and a built-in drive circuit unit including a data driver unit 82 and a scan driver unit 83. The display pixel area 81 has a pixel area defined by signal lines 90 and scanning lines 91, and there is a liquid crystal capacitor 94 of a liquid crystal cell to which an image signal is input via a pixel TFT 92. The data driver unit 82 is connected to the display pixel region via the signal line 90 and includes, for example, a shift register 84, a level shifter 85, a video line 87, an analog switch 86, and the like. On the other hand, the scanning driver unit 83 is connected to the display pixel region via the scanning line 91 and includes a shift register 88, a level shifter 89, and the like. Many of the built-in drive circuits such as the shift registers 84 and 88 have an inverter shown in FIG. 2B as a basic component, and these inverters have a CMOS configuration with an N-type TFT n1 and a P-type TFT p1. Eventually, at least three types of TFTs are generally formed on an active matrix substrate with a built-in drive circuit. In other words, the pixel TFT 92 and the N-type TFT used for the drive circuit and the P-type TFT used for the arrow drive circuit. These are schematically shown in FIG. In FIG. 1, contact holes in the interlayer insulating film and electrodes electrically connected to the source / drain regions through the contact holes are omitted. Shown on the left side of FIG. 1 is a pixel TFT 10, which is an N-type as an example here. Of course, this may be a P-type or a CMOS TFT. The N-type driving circuit TFT 20 is shown in the center, and the P-type driving circuit TFT 30 is shown on the right side. Among these TFTs, the N-type drive circuit TFT 20 and the P-type drive circuit TFT 30 have a CMOS configuration and constitute an inverter of the drive circuit as described above.

  In the active matrix substrate 1 of the present invention, the N-type pixel TFT 10 has a low concentration source / drain region 111 in a portion of the source / drain regions 11, 12 facing the gate electrode 15 via the gate insulating film 14. , 121 has an LDD structure. Therefore, since the off-leakage current is small, it is possible to prevent the occurrence of display unevenness and flicker, and the display quality is considerably improved.

  Further, the N-type driving circuit TFT 20 and the P-type driving circuit TFT 30 are also opposed to the gate electrodes 25 and 35 in the source / drain regions 21, 22, 31 and 32 through the gate insulating films 24 and 34. The LDD structure is provided with low-concentration source / drain regions 211, 221, 311, 321 in a part.

FIG. 3 shows the channel length dependence of the drain breakdown voltage (S / D breakdown voltage) in a TFT having such an LDD structure with a TFT having a channel width W of 10 μm. In FIG. 3A, the solid line L21 shows the channel length dependence of the drain breakdown voltage in the N-type TFT having the LDD structure, and the solid line L23 shows the channel length dependence of the drain breakdown voltage in the self-aligned N-type TFT. . In FIG. 3B, the solid line L22 shows the channel length dependence of the drain breakdown voltage in the P-type TFT with the LDD structure, and the solid line L24 shows the channel length dependence of the drain breakdown voltage in the self-aligned P-type TFT. Yes. As clearly shown in these figures, the TFT with the LDD structure has a sufficient drain breakdown voltage even if the channel length is shortened to about ½ of the TFT with the self-alignment structure. For example, it is possible to shorten the channel length to about 1.5 μm for a P-type LDD TFT and to about 2.5 μm for an N-type LDD TFT. Therefore, the drive circuit composed of these LDD TFTs can significantly reduce the gate capacitance due to the shortening of the channel, and at the same time increase the on-current. Thus, the drive frequency can be increased or the power supply voltage (Vdd) can be lowered, which greatly contributes to the improvement of the characteristics of the active matrix substrate.
(First embodiment of the present invention)
(Configuration of each TFT according to the first embodiment)
Here, after simply explaining that a good CMOS TFT cannot be obtained by simply forming the N-type driving circuit TFT 20 and the P-type driving circuit TFT 30 with the LDD structure, the first embodiment of the present invention will be described in detail. . In general, the on-current of the P-type driving circuit TFT 30 is about several tens of percent smaller than the on-current of the N-type driving circuit TFT 20.
This is because the hole mobility is about 2/3 of the electron mobility. This situation naturally holds true for CMOS LDD TFTs as well. That is, when the N-type driving circuit TFT 20 and the P-type driving circuit TFT 30 constituting the CMOS circuit are formed with the same element size and the same manufacturing conditions in the LDD structure, the P-type LDD TFT as shown in FIG. The on-state current (indicated by a dotted line L2 in FIG. 4) is smaller than the on-state current (indicated by the solid line L1 in FIG. 4) of the N-type LDD TFT. If the on-current balance is poor between the P-type and N-type TFTs in this way, the timing at the time of turning on or off is shifted, which may suppress the operation speed of the circuit or cause a malfunction. On the other hand, if the element size such as the channel length is changed in order to balance the on-current, the gate capacitance balance between the P-type and N-type TFTs will be lost this time, and the operation speed of the arrow-carrying circuit will be suppressed or malfunction will occur. This is because a CMOS TFT with good performance cannot be obtained.

Therefore, in the present invention, the length and width of the source regions 21 and 31, the drain regions 22 and 32, and the channel formation regions 23 and 33 are substantially the same between the N-type driving circuit TFT 20 and the P-type driving circuit TFT 30. As a dimension, symmetry in the layout is ensured, and on-current balance is further improved. This is achieved by increasing the impurity concentration in the LDD region of the P-type LDD TFT compared to that of the N-type LDD TFT. Specifically, in the N-type driving circuit TFT 20, the impurity concentration of the low concentration source / drain regions 211 and 221 is in a range from about 0.2 × 10 ¹⁸ cm ⁻³ to about 0.5 × 10 ¹⁸ cm ^−3. In contrast, in the P-type driving circuit TFT 30, the impurity concentration of the low-concentration source / drain regions 311 and 321 is about 1.5 × 10 ¹⁸ cm ⁻³ to about 3.0 × 10 ¹⁸ cm ^−. The range up to ³ is set. That is, the impurity concentration of the low concentration source / drain regions 311 and 321 in the P-type TFT 30 is about 6 times to about 8 times the impurity concentration of the low concentration source / drain regions 211 and 221 in the N type driving circuit TFT 20. It is set in the range.

On the other hand, since the N-type pixel TFT 10 is formed at the same time as the N-type drive circuit TFT 20, the impurity concentration of the low-concentration source / drain regions 111 and 121 is about the same as that of the N-type drive circuit TFT 20. The range is from 0.2 × 10 ¹⁸ cm ⁻³ to about 0.5 × 10 ¹⁸ cm ⁻³ .

Of the source regions 11 and 21 and the drain regions 12 and 22 of the N-type pixel TFT 10 and the N-type driver circuit TFT 20, the regions other than the low-concentration source / drain regions 111, 121, 211, and 221 are The high concentration source / drain regions 112, 122, 212, and 222 having an impurity concentration of about 0.5 × 10 ²⁰ cm ⁻³ . Of the source region 31 and the drain region 32 of the P-type driving circuit TFT 30, the regions other than the low concentration source / drain regions 311 and 321 have a high impurity concentration of about 2.0 × 10 ²⁰ cm ⁻³ . Source / drain regions 312 and 322. Electrodes (not shown) such as signal lines and pixel electrodes for each TFT are electrically connected to these high concentration regions through contact holes in the interlayer insulating film 4.
(On / off leakage current characteristics of each TFT according to the first embodiment)
FIG. 5 shows the on / off leakage current characteristics of the N-type pixel transistor 10 and the N-type driver circuit TFT 20 with a solid line L3, and a dotted line L4 for the TFT with the P-type driver circuit. The on / off leakage current characteristics of the TFT 30 are shown. As can be seen from FIG. 5, in the P-type drive circuit TFT 30, the impurity concentration of the low-concentration source / drain regions 311 and 321 is compared with that of the N-type TFT (N-type pixel transistor 10 and drive circuit TFT 20). Therefore, even if the hole mobility is smaller than the electron mobility, the on-current characteristics of the P-type driving circuit TFT 30 are improved to the same level as the N-type driving circuit TFT 20. ing. Therefore, a sufficient margin can be ensured for the operating conditions in the shift register, so that malfunction due to on-current imbalance does not occur. In addition, since the element size is substantially the same between the P-type TFT and the N-type TFT, the gate capacitance is also substantially the same. In addition, since the N-type driving circuit TFT 20 and the N-type driving circuit TFT 30 have a small off-leakage current, a malfunction due to the off-leakage current does not occur and a current passing between the power supply terminals of the CMOS circuit is small.

Further, even in the N-type pixel TFT 10, since the off-leakage current is small, display unevenness and flicker do not occur. Further, when the off-state current is small, the holding characteristics are improved, and there is an advantage that the contrast is improved.
(Example 1: Manufacturing method of each TFT according to the first embodiment)
Such an LDD structure TFT can be manufactured by the following method. In the following description, the impurity concentration is expressed by the impurity concentration after activation annealing.

  First, as shown in FIG. 6A, a semiconductor film 3 (polysilicon thin film) is formed on the surface of an insulating substrate 2 such as a quartz substrate using an LPCVD method or a plasma CVD method. There is also a method of forming a polysilicon thin film by laser annealing or solid phase growth after forming an amorphous silicon thin film.

  Next, as shown in FIG. 6B, the semiconductor film 3 is patterned by photolithography to form island-shaped semiconductor films 11a, 21a, and 31a.

  Next, as shown in FIG. 6C, the thickness of the island-shaped semiconductor films 11a, 21a, and 31a is increased by a thermal oxidation method, a TEOS-CVD method, an LPCVD method, a plasma CVD method, an HTO method, or the like. The gate insulating films 14, 24, and 34 made of a silicon oxide film having a thickness of about 1200 angstroms are formed (gate insulating film forming step).

  Next, as shown in FIG. 6D, gate electrodes 15, 25, and 35 made of doped silicon, a silicide film, and the like are formed on the surfaces of the gate insulating films 14, 24, and 34.

Next, as shown in FIG. 7A, the insulating substrate 2 is covered by the LPCVD method, the APCVD method, the plasma CVD method, the O ₃ TEOS method, the O ₂ TEOS method and the like so as to cover the entire surface. A first interlayer insulating film 41 made of a silicon oxide film of angstrom to 3000 angstrom is formed. As a result, at the end portions of the gate electrodes 15, 25, 35, the first interlayer insulating film 41 is thickened by an amount corresponding to the thickness of the gate electrodes 15, 25, 35. For example, if the thickness of the gate electrodes 15, 25, 35 is about 5000 angstroms, the thickness of the gate insulating films 14, 24, 34 is about 1200 angstroms, and the thickness of the first interlayer insulation 41 is about 2000 angstroms, The thickness of the first interlayer insulation 41 is about 3200 angstroms at a position about 1 μm away from the gate electrode end, and the thickness is about 8200 angstroms near the gate electrodes 15, 25, and 35. By utilizing such a difference in thickness, a TFT having an LDD structure is formed in the subsequent steps.

First, as shown in FIG. 7B, a region where the pixel TFT 10 is to be formed and a region where the N-type driving circuit TFT 20 is to be formed are covered with a resist mask 51 on the surface side of the insulating substrate 2. In this state, acceptor-type impurities such as boron ions are implanted at a dose of 2.0 × 10 ¹⁵ cm ⁻² to form the source region 31 and the drain region 32 in a self-aligned manner with respect to the gate electrode 35. Form (P-type impurity introduction step). As other impurity introduction methods, there are an ion doping method, a plasma doping method, a laser doping method, and the like.

As a result, the portion where no impurity is introduced becomes the channel formation region 33. However, in the portion of the source region 31 and the drain region 32 facing the end of the gate electrode 35, the first interlayer insulating film 41 covering the portion is thick, so that the actual impurity introduction amount is larger than the other portions. Is about two digits lower. Therefore, in the source region 31 and the drain region 32, low concentration source / drain regions 311 and 321 having an impurity concentration of about 2.0 × 10 ¹⁸ cm ⁻³ are formed in the portion facing the end of the gate electrode 35. On the other hand, the impurity concentration of the high-concentration source / drain regions 312 and 322 excluding that is about 2.0 × 10 ²⁰ cm ⁻³ . In this way, a P-type driving circuit TFT 30 is formed. Thereafter, the resist mask 51 is removed.

Next, as shown in FIG. 7C, the formation region of the P-type driving circuit TFT 30 is covered with a resist mask 52. In this state, donor-type impurities such as phosphorus ions are ion-implanted at a dose of 0.5 × 10 ¹⁵ cm ⁻² , and the source regions 11 and 21 and the drain are self-aligned with the gate electrodes 15 and 25. Regions 12 and 22 are formed (N-type impurity introduction step).

As a result, portions where impurities are not introduced become channel forming regions 13 and 23. However, in the source regions 11 and 21 and the drain regions 12 and 22, the portions facing the end portions of the gate electrodes 15 and 25 are thicker than the other portions because the first interlayer insulating film 41 covering them is thick. The actual impurity introduction amount is about two orders of magnitude lower. Therefore, in the source regions 11 and 21 and the drain regions 12 and 22, the low concentration source / drain regions 111 having an impurity concentration of about 0.5 × 10 ¹⁸ cm ⁻³ are formed in portions facing the end portions of the gate electrodes 15 and 25. , 121, 211, 221 are formed. On the other hand, the impurity concentration of the high-concentration source / drain regions 112, 122, 212, and 222 excluding that is about 0.5 × 10 ²⁰ cm ⁻³ . In this way, the pixel TFT 10 and the N-type driving circuit TFT 20 are formed. Thereafter, the resist mask 52 is removed.

  Next, as shown in FIG. 7D, after forming the second interlayer insulating film 42 on the surface of the first interlayer insulating film 41 and performing annealing for activation, the active shown in FIG. A matrix substrate 1 is formed. Here, the total film thickness of the first interlayer insulating film 41 and the second interlayer insulating film 42 is about 1.5 μm to about 2.0 μm. For each TFT, a contact hole is formed in the interlayer insulating film 4 composed of the first and second interlayer insulating films 41 and 42, and then predetermined electrodes (signal lines and pixel electrodes) are formed.

If formed by such a method, a TFT having an LDD structure can be formed with a small number of steps, so that off-leakage current can be easily reduced. In addition, the balance of the on-current can be ensured only by controlling the dose amount when forming the source regions 11, 21, 31 and the drain regions 12, 22, 32 in the impurity introduction step.
(Example 2: Another manufacturing method of each TFT according to the first embodiment)
The TFT having the structure shown in FIG. 1 can also be manufactured by the following method.

  In the method described below, the steps shown in FIGS. 6A to 6D are the same as those in the manufacturing method described above. Therefore, the description of these steps is omitted, and the step shown in FIG. Only the process performed after the process will be described.

First, as shown in FIG. 8A, after forming the gate electrodes 15, 25, and 35, the pixel TFTs 10 and N are formed in a state where the formation region of the P-type driving circuit TFT 30 is covered with a resist mask 53. A donor type impurity, for example, phosphorus ion is ion-implanted at a dose of about 0.5 × 10 ¹³ cm ⁻² into a region where a TFT 20 for a driver circuit is to be formed. Consistently, low concentration source / drain regions 11b, 12b, 21b, 22b having an impurity concentration of about 0.5 × 10 ¹⁸ cm ⁻³ are formed. Note that portions where impurities are not introduced become channel formation regions 13 and 23. Thereafter, the resist mask 53 is removed.

Next, as shown in FIG. 8B, in addition to the region where the P-type driving circuit TFT 30 is to be formed, the gate electrodes 15 and 25 of the pixel TFT 10 and the N-type driving circuit TFT 20 are also covered widely. After the resist mask 54 is formed, donor-type impurities such as phosphorus ions are ion-implanted at a dose of 0.5 × 10 ¹⁵ cm ⁻² . Here, the distance between the end portion of the resist mask 54 and the end portions of the gate electrodes 15 and 25 is suitably about 0.5 μm to 2.0 μm. As a result, high concentration source / drain regions 112, 122, 212, 222 having an impurity concentration of 0.5 × 10 ²⁰ cm ⁻³ are formed in the low concentration source / drain regions 11b, 12b, 21b, 22b. .
On the other hand, the portions of the low concentration source / drain regions 11b, 12b, 21b, 22b that are covered with the resist mask 54 have the low impurity concentration of about 0.5 × 10 ¹⁸ cm ^−3. Regions 111, 121, 211, and 221 are formed. In this way, the pixel TFT 10 and the N-type driving circuit TFT 20 are formed. Thereafter, the resist mask 54 is removed.

Next, as shown in FIG. 8C, with the pixel TFT 10 and the N-type driving circuit TFT 20 covered with a resist mask 55, an acceptor is formed with respect to the region where the P-type driving circuit TFT 30 is to be formed. A type impurity such as boron ions is implanted at a dose of about 2.0 × 10 ¹³ cm ⁻² , and the impurity concentration is about 2.0 × 10 ¹⁸ cm ^{−3 in a} self-aligned manner with respect to the gate electrode 35. The low concentration source / drain regions 31b and 32b are formed. Note that a portion where no impurity is introduced becomes a channel formation region 33. Thereafter, the resist mask 55 is removed.

Next, as shown in FIG. 8D, in addition to the pixel TFT 10 and the N-type drive circuit TFT 20, a resist mask 56 that covers the gate electrode 35 of the P-type drive circuit TFT 30 is formed. Thereafter, an acceptor type impurity such as boron ion is ion-implanted at a dose of 2.0 × 10 ¹⁵ cm ⁻² . Here, the distance between the end portion of the resist mask 56 and the end portion of the gate electrode 35 is suitably about 0.5 μm to 2.0 μm. As a result, high concentration source / drain regions 312, 322 having an impurity concentration of 2.0 × 10 ²⁰ cm ⁻³ are formed in the low concentration source / drain regions 31b, 32b. On the other hand, portions of the low concentration source / drain regions 31 and 32 that are covered with the resist mask 56 are low concentration source / drain regions 311 and 321 having an impurity concentration of about 2.0 × 10 ¹⁸ cm ⁻³ as it is. It becomes. In this way, a P-type driving circuit TFT 30 is formed.

In addition to such a manufacturing method, there is a method in which a sidewall is left on the side surfaces of the gate electrodes 15, 25, and 35 by anisotropic etching, and a TFT having an LDD structure is manufactured using the sidewall.
(LDD concentration in the first form)
In Example 2 described above, when TFTs are used as pixel TFTs and drive circuit TFTs of the active matrix substrate 1, it is possible to reliably prevent the occurrence of malfunctions due to poor on-current balance without changing the element size. However, the impurity concentration of the low-concentration source / drain regions 311 and 321 of the P-type driving circuit TFT 30 is set to about 2 from the viewpoint of surely preventing the occurrence of flicker due to off-leakage current and the consumption of useless current. 0 × 10 ¹⁸ cm ^-3 is set to approximately 0.5 × the low concentration impurity concentration of the source and drain regions 111,121,211,221 of TFT20 for TFT10 and N type driving circuit for pixel 10 ¹⁸ cm ^-3 It was set to, P-type about 3.0 from the low concentration source and drain impurity concentration regions of approximately 1.5 × 10 ¹⁸ cm ^-3 of a TFT × 10 ¹⁸ cm ^-3 In the range of at, an impurity concentration of the low concentration source and drain regions of the N-type TFT is may be in the range of about 0.2 × 10 ¹⁸ cm ^-3 to about 0.5 × 10 ¹⁸ cm ^-3 This will be described with reference to FIGS. 9 and 10.

FIG. 9 shows the relationship between the impurity concentration in the low concentration source / drain region and the on-current in the LDD structure N-type TFT by a solid line L5, and the impurity in the low concentration source / drain region in the LD type P type TFT. The relationship between the concentration and the on-current is indicated by a solid line L6. Here, the channel has a W / L of 10/10 (μm), a drain-source voltage of 5 v, and a gate voltage of 10 v. From these examination results, in order to secure an on-current of 2 × 10 ⁻⁵ A or more, which is generally required for the TFT of the drive circuit, the impurity concentration of the low concentration source / drain region is low in the N type TFT. is about 0.2 × 10 ¹⁸ cm ^-3 or more, the P TFT, and the impurity concentration of the low concentration source and drain regions is about 1.5 × 10 ¹⁸ cm ^-3 or more.

On the other hand, FIG. 10 shows a relationship between the impurity concentration of the low concentration source / drain region and the off-leakage current in the LDD structure N-type TFT by a solid line L7, and the low concentration source / drain region in the LDD structure P-type TFT. The relationship between the impurity concentration and the on-current is indicated by a solid line L8. Here, the channel has a W / L of 10/10 (μm), a drain-source voltage of 5 v, and a gate voltage of 0 v.
From these examination results, the level of 1 × 10 ⁻¹³ A or less, which is the upper limit of the off-leakage current in a general driving circuit, is that the impurity concentration of the low-concentration source / drain region is low in the N-type TFT. About 1.3 × 10 ¹⁹ cm ⁻³ or less, in a P-type TFT, the impurity concentration of the low-concentration source / drain region is about 3.0 × 10 ¹⁸ cm ⁻³ or less.

Accordingly, in the P-type TFT, if the impurity concentration in the low concentration source / drain region is in a range from about 1.5 × 10 ¹⁸ cm ⁻³ to about 3.0 × 10 ¹⁸ cm ⁻³ , its on-current characteristics are obtained. In addition, the off-leakage characteristic is a sufficient level for the drive circuit. On the other hand, the N-type TFT is the same as the P-type TFT in which the impurity concentration in the low-concentration source / drain region is in a range from about 1.5 × 10 ¹⁸ cm ⁻³ to about 3.0 × 10 ¹⁸ cm ^−3. In order to obtain the on-current level, the impurity concentration of the low concentration source / drain region is about 0.2 × 10 ¹⁸ cm ^{−3 in} the range from about 0.2 × 10 ¹⁸ cm ⁻³ to about 1.3 × 10 ¹⁹ cm ^−3. The range may be from 10 ¹⁸ cm ⁻³ to about 0.5 × 10 ¹⁸ cm ⁻³ . In the impurity concentration range thus set, not only can the on-current balance be improved, but the level of the off-leak current of the N-type TFT can be reduced to about 1 × 10 ⁻¹⁴ A or less, which is sufficient when used as a pixel TFT. Advantageous holding properties.

Further, according to the examination result shown in FIG. 9, in the CMOS circuit in various thin film semiconductor devices, from the viewpoint of ensuring the balance of the on-current without destroying the balance of the gate capacitance and the like, in the P-type TFT. the impurity concentration of the low concentration source and drain regions may be higher than the impurity concentration of the low concentration source and drain regions in the N TFT, and the from the viewpoint of ensuring a balance of more accurately on-current, from 6 times The range may be up to 8 times.

As an application example of the CMOS TFT of the present invention, in addition to a liquid crystal display device, a substrate on which a thin film semiconductor device such as a contact image sensor or SRAM (Static Random Access Memories) is formed is a part of the constituent elements. There are electronic devices.
(Invention form in low temperature process LDD TFT)
Next, a first aspect of the invention relating to a thin film transistor manufactured by a low temperature process will be described. Here, the low temperature process refers to a TFT manufacturing method in which the maximum process temperature when forming a TFT is about 600 ° C. or less excluding local heating such as laser irradiation or rapid thermal processing (RTA). Since a thermal oxidation method of about 1000 ° C. is not used in the low temperature process, the semiconductor film is modified by laser irradiation or RTA, and the insulating film is formed by a CVD method, a PVD method, or the like. According to the results of the inventor's repeated experiments with TFTs manufactured by such a low temperature process, the impurity concentration of the low concentration source / drain region of each TFT is set as follows. The target characteristics can be optimized.

First, the film thickness of a semiconductor film such as silicon constituting the low concentration source / drain region of each LDD TFT is t (cm), and the low concentration source / drain regions 311 and 321 of the P-type driving circuit TFT 30 are formed. When the impurity concentration is C _DrPLDD (cm ⁻³ ), t and C _DrPLDD are the following formulas: 1 × 10 ⁻⁶ cm ≦ t ≦ 4.5 × 10 ⁻⁶ cm
1.2 × 10 ¹² cm ⁻² ≦ C _DrPLDD · t ≦ 1.8 × 10 ¹³ cm ⁻² is set. Similarly, when the impurity concentration of the low-concentration source / drain regions 211 and 221 in the N-type driving circuit TFT 20 is C _DrNLDD (cm ⁻³ ), t and C _DrNLDD are _expressed by the following equations 1 × 10 ⁻⁶ cm ≦ t ≦ 4.5 × 10 ⁻⁶ cm
2.4 × 10 ¹¹ cm ⁻² ≦ C _DrNLDD · t ≦ 6.0 × 10 ¹² cm ⁻² is set. Alternatively, t, C _DrNLDD and C _DrPLDD are the following formulas: 1 × 10 ⁻⁶ cm ≦ t ≦ 4.5 × 10 ⁻⁶ cm
3 ≦ C _DrPLDD / C _DrNLDD ≦ 5
Set to satisfy.

  For example, when the film thickness of the semiconductor film of each LDD TFT is 40 nm, the low-concentration source / drain regions 211 and 221 in the N-type drive circuit TFT 20 and the low-concentration source / drain in the P-type drive circuit TFT 30 In the drain regions 311 and 321, the impurity concentration range is set as follows.

3.0 × 10 ¹⁷ cm ⁻³ ≦ C _DrPLDD ≦ 4.5 × 10 ¹⁸ cm ⁻³ 6.0 × 10 ¹⁶ cm ⁻³ ≦ C _DrNLDD ≦ 1.5 × 10 ¹⁸ cm ⁻³ Even when a TFT is formed from a silicon film formed by a low-temperature process, a balance of on-current between the N-type driving circuit TFT 20 and the P-type driving circuit TFT 30 can be secured. This is due to the low activation rate of donors and acceptors injected into the LDD region because the maximum process temperature is about 600 ° C. in the low temperature process. If the film thickness is about 45 nm or more, activation becomes relatively easy,
1.2 × 10 ¹² cm ⁻² ≦ C _DrPLDD · t ≦ 1.8 × 10 ¹³ cm ⁻² 2.4 × 10 ¹¹ cm ⁻² ≦ C _DrNLDD · t ≦ 6.0 × 10 ¹² cm ⁻² 3 ≦ C _DrPLDD / C _DrNLDD ≦ 5
Each of these conditions is satisfied regardless of the film thickness.
(Layout according to the present invention)
The transistor layout according to all the inventions of the present application will be described.

The layout of each LDD TFT may be configured as follows from the viewpoint of securing a balance of gate capacitance between the N-type driving circuit TFT 20 and the P-type driving circuit TFT 30. That is, in FIG. 11, the planar shapes of the N-type TFT and the P-type TFT are imitated, and the channel length and channel width of the N-type TFT (N-type driving circuit TFT 20) are set to L _DrN and W _DrN , respectively. When the channel length and channel width of the P-type driving circuit TFT are L _DrP and W _DrP , respectively, L _DrN , W _DrN , L _DrP , and W _DrP can be _expressed by the following formula: L _DrN · W _DrN = It is ideal to satisfy L _DrP / W _DrP . In this way, the gate capacitances of the TFTs become equal, and then the gate capacitance and the on-current can be balanced at the same time if the on-current value is adjusted in accordance with the present invention so that the on-current values are equal for the P-type TFT and N-type TFT. It is. Although not ideal, L _DrN , W _DrN , L _DrP , and W _{DrP satisfy the} following formula 0.8 ≦ (L _DrN · W _DrN ) / (L _DrP · W _DrP ) ≦ 1.25 If it is within, the balance of the gate capacity can be secured. For example, when it is necessary to make W _DrN and W _DrP equal from the layout surface, L _DrN and L _DrP are _expressed by the following equation: 0.8 ≦ L _DrN / L _DrP ≦ 1.25
Set to satisfy.

Further, as shown in FIG. 11, the length and width of the low concentration source / drain regions 111 and 121 of the N-type pixel TFT 10 are L _PiNLDD and W _PiNLDD , respectively. each L _DrNLDD length and width of the drain region 211 and 221, and W _DrNLDD, and the length of the low concentration source and drain regions 311 and 321 of the TFT30 for P type driving circuit and the width of each L _DrPLDD, and W _DrPLDD Sometimes, L _PiNLDD , W _PiNLDD , L _DrNLDD , W _DrNLDD may be set so as to satisfy the following formula (L _PiNLDD / W _PiNLDD ) ≧ (L _DrNLDD / W _DrNLDD ). That is, the resistance values of the low-concentration source / drain regions 111 and 121 in the N-type pixel TFT 10 are set high, and the resistance values of the low-concentration source / drain regions 211 and 221 in the N-type driving circuit TFT 20 are set low. It may be set. With this configuration, while improving the electrical characteristics in the CMOS circuit from the aspect of impurity concentration, the off-leak current of the pixel TFT is reduced from the layout aspect, and the on-current in the driving circuit TFT is increased. Can be planned.
(Second embodiment of the present invention)
(Configuration of each TFT according to the second embodiment)
Since the basic configuration of each LDD TFT of the present invention is the same as that of the first embodiment, it will be described with reference to FIG. 1 and the same reference numerals will be given to portions having corresponding functions, and detailed descriptions thereof will be given. Is omitted.

  In the present invention, as shown in FIG. 1, in the N-type pixel TFT 10, the N-type drive circuit TFT 20, and the P-type drive circuit TFT 30, in the source regions 11, 21, and 31 and the drain regions 12, 22, and 32. The low concentration source / drain regions 111, 121, 211, 221, 311 and 321 are formed at portions facing the end portions of the gate electrodes 15, 25 and 35 through the gate insulating films 14, 24 and 34, respectively. Each TFT has an LDD structure.

  In the present invention, as indicated by a solid line L11 in FIG. 12, the impurity concentration of the low concentration source / drain regions 211 and 221 is shifted to the high concentration side in order to increase the on-current of the N-type driving circuit TFT 20. In addition, the low concentration source / drain regions 111 and 121 of the N-type pixel TFT 10 are also intended to prevent the impurity concentration from shifting to a high concentration side and increasing the off-leakage current. Conversely, in the N-type pixel TFT 10, as shown by the one-dot chain line L 12 in FIG. 12, when the off-leakage current is reduced, the N-type driver circuit TFT 20 is prevented from being reduced in on-current. With the goal.

The liquid crystal display device of the present invention includes a first conductive type and a second conductive type thin film transistor for a driving circuit constituting a CMOS circuit in a driving circuit portion on an active matrix substrate, and a first conductive type pixel formed in a pixel region. The thin film transistor for a driving circuit and the thin film transistor for a pixel have a low concentration source / drain region in a portion of the source / drain region facing the end of the gate electrode through a gate insulating film. The impurity concentration of the low-concentration source / drain region in the first conductivity type pixel thin film transistor is compared with the impurity concentration of the low-concentration source / drain region in the first conductivity type driving circuit thin film transistor. And is low. For example, if the first conductivity type is N-type, the impurity concentration of the low-concentration source / drain regions 111 and 121 in the N-type pixel TFT 10 shown in FIG. 1 is the low-concentration source / drain region 211 in the N-type driver circuit TFT 20. 221 is set lower than the impurity concentration of 221. That is, the impurity concentration in the low-concentration source / drain regions 111 and 121 of the N-type pixel TFT 10 is about 0.4 × 10 ¹⁸ cm ⁻³ , whereas the low-concentration source of the N-type driver circuit TFT 20 The impurity concentration in the drain regions 211 and 221 is about 0.7 × 10 ¹⁸ cm ⁻³ . Of course, the same is true even if the first conductivity type is the P type.

In the present invention, the impurity concentration in the low-concentration source / drain regions 311 and 321 of the P-type driving circuit TFT 30 is set to the impurity concentration in the low-concentration source / drain regions 211 and 221 of the N-type driving circuit TFT 20. It is set high. For example, in the N-type drive circuit TFT 20, the impurity concentration of the low-concentration source / drain regions 211 and 221 is set to about 0.7 × 10 ¹⁸ cm ⁻³ , whereas for the P-type drive circuit In the TFT 30, the impurity concentration of the low concentration source / drain regions 311 and 321 is set to about 5.0 × 10 ¹⁸ cm ⁻³ . That is, the impurity concentration of the low-concentration source / drain regions 311 and 321 in the P-type driving circuit TFT 30 is about 6 times the impurity concentration of the low-concentration source / drain regions 211 and 221 in the N-type driving circuit TFT 20. The range is up to about 8 times.

Of the source regions 11, 21, and 31 and the drain regions 12, 22, and 32 of the N-type pixel TFT 10, the N-type drive circuit TFT 20, and the P-type drive circuit TFT 30, low-concentration source / drain The regions excluding the regions 111, 121, 211, 221, 311, and 321 are high-concentration source / drain regions 112, 122, 212, 222, 312, and 322 having an impurity concentration of about 1.0 × 10 ¹⁹ cm ⁻³ or more. is there. In the present invention, the features of the previous layout are naturally applied.
(On / off leakage current characteristics of each TFT according to the second embodiment)
In the on / off leakage current characteristics of the TFT configured as described above, in the driving circuit TFT, as shown in FIG. 9, the on-current can be increased by the amount of the impurity concentration in the low-concentration source / drain region. it can. Further, as shown in FIG. 10, in the pixel TFT, it can be said that the off-leakage current can be reduced as much as the impurity concentration in the low-concentration source / drain region is lowered. Further, in the CMOS circuit, the impurity concentration of the low concentration source / drain region in the P-type TFT is set to be the low concentration source in the N-type TFT from the viewpoint of ensuring the balance of the on-current without breaking the balance of the gate capacitance and the like. The range is set from about 6 times to about 8 times the impurity concentration of the drain region. Therefore, in the active matrix substrate 1 of the present invention, first, in addition to the TFTs having the LDD structure, the N type driving circuit TFT 20 has an impurity concentration of about 0 in the low concentration source / drain regions 211 and 221. Since it is set on the high concentration side up to 0.7 × 10 ¹⁸ cm ⁻³ , the on-current is large as shown by a solid line L11 in FIG. 12, while the N-type pixel TFT 10 has a low concentration source region 111 and a low concentration. Since the impurity concentration of the drain region 121 is set to a low concentration side up to about 0.4 × 10 ¹⁸ cm ⁻³ , the off-leakage current is small as shown by a one-dot chain line L12 in FIG. Moreover, the P-type driving circuit TFT 30 has a low-concentration source region 211 of the N-type driving circuit TFT 20 until the impurity concentration in the low-concentration source region 311 and the low-concentration drain region 321 is about 5.0 × 10 ¹⁸ cm ^−3. In addition, since the impurity concentration in the low concentration drain region 221 is set higher than the impurity concentration, the on-current is improved to a level equivalent to the on-current of the N-type driving circuit TFT 20 as indicated by a dotted line L13 in FIG. ing. Therefore, a sufficient margin can be secured for the operating conditions of the shift register, and no malfunction caused by an on-current imbalance occurs. In addition, since the element sizes are approximately equal between the P-type TFT and the N-type TFT, the gate capacitance is also approximately equal.
(Example 3: Manufacturing method of LDD TFT according to the second embodiment)
A TFT having such a structure can be manufactured, for example, by the following method. In the following description, the impurity concentration is expressed as the impurity concentration after activation annealing. However, the steps from the formation of the semiconductor film to the formation of the gate electrode and the interlayer insulating film are the same as those described in Embodiment 1 with reference to FIGS. 4A to 5B. . The subsequent steps are basically the same. Accordingly, as shown in FIG. 13A, only the process after the formation of the interlayer insulating film 41 will be described, and detailed description of the subsequent process will be omitted. Also in this example, the interlayer insulating film 41 is thick at the end portions of the gate electrodes 15, 25, and 35 by an amount corresponding to the thickness of the gate electrodes 15, 25, and 35, and the difference in thickness is used. In subsequent steps, a TFT having an LDD structure is formed.

First, as shown in FIG. 13B, a region where the pixel TFT 10 is to be formed and a region where the N-type driving circuit TFT 20 is to be formed are covered with a resist mask 51A on the surface side of the insulating substrate 2. In this state, acceptor-type impurities such as boron ions are ion-implanted at a dose of 5.0 × 10 ¹⁵ cm ⁻² to form the source region 31 and the drain region 32 in a self-aligned manner with respect to the gate electrode 35. Form (P-type impurity introduction step).

As a result, the portion where no impurity is introduced becomes the channel formation region 33. However, in the portion of the source region 31 and the drain region 32 facing the end portion of the gate electrode 35, the interlayer insulating film 41 covering the portion is thick, so that the actual impurity introduction amount is about two orders of magnitude compared to the other portions. Low. Therefore, in the source region 31 and the drain region 32, low-concentration source / drain regions 311 and 321 having an impurity concentration of about 5.0 × 10 ¹⁸ cm ⁻³ are formed in a portion facing the end portion of the gate electrode 35. The portions other than these become high-concentration source / drain regions 312 and 322 having an impurity concentration of about 5.0 × 10 ²⁰ cm ⁻³ . In this way, a P-type driving circuit TFT 30 is formed. Thereafter, the resist mask 51A is removed.

Next, as shown in FIG. 13C, the formation region of the N-type pixel TFT 10 and the formation region of the P-type driving circuit TFT 30 are covered with a resist mask 52A. In this state, donor-type impurities such as phosphorus ions are ion-implanted at a dose of 0.7 × 10 ¹⁵ cm ⁻² to form the source region 21 and the drain region 22 in a self-aligned manner with respect to the gate electrode 25. (N-type impurity introduction step).

As a result, the portion where no impurity is introduced becomes the channel formation region 23. However, in the portion of the source region 21 and the drain region 22 facing the end portion of the gate electrode 25, the interlayer insulating film 41 covering the portion is thick, so that the actual impurity introduction amount is about two orders of magnitude compared to the other portions. Low. Therefore, in the source region 21 and the drain region 22, low concentration source / drain regions 211 and 221 having an impurity concentration of about 0.7 × 10 ¹⁸ cm ⁻³ are formed in a portion facing the end of the gate electrode 25. The portions other than these become high-concentration source / drain regions 212 and 222 having an impurity concentration of about 0.7 × 10 ²⁰ cm ⁻³ . In this way, the N type driving circuit TFT 20 is formed. Thereafter, the resist mask 52A is removed.

Next, as shown in FIG. 13D, the formation region of the N-type drive circuit TFT 20 and the formation region of the P-type drive circuit TFT 30 are covered with a resist mask 53A. In this state, donor-type impurities such as phosphorus ions are ion-implanted at a dose of 0.4 × 10 ¹⁵ cm ⁻² to form the source region 11 and the drain region 12 in a self-aligned manner with respect to the gate electrode 15. (N-type impurity introduction step).

As a result, the portion where no impurity is introduced becomes the channel formation region 13. However, in the portion of the source region 11 and the drain region 12 facing the end portion of the gate electrode 15, the interlayer insulating film 41 covering the portion is thick, so that the actual impurity introduction amount is about two orders of magnitude compared to the other portions. Low. Accordingly, in the source region 11 and the drain region 12, low concentration source / drain regions 111 and 121 having an impurity concentration of about 0.4 × 10 ¹⁸ cm ⁻³ are formed in a portion facing the end of the gate electrode 15. The portions other than these become high-concentration source / drain regions 112 and 122 having an impurity concentration of about 0.4 × 10 ²⁰ cm ⁻³ . In this way, an N-type pixel TFT 10 is formed.

If formed by such a method, the on-current / off-current characteristics of each TFT can be optimized by controlling the dose amount in each impurity introduction step with a minimum number of steps. In addition, you may interchange the process order in said manufacturing method between the processes shown in FIG.13 (b), (c), (d).
(Example 4: Another manufacturing method of LDD TFT according to the second embodiment)
The TFT of this example can also be manufactured by the following method.

  In the method described below, the steps from the formation of the semiconductor film to the formation of the gate electrode are the same as those described in Embodiment 1 with reference to FIGS. 4A to 4D. It is. Therefore, as shown in FIG. 14A, a process after forming the gate electrodes 15, 25, and 35 will be described.

First, as shown in FIG. 14A, after forming the gate electrodes 15, 25, 35, the pixel TFTs 10 and N are formed in a state where the formation region of the P-type drive circuit TFT 30 is covered with a resist mask 54 A. A donor type impurity, for example, phosphorus ion is ion-implanted at a dose of about 0.4 × 10 ¹³ cm ⁻² into a region where a TFT 20 for a driver circuit is to be formed. Consistently, low concentration source / drain regions 11b, 12b, 21b, 22b having an impurity concentration of about 0.4 × 10 ¹⁸ cm ⁻³ are formed. Note that portions where impurities are not introduced become channel formation regions 13 and 23. Thereafter, the resist mask 54A is removed.

Next, as shown in FIG. 14B, the N-type driver circuit TFT 20 is formed in a state where the regions where the N-type pixel TFT 10 and the P-type driver circuit TFT 30 are to be formed are covered with a resist mask 55A. A donor-type impurity, for example, phosphorus ion is ion-implanted into the predetermined region at a dose of about 0.3 × 10 ¹³ cm ⁻² , and the low-concentration source / drain region 21b of the N-type driver circuit TFT 20 is formed. The impurity concentration of 22b is increased to about 0.7 × 10 ¹⁸ cm ⁻³ . Thereafter, the resist mask 55A is removed.

Next, as shown in FIG. 14C, in addition to the region where the P-type driving circuit TFT 30 is to be formed, the gate electrodes 15 and 25 of the N-type pixel TFT 10 and the N-type driving circuit TFT 20 are provided. After the resist mask 56A is formed to cover a wider area, donor-type impurities such as phosphorus ions are ion-implanted at a dose of 1.0 × 10 ¹⁵ cm ⁻² . Here, the distance between the end portion of the resist mask 54A and the end portions of the gate electrodes 15 and 25 is suitably about 0.5 μm to 2.0 μm. As a result, high concentration source / drain regions 112, 122, 212, 222 having an impurity concentration of 1.0 × 10 ²⁰ cm ⁻³ are formed in the low concentration source / drain regions 11b, 12b, 21b, 22b. . On the other hand, portions of the low concentration source / drain regions 11b, 12b, 21b, and 22b that are covered with the resist mask 56A have a low concentration source / drain with an impurity concentration of about 0.4 × 10 ¹⁸ cm ⁻³ as it is. The regions 111 and 121 and the low-concentration source / drain regions 211 and 221 having an impurity concentration of about 0.7 × 10 ¹⁸ cm ⁻³ are formed. In this way, the pixel TFT 10 and the N-type driving circuit TFT 20 are formed. Thereafter, the resist mask 56A is removed.

Next, as shown in FIG. 14D, the N-type pixel TFT 10 and the N-type drive circuit TFT 20 are covered with a resist mask 57A, and the P-type drive circuit TFT 30 is to be formed. Then, acceptor-type impurities, for example, boron ions are implanted at a dose of about 5.0 × 10 ¹³ cm ⁻² , and the impurity concentration is about 5.0 × 10 ^{18 in a} self-aligned manner with respect to the gate electrode 35. Low concentration source / drain regions 31b and 32b of cm ⁻³ are formed. A portion where no impurity is introduced becomes a channel formation region 33. Thereafter, the resist mask 57A is removed.

Next, as shown in FIG. 14E, in addition to the pixel TFT 10 and the N-type drive circuit TFT 20, a resist mask 58A that covers the gate electrode 35 of the P-type drive circuit TFT 30 is formed. Thereafter, an acceptor-type impurity such as boron ion is ion-implanted at a dose of 1.0 × 10 ¹⁵ cm ⁻² . Here, the distance between the end portion of the resist mask 58A and the end portion of the gate electrode 35 is suitably about 0.5 μm to 2.0 μm. As a result, high concentration source / drain regions 312, 322 having an impurity concentration of 1.0 × 10 ²⁰ cm ⁻³ are formed in the low concentration source / drain regions 31b, 32b. On the other hand, of the low concentration source / drain regions 31b, 32b, the portions covered with the resist mask 58A remain as they are in the low concentration source / drain regions 311, 321 having an impurity concentration of about 5.0 × 10 ¹⁸ cm ⁻³ . It becomes. In this way, a P-type driving circuit TFT 30 is formed.

In addition to such a manufacturing method, there is a method in which a sidewall is left on the side surfaces of the gate electrodes 15, 25, and 35 by anisotropic etching, and a TFT having an LDD structure is manufactured using the sidewall.
(Impurity concentration related to the second form)
In the active matrix substrate of the present invention, the impurity concentration of the low-concentration source / drain region of the N-type pixel TFT is about 0.4 × 10 ¹⁸ cm ^−3, and the low-concentration source of the N-type driver circuit TFT is used. Although the impurity concentration in the drain region is about 0.7 × 10 ¹⁸ cm ⁻³ , the impurity concentration in the low concentration source / drain region of the N-type pixel TFT is not limited to such an impurity concentration. As long as it is set lower than the impurity concentration in the low-concentration source / drain region of the driver circuit TFT, the reduction of the TFT off-leakage current in the pixel region and the increase of the on-current of the TFT in the driver circuit portion are combined. realizable.

Further, here, the impurity concentration of the low concentration source / drain region of the N type driving circuit TFT is about 0.7 × 10 ¹⁸ cm ^−3, and the impurity concentration of the low concentration source / drain region of the P type driving circuit TFT is set. the it was about 5.0 × 10 ¹⁸ cm ^-3, according to the impurity concentration without limitation, P-type low concentration source and the impurity concentration in the drain region N type driving circuit TFT of the driver circuit TFT As long as the impurity concentration is set higher than the impurity concentration in the low concentration source / drain region, the balance of the on-current in the drive circuit can be improved. In particular, the impurity concentration in the low-concentration source / drain region of the P-type driving circuit TFT is in the range of about 6 to about 8 times the impurity concentration in the low-concentration source / drain region of the N-type driving circuit TFT. If set to, their on-currents can be made substantially equal.

In this example, the first conductivity type is N-type and the second conductivity type is P-type, but it may be reversed, and the pixel TFT may be P-type.
(Third embodiment of the present invention)
Since the basic configuration of each LDD TFT of the present invention is the same as that of the first and second embodiments, it will be described with reference to FIG. 1 and parts having corresponding functions will be denoted by the same reference numerals and their details. The detailed explanation is omitted.

In the liquid crystal display device of the present invention, the low-concentration source / drain regions of the first conductivity type pixel thin film transistor have the same amount of the first conductivity type impurities as the low-concentration source / drain regions of the first conductivity type driving circuit thin film transistor. The second conductivity type impurity is introduced in an amount equal to that of the low-concentration source / drain region of the second conductivity type thin film transistor for driver circuit, which is smaller than the impurity dose. Thus, the first conductivity type impurity concentration of the low concentration source / drain region of the first conductivity type pixel thin film transistor is substantially lower than that of the low concentration source / drain region of the driver circuit thin film transistor. For example, when the first conductivity type is N-type, the impurity concentration of the low-concentration source / drain regions 111 and 121 of the N-type pixel TFT 10 is in the low-concentration source / drain regions 211 and 222 of the N-type drive circuit TFT 20. It is set substantially lower than the impurity concentration. That is, the impurity concentration in the low-concentration source / drain regions 211 and 221 of the N-type driving circuit TFT 20 is about 3.0 × 10 ¹⁸ cm ⁻³ , and the low-concentration source / drain of the P-type driving circuit TFT 30. The impurity concentration in the regions 311 and 321 is about 2.0 × 10 ¹⁸ cm ⁻³ , but the low-concentration source / drain regions 111 and 121 of the N-type pixel TFT 10 have the N-type driver circuit TFT 20. N-type impurities (phosphorus ions having an impurity concentration of about 3.0 × 10 ¹⁸ cm ⁻³ ) equivalent to the low-concentration source / drain regions 211 and 221 and the low-concentration source / drain region of the P-type driver circuit TFT 30 P-type impurities (boron ions having an impurity concentration of about 2.0 × 10 ¹⁸ cm ⁻³ ) equivalent to 311 and 321 are introduced. Therefore, the low-concentration source / drain regions 111 and 121 of the N-type pixel TFT 10 are substantially low-concentration N-type regions having an impurity concentration of about 1.0 × 10 ¹⁸ cm ⁻³ . Such low-concentration source / drain regions 111 and 121 are substantially equivalent in electrical characteristics to a low-concentration N-type region into which only phosphorus ions having an impurity concentration of about 1.0 × 10 ¹⁸ cm ⁻³ are implanted.
(Example 5: Manufacturing method of each LDD TFT according to the third embodiment)
The active matrix substrate 1 having such a structure can be manufactured, for example, by the following method. In the following description, the impurity concentration is expressed as the impurity concentration after activation annealing.

  First, as shown in FIG. 15A, a semiconductor film is formed on the surface of an insulating substrate 2 such as a quartz substrate using an LPCVD method or a plasma CVD method, and then the semiconductor film is patterned by a photolithography method. This is made into island-shaped semiconductor films 10a, 20a, 30a. Note that the semiconductor film may be formed by laser annealing or solid phase growth after forming an amorphous semiconductor film. Next, the island-shaped semiconductor films 10a, 20a, and 30a are formed of a silicon oxide film having a thickness of about 1200 angstroms by thermal oxidation, TEOS-CVD, LPCVD, plasma CVD, HTO, or the like. Gate insulating films 14, 24, and 34 are formed.

  Next, as shown in FIG. 15B, gate electrodes 15, 25, and 35 made of doped silicon, a silicide film, or the like are formed on the surfaces of the gate insulating films 14, 24, and 34.

Next, the region where the N-type driving circuit TFT 20 is to be formed is covered with a resist mask 71, while the region where the N-type pixel TFT 10 is to be formed is opened. In this state, an acceptor-type impurity, for example, boron ion is ion-implanted to the formation region of the P-type driver circuit TFT 30 at a dose of about 2.0 × 10 ¹³ cm ⁻² to the gate electrode 35. On the other hand, low concentration source / drain regions 31a and 32a having an impurity concentration of about 2.0 × 10 ¹⁸ cm ⁻³ are formed in a self-aligned manner (first impurity introduction step / low concentration second conductivity type impurity introduction step). ). Note that a portion where no impurity is introduced becomes the channel formation region 33. At this time, since the N-type pixel TFT 10 is in an open state, boron ions are about 2.0 × 10 ^{13 in a} self-aligned manner with respect to the gate electrode 15 even in a region where the N-type pixel TFT 10 is to be formed. Ions are implanted at a dose of cm ⁻² . As a result, P-type source / drain regions 11b and 12b having a low concentration (impurity concentration of about 2.0 × 10 ¹⁸ cm ⁻³ ) are formed. Note that a portion where no impurity is introduced becomes the channel formation region 13. Thereafter, the resist mask 71 is removed.

Next, as shown in FIG. 15C, the N-type pixel TFT 10 and the N-type drive circuit TFT 20 are formed in a state where the formation region of the P-type drive circuit TFT 30 is covered with the resist mask 72. A donor type impurity, for example, phosphorus ion is ion-implanted into the predetermined region at a dose of about 3.0 × 10 ¹³ cm ⁻² (second impurity introduction step / low concentration first conductivity type impurity introduction step). . As a result, low concentration source / drain regions 21a and 22a are formed in the region where the N-type driver circuit TFT 20 is to be formed. At this time, in the region where the N-type pixel TFT 10 is to be formed, a low-concentration (impurity concentration is about 2.0 × 10 ¹⁸ cm ⁻³ ) P-type in the low-concentration second conductivity type impurity introduction step. Although the source / drain regions 11b and 12b are formed, the conductivity type of the source / drain regions 11b and 12b is inverted from the P type to the N type by the introduction of the impurities this time, and the low concentration N is substantially obtained. Type source / drain regions 11a and 12a. Here, the substantial concentration of phosphorus ions in the low-concentration source / drain regions 11a and 12a is an N-type impurity corresponding to the difference between the previous P-type impurity introduction amount and the current N-type impurity introduction amount. The concentration can be considered as about 1.0 × 10 ¹⁸ cm ⁻³ . Thereafter, the resist mask 72 is removed.

Next, as shown in FIG. 15D, in addition to the N-type pixel TFT 10 and the N-type drive circuit TFT 20, a resist mask 73 covering the gate electrode 35 of the P-type drive circuit TFT 30 so as to be wide. Then, acceptor-type impurities such as boron ions are implanted at a dose of 1.0 × 10 ¹⁵ cm ⁻² (third impurity introduction step / high concentration second conductivity type impurity introduction step). Here, the distance between the end portion of the resist mask 73 and the end portion of the gate electrode 35 is suitably about 0.5 μm to 2.0 μm. As a result, high concentration source / drain regions 312, 322 having an impurity concentration of 1.0 × 10 ²⁰ cm ⁻³ are formed in the low concentration source / drain regions 31a, 32a. On the other hand, portions of the lightly doped source / drain regions 31a, 32a that are covered with the resist mask 73 are lightly doped source / drain regions 311, 321 having an impurity concentration of about 2.0 × 10 ¹⁸ cm ⁻³ as it is. It becomes. In this way, a P-type driving circuit TFT 30 is formed. Thereafter, the resist mask 73 is removed.

Next, as shown in FIG. 15E, in addition to the region where the P-type driving circuit TFT 30 is formed, the gate electrodes 15 and 25 of the N-type pixel TFT 10 and the N-type driving circuit TFT 20 are also widened. Then, a donor type impurity, for example, phosphorus ion is ion-implanted at a dose of 1.0 × 10 ¹⁵ cm ⁻² (fourth impurity introduction step / high concentration first conductivity type impurity introduction). Process). Here, the distance between the end portion of the resist mask 74 and the end portions of the gate electrodes 15 and 25 is suitably about 0.5 μm to 2.0 μm. As a result, high concentration source / drain regions 112, 122, 212, 222 having an impurity concentration of 1.0 × 10 ²⁰ cm ⁻³ are formed in the low concentration source / drain regions 11a, 12a, 21a, 22a. . On the other hand, the portions of the low concentration source / drain regions 11a, 12a that are covered with the resist mask 74 are low concentration source / drain regions 111, 121 having an impurity concentration of about 1.0 × 10 ¹⁸ cm ⁻³ as it is. It becomes. Of the low-concentration source / drain regions 21a and 22a, portions of the low-concentration source / drain regions 21a and 22a that are covered with the resist mask 74 are directly low-concentration source / drain regions 211 and 221 with an impurity concentration of about 3.0 × 10 ¹⁸ cm ^−3. It becomes. In this way, the N-type pixel TFT 10 and the N-type drive circuit TFT 20 are formed.

As described above, in the manufacturing method of the active matrix substrate 1 of this example, the low-concentration second conductivity type impurity introduction step for forming the low-concentration source / drain regions 311 and 321 of the P-type driving circuit TFT 30, and the N-type Formation of the low concentration source / drain regions 111 and 121 of the N-type pixel TFT 10 in the low concentration first conductivity type impurity introduction step for forming the low concentration source / drain regions 211 and 221 of the driving circuit TFT 20. Acceptor-type and donor-type impurities are respectively introduced into the regions, and low-concentration source / drain regions 111 and 121 of the pixel TFT 10 are formed by the difference in impurity concentration between them. In other words, the N-type pixel TFT 10 having electrical characteristics different from those of the N-type drive circuit TFT 20 can be formed using the manufacturing process of the N-type and P-type drive circuit TFTs 20 and 30. Accordingly, five types (n ⁺ , p ⁺ , pixel n ⁻ , circuit n ⁻ , p ⁻ are formed by four mask formation steps and four impurity introduction steps for forming the resist masks 71 to 74. ) Different source / drain regions are formed. Thus, it becomes possible to optimize the electrical characteristics of the TFT for each pixel region and the drive circuit unit without increasing the number of manufacturing processes, display non-uniformity, and the operation speed of the drive circuit unit are reduced. A high active matrix substrate can be manufactured at low cost.
(Example 6: Another method for manufacturing each LDD TFT according to the third embodiment)
The liquid crystal display active matrix substrate 1 according to the third embodiment of the present invention can also be manufactured by the method described below. That is, in the low concentration first conductivity type impurity introduction step for forming the low concentration source / drain region of the first conductivity type driving circuit thin film transistor (Dr1 TFT), the formation of the source / drain region of the Dr1 TFT is performed in the region to be formed. In addition, a low-concentration first conductivity type impurity is also introduced into regions where the low-concentration source / drain regions of the pixel thin film transistor are to be formed. Thereafter, in the low concentration second conductivity type impurity introduction step for forming the low concentration source / drain region of the second conductivity type thin film transistor for driving circuit (Dr2 TFT), the formation of the source / drain region of the Dr2 TFT is performed. In addition, the second conductivity type impurity having a dose amount smaller than the dose amount of the first conductivity type impurity in the low concentration first conductivity type impurity introduction step is also applied to the region where the low concentration source / drain region of the pixel thin film transistor is to be formed. Introduce. Thus, by substantially reducing the impurity concentration in the region where the low concentration source / drain region of the pixel thin film transistor previously formed in the low concentration first conductivity type impurity introduction step is formed, the low concentration of the pixel thin film transistor is reduced. This is because a source / drain region is formed. Specifically, it is manufactured as follows.

First, as shown in FIG. 16A, a semiconductor film is formed on the surface of an insulating substrate 2 such as a quartz substrate by using an LPCVD method or a plasma CVD method, and then the semiconductor film is patterned by a photolithography method. These are made into island-shaped semiconductor films 10a, 20a, 30a. Note that the semiconductor film may be formed by laser annealing or solid phase growth after forming an amorphous semiconductor film.
Next, the island-shaped semiconductor films 10a, 20a, and 30a are formed from a silicon oxide film having a thickness of about 1200 angstroms by thermal oxidation, TEOS-CVD, LPCVD, plasma CVD, HTO, or the like. Gate insulating films 14, 24, and 34 are formed. Here, if necessary, ion implantation (channel dope process) for adjusting the threshold voltage of the transistor may be performed. As an example of channel dope, boron ion implantation with a dose of about 1 × 10 ¹² cm ⁻² can be performed.

Next, as shown in FIG. 16B, gate electrodes 15, 25, and 35 made of doped silicon, a silicide film, or the like are formed on the surfaces of the gate insulating films 14, 24, and 34. Next, in the state where the region where the P-type driving circuit TFT 30 is to be formed is covered with the resist mask 81, the donor-type impurity is applied to the region where the N-type pixel TFT 10 and the N-type driving circuit TFT 20 are to be formed. For example, phosphorus ions are ion-implanted at a dose of about 3.0 × 10 ¹³ cm ⁻² (first impurity introduction step / low concentration first conductivity type impurity introduction step). As a result, low concentration source / drain regions 21a and 22a having an impurity concentration of about 3.0 × 10 ¹⁸ cm ⁻³ are formed in the region where the N-type driving circuit TFT 20 is to be formed. Note that a portion where no impurity is introduced becomes the channel formation scheduled region 23. At this point, the source / drain regions 11a and 12a having a low concentration (impurity concentration of about 3.0 × 10 ¹⁸ cm ⁻³ ) are also formed in the region where the N-type pixel TFT 10 is to be formed. Thereafter, the resist mask 81 is removed.

Next, as shown in FIG. 16C, the region where the N-type driving circuit TFT 20 is to be formed is covered with a resist mask 82, while the region where the N-type pixel TFT 10 is to be formed is opened. In this state, an acceptor-type impurity, for example, boron ion is ion-implanted with a dose amount of about 2.0 × 10 ¹³ cm ⁻² into the region where the P-type driver circuit TFT 30 is to be formed. Low concentration source / drain regions 31a and 32a having an impurity concentration of about 2.0 × 10 ¹⁸ cm ⁻³ are formed in a self-aligned manner (second impurity introduction step / low concentration second conductivity type impurity introduction) Process). Here, since the N-type pixel TFT 10 is in an open state, boron ions are also ion-implanted there in a dose of about 2.0 × 10 ¹³ cm ⁻² . As a result, the impurity concentration of the N-type source / drain regions 11a and 12a, which initially had an impurity concentration of about 3.0 × 10 ¹⁸ cm ⁻³ , is substantially reduced by the introduction of this impurity. That is, the source / drain regions 11a and 12a have a donor-type impurity concentration (approximately 1.0 × 10 ¹⁸ cm ⁻³⁾ corresponding to the difference between the previous N-type impurity introduction amount and the current P-type impurity introduction amount. The low concentration N-type region into which only the phosphorous ions are introduced is a region substantially equivalent in electrical characteristics. Thereafter, the resist mask 82 is removed.

Next, as shown in FIG. 16D, in addition to the regions where the N-type pixel TFT 10 and the N-type drive circuit TFT 20 are to be formed, the gate electrode 35 of the P-type drive circuit TFT 30 is also made wider. After forming the resist mask 83 to be covered, an acceptor-type impurity, for example, boron ion is ion-implanted at a dose of 1.0 × 10 ¹⁵ cm ⁻² (third impurity introduction step / high-concentration second conductivity type impurity introduction). Process). As a result, high concentration source / drain regions 312, 322 having an impurity concentration of 1.0 × 10 ²⁰ cm ⁻³ are formed in the low concentration source / drain regions 31a, 32a. On the other hand, portions of the lightly doped source / drain regions 31a, 32a that are covered with the resist mask 83 are directly doped with lightly doped source / drain regions 311, 321 having an impurity concentration of about 2.0 × 10 ¹⁸ cm ⁻³ . It becomes. In this way, a P-type driving circuit TFT 30 is formed. Thereafter, the resist mask 83 is removed.

Next, as shown in FIG. 16E, in addition to the region where the P-type driving circuit TFT 30 is to be formed, the gate electrodes 15 and 25 of the N-type pixel TFT 10 and the N-type driving circuit TFT 20 are provided. After the resist mask 84 is formed to cover a wider area, donor-type impurities, for example, phosphorus ions are ion-implanted at a dose of 1.0 × 10 ¹⁵ cm ⁻² (fourth impurity introduction step / high-concentration first conductivity type impurity). Introduction process). As a result, high concentration source / drain regions 112, 122, 212, 222 having an impurity concentration of 1.0 × 10 ²⁰ cm ⁻³ are formed in the low concentration source / drain regions 11a, 12a, 21a, 22a. . On the other hand, portions of the lightly doped source / drain regions 11a, 12a that are covered with the resist mask 84 are directly doped with lightly doped source / drain regions 111, 121 having an impurity concentration of about 1.0 × 10 ¹⁸ cm ^−3. It becomes. Of the low-concentration source / drain regions 21a, 22a, the portions covered with the resist mask 84 are low-concentration source / drain regions 211, 221 having an impurity concentration of about 3.0 × 10 ¹⁸ cm ⁻³ as it is. It becomes. In this manner, the N-type pixel TFT 10 and the N-type drive circuit TFT 20 are formed.

In this manufacturing method, the low-concentration first conductivity type impurity introduction step for forming the low-concentration source / drain regions 211 and 221 of the N-type driving circuit TFT 20 and the low-concentration source / drain of the P-type driving circuit TFT 30 are also performed. The low-concentration source / drain regions 111 and 121 of the pixel TFT 10 can be formed using the difference in impurity concentration implanted in the low-concentration second conductivity type impurity introduction step for forming the drain regions 311 and 321. In other words, the N-type pixel TFT 10 having different electrical characteristics from the N-type drive circuit TFT 20 is formed while using the manufacturing process of the N-type and P-type drive circuit TFTs 20 and 30. Accordingly, five types of source / drain are manufactured on the active matrix substrate 1 by the four mask formation steps and the four impurity introduction steps for forming the resist masks 81 to 84. Therefore, it becomes possible to optimize the electrical characteristics of the TFT for each pixel region and the drive circuit unit without increasing the number of manufacturing processes, display non-uniformity is difficult to occur, and the operation speed of the drive circuit unit is reduced. This is because a liquid crystal display device using a high active matrix substrate can be manufactured at low cost.
(Other manufacturing method of each LDD TFT according to the third embodiment)
In addition to the ion implantation method, an impurity doping method, an ion doping method, a plasma doping method, a laser doping method, or the like may be used.

  In forming the low concentration source / drain regions, in addition to a method using a mask, sidewalls are left on the side surfaces of the gate electrodes 15, 25, and 35 by anisotropic etching. Concentration source / drain regions may be formed. Further, the mask material is not limited to the resist mask.

  Further, impurities of the first conductivity type and the second conductivity type are introduced into regions where the low concentration source / drain regions 111 and 121 are to be formed in the N type pixel TFT 10, and the difference in the impurity concentration causes the pixel TFT 10. If the low-concentration source / drain regions 111 and 121 are formed at a substantially lower concentration than the low-concentration source / drain regions 211 and 221 of the N-type driving circuit TFT 20, the high-concentration source / drain regions are formed. There is no limitation on the order of the steps to be formed.

For example, in Tables 1 to 3, the channel doping process is C / D, the gate electrode forming process is G, the low concentration N-type impurity introduction step is N ⁻ , the high concentration N-type impurity introduction step is N ⁺ , and the low concentration The channel doping step is performed before the gate electrode forming step, so that the P-type impurity introduction step is represented by P ⁻ and the high-concentration P-type impurity introduction step is represented by P ^+. As long as the concentration P-type impurity introduction step is performed after the gate electrode formation step, any sequence may be employed. Further, the channel doping process may be omitted.

（第３形態に於ける不純物濃度の関係）
本発明の第３形態に関し、先の例ではＮ型の画素用ＴＦＴ１０の低濃度ソース・ドレイン領域１１１、１２１の不純物濃度を約１．０×１０¹⁸ｃｍ^-3とし、Ｎ型の駆動回路用ＴＦＴ２０の低濃度ソース・ドレイン領域２１１、２２１の不純物濃度を約３．０×１０¹⁸ｃｍ^-3としたが、画素用ＴＦＴ１０の低濃度ソース・ドレイン領域１１１、１２１をＮ型の駆動回路用ＴＦＴ２０の低濃度ソース・ドレイン領域２１１、２２１に比して実質的に低濃度に形成して、画素領域におけるＴＦＴのオフリーク電流の低減と、駆動回路部におけるＴＦＴのオン電流の増大とを併せて実現できる条件であれば、上記実施例に記載の不純物濃度に限定されるものではない。たとえばＮ型の駆動回路用ＴＦＴ２０の低濃度ソース・ドレイン領域２１１、２２１の不純物濃度を約１．０×１０¹⁷ｃｍ^-3以下とした場合にはそのオフリーク電流を１×１０^-14 Ａ以下にまで確実に低減できるので、液晶表示装置における表示の品位が大幅に向上する。

(Relationship of impurity concentration in the third embodiment)
With respect to the third embodiment of the present invention, in the previous example, the impurity concentration of the low-concentration source / drain regions 111 and 121 of the N-type pixel TFT 10 is about 1.0 × 10 ¹⁸ cm ⁻³ , and the N-type driver circuit is used. The impurity concentration of the low-concentration source / drain regions 211 and 221 of the TFT 20 is about 3.0 × 10 ¹⁸ cm ⁻³ , but the low-concentration source / drain regions 111 and 121 of the pixel TFT 10 are the N-type driving circuit TFT 20. The low concentration source / drain regions 211 and 221 are formed at a substantially lower concentration, and the reduction of the TFT off-leakage current in the pixel region and the increase of the on-current of the TFT in the drive circuit unit are realized. The impurity concentration is not limited to that described in the above embodiment as long as it can be performed. For example, when the impurity concentration of the low-concentration source / drain regions 211 and 221 of the N-type driving circuit TFT 20 is set to about 1.0 × 10 ¹⁷ cm ⁻³ or less, the off-leakage current is set to 1 × 10 ⁻¹⁴ A or less. Therefore, the display quality in the liquid crystal display device is greatly improved.

Here, a preferable relationship to be satisfied by the LDD impurity concentration in the third embodiment will be described. First, the amount of impurities implanted in the low concentration source / drain regions of the first conductivity type driving circuit TFT (Dr1 TFT) and the first conductivity type pixel TFT (Pi1 TFT) is defined as N _I cm ⁻³ . The amount of the second conductivity type impurity implanted into the low concentration source / drain region of the conductivity type driving circuit TFT (Dr2 TFT) is N _II cm ⁻³ . At this time, if N _I and N _II satisfy the relationship 0 <N _II <N _I <10 × 10 ¹⁸ (1), the Pi1 TFT becomes the first conductivity type LDD TFT, and both the Dr1 TFT, the Dr2 TFT, and the LDD TFT Become. This condition range corresponds to a triangular region surrounded by (A), (D), and (H) in FIG. Further, if the condition (1) is satisfied and (N _I −N _II ) ≦ 3 × 10 ¹⁸ (2) is satisfied, the off-leak current of the Pi1 TFT is sufficiently small. This condition range corresponds to a rectangular region surrounded by (A), (D), (C), and (B) in FIG.
Furthermore, N _I and N _II are 0 <N _II ≦ (4 × 10 ¹⁸ )
If N _II <N _I ≦ (N _II + 3 × 10 ¹⁸ ) (3) is satisfied, the Dr2 TFT has a sufficiently high S / D breakdown voltage even if the channel length of the Dr2 TFT is as short as about 4 μm or less. Therefore, it is possible to avoid the bad requirement that the threshold voltage (Vth) of the transistor varies depending on the difference in Vds. That is, the scaling law can be applied to Dr2 TFT. This condition range corresponds to a rectangular region surrounded by (F), (D), (C), and (I) in FIG. Further, N _I and N _II are 0 <N _II <N _I ≦ (N _II + 3 × 10 ¹⁸ ) N _I ≦ (4 × 10 ¹⁸ ) (4)
If the condition is satisfied, the Dr1 TFT has a sufficiently high S / D breakdown voltage even if the channel length of the Dr1 TFT is as short as about 4 μm or less. That is, the scaling law can be applied to both the Dr1 TFT and the Dr2 TFT. This condition range corresponds to a rectangular region surrounded by (F), (D), (C), and (E) in FIG.
Further, when the first conductivity type is N type and the second conductivity type is P type, N _I and N _II are 0 <N _II <N _I ≦ (4 × 10 ¹⁸ ) (N _I −3 × 10 ¹⁸ ) ≦ N _II ≦ (3 × 10 ¹⁸ ) (5) If the channel length of the Dr2 TFT (P-type TFT) is as short as about 3 μm or less, the Dr2 TFT has a sufficiently high S / D breakdown voltage. . That is, the Dr2 TFT can be miniaturized. This condition range corresponds to a pentagonal region surrounded by (G) (D) (C) (E) (J) in FIG. Further, when the channel length L _Dr1 of the first conductive type (N-type) driving circuit thin film transistor is x (μm) (where 0 <x ≦ 3), x and N _I and N _II are 0 <N _II < If N _I ≦ (x × 10 ¹⁸ ) (6) is satisfied, even if the channel length of the N-type Dr1 TFT is as short as 3 μm or less, the Dr1 TFT has a sufficiently high S / D breakdown voltage. . That is, under these conditions, both the Dr1 TFT and the Dr2 TFT can be miniaturized. This condition range corresponds to a triangular region surrounded by (G), (D), and (C) in FIG.
(Conductive type in the third form)
In the above description, the first conductivity type is N-type and the second conductivity type is P-type, but these conductivity types may be reversed except for the conditional expressions (5) and (6). That is, the first conductivity type is P-type and the second conductivity type is N-type. In this case, the pixel TFT is configured as a P-type. In general, the P-type TFT has less dependency on the gate voltage of the off-leakage current (the leakage current does not become so large even if the gate voltage of the P-type TFT is set to a large positive value), so the display quality is remarkably improved. There is an advantage of doing. In addition, in this case, since the LDD concentration of the DrP TFT is higher than the LDD concentration of the DrN TFT, the condition of the first embodiment of the present invention is satisfied and the effect of the first embodiment can be obtained. As an example of the dose, a P type impurity of 6 × 10 ¹⁸ cm ⁻³ is implanted into the low concentration source / drain region of the P-type drive circuit TFT, and 1 × in the low concentration source / drain region of the N type drive circuit TFT. If an N-type impurity of 10 ¹⁸ cm ⁻³ is implanted, the impurity concentration of the P-type pixel TFT is substantially 5 × 10 ¹⁸ cm ⁻³ . An appropriate impurity concentration in the LDD region when the first conductivity type and the second conductivity type are interchanged is in a condition range in which the horizontal axis and the vertical axis are interchanged in FIG.
(Layout in the third form)
Of course, in the third embodiment, the layout described in the section of the first embodiment (the layout according to the present invention) is applied. In addition, as shown in FIG. 11, the length and width of the low-concentration source / drain regions 111 and 121 of the N-type pixel TFT 10 are L _PiNLDD and W _PiNLDD respectively, and the low-concentration of the N-type drive circuit TFT 20 is obtained. source and drain regions 211 and 221 of the length and width, respectively L _DrNLDD, W and _DrNLDD, P-type low concentration source and drain regions 311, 321 the length and width L, respectively _DrPLDD the driver circuit TFT30, W _DrPLDD In this case, L _PiNLDD , W _PiNLDD , L _DrNLDD , W _DrNLDD preferably satisfy the formula (L _PiNLDD / W _PiNLDD ) ≧ (L _DrNLDD / W _DrNLDD ). This is because the Pi TFT can more reliably suppress the off-leak current, and the Dr TFT can obtain a sufficiently high on-current. Further, it is desirable that L _DrNLDD , W _DrNLDD , L _DrPLDD , and W _DrPLDD satisfy the formula of (L _DrNLDD / W _DrNLDD )> (L _DrPLDD / W _DrPLDD ). If the first conductivity type is N-type in the third aspect of the invention, the LDD concentration of the drive circuit P-type TFT is always lower than the LDD concentration of the drive circuit N-type TFT. The condition cannot be met. That is, the parasitic resistance caused by the LDD region of the P-type LDD TFT having a lower mobility than that of the N-type is higher than that of the N-type LDD. Therefore, when the layout of the LDD region is set as in the above equation, the on-current values of the P-type TFT and the type TFT can be made uniform without satisfying the conditions of the first embodiment. That is, even in the third embodiment, the gate capacity can be balanced and the on-current can be balanced at the same time.
(4th form of this invention)
In the first to third embodiments of the present invention, the impurity concentration of the low-concentration source / drain region is optimized in optimizing the characteristics of each TFT. In the present invention, the characteristics of each TFT are optimized by the structure. . However, since the basic configuration of each TFT is the same as that of the first to third embodiments, it will be described with reference to FIG. 1 and parts having corresponding functions will be denoted by the same reference numerals. Detailed description is omitted.

  The liquid crystal display device of the present invention includes a first conductive type thin film transistor for a driving circuit and a second conductive type which are formed in a driving circuit portion on an active matrix substrate and constitute a CMOS circuit, and a first conductive type thin film transistor formed in a pixel region. At least a pixel thin film transistor. The first conductivity type pixel thin film transistor, the first conductivity type drive circuit thin film transistor, and the second conductivity type drive circuit thin film transistor all have a gate insulating film on the end of the gate electrode in the source / drain regions. A low-concentration source / drain region having a low-concentration source / drain region in a portion opposed to the first-conductivity-type pixel thin film transistor. It is set longer than the length of the low concentration source / drain region. This will be specifically described with reference to FIG. Here, the first conductivity type is described as N-type and the second conductivity type is described as P-type. Of course, the first conductivity type may be P-type and the second conductivity type may be N-type.

  In FIG. 1, the lengths of the low concentration source / drain regions 111 and 121 of the N type pixel TFT 10 are set longer than the lengths of the low concentration source / drain regions 211 and 221 of the N type driving circuit TFT 20. For example, the length of the low concentration source / drain regions 111, 121 of the N-type pixel TFT 10 is about 2 μm, whereas the length of the low concentration source / drain regions 211, 221 of the N-type driving circuit TFT 20 is About 1.5 μm.

Furthermore, in the liquid crystal display device of the present invention, the length of the low concentration source / drain region of the P-type driving circuit thin film transistor is set shorter than the length of the low concentration source / drain region of the N type driving circuit thin film transistor. That is, the lengths of the low concentration source / drain regions 311 and 321 of the P type driving circuit TFT 30 in FIG. 1 are set shorter than the lengths of the low concentration source / drain regions 211 and 221 of the N type driving circuit TFT 20. It is. For example, if the lengths of the low concentration source / drain regions 211 and 221 of the N-type driving circuit TFT 20 are about 1.5 μm, the length and the low concentration of the low concentration source region 311 of the P-type driving circuit TFT 30 will be described. The length of the drain region 321 is about 0.8 μm. This LDD length relationship is such that the length of the low concentration source / drain regions 211 and 221 is preferably set to about 0.8 to 2 μm in the N type driving circuit TFT 20, and the P type driving circuit TFT 30. Then, the length of the low concentration source / drain regions 311 and 321 is set to about 0.5 to 1 μm. Further, under these conditions, the lengths of the low concentration source / drain regions 311 and 321 in the N type driving circuit TFT 30 are approximately equal to the lengths of the low concentration source / drain regions 211 and 221 in the P type driving circuit TFT 20. It is ideal if it is set in a range from 1.5 times to about 3 times. Note that the matters described in the section of the first embodiment (layout according to the present invention) are also applicable to the CMOS TFT of the fourth embodiment. That is, if L _DrN , W _DrN , L _DrP , and W _DrP are within the range satisfying the following formula 0.8 ≦ (L _DrN · W _DrN ) / (L _DrP · W _DrP ) ≦ 1.25, Balance can be secured. For example, when it is necessary to make W _DrN and W _DrP equal from the layout surface, L _DrN and L _DrP are _expressed by the following equation: 0.8 ≦ L _DrN / L _DrP ≦ 1.25
Set to satisfy.

Further, as shown in FIG. 11, the lengths and widths of the low concentration source / drain regions 111 and 121 of the N-type pixel TFT 10 are L _PiNLDD and W _PiNLDD , respectively. each L _DrNLDD length and width of the drain region 211 and 221, and W _DrNLDD, and the length of the low concentration source and drain regions 311 and 321 of the TFT30 for P type driving circuit and the width of each L _DrPLDD, and W _DrPLDD Sometimes L _PiNLDD , W _PiNLDD , L _DrNLDD , W _DrNLDD can be _expressed by the following formula (L _PiNLDD / W _PiNLDD ) ≧ (L _DrNLDD / W _DrNLDD ) 1.5 <(L _DrNLDD / W _DrNLDD ) / (L _DrPLDD / W _DrPLDD ) <3.0 is preferably satisfied. This is because the gate capacity can be balanced and the on-current can be balanced at the same time.

FIG. 18 and FIG. 19 show the relationship between the length of the low concentration source / drain region and the on / off current characteristics in each TFT configured as described above. First, in FIG. 18, the relationship between the length of the low concentration source / drain region in the LDD structure N-type TFT and the on-current is indicated by a solid line L28. The relationship between the length and the on-current is indicated by a solid line L29. Here, the impurity concentration of the low concentration source / drain region is about 2 × 10 ¹⁸ cm ^{−3 in} both the P-type and N-type TFTs. The channel size of the TFT is W / L = 10/10 (μm), the source / drain voltage is Vds = 5V, and the gate voltage is Vgs = 10V. According to this examination result, in both the P-type and N-type TFTs, when the length of the low-concentration source / drain region is shortened, the parasitic resistance value in this portion becomes smaller, so that a larger on-current. It can be said that can be obtained. Therefore, from the viewpoint of ensuring the balance of on-current at the same time without destroying the gate capacitance balance of the CMOS circuit, the length of the low-concentration source / drain region in the N-type TFT is reduced to the low-concentration source / drain in the P-type TFT. A range from about 1.5 times to about 3 times the length of the drain region may be used.

On the other hand, FIG. 19 shows a relationship between the length of the low concentration source / drain region and the off-leakage current in the LDD N-type TFT by a solid line L30. The relationship with the off-leakage current is indicated by a solid line L31. Here, the impurity concentration of the low-concentration source / drain regions is about 2 × 10 ¹⁸ cm ^{−3 in} both the P-type and N-type TFTs. The channel size is W / L = 10/10 (μm), the source-drain voltage is Vds = 5V, and the gate voltage Vgs = 0V. According to this examination result, it can be said that the longer the length of the low-concentration source / drain region, the more efficient the electric field relaxation at the drain end, and hence the reduction of the off-leakage current.

As described above, in the active matrix substrate used in the liquid crystal display device of the present invention, in addition to each TFT having an LDD structure, the lengths of the low concentration source / drain regions 211 and 221 of the TFT 20 for the N-type drive circuit are set. The length is set shorter than the lengths of the low concentration source / drain regions 111 and 121 of the N-type pixel TFT 10, and the value is about 0.8 to 2 μm. On the other hand, the lengths of the low concentration source / drain regions 111 and 121 of the N-type pixel TFT 10 are about 1 to 2.5 μm. Reflecting these facts, the on-current of the N-type driving circuit TFT 20 is sufficiently large as shown by a solid line L42 in FIG. 20, while the off-leakage current of the N-type pixel TFT 10 is shown by a one-dot chain line L43. Complimented and small. In addition, the lengths of the low concentration source / drain regions 311 and 321 of the P-type driving circuit TFT 30 are made shorter than the lengths of the low concentration source / drain regions 211 and 221 of the N-type driving circuit TFT 20. Is about 0.5 to 1 μm. As a result, as indicated by a dotted line L44 in FIG. 20, the on-current of the P-type driving circuit TFT 30 is improved to a level equivalent to the on-current of the N-type driving circuit TFT 20. Therefore, a sufficient margin can be secured for the operating conditions of the shift register, and no malfunction caused by the on-current imbalance occurs. Moreover, since the element size is substantially the same between the P-type TFT and the N-type TFT, the gate capacitance is also substantially the same.
(LDD length in the fourth form)
In the above description, the length of the low-concentration source / drain region of the N-type pixel TFT is 2 μm, and the length of the low-concentration source / drain region of the N-type driver TFT is 1.5 μm. The length is not limited to this. If the length of the low concentration source / drain region of the N-type pixel TFT is set to be longer than the length of the low concentration source / drain region of the N-type driving circuit TFT, the off-leak current of the TFT in the pixel region can be reduced. In addition, an increase in the on-current of the TFT in the drive circuit portion can be realized. The length of the low concentration source / drain region of the N type driving circuit TFT is 0.8 to 2.0 μm, and the length of the low concentration source / drain region of the P type driving circuit TFT is 0.5 to 2.0 μm. Although it has been described as 1.0 μm, it is not limited to the length of the arrow. As long as the length of the lightly doped source / drain region of the P-type driver circuit TFT is set shorter than the length of the lightly doped source / drain region of the N-type driver circuit TFT, the on-current balance in the driver circuit is reduced. It can be improved. In particular, the length of the low concentration source / drain region of the P-type driving circuit TFT is set to about 1/3 to about 1/1. If the range is up to 5 times, their on-currents can be made substantially equal.
(Fifth embodiment of the present invention)
In the fifth embodiment of the present invention, the characteristics of each LDD TFT are optimized depending on the impurity concentration of the low concentration source / drain region and its structure. However, since the basic configuration of each TFT is the same as that of the first to fourth embodiments, it will be described with reference to FIG. 1 and parts having corresponding functions will be denoted by the same reference numerals. Detailed description is omitted.

The liquid crystal display device according to the present invention includes a first conductive type thin film transistor for a driving circuit and a second conductive type which are formed in a driving circuit portion on an active matrix substrate and constitute a CMOS circuit, and a first conductive type thin film transistor formed in a pixel region. At least a pixel thin film transistor. The first conductivity type pixel thin film transistor, the first conductivity type drive circuit thin film transistor, and the second conductivity type drive circuit thin film transistor all have a gate insulating film on the edge of the gate electrode in the source / drain regions. A low-concentration source / drain region having a low-concentration source / drain region in a portion opposed to the first-conductivity-type pixel thin-film transistor. It is set longer than the length of the low concentration source / drain region. Further, the impurity concentration of the low concentration source / drain region in the first conductivity type pixel thin film transistor is lower than the impurity concentration of the low concentration source / drain region in the first conductivity type driving circuit thin film transistor.
This will be specifically described with reference to FIG. Here, the first conductivity type is described as N-type and the second conductivity type is described as P-type. Of course, the first conductivity type may be P-type and the second conductivity type may be N-type.

In FIG. 1, the lengths of the low concentration source / drain regions 111 and 121 of the N type pixel TFT 10 are set longer than the lengths of the low concentration source / drain regions 211 and 221 of the N type driving circuit TFT 20. For example, the length of the low concentration source / drain regions 111, 121 of the N-type pixel TFT 10 is about 2 μm, whereas the length of the low concentration source / drain regions 211, 221 of the N-type driving circuit TFT 20 is About 1.5 μm. At the same time, the impurity concentration of the low-concentration source / drain regions 111 and 121 in the N-type pixel TFT 10 is set lower than the impurity concentration of the low-concentration source / drain regions 211 and 221 in the N-type driver circuit TFT 20. . As an example, the impurity concentration in the low-concentration source / drain regions 111 and 121 of the N-type pixel TFT 10 is about 0.4 × 10 ¹⁸ cm ^−3, and the low-concentration source / drain region 211 of the N-type driver circuit TFT 20 is used. The impurity concentration at 221 is about 0.7 × 10 ¹⁸ cm ⁻³ .

Further, in the liquid crystal display device of the present invention, the lengths of the low concentration source / drain regions 311 and 321 of the P-type driving circuit thin film transistor are shorter than the lengths of the low concentration source / drain regions 211 and 221 of the N type driving circuit thin film transistor. It is set. For example, if the lengths of the low concentration source / drain regions 211 and 221 of the N-type driving circuit TFT 20 are about 1.5 μm, the length and the low concentration of the low concentration source region 311 of the P-type driving circuit TFT 30 will be described. The length of the drain region 321 is about 0.8 μm.
This LDD region length relationship is such that the length of the low-concentration source / drain regions 211 and 221 is preferably set to about 0.8 to 2 μm in the N-type drive circuit TFT 20, and the P-type drive circuit TFT 30. Then, the length of the low concentration source / drain regions 311 and 321 is set to about 0.5 to 1 μm. Further, under these conditions, the lengths of the low concentration source / drain regions 311 and 321 in the N type driving circuit TFT 30 are approximately equal to the lengths of the low concentration source / drain regions 211 and 221 in the P type driving circuit TFT 20. It is ideal if it is set in a range from 1.5 times to about 3 times. In the present invention, the impurity concentration in the low concentration source / drain regions 311 and 321 of the P-type driving circuit TFT 30 is higher than the impurity concentration in the low concentration source / drain regions 211 and 221 of the N-type driving circuit TFT 20. It is set. For example, in the N-type drive circuit TFT 20, the impurity concentration of the low-concentration source / drain regions 211 and 221 is set to about 0.7 × 10 ¹⁸ cm ⁻³ , whereas for the P-type drive circuit In the TFT 30, the impurity concentration of the low concentration source / drain regions 311 and 321 is set to about 5.0 × 10 ¹⁸ cm ⁻³ . That is, the impurity concentration of the low-concentration source / drain regions 311 and 321 in the P-type driving circuit TFT 30 is about 6 times the impurity concentration of the low-concentration source / drain regions 211 and 221 in the N-type driving circuit TFT 20. The range is up to about 8 times. Note that the matters described in the section of the first embodiment (layout according to the present invention) are also applied to the CMOS TFT of the fifth embodiment. That is, if L _DrN , W _DrN , L _DrP , and W _DrP are within the range satisfying the following formula 0.8 ≦ (L _DrN · W _DrN ) / (L _DrP · W _DrP ) ≦ 1.25, Balance can be secured. Furthermore, the length and width of the lightly doped source / drain region of the N type driving circuit thin film transistor are L _DrNLDD and W _DrNLDD , respectively, and the length and width of the lightly doped source / drain region of the P type driving circuit thin film transistor are respectively When L _DrPLDD and W _DrPLDD are _satisfied , L _DrNLDD , W _DrNLDD , L _DrPLDD and W _DrPLDD satisfy the following formula: 1.5 <(L _DrNLDD / W _DrNLDD ) / (L _DrPLDD / W _DrPLDD ) <3.0 It is desirable to stay. This is because the on-resistance is made uniform and the gate capacitance can be balanced simultaneously.

Note that the relationship of the LDD length in the fifth embodiment conforms to (LDD length in the fourth embodiment). Further, the relationship of the impurity concentration in the LDD region is in accordance with (impurity concentration related to the second embodiment).
(Sixth embodiment of the present invention)
The sixth embodiment of the present invention relates to a thin film semiconductor device in which a CMOS circuit is constituted by N-type and P-type thin film transistors. Here, as shown in FIG. 11, the length and width of the low concentration source / drain region of the N-type thin film transistor are L _DrNLDD and W _DrNLDD , respectively, and the length and width of the low concentration source / drain region of the P type thin film transistor are When L _DrPLDD and W _DrPLDD are used, L _DrNLDD , W _DrNLDD , L _DrPLDD and W _{DrPLDD satisfy} the following formula (L _DrNLDD / W _DrNLDD ) ≧ (L _DrPLDD / W _DrPLDD ), _respectively . Furthermore, the present invention is an electronic apparatus having a substrate on which such a thin film semiconductor device is formed as a component.

As described above, the on-resistance of the LDD TFT is determined by both the channel resistance represented by mobility and the LDD resistance caused by the LDD region. On the other hand, since the P-type mobility is usually lower than the N-type mobility, the channel resistance of the P-type TFT is necessarily higher than that of the N-type TFT. Therefore, in the present invention, this difference in channel resistance is offset by the difference in LDD resistance. In the P-type driving circuit TFT 30, the resistance value in the low concentration source / drain regions 311, 321 is thus smaller than that of the N-type. It is possible to have almost the same cocoons. From the viewpoint of balancing the gate capacity, L _DrN , W _DrN , L _DrP , and W _DrP satisfy the following formula: 0.8 ≦ (L _DrN · W _DrN ) / (L _DrP · W _DrP ) ≦ 1.25 It is desirable to stay. In particular, if W _DrN = W _DrP or L _DrN = L _DrP , a complicated circuit layout can be facilitated, and a CMOS thin film semiconductor device having higher functions can be obtained. Therefore, various circuits are formed by using such a thin film semiconductor device, and an electronic device such as a portable computer with high performance is realized. In the sixth aspect of the invention, no limitation is imposed on the impurity concentration of the LDD region. That is, it is possible to combine the conditions of the first embodiment, or it is possible to combine with a so-called offset structure in which the impurity concentration of the LDD region is the same as the impurity concentration of the channel formation region.

The same idea as described above can be applied to a liquid crystal display device using LDD TFTs. That is, the liquid crystal display device of the present invention includes a first conductive type and a second conductive type thin film transistor for a driving circuit constituting a CMOS circuit in a driving circuit portion on an active matrix substrate, and a first conductive type pixel formed in a pixel region. The thin film transistor for driving circuit and the thin film transistor for pixel have a low concentration source / drain region in a portion of the source / drain region facing the end of the gate electrode through the gate insulating film. It consists of a structure. At this time, the length and width of the low-concentration source / drain regions 111 and 121 of the first conductivity type pixel thin film transistor are L _PiILDD and W _PiILDD , respectively. If L _DrILDD and W _DrILDD are the lengths and widths of ₂₁₁ and ₂₂₁ respectively, L _PiILDD , W _PiILDD , L _DrILDD and W _DrILDD are
The _expression (L _PiILDD / W _PiILDD ) ≧ (L _DrILDD / W _DrILDD ) is satisfied.

With this configuration, the N-type driving circuit TFT 20 can obtain a large on-current as much as the resistance value in the low-concentration source / drain regions 211 and 221 decreases. On the other hand, in the N-type pixel TFT 10, since the electric field relaxation proceeds to the low concentration source / drain regions 111 and 121, the off-leak current can be reduced.
(Configuration of the present invention)
As described in the first to third embodiments, the invention improves the electrical characteristics of the TFT by optimizing the impurity concentration of the low-concentration source / drain region in each TFT, and the fourth and sixth embodiments. As described above, the invention for improving the electrical characteristics of the TFT by optimizing the size of the low-concentration source / drain region in each TFT may be used individually. Each configuration may be combined. For example, when the third embodiment and the sixth embodiment are combined, there is a restriction on the amount of impurities introduced into each region, so that a drive circuit that cannot be achieved simply by changing the impurity concentration of the low concentration source / drain region in each TFT. The balance of the on-current between the TFTs for the TFT can also be achieved by optimizing the size of the low concentration source / drain regions in each TFT.

  In any of the embodiments, writing to the pixel is performed via one TFT per pixel. Writing to the pixel is performed via a CMOS circuit using the TFT of the present invention. Also good.

(Electronic device using the liquid crystal display device of the present invention)
The liquid crystal display device obtained according to the present invention was incorporated in the casing of a full-color portable personal computer (notebook PC). Clock generation circuit, shift register circuit, NOR gate, digital video signal line, latch circuit 1, latch pulse line, latch circuit 2, reset line 1, AND gate, reference potential line, reset line 2, 6-bit D depending on capacitance division An active matrix substrate incorporates a 6-bit digital data driver comprising an A / A converter, a CMOS analog switch, etc., and all these high-level circuits are also made from the CMOS thin film semiconductor device of the present invention. In this liquid crystal display device, since the digital video signal from the computer can be directly input to the liquid crystal display device, the external circuit configuration is simplified, and at the same time, the power consumption is reduced. In addition, since the Pi TFT used for the display panel has high performance, this notebook PC is a good electronic device having a very beautiful display screen. As a result, an ultra-compact and lightweight electronic device that can be used for a long time and has a clean display screen has been created.

  As described above, in the thin film semiconductor device according to the first embodiment of the present invention, the N-type and P-type TFTs included in the CMOS circuit have an LDD structure and the low concentration in the P-type TFT. The impurity concentration in the drain region is higher than the impurity concentration in the low concentration source / drain region in the N-type TFT. Therefore, according to the present invention, since the portions facing the end portion of the gate electrode are the low concentration source region and the low concentration drain region, the electric field strength at the drain end is reduced. For this reason, the S / D breakdown voltage and the S / G breakdown voltage are increased, and the TFT can be miniaturized such as a short channel length. As a result, the on-current increases and the drive circuit can operate at high speed. In addition, since the gate capacitance is reduced by shortening the channel length, the driving circuit can be operated at high speed also from this point. Further, in the drive circuit, since the off-leakage current of the TFT is small, malfunctions are unlikely to occur, and the current consumption of the CMOS circuit is also small. Further, since the impurity concentration of the low-concentration source / drain region in the P-type TFT is higher than that in the N-type TFT, the element sizes are almost the same or the same between the TFTs. The on-current characteristics between the TFTs can be made equal, the balance of the gate capacitance is not lost, and the malfunction of the circuit is less likely to occur. In addition, since the electric field relaxation at the drain end proceeds, the reliability of the circuit is remarkably improved.

  In the liquid crystal display device according to the second embodiment of the present invention, each TFT has an LDD structure, and the impurity concentration of the low concentration source / drain region in the first conductivity type pixel TFT is the first conductivity type. It is characterized by being lower than the impurity concentration of the low concentration source / drain region in the TFT for driving circuit. Therefore, according to the present invention, in addition to the effect of the LDD structure, it is possible to achieve further reduction of the off current of the pixel TFT and further increase of the on current of the driving circuit TFT. Therefore, it is possible to realize a liquid crystal display device in which display unevenness does not occur and the operation speed of the drive circuit unit is higher.

  In the third embodiment of the present invention, each TFT has an LDD structure, and the low-concentration source / drain regions of the pixel TFT are doped with impurities of the first conductivity type and the second conductivity type. The first conductivity type region is substantially lower in concentration than the low concentration source / drain region of the first conductivity type driving circuit TFT. Therefore, according to the present invention, a pixel TFT having electrical characteristics different from that of the first conductivity type driving circuit TFT while utilizing the manufacturing process of the first conductivity type and second conductivity type driving circuit TFTs. Can be formed. Therefore, by optimizing the TFT electrical characteristics for each pixel region and drive circuit section without increasing the number of manufacturing steps, an active matrix that is less likely to cause display unevenness and has a high operation speed of the drive circuit section. A substrate can be manufactured.

  In the liquid crystal display devices according to the fourth and sixth embodiments of the present invention, each TFT has an LDD structure, and the area of the low concentration source / drain region in each TFT is optimized. Therefore, according to the present invention, in addition to the effect of the LDD structure, the off current of the pixel TFT is further reduced, the on current of the drive circuit TFT is further increased, the on current and the gate capacitance of the drive circuit TFT. A balance can be secured. Therefore, it is possible to realize a liquid crystal display device in which display unevenness does not occur and the operation speed of the drive circuit unit is higher.

  In the liquid crystal display device according to the fifth embodiment of the present invention, each TFT has an LDD structure, and the area of the low concentration source / drain region in each TFT is optimized, and the impurity concentration in the LDD region is also optimized. It is characterized by that. Therefore, according to the present invention, in addition to the effect of the LDD structure, the off current of the pixel TFT is further reduced, the on current of the drive circuit TFT is further increased, the on current and the gate capacitance of the drive circuit TFT. A balance can be secured. Therefore, it is possible to realize a liquid crystal display device in which display unevenness does not occur and the operation speed of the drive circuit unit is higher.

It is sectional drawing which shows typically the active matrix substrate using the thin-film transistor concerning this invention. (A) is explanatory drawing of the active matrix substrate of the liquid crystal display device using the thin-film transistor shown in FIG. 1, (b) is explanatory drawing of the CMOS circuit used for the drive circuit. (A), (b) is a graph which shows the channel length dependence of the drain proof pressure in N type and P type TFT. It is a graph which compares and shows the on / off leak current characteristic of the conventional N-type and P-type thin film transistor. In the liquid crystal display device which concerns on this invention, it is a graph which shows on / off leak current characteristic of each TFT formed on the active matrix in comparison. It is process sectional drawing which shows to the formation process of a gate electrode among the manufacturing methods of the active matrix substrate which concerns on this invention. It is process sectional drawing which shows the process after the formation process of a gate electrode among the manufacturing methods of the active matrix substrate which concerns on this invention. It is process sectional drawing which shows the process after the formation process of a gate electrode among another manufacturing methods of the active matrix substrate which concerns on this invention. In the liquid crystal display device according to the present invention, it is a graph showing the relationship between the impurity concentration of the low concentration source / drain region and the on-current characteristics in each TFT formed on the active matrix. In the liquid crystal display device according to the present invention, it is a graph showing the relationship between the impurity concentration of the low concentration source / drain region and the off-leakage current characteristics in each TFT formed on the active matrix. In the liquid crystal display device according to the present invention, it is an explanatory diagram for explaining a configuration in terms of size in N-type and P-type thin film transistors. 4 is a graph showing comparison of on / off leakage current characteristics of TFTs formed on an active matrix in a liquid crystal display device according to the present invention. It is process sectional drawing which shows the process after the formation process of a gate electrode among the manufacturing methods of the active matrix substrate which concerns on this invention. It is process sectional drawing which shows the process after the formation process of a gate electrode among another manufacturing methods of the active matrix substrate which concerns on this invention. It is process sectional drawing which shows the manufacturing method of the active matrix substrate which concerns on this invention. It is process sectional drawing which shows another manufacturing method of the active matrix substrate which concerns on this invention. It is a graph for demonstrating the impurity introduction conditions to the low concentration source / drain region of each TFT of the active matrix substrate which concerns on this invention. 4 is a graph showing on-current characteristics of TFTs formed on an active matrix substrate in the liquid crystal display device according to the present invention. 4 is a graph showing off-leakage current characteristics of each TFT formed on an active matrix substrate in the liquid crystal display device according to the present invention. 4 is a graph showing comparison of on / off leakage current characteristics of TFTs formed on an active matrix in a liquid crystal display device according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Active matrix substrate 2 ... Insulating substrate 10 ... N type TFT for pixels
20 ... TFT for N-type drive circuit
30 ... P-type drive circuit TFT
n1, n2 ... N-type TFT
p1, p2 ... P-type TFT
11, 21, 31 ... source regions 12, 22, 32 ... drain regions 13, 23, 33 ... channel forming regions 14, 24, 34 ... gate insulating films 15, 25, 35 ... Gate electrode 82... Data driver section (drive circuit)
83 ... Scanning driver section (drive circuit)
84, 88 ... shift registers 85, 89 ... level shifter 90 ... signal line 91 ... scanning line 92 ... pixel TFT
94: Capacitances 111, 121, 211, 221, 311, 321 of the liquid crystal cell Low concentration source / drain regions 112, 122, 212, 222, 312, 322 ... High concentration source / drain regions

Claims (6)

On the active matrix substrate, there are provided first conductive type and second conductive type thin film transistors for driving circuits constituting the driving circuit unit, and first conductive type thin film transistors for pixels formed in the pixel region, and the first conductive type thin film transistors. In a liquid crystal display device in which the conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type,
The first conductive type thin film transistor for a pixel, the first conductive type thin film transistor for a drive circuit, and the second conductive type thin film transistor for a drive circuit are gated with respect to an end portion of a gate electrode in a source / drain region. Having an LDD structure including low-concentration source / drain regions having the same impurity concentration in a portion facing through the insulating film;
The length of the low-concentration source / drain region of the first conductivity type pixel thin film transistor is longer than the length of the low-concentration source / drain region of the first conductivity type driving circuit thin film transistor,
The length of the low concentration source / drain region of the P-type driving circuit thin film transistor is shorter than the length of the low concentration source / drain region of the N type driving circuit thin film transistor, and the length of the N type driving circuit the thin film transistor of the low concentration source and drain regions of the length and width, respectively L _DrNLDD, W and _DrNLDD, the P-type driving circuit TFT of low concentration source and drain regions of the length and width, respectively L _DrPLDD, and W _DrPLDD L _DrNLDD , W _DrNLDD , L _DrPLDD , W _DrPLDD can be _expressed by the following formula 1.5 <(L _DrNLDD / W _DrNLDD ) / (L _DrPLDD / W _DrPLDD ) <3.0
When the channel length and channel width of the N-type driving circuit thin film transistor are L _DrN and W _DrN , respectively, and the channel length and channel width of the P-type driving circuit thin film transistor are L _DrP and W _DrP , respectively. , L _DrN , W _DrN , L _DrP , W _DrP have the following formula: 0.8 ≦ (L _DrN · W _DrN ) / (L _DrP · W _DrP ) ≦ 1.25
The liquid crystal display device characterized by satisfy | filling.   2. The length of the low-concentration source / drain region of the N-type driver circuit thin film transistor according to claim 1 is 1. A liquid crystal display device having a range of 5 to 3 times. On the active matrix substrate, there are provided first conductive type and second conductive type thin film transistors for driving circuits constituting the driving circuit unit, and first conductive type thin film transistors for pixels formed in the pixel region, and the first conductive type thin film transistors. In a liquid crystal display device in which the conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type,
The first conductive type thin film transistor for a pixel, the first conductive type thin film transistor for a drive circuit, and the second conductive type thin film transistor for a drive circuit are gated with respect to an end portion of a gate electrode in a source / drain region. It has an LDD structure having a low concentration source / drain region in a portion facing through an insulating film,
The length of the low-concentration source / drain region of the first conductivity type pixel thin film transistor is longer than the length of the low-concentration source / drain region of the first conductivity type driving circuit thin film transistor,
The length and width of the low concentration source / drain region of the N-type driving circuit thin film transistor are L _DrNLDD and W _DrNLDD , respectively, and the length and width of the low concentration source / drain region of the P type driving circuit thin film transistor are When L _DrPLDD and W _DrPLDD are used, L _DrNLDD , W _DrNLDD , L _DrPLDD and W _DrPLDD are expressed as follows: 1.5 <(L _DrNLDD / W _DrNLDD ) / (L _DrPLDD / W _DrPLDD ) <3.0
The filling,
When the channel length and channel width of the N-type driving circuit thin film transistor are L _DrN and W _DrN , respectively, and the channel length and channel width of the P-type driving circuit thin film transistor are L _DrP and W _DrP , respectively, _DrN , W _DrN , L _DrP , W _DrP are _expressed by the following formula 0.8 ≦ (L _DrN · W _DrN ) / (L _DrP · W _DrP ) ≦ 1.25
And the impurity concentration of the low-concentration source / drain region in the first-conductivity-type pixel thin-film transistor is compared with the impurity concentration of the low-concentration source-drain region in the first-conduction-type driver circuit thin-film transistor. Low,
The impurity concentration of the low-concentration source / drain region in the P-type driver circuit thin film transistor is higher than the impurity concentration of the low-concentration source / drain region in the N-type driver circuit thin film transistor. Liquid crystal display device.   4. The length of the low concentration source / drain region of the P-type driving circuit thin film transistor is shorter than the length of the low concentration source / drain region of the N type driving circuit thin film transistor according to claim 3. Liquid crystal display device.   5. The length of the low-concentration source / drain region of the N-type driving circuit thin film transistor according to claim 4 is 1. A liquid crystal display device having a range of 5 to 3 times.   6. The impurity concentration of the low-concentration source / drain region in the P-type driving circuit thin film transistor according to claim 4 or 5 relative to the impurity concentration of the low-concentration source / drain region in the N-type driving circuit thin film transistor. A liquid crystal display device having a range of 6 to 8 times.

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