JP3765262B2 - Control apparatus, semiconductor test apparatus, and program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control device or the like that is connected to a plurality of power supply current analysis devices that apply a test pattern to a device under measurement and analyze the power supply current of the device under measurement, and controls the operation of each of the power supply current analysis devices.
[0002]
[Prior art]
FIG. 7 is a block diagram showing a configuration of a conventional semiconductor test apparatus 800. The semiconductor test apparatus 800 includes a power supply current analyzing apparatus 811 to 81n (hereinafter, collectively referred to as a power supply current analyzing apparatus 81) and a computer 87, and each of the power supply current analyzing apparatus 81 includes a DUT (Device Under Test: Device). Under Test) 861 to 86n (hereinafter, collectively referred to as DUT 86) are connected.
[0003]
The power source current analysis device 811 includes a DUT power source 821 (hereinafter, generically referred to as a DUT power source 82), a power source current detection unit 831 (hereinafter, generically referred to as a power source current detection unit 83), and a frequency analysis unit. 841 (hereinafter collectively referred to as frequency analysis unit 84) and test pattern generation unit 851 (hereinafter generally referred to as test pattern generation unit 85). The power supply current analysis devices 812 to 81n have the same configuration and are connected to the computer 87 in parallel.
[0004]
The output of the computer 87 is connected to a DUT power supply 82, a frequency analysis unit 84, and a test pattern generation unit 85. The output of the DUT power supply 82 is connected to the power supply current detection unit 83, and the output of the power supply current detection unit 83 is connected to the frequency analysis unit 84 and the power supply pins of the DUT 86. The output of the test pattern generation unit 85 is connected to the IO pin of the DUT 86.
[0005]
The DUT power supply 82 outputs the voltage set by the computer 87 and applies the voltage to the power supply pin of the DUT 86 via the power supply current detection unit 83.
[0006]
The power supply current detection unit 83 measures the current value of the power supply pin of the DUT 86, outputs the result to the frequency analysis unit 84, and further outputs it to the computer 87.
[0007]
The frequency analysis unit 84 performs frequency analysis on the current value of the power supply pin of the DUT 86 input from the power supply current detection unit 83 in accordance with the measurement conditions specified by the computer 87 and outputs the result to the computer 87.
[0008]
The test pattern generation unit 85 outputs a test pattern signal to the IO pin of the DUT 86 according to the operation timing instructed by the computer 87.
[0009]
The computer 87 sets a voltage to be applied to the power supply pin of the DUT 86 with respect to the DUT power supply 82, inputs a measurement result from the frequency analysis unit 84, and performs data processing and determines the failure of the DUT 86. Further, the current value of the power supply pin of the DUT 86 is input from the power supply current detection unit 83 and the analysis condition of the frequency analysis unit 84 is set. Then, a test pattern generated by the test pattern generation unit 85 and a signal indicating the operation timing of the power supply current detection unit 83 and the frequency analysis unit 84 are output.
[0010]
FIG. 8 is a diagram for explaining a conventional semiconductor test method using the semiconductor test apparatus 800 of FIG. The computer 87 receives the analysis result of the power source current analysis device 81 regarding the n DUTs 86. The computer 87 determines the failure of each DUT 86 by comparing the analysis result with a preset reference value.
[0011]
[Problems to be solved by the invention]
Here, in the semiconductor test apparatus 800, it is important to determine whether or not a DUT is defective. However, when a defective DUT is detected, the occurrence of a defective operation is detected in the test pattern input to the DUT. Is also desirable.
[0012]
However, in the conventional semiconductor test method, it is possible to determine good / bad, but it is not possible to detect a defective portion for a defective DUT. For this reason, in order to detect a defective portion, for example, a failure detection method such as Japanese Patent Laid-Open No. 9-2111088 is known, but another analysis means or device is required, and the time and cost for that are required. Needed.
[0013]
Furthermore, when the reference value set in the computer 87 is determined, the reference value is determined by performing a plurality of tests on a plurality of DUTs, so that time and labor are required for setting the reference value. I was trying.
[0014]
An object of the present invention is to perform a DUT test without previously setting a reference value, and to detect a defective portion.
[0015]
[Means for Solving the Problems]
The control apparatus according to the first aspect of the invention (for example, the computer 17 in FIG. 1) is a power supply current analyzing apparatus (for example, the power supply in FIG. 1) that applies a test pattern to the device to be measured and analyzes the power supply current of the device to be measured. Current analysis device 111) In a control device connected to a plurality of devices and controlling the operation of each of the power supply current analysis devices, receiving means (for example, communication unit 26 in FIG. 2) for receiving the analysis results of each of the power supply current analysis devices; The determination means for determining the quality of the device under measurement measured by each of the power supply current analysis devices by comparing the analysis results of each of the power supply current analysis devices received by the receiving means (for example, FIG. And a test execution program 231).
[0016]
Furthermore, the program of the invention described in claim 6 is connected to a plurality of power source current analyzing devices that apply a test pattern to the device under measurement and analyze the power source current of the device under test, and controls the operation of each of the power source current analyzing devices. The power supply current analyzing apparatus by comparing the analysis results of the power supply current analyzing apparatuses received by the receiving means with the receiving means for receiving the analysis results of the power supply current analyzing apparatuses And determining means for determining the quality of the device under measurement measured by each of the devices.
[0017]
According to the first and sixth aspects of the present invention, it is not necessary to set a reference value in advance by determining the failure of the device under measurement by comparing the analysis results output from the plurality of power supply current analysis devices. , Reduce the time and effort to determine the reference value.
[0018]
The control device according to claim 1, further comprising setting means for setting a power supply current analyzing device as a reference among the plurality of power supply current analyzing devices, as in the control device according to claim 1, May compare the analysis results of other power supply current analysis devices on the basis of the analysis result of the power supply current analysis device set by the setting means.
[0019]
According to the second aspect of the present invention, for example, a device to be measured that is already known to be non-defective is installed in the power source current analyzing apparatus set by the setting means, and the analysis result of the power source current analyzing apparatus and other power source currents are set. Compare the analysis results of the analyzer. This eliminates the need to set a reference value in advance, thereby reducing time and labor for determining the reference value.
[0020]
Furthermore, as in the invention described in claim 3, in the control device according to claim 1 or 2, section dividing means for dividing the test pattern into one or more pattern sections, and a pattern divided by the section dividing means. You may comprise the control apparatus further provided with the control means (For example, the defect location identification process program 232 of FIG. 2) which controls the analysis operation | movement of the said power supply current analyzer based on the area.
[0021]
According to the third aspect of the invention, by dividing the test pattern and analyzing the failure of the device under measurement, it is possible to detect the occurrence of a failure in the test pattern in the device under measurement that is defective. As an example, for example, as in the invention described in claim 4, the section dividing means may further comprise means for recursively dividing the divided pattern section into one or more pattern sections. This eliminates the need for another measurement for detecting a defective portion, thereby reducing time and labor.
[0022]
According to the fourth aspect of the invention, by repeating the division of the test pattern, it is possible to detect a defect occurrence location in the test pattern in the device under test that is defective.
[0023]
Of course, you may comprise the semiconductor testing apparatus provided with these control apparatuses. 6. A plurality of power supply current analyzing apparatuses that analyze a power supply current of a device under test by applying a test pattern to the device under measurement as in the semiconductor test apparatus according to claim 5 and connected to each of the power supply current analysis devices. You may comprise a semiconductor test apparatus provided with the control apparatus in any one of 1-4.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment to which the present invention is applied will be described in detail with reference to FIGS. FIG. 1 is a diagram showing a block configuration of a semiconductor test apparatus 100 according to the present embodiment. The block configuration of the semiconductor test apparatus 100 according to the present embodiment is the same as that in FIG. Different functional blocks are a computer 17 and a test pattern generation unit 151 (hereinafter collectively referred to as a test pattern generation unit 15). For this reason, the same functional blocks are denoted by the same reference numerals, and detailed description thereof is omitted.
[0025]
The test pattern generation unit 15 receives a setting signal based on the pattern section in which the test is executed from the computer 17 and outputs a test pattern signal to the IO pin of the DUT 86 for the pattern section.
[0026]
The computer 17 sets a voltage to be applied to the power supply pin of the DUT 86 with respect to the DUT power supply 82, inputs a measurement result from the frequency analysis unit 84, and performs data processing or a failure determination of the DUT 86. Further, the current value of the power supply pin of the DUT 86 is input from the power supply current detection unit 83, the analysis condition of the frequency analysis unit 84 is set, the pattern section is set in the test pattern generated by the test pattern generation unit 15, and the setting signal Is output. Then, a test pattern generated by the test pattern generation unit 15 and a signal indicating the operation timing of the power source current detection unit 831 and the frequency analysis unit 84 are output.
[0027]
FIG. 2 is a diagram illustrating a hardware configuration of the computer 17, and includes a CPU (Central Processing Unit) 21, a RAM (Random Access Memory) 22, a storage unit 23, an input unit 24, a display unit 25, and a communication unit. 26, and each part is connected by a bus 27.
[0028]
The CPU 21 stores the designated application program in the various application programs stored in the storage unit 23 in the RAM 22 and executes various processes in accordance with the application program stored in the RAM 22 according to the input instruction and input data. The processing result is stored in the RAM 22 and displayed on the display unit 25.
[0029]
The RAM 22 stores data created by executing various application programs. The analysis result storage area 221 is an area for storing an analysis result transmitted from the power supply current analysis device 11 to the computer 17 by the execution of the test execution program 231.
[0030]
The storage unit 23 stores various application programs and data, and includes a hard disk or the like. Here, a test execution program 231 and a defective part identification processing program 232 are stored.
[0031]
The test execution program 231 is a program for the computer 17 to cause the power supply current analyzer 11 to execute the test of the DUT 86, and the defect location specifying processing program 232 is a case where a defect is detected during the test of the DUT 86, This is a program for detecting a defective portion in a test pattern.
[0032]
The input unit 24 is for a user of the computer 17 to input numerical values or to execute an application program, and is configured with a keyboard or the like.
[0033]
The display unit 25 is a part for displaying data necessary for using the computer 87, such as characters and codes input in the input unit 24, and processing results of the application program, and includes a CRT (Cathode Ray Tube) It consists of LCD (Liquid Crystal Display).
[0034]
The communication unit 26 is an interface for transmitting / receiving a signal to / from an external device such as the power supply current analysis device 11, and operates according to a signal from the CPU 21.
[0035]
FIG. 3 is a diagram for explaining a semiconductor test method in the present embodiment. The computer 17 receives the measurement results of the n power source current analyzers 11. Here, a non-defective DUT is connected in advance to the power supply current analysis device 111, and the computer 17 uses the measurement result of the power supply current analysis device 111 among the input measurement results as a reference value, and the measurement result and the power supply current analysis device. A defect is determined by comparing the measurement results of 112 to 11n. Thereby, since it is not necessary to previously set a reference value for defect determination in the computer 17, work time for determining the reference value can be reduced.
[0036]
The DUT that is a non-defective product does not necessarily have to be connected to the power supply current analysis device 111, and may be other than that.
[0037]
Next, a method for detecting a defective part when a defect is detected in the semiconductor test method of the present embodiment will be described. First, FIG. 4 is a diagram showing an example of the structure of the test pattern 40 used in the test of the DUT 86. The test pattern 40 is constituted by a set of test signals generated by the circuit of the test pattern generation unit 15 and input to the IO pin of the DUT 86 in accordance with a program executed by the computer 17. The numbers L0 to L999 are line numbers in the test pattern 40.
[0038]
In FIG. 3, for example, when a semiconductor test of the DUT 86 is performed according to the test pattern 40 and a defect is found in a certain DUT 86, the test pattern 40 is divided into two parts, L0 to L500 (regions A and B in FIG. 4). The test patterns of L501 to L999 (areas C and D) are tested. When no defect is detected in the test patterns L0 to L500, the test patterns L501 to L999 are tested next. If a defect is detected at this time, the test patterns L501 to L999 are further divided into two, and the test patterns L501 to L750 (region C) and L751 to L999 (region D) are tested. At this time, when a defect is detected for the test patterns L501 to L750, the test patterns L501 to L750 are further divided into two, and each test pattern is tested.
[0039]
FIG. 5 is a flowchart showing the operation of the computer 17 related to the execution of the test execution program 231 by the CPU 21. First, the CPU 21 outputs various signals indicating the start of the test to the power supply current analyzing apparatus 11 and executes the test (step A1). Specifically, the DUT power supply 82, the frequency analysis unit 84, and the test pattern generation unit 15 output a signal indicating a test start, a setting signal indicating a voltage applied to the power supply pin of the DUT 86, and the like to the DUT power supply 82. . Further, in the test pattern 40, a setting signal for the pattern section used for the test is output to the test pattern generation unit 15. After the test, the frequency analysis unit 84 performs frequency analysis on the power supply current detected by the power supply current detection unit 83, and the analysis result is stored in the analysis result storage area 221 via the communication unit 26.
[0040]
Next, 2 is substituted into the variable m (step A2), the CPU 21 reads the analysis result storage area 221, and the analysis result of the power source current analysis device 111 to which the non-defective DUT is connected and the power source current analysis device 11m. The analysis result is compared (step A3).
[0041]
When the analysis result of the power supply current analysis device 111 to which the non-defective DUT is connected matches the analysis result of the power supply current analysis device 11m (step A4: No), the CPU 21 detects the DUT connected to the power supply current analysis device 11m. Is determined to be non-defective, and the process proceeds to step A6.
[0042]
On the other hand, if the two analysis results do not match (step A4: Yes), the CPU 21 determines that the DUT 16m connected to the power supply current analysis device 11m is defective, and shifts the processing to the defect location specifying processing program 232. Details of the program will be described later.
[0043]
Subsequently, the CPU 21 displays the comparison result in step A3, the processing result of the defective part identification processing program 232 in step A5, and the like on the display unit 25 (step A6), and adds 1 to the variable m (step A7).
[0044]
Next, the CPU 21 compares the variable n (n is the number of DUTs 86) with the variable m. If the variable m is equal to or less than the variable n (step A8: Yes), the CPU 21 proceeds to step A3. On the other hand, when the variable m is larger than the variable n (step A8: No), the CPU 21 ends the process on the assumption that all the analysis results of the power source current analysis device 11 are compared.
[0045]
FIG. 6 is a flowchart showing the operation of the computer 17 related to the execution of the defective part identification processing program 232 by the CPU 21. First, the CPU 21 substitutes the minimum line number of the test pattern 40 for the variable Lmin and the maximum line number of the test pattern 40 for the variable Lmax (step B1). For example, in the case of the test pattern 40, Lmin = 0 and Lmax = 999.
[0046]
Subsequently, the CPU 21 substitutes the calculation result of Lmax / 2 for the variable X (step B2). Here, variable X is a positive integer, and the fractional part of the solution of Lmax / 2 is rounded up.
[0047]
Next, the CPU 21 applies the patterns of line numbers Lmin to X to the power supply current analyzing apparatus connected to the defective DUT connected to the power supply current analyzing apparatus 111 connected to the non-defective DUT. The test for the section is executed, and the analysis results are compared (step B3).
[0048]
If the analysis results do not match (step B4: Yes), it is determined that a defective portion exists in the pattern section of the line numbers Lmin to X, and the defect is further detected in the section. CPU21 substitutes the variable X for the variable Lmax (step B5), and transfers a process to step B9.
[0049]
On the other hand, if the analysis results match (step B4: No), the CPU 21 is connected to the power supply current analysis device 111 to which the non-defective DUT is connected, assuming that no defective portion exists in the pattern section of the line numbers Lmin to X. The analysis results for the pattern sections of the line numbers X + 1 to Lmax are compared with the power supply current analyzing apparatus to which the DUT determined to be defective is connected (step B6).
[0050]
If the analysis results match (step B7: No), the CPU 21 ends the process, assuming that no defective portion has been detected. On the other hand, if the analysis results do not match (step B7: Yes), it is determined that a defective portion exists in the pattern section of the line numbers X + 1 to Lmax, and further defect detection is performed for the section. The CPU 21 substitutes the variable X + 1 for the variable Lmin (step B5), and compares Lmax and Lmin. If Lmax and Lmin are not the same value (step B9: No), the CPU 21 determines that further division is possible in the pattern section in which the defect is detected, and shifts the processing to step B2.
[0051]
On the other hand, if Lmax and Lmin are the same value (step B9: Yes), the CPU 21 stores the line number Lmin (or line number Lmax) in the RAM 22 as a defective line number (step B10), assuming that a defective part has been detected. The process is terminated.
[0052]
As described above, when a defect is found in the DUT 86 in the semiconductor test, the pattern section of the test pattern 40 is gradually reduced by recursively dividing the pattern section of the test pattern 40, so that the defective portion in the test pattern 40 is determined. To detect.
[0053]
Here, the line number of the test pattern 40 is divided into two. However, since the test pattern 40 includes a plurality of tests and each test is a series, it may not be separated by an arbitrary line number. Can occur. In that case, it can be realized by dividing the test pattern 40 at a part where it can be divided. More specifically, it can be realized by specifying in advance a portion that can be divided in the test pattern 40 and performing a recursive division based on the designated portion in the defective portion identification processing program 232.
[0054]
Moreover, although the defective part identification process program 232 demonstrated the case where there was one defective part, when there are a plurality of defective parts, the defective part identification process program 232 is repeated as many times as the number of defective parts. At that time, the line number that has already been detected as a defective portion needs to be removed from the detection target by storing it in the RAM 221 or the like.
[0055]
As described above, by connecting the non-defective DUT to one power supply current analyzing device among the n power supply current analyzing devices 81 and executing the test, the power supply current analyzing device to which the non-defective DUT is connected can be obtained. The analysis result is used as a reference value and compared with the analysis result of another power supply current analysis device 81. Thereby, there is no setting for determining the reference value before the test execution and storing it in the computer 87, and the test time and labor can be reduced.
[0056]
In addition, when a defective DUT is found, by executing the defective portion specifying processing program 232, by repeatedly dividing the pattern division until the defective portion in the test pattern 40 is detected, and comparing the analysis results, Detect defective parts. As a result, it is not necessary to perform another measurement for detecting a defective portion, and the test time, labor, and cost for the test can be reduced.
[0057]
【The invention's effect】
According to the first and sixth aspects of the invention, the reference value for comparing the analysis results is set in advance by determining the failure of the device under measurement by comparing the analysis results output from the plurality of power source current analysis devices. There is no need to do this, and the time and labor for determining the reference value can be reduced.
[0058]
According to the second aspect of the present invention, for example, a device to be measured that is already known as a non-defective product is installed in the power supply current analysis device set by the setting means, and the analysis result of the power supply current analysis device and other power supply current analysis By comparing with the analysis result of the apparatus, it is not necessary to set in advance a reference value for comparing the analysis result, so that time and labor for determining the reference value can be reduced.
[0059]
According to the third aspect of the present invention, by dividing the test pattern and analyzing the failure of the device under measurement, it is possible to detect the occurrence of a failure in the test pattern in the device under measurement that is defective. This eliminates the need for another measurement for detecting a defective portion, thereby reducing time and labor.
[0060]
According to the fourth aspect of the present invention, by repeating the division of the test pattern, it is possible to detect a defect occurrence location in the test pattern in the defective device under measurement. Therefore, another measurement for detecting a defective portion is unnecessary, and time and labor can be reduced.
[0061]
According to the fifth aspect of the present invention, a device under test that is already known to be non-defective is connected to one power source current analyzing device among the plurality of power source current analyzing devices, and the analysis result of the power source current analyzing device and the other By comparing with the analysis result of the power source current analysis device, it is not necessary to set a reference value for comparing the analysis result in advance, so that time and labor for determining the reference value can be reduced. Further, by repeating the division of the test pattern, for example, when a defective product is found in the device under measurement, it is possible to detect a defect occurrence location in the test pattern. This eliminates the need for another measurement for detecting a defective portion, thereby reducing time and labor. In addition, the costs associated with semiconductor testing can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor test apparatus in the present embodiment.
FIG. 2 is a diagram showing a hardware configuration of a computer 87 in the present embodiment.
FIG. 3 is a diagram showing a semiconductor test method in this embodiment.
FIG. 4 is a diagram illustrating an example of a test pattern used in a DUT test.
FIG. 5 is an operation flowchart of a test execution program.
FIG. 6 is an operation flowchart of a defect location identification processing program.
FIG. 7 is a block diagram showing a configuration of a conventional semiconductor test apparatus.
FIG. 8 shows a conventional semiconductor test method.
[Explanation of symbols]
21 CPU
22 RAM
221 Analysis result storage area 23 Storage unit 231 Test execution program 232 Defective point identification processing program 24 Input unit 25 Display unit 26 Communication unit 111 Power supply current analysis device 821 Power supply for DUT 831 Power supply current detection unit 841 Frequency analysis unit 151 Test pattern generation unit 861 DUT
17 Computer

Claims (6)

In a control device for controlling the operation of each of the power supply current analysis devices, connected to a plurality of power supply current analysis devices that apply a test pattern to the device under measurement and analyze the power supply current of the device under measurement,
Receiving means for receiving an analysis result of each of the power supply current analysis devices;
A determination unit that determines pass / fail of a device under measurement measured by each of the power supply current analysis devices by comparing the analysis results of each of the power supply current analysis devices received by the reception unit;
A control device comprising: Of the plurality of power supply current analysis devices, further comprising setting means for setting a power supply current analysis device as a reference,
The control device according to claim 1, wherein the determination unit compares analysis results of other power source current analysis devices with reference to an analysis result of the power source current analysis device set by the setting unit. Section dividing means for dividing the test pattern into one or more pattern sections;
Control means for controlling the analysis operation of the power supply current analyzing device based on the pattern section divided by the section dividing means;
The control device according to claim 1, further comprising: 4. The control apparatus according to claim 3, wherein the section dividing means further comprises means for recursively dividing the divided pattern section into one or more pattern sections. A plurality of power supply current analyzers that apply a test pattern to the device under test and analyze the power source current of the device under test
The control device according to any one of claims 1 to 4, connected to each of the power supply current analysis devices,
A semiconductor test apparatus comprising: Connected to a plurality of power supply current analysis devices that apply a test pattern to the device under measurement and analyze the power supply current of the device under measurement, and a computer for controlling the operation of each of the power supply current analysis devices,
Receiving means for receiving an analysis result of each of the power supply current analysis devices;
A determination unit that determines pass / fail of a device under measurement measured by each of the power supply current analysis devices by comparing the analysis results of each of the power supply current analysis devices received by the reception unit;
Program to make it work.

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