JP3741182B2 - Microcomputer, electronic equipment and debugging system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microcomputer, an electronic device including the microcomputer, and a debugging system.
[0002]
[Background Art and Problems to be Solved by the Invention]
In recent years, there has been an increasing demand for microcomputers that are incorporated in electronic devices such as game devices, car navigation systems, printers, and portable information terminals, and that can realize advanced information processing. Such an embedded microcomputer is usually mounted on a user board called a target system. A software development support tool called ICE (In-Circuit Emulator) is widely used to support the development of software for operating the target system.
[0003]
Conventionally, as such ICE, an ICE called a CPU replacement type as shown in FIG. In this CPU replacement type ICE, the microcomputer 302 is removed from the target system 300 during debugging, and the probe 306 of the debugging tool 304 is connected instead. Then, the debugging tool 304 is made to emulate the operation of the removed microcomputer 302. Further, the debug tool 304 is caused to perform various processes necessary for debugging.
[0004]
However, this CPU replacement type ICE has a drawback that the number of pins of the probe 306 increases and the number of lines 308 of the probe 306 increases. For this reason, it becomes difficult to emulate the high frequency operation of the microcomputer 302 (for example, about 33 MHZ is a limit). Also, the design of the target system 300 becomes difficult. Furthermore, the operating environment (signal timing and load condition) of the target system 300 changes between the actual operation in which the microcomputer 302 is mounted and operated and the debug mode in which the debugging tool 304 emulates the operation of the microcomputer 302. Resulting in. In addition, this CPU replacement type ICE has a problem that, if the microcomputer is different, even if it is a derivative product, it is necessary to use a debugging tool with a different design or a probe with a different number of pins or pin positions. there were.
[0005]
On the other hand, as a means for solving such a disadvantage of the CPU replacement type ICE, there is known an ICE of a type in which a debugging pin and a function for realizing the same function as the ICE are mounted on a mass production chip. Such a debug function implementation type ICE normally has a user mode and a debug mode. The user program is executed in the user mode, and the debugging program is executed in the debug mode.
[0006]
In a microcomputer having a user mode and a debug mode, the program may be runaway or in an infinite loop during execution of the user program in the user mode during debugging. In such a case, a means for forcibly shifting from the user mode to the debug mode is required. For this reason, a forced break function is provided, and a dedicated external terminal for realizing a normal forced break is provided.
[0007]
When the external input terminal for realizing the forced break is provided as described above, the number of pins of the package is increased. However, it is preferable that the number of terminals necessary only for debugging and unnecessary for the end user is as small as possible.
[0008]
On the other hand, in such a debug function mounting type ICE, communication with the outside (hardware other than the chip) is indispensable. However, transmission / reception with an external debug tool is performed only in the debug mode. Therefore, this transmission / reception terminal is not used in the user mode.
[0009]
The number of terminals for inputting a forced break and the terminals used only in the debug mode are unnecessary because they are unnecessary for the end user.
[0010]
The present invention has been made in view of the technical problems as described above, and an object thereof is to input a forced break in an ICE of a type in which debugging pins and functions are mounted on a mass-produced chip. It is an object of the present invention to provide a microcomputer, an electronic device including the microcomputer, and a debugging system that can save unnecessary terminals for an end user such as a terminal used only in the debugging mode.
[0011]
[Means for Solving the Problems]
In order to solve the above problems, the present invention is a microcomputer having a user mode and a debug mode, wherein the user mode and the debug mode are formed to be switchable, and a central processing unit that executes instructions in each mode, and And switching means for switching the central processing unit from the user mode to the debug mode when a forced break is input through a terminal not used in the user mode.
[0012]
Here, the forced break refers to forcibly shifting from the user mode to the debug mode.
[0013]
According to the present invention, a forced break is input using a terminal that is not used in the user mode, for example, a terminal that is used only in the debug mode. Accordingly, since there is no need to provide a dedicated terminal for forced break, the terminals of the microcomputer can be saved, and more terminals that can be used by the user can be secured.
[0014]
The present invention also includes a debugging communication terminal to which the microcomputer has an on-chip debugging function, and a communication line for transmitting and receiving debugging information for performing on-chip debugging with an external debugging tool is connected. A forced break is input through the debugging terminal.
[0015]
A microcomputer having an on-chip debugging function usually requires communication with the outside (hardware other than a chip). However, transmission / reception with an external debug tool is performed only in the debug mode, and this debug terminal is not used in the user mode.
[0016]
On the other hand, the forced break input occurs only in the user mode since it is an input for switching from the user mode to the debug mode.
[0017]
As described above, debug information and forced break input occur only in different modes. Therefore, even if the same terminal is shared, each can be distinguished and no confusion occurs.
[0018]
According to the present invention, since a terminal necessary for on-chip debugging and a terminal for inputting a forced break are shared, more terminals that can be used by the user can be secured.
[0019]
The present invention also provides a primitive in which the microcomputer transmits / receives data to / from second monitor means that is provided outside the microcomputer and performs processing for converting a debug command into at least one primitive command. A first monitor means for determining a command based on the received data from the second monitor means and performing a process for executing the determined primitive command, and transmitting the data by half-duplex bidirectional communication Including a debugging terminal to which one communication line for performing transmission and reception is connected, the central processing unit performs execution processing of a user program in user mode, performs execution processing of the primitive command in debug mode, The switching means is forcibly blurred via the debugging terminal. When the input of the click is, and switches the central processing unit to the debug mode from user mode.
[0020]
According to the present invention, the second monitoring means provided outside the microcomputer performs processing for converting (decomposing) a debug command issued by the host system or the like into a primitive command. The first monitor means receives data from the second monitor means and performs a process for executing the primitive command determined based on the received data. According to the present invention, the monitor program for executing the process of the first monitor means does not need to have a complicated routine for executing each debug command. Therefore, the instruction code size of the monitor program can be remarkably reduced, and an on-chip debugging function can be realized with a small hardware scale.
[0021]
Further, the number of debugging terminals (pins) of the microcomputer can be reduced, and the cost of the microcomputer can be reduced.
[0022]
The present invention further includes means for holding a terminal to which a forced break is input at a first level which is either high or low when an external debug tool is not connected, and the central processing unit includes: When the terminal to which the forced break is input at the reset is the first level, the execution is started in the user mode, and the terminal to which the forced break is input at the reset is not the first level. Is characterized by starting execution in debug mode.
[0023]
According to the present invention, when an external debug tool is not connected, it is held at the first level indicating either high or low by pull-up or the like. Therefore, if the terminal to which the forced break is input is configured to be at a level opposite to the first level by connecting the debugging terminal, should the terminal be started in user mode at reset? It is possible to determine whether to start in debug mode.
[0024]
On the other hand, when an external debugging tool is connected, the debugging is being performed, so it is preferable to start the execution in the debugging mode at the time of resetting. Further, when the debug tool is not connected, it is preferable to start the execution in the user mode without the user being aware of it.
[0025]
According to the present invention, it is possible to start execution in an appropriate mode at the time of resetting with a simple configuration in which it is detected whether the debugging terminal is high or low, without the user being aware of it.
[0026]
An electronic apparatus according to the present invention includes any one of the microcomputers described above, an input source of data to be processed by the microcomputer, and an output device for outputting data processed by the microcomputer. It is characterized by that.
[0027]
In this way, it becomes possible to improve the efficiency of debugging work such as a program for operating the electronic device, thereby shortening the development period of the electronic device and reducing the cost.
[0028]
The present invention is also a debug system for a target system including a microcomputer, wherein the second monitor means performs processing for converting a debug command issued by the host system into at least one primitive command;
Data is transmitted / received to / from the second monitoring means, a primitive command to be executed is determined based on the received data from the second monitoring means, and processing for executing the determined primitive command is performed. Monitor means, a user processing mode and a debugging mode are formed so as to be switchable. In the user mode, the primitive command is executed. The central processing unit is provided in a chip including the central processing unit. When a forcible break is input via a debugging terminal to which one communication line for performing two-way communication is connected and the debugging terminal, the central processing unit is switched from the user mode to the debugging mode. And switching means.
[0029]
According to the present invention, the instruction code size of the monitor program for executing the processing of the first monitoring means can be remarkably reduced. This makes it possible to increase the number of memory areas and terminals that can be freely used by the user. In addition, it is possible to provide a debugging system that can debug the target system in the same environment as the actual operating environment.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0031]
1. Features of this embodiment
First, features of the present embodiment will be described with reference to FIGS. 2A and 2B are diagrams showing a state in which the microcomputer 10 having the user mode and the debug mode and the debug tool 14 are connected.
[0032]
The microcomputer 10 includes a CPU (central processing unit) 12, an on-chip debugging unit 13, a forced break control unit 15, and a clock generation unit 17. The on-chip debug unit 13 transmits / receives debug information to / from the debug tool 14 in the debug mode, executes a debug program, and performs various debug processes.
[0033]
The microcomputer 10 includes SIOD 16 and BCLK 18 as debugging terminals. The SIOD 16 receives a forced break input signal in the user mode, and transmits / receives debug information to / from the external debug tool 14 by an asynchronous SIO in the debug mode. BCLK 18 is supplied by the clock generation unit 17 and is used as an asynchronous synchronous clock.
[0034]
By the way, transmission / reception with the external debugging tool 14 is performed only in the debugging mode, and this debugging terminal is not used in the user mode. On the other hand, the forced break input occurs only in the user mode because it is an input for switching from the user mode to the debug mode.
[0035]
Therefore, when the forced break control unit 15 receives a signal in the user mode, the forced break control unit 15 determines that a forced break has been input, and performs processing to switch the CPU 12 from the user mode to the debug mode (see FIG. 2A). . If a signal is received in the debug mode, it is determined as debug information, and the debug information is output to the on-chip debug unit 13 (see FIG. 2B).
[0036]
As described above, since the transmission / reception of debug information and the input of forced break occur only in different modes, even if the same terminal is shared as shown in FIGS. 2A and 2B, each can be distinguished and no confusion occurs. .
[0037]
Therefore, in the present embodiment, the SIOD 16 functions as a terminal for inputting a forced break input signal as shown in FIG. 2A in the user mode, and debug information as shown in FIG. 2B in the debug mode. It is configured to function as a terminal for performing transmission / reception.
[0038]
By doing so, the number of terminals required for debugging can be saved, and more terminals usable by the user can be secured.
[0039]
FIG. 3 is a timing chart showing the relationship between the forced break input and the state of the SIOD terminal.
[0040]
Reference numeral 16 'denotes SIOD of the output state on the debug tool 14 side, and 16 denotes SIOD of the input state on the microcomputer side. The debug tool outputs a high level signal during the user mode, and a low pulse is output in response to a forced break input from the outside (222). The microcomputer receives the low pulse and shifts from the user mode to the debug mode (228). The debug tool 14 outputs a high level signal for a certain period (224), and then starts communication of debug information in an asynchronous manner.
[0041]
4A and 4B are diagrams for explaining a second feature of the present embodiment. As shown in FIG. 4A, when the microcomputer 10 is not connected to the debugging tool, the SIOD terminal is pulled up to a high level. However, by connecting the debug tool 14 as shown in FIG. 4B, the SIOD terminal 16 can be set to an arbitrary level (high level or low level).
[0042]
In the present embodiment, by connecting the debug tool 14 to the microcomputer 10, a low level signal is output from the debug tool 14 so that the SIOD terminal 16 is at a low level.
[0043]
5A and 5B are diagrams for explaining the state of the SIOD terminal and the start mode at reset.
[0044]
As shown in FIG. 5A, when the SIOD is at the high level at the rise of the user RESET (230), the microcomputer starts execution in the user mode (232).
[0045]
As shown in FIG. 5B, when SIOD is at a low level at the rise of user RESET (234), the microcomputer starts execution in the debug mode (236). Therefore, the microcomputer shifts to the debug mode (238), and the debug tool side outputs a high level signal for a certain period (240), and then starts communication of debug information in an asynchronous manner (242).
[0046]
In this way, with a simple configuration of detecting whether the SIOD is at a high level or a low level at the time of user resetting, execution can be started in an appropriate mode at the time of resetting without the user being aware of it.
[0047]
Next, a third feature of the present embodiment will be described. This corresponds to the case where the on-chip debug unit 14 in FIGS. 2A and 2B has a function corresponding to the mini-monitor unit 314 described below.
[0048]
As shown in FIG. 6, in the present embodiment, the microcomputer 10 includes a CPU (central processing unit) 12 and a mini monitor unit (first monitor means) 314. A main monitor unit (second monitor means) 316 is provided outside the microcomputer 10. Here, the main monitor unit 316 performs processing for converting (decomposing) a debug command issued by, for example, the host system into a primitive command. The mini monitor unit 314 transmits and receives data to and from the main monitor unit 316. Then, the mini monitor unit 314 determines a primitive command to be executed based on the received data from the main monitor unit 316, and performs processing for executing the primitive command.
[0049]
Here, debug commands to be converted by the main monitor unit 316 include program load, GO, step execution, memory write, memory read, internal register write, internal register read, breakpoint setting, breakpoint release, etc. You can think of commands. The main monitor unit 316 sends these various complicated debug commands to, for example, GO, write (write to a given address on the memory map in the debug mode), and read (from a given address on the memory map). (Read), etc., to convert to simple and primitive commands. In this way, the instruction code size of the mini monitor program that performs the processing of the mini monitor unit 314 can be significantly reduced. Thereby, the on-chip debugging function of the microcomputer 10 can be realized.
[0050]
Normally, a debugging program has all processing routines for debugging commands such as program loading, GO, and step execution, so that it requires a large memory and is practically difficult to incorporate in a microcomputer.
[0051]
However, in the present embodiment, the mini-monitor program that performs processing of the mini-monitor unit 314 has only a simple primitive command processing routine such as GO, write, and read, and the instruction code size is very small (for example, 256 bytes). Therefore, the mini monitor program can be built in the microcomputer 10 and an on-chip debugging function can be realized. It is also possible to reduce the memory area that can be freely used by the user from the minimum to zero.
[0052]
2. Detailed configuration example
FIG. 7 shows a detailed configuration example of the microcomputer and the debug system of this embodiment. As shown in FIG. 7, the microcomputer 20 includes a CPU 22, a BCU (bus control unit) 26, an internal memory (an internal ROM and an internal RAM other than the mini monitor ROM 42 and the mini monitor RAM 44) 28, a clock generation unit 30, and a mini monitor unit 40 (first monitor). 1 monitoring means) and a trace unit 50.
[0053]
Here, the CPU 22 executes various instructions and includes an internal register 24. The internal registers 24 include general-purpose registers R0 to R15, special registers SP (stack pointer register), AHR (higher register of product-sum result data), ALR (lower register of product-sum result data), and the like. The CPU 22 has a user mode and a debug mode, and is configured to switch from the user mode to the debug mode when receiving a forced break input from the forced break control unit 49 via the line 51.
[0054]
The BCU 26 controls the bus. For example, a Harvard architecture bus 31 connected to the CPU 22, a bus 32 connected to the internal memory 28, an external bus 33 connected to the external memory 36, an internal connected to the mini monitor unit 40, the trace unit 50, and the like. The bus 34 is controlled. The clock generation unit 30 generates various clocks used in the microcomputer 20. The clock generation unit 30 also supplies a clock to the external debug tool 60 via BCLK.
[0055]
The mini monitor unit 40 includes a mini monitor ROM 42, a mini monitor RAM 44, a control register 46, an SIO 48, and a forced break control unit 49.
[0056]
Here, the mini monitor ROM 42 stores a mini monitor program. In the present embodiment, this mini monitor program only processes simple and primitive commands such as GO, read, and write. For this reason, the memory capacity of the mini-monitor ROM 42 can be suppressed to, for example, about 256 bytes, and the microcomputer 20 can be reduced in size while having an on-chip debugging function.
[0057]
The content of the internal register 24 of the CPU 22 is saved in the mini monitor RAM 44 when the mode is shifted to the debug mode (when a break of the user program occurs). As a result, the execution of the user program can be restarted properly after the debug mode ends. In addition, reading of the contents of the internal register can be realized by a primitive read command etc. possessed by the mini monitor program.
[0058]
The control register 46 is a register for controlling various debugging processes, and includes a step execution enable bit, a break enable bit, a break address bit, a trace enable bit, and the like. Various debugging processes are realized by the CPU 22 operating by the mini-monitor program writing data to each bit of the control register 46 or reading the data of each bit.
[0059]
The SIO 48 controls data for debugging transmitted / received to / from a debugging tool 60 provided outside the microcomputer 20.
[0060]
The forced break control unit 49 and the debug tool 60 are connected by SIOD (data transmission / reception line), and the forced break input and debug information are transmitted / received.
[0061]
The forced break control unit 49 determines that a forced break has been input when receiving a signal in the user mode via the SIOD, and switches the CPU 12 from the user mode to the debug mode via the line 51. Process to send a signal. When a signal is received in the debug mode, it is determined that the information is debug information, and processing for outputting the debug information to the SIO 48 is performed.
[0062]
The trace unit 50 is for realizing a real-time trace function. The trace unit 50 and the debug tool 60 are connected by four lines of 3-bit DST [2: 0] representing the instruction execution state of the CPU 22 and DPCO representing the branch destination PC (program counter) value. Has been.
[0063]
The debug tool 60 includes a main monitor unit 62 and is connected to a host system 66 realized by a personal computer or the like. When the host system 66 issues a debug command such as program load or step execution by a user operation, the main monitor unit 62 performs processing for converting (decomposing) the debug command into a primitive command. When the main monitor unit 62 transmits data instructing execution of a primitive command to the mini-monitor unit 40, the mini-monitor unit 40 performs processing for executing the instructed primitive command.
[0064]
FIG. 8 shows an example of a memory map in the debug mode. As indicated by D1, D2, and D3 in FIG. 8, in the debug mode, the addresses of the control register 46, mini monitor RAM 44, and mini monitor ROM 42 in FIG. 7 are also allocated on the memory map.
[0065]
3. Conversion to primitive command
FIGS. 9A, 9B, 9C, and 9D schematically show processing for converting various debug commands into primitive commands.
[0066]
For example, as shown in FIG. 9A, a 12-byte program (ADD ..., SUB ..., AND ..., OR ..., XOR ..., LD.W ...) Assume that a debug command for loading at address 80010h is issued. In this case, the program load command includes write (80010h, ADD ..., SUB), write (80013h, AND ..., OR ...), write (80018h, XOR ..., LD.W ... .) Is converted into three primitive write commands. That is, the program load command is realized by the mini monitor program executing these three primitive write commands.
[0067]
Assume that a debug command called a step execution command is issued as shown in FIG. Then, this step execution command is converted into a write command to the step execution enable bit of the control register 46 in FIG. 7 (write command to the address D1 in FIG. 8) and a GO command. That is, the mini monitor program executes the primitive write command and the GO command, thereby realizing a step execution command.
[0068]
Assume that a debug command called an internal register read command is issued as shown in FIG. Then, this internal register read command is converted into a read command (read command from the address D2 in FIG. 8) from the mini monitor RAM (save destination of the contents of the internal register) on the memory map. That is, when the mini monitor program executes this primitive read command, the internal register read command is realized. The internal register write command, memory read command, and memory write command are also realized in the same manner.
[0069]
Assume that a debug command called a breakpoint setting command is issued as shown in FIG. Then, this breakpoint setting command is converted into a write command to the break enable bit and break address bit of the control register 46. That is, the breakpoint setting command is realized by the mini monitor program executing this primitive write command.
[0070]
As described above, in this embodiment, complicated and various debug commands are converted into primitive, simple read, write, and GO commands. Since the mini-monitor program only needs to execute these primitive read, write, and GO commands, the instruction code size of the mini-monitor program becomes very small. As a result, the memory capacity of the mini monitor ROM 42 can be reduced, and an on-chip debugging function can be realized with a small hardware scale.
[0071]
4). SIO configuration example
FIG. 10 shows a configuration example of the SIO 48. The SIO 48 includes a transmission / reception buffer 70, a shift register 76, a transmission / reception switching unit 78, a clock control unit 80, and a control register 84.
[0072]
Here, the transmission / reception buffer 70 is for temporarily storing transmission data and reception data, and includes a transmission buffer 72 and a reception buffer 74. The shift register 76 has a function of converting transmission data from the transmission buffer 72 from parallel data to serial data and outputting it to the transmission / reception switching unit 78. Also, it has a function of converting received data from the transmission / reception switching unit 78 from serial data to parallel data and outputting it to the reception buffer 74. The transmission / reception switching unit 78 is for switching between transmission and reception of data. Thereby, half-duplex data transmission / reception using SIOD becomes possible.
[0073]
The clock control unit 80 divides BCLK by the built-in frequency dividing circuit 82, and outputs the sampling clock SMC 1 obtained by this frequency division to the shift register 76. The shift register 76 operates based on this SMC1. Further, since this BCLK is supplied to the debug tool 60, the BCLK is shared by the microcomputer 20 and the debug tool 60.
[0074]
The frequency dividing ratio in the frequency dividing circuit 82 is set by the control register 84. That is, the mini monitor program executed by the CPU 22 writes a desired frequency dividing ratio in the control register 84, whereby the frequency dividing ratio in the frequency dividing circuit 82 is set.
[0075]
5. Debug tool configuration example
FIG. 11 shows a configuration example of the debug tool 60.
[0076]
The CPU 90 executes a program stored in the ROM 108 and controls the entire debug tool 60. The transmission / reception switching unit 92 is for switching between transmission and reception of data. The clock control unit 94 controls a clock supplied to the SCLK terminal of the CPU 90, the address up counter 100, and the trace memory 104. The clock control unit 94 receives BCLK from the microcomputer 20 (SIO 48). The clock control unit 94 includes a frequency detection circuit 95 and a frequency dividing circuit 96. The frequency detection circuit 95 detects the frequency range to which BCLK belongs and outputs the result to the control register 98. The frequency dividing ratio in the frequency dividing circuit 96 is controlled by the control register 98. That is, the main monitor program (stored in the main monitor ROM 110) executed by the CPU 90 reads the frequency range of BCLK from the control register 98. Then, the main monitor program determines an optimum frequency division ratio corresponding to this frequency range, and writes this frequency division ratio in the control register 98. Then, the frequency dividing circuit 96 divides BCLK by this frequency dividing ratio to generate SMC2, and outputs it to the SCLK terminal of the CPU 90.
[0077]
The address up counter 100 is for counting up the address of the trace memory. The selector 102 selects either the line 122 (address output from the address up counter 100) or the line 124 (address from the address bus 120), and outputs data to the address terminal of the trace memory 104. The selector 106 selects either the line 126 (DST [2: 0], DPCO which is the output of the trace unit 50 in FIG. 3) or the line 128 (data bus 118), and the data is input to the data terminal of the trace memory 104. Or retrieve data from the data terminal.
[0078]
The ROM 108 includes a main monitor ROM 110 (corresponding to the main monitor unit 62 in FIG. 3), and the main monitor ROM 110 stores a main monitor program. As described with reference to FIGS. 5A to 5D, the main monitor program performs processing for converting a debug command into a primitive command. The RAM 112 serves as a work area for the CPU 90.
[0079]
The RS232C interface 114 and the parallel interface 116 serve as an interface with the host system 66 of FIG. 3, and debug commands from the host system 66 are input to the CPU 90 via these interfaces. The clock generation unit 118 generates a clock for operating the CPU 90 and the like.
[0080]
6). Send and receive data
Now, as shown in FIG. 12A, as a method of communication of debug data between the mini monitor unit 40 and the main monitor unit 62, TXD (transmission) and RXD (reception) lines are provided separately, A method of communicating in duplex is conceivable.
[0081]
However, if two lines (terminals) are used for communication of debug data in this way, the number of terminals (number of pins) of the microcomputer increases accordingly, which is a high cost of the microcomputer. Invite
[0082]
Therefore, in the present embodiment, as shown in FIG. 12B, a single TXD / RXD line (bidirectional communication line) is provided between the mini monitor unit 40 and the main monitor unit 62, and a half duplex bidirectional operation is performed. Communicate. In this embodiment, this line is shared with SIOD for inputting a forced break. For this reason, the increase in the number of terminals of the microcomputer can be minimized, and the cost of the microcomputer can be reduced.
[0083]
Further, in the present embodiment, as shown in FIG. 12C, the processing corresponding to the received data is performed on condition that the mini-monitor unit 40 serving as the slave has received data from the main monitor unit 62 serving as the master. The response data corresponding to the received data is transmitted to the main monitor unit 62. That is, when the main monitor unit 62 transmits data (command) to the mini-monitor unit 40, the mini-monitor unit 40 in the wait state receives this, and performs processing corresponding to the received data. Then, data (reply) corresponding to the received data is transmitted to the main monitor unit 62. Thereafter, the mini monitor unit 40 waits until data is received from the main monitor unit 62. That is, the mini monitor unit 40 stops operating until data is received from the main monitor unit 62, and starts operating on the condition that the data has been received. In this way, data can be properly transmitted and received while the communication line between the mini monitor unit 40 and the main monitor unit 62 is single.
[0084]
7). Detailed processing example of the mini monitor
Next, a detailed processing example of the mini monitor unit will be described.
[0085]
As shown in FIG. 13, when a break occurs during execution of the user program, processing of the mini-monitor program starts and shifts from the user program execution mode to the debug mode. When the mini monitor program executes a given command process and executes a return instruction, the program returns from the debug mode to the user program execution mode.
[0086]
FIGS. 14 and 15 are flowcharts showing the processing of the mini monitor program in the debug mode.
[0087]
When shifting to the debug mode, the mini-monitor program first saves the contents of the internal register 24 of the CPU 22 in FIG. 7 to the monitor RAM 44 (step S1). Then, setting processing of the control register 46 used by the mini monitor program is performed (step S2).
[0088]
Next, the 14-byte data received from the debug tool 60 is written to the reception buffer 74 (see FIG. 10) (step S3). Then, the first byte (command identification data ID) of the data in the reception buffer 74 is checked (step S4).
[0089]
Then, as shown in FIG. 13, when the ID indicates a read command, a read address is acquired from the reception buffer 74 (steps S5 and S6). Then, data is read from the acquired read address and written to the transmission buffer 72 (step S7). Next, the data in the transmission buffer 72 is transmitted to the debug tool 60 (step S8). Then, the process returns to step S3 in FIG.
[0090]
If the ID indicates a write command, the write address is acquired from the reception buffer 74 (steps S9 and S10). Then, write data is acquired from the reception buffer 74 and written to the write address acquired in step S10 (step S11).
[0091]
If the ID indicates an external routine jump command, the routine address is acquired from the reception buffer 74 (steps S12 and S13). Then, after jumping to the external routine, the process returns to the mini monitor program (step S14).
[0092]
If the ID indicates a GO command, the data saved in the monitor RAM 44 is restored to the internal register 24 (steps S15 and S16). Then, as shown in FIG. 13, the process returns to the user program and exits from the debug mode (step S17).
[0093]
On the other hand, if the ID is not any of read, write, external routine jump, and GO command, it is determined that no processing is required (steps S15 and S18). Then, dummy data is written to the transmission buffer 72 (step S19). In FIG. 15, the processing of the data fill command is omitted.
[0094]
As described above, the primitive command obtained by converting the debug command is executed by the mini monitor program.
[0095]
8). Electronics
Next, an electronic apparatus including the microcomputer according to this embodiment will be described.
[0096]
For example, FIG. 16A shows an internal block diagram of a car navigation system which is one of electronic devices, and FIG. 17A shows an external view thereof. The operation of the car navigation system is performed using the remote controller 510, and the position detection unit 520 detects the position of the vehicle based on information from the GPS and the gyro. Information such as a map is stored in a CDROM 530 (information storage medium). The image memory 540 is a memory serving as a work area for image processing, and the generated image is displayed to the driver using the image output unit 550. The microcomputer 500 receives data from a data input source such as the remote controller 510, the position detection unit 520, and the CDROM 530, performs various processes, and outputs the processed data using an output device such as the image output unit 550.
[0097]
FIG. 16B shows an internal block diagram of a game device which is one of electronic devices, and FIG. 17B shows an external view thereof. In this game apparatus, based on the operation information of the player from the game controller 560, the game program from the CD ROM 570, the player information from the IC card 580, and the like, a game image and game sound are generated using the image memory 590 as a work area. Output is performed using the output unit 610 and the sound output unit 600.
[0098]
FIG. 16C shows an internal block diagram of a printer which is one of electronic devices, and FIG. 17C shows an external view thereof. In this printer, based on the operation information from the operation panel 620 and the character information from the code memory 630 and the font memory 640, a print image is generated using the bitmap memory 650 as a work area and is output using the print output unit 660. . The printer status and mode are communicated to the user using the display panel 670.
[0099]
According to the microcomputer or the debugging system of the present embodiment, it becomes possible to facilitate the development of a user program for operating the electronic devices of FIGS. 16A to 17C and shorten the development period. In addition, since the user program can be debugged in the same environment as the environment in which the microcomputer actually operates, the reliability of the electronic device can be improved. Further, since the hardware of the microcomputer incorporated in the electronic device can be reduced in size and cost, the cost of the electronic device can be reduced. Furthermore, since the instruction code size of the mini monitor program is small, it becomes possible that the user does not use any memory area used for storing the program and various data.
[0100]
In addition to the above, the electronic apparatus to which the microcomputer of the present embodiment can be applied includes, for example, a mobile phone (cellular phone), a PHS, a pager, an audio device, an electronic notebook, an electronic desk calculator, a POS terminal, and a touch panel. Various devices such as a projector, a word processor, a personal computer, a television, a viewfinder type or a monitor direct-view type video tape recorder can be considered.
[0101]
In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.
[0102]
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of a CPU replacement type ICE.
FIGS. 2A and 2B are diagrams for explaining the features of the present embodiment. FIGS.
FIG. 3 is a timing chart showing the relationship between forced break input and the state of a SIOD terminal.
4A and 4B are diagrams for explaining a second feature of the present embodiment. FIG.
FIGS. 5A and 5B are diagrams for explaining a state of a SIOD terminal and a start mode at reset.
FIG. 6 is a diagram for explaining a third feature of the present embodiment.
FIG. 7 is a functional block diagram illustrating a configuration example of a microcomputer and a debugging system according to the present embodiment.
FIG. 8 is a diagram showing a memory map in a debug mode.
FIGS. 9A, 9B, 9C, and 9D are diagrams for explaining processing for converting (decomposing) a debug command into a primitive command.
FIG. 10 is a functional block diagram illustrating a configuration example of an SIO.
FIG. 11 is a functional block diagram illustrating a configuration example of a debug tool.
FIGS. 12A, 12B, and 12C are diagrams for explaining a communication method between a mini-monitor unit and a main monitor unit.
FIG. 13 is a diagram for explaining a transition from a user program execution mode to a debug mode.
FIG. 14 is a flowchart for explaining a detailed processing example of the present embodiment;
FIG. 15 is a flowchart for explaining a detailed processing example of the present embodiment;
16A, 16B, and 16C are examples of internal block diagrams of various electronic devices.
17A, 17B, and 17C are examples of external views of various electronic devices.
[Explanation of symbols]
10 Microcomputer
12 CPU (Central Processing Unit)
13 On-chip debug section
14 Debug Tool
15 Forced break control unit
16 SIOD
17 Clock controller
18 BCLK
20 Microcomputer
22 CPU (Central Processing Unit)
24 Internal registers
26 BCU (Bus Control Unit)
28 Internal memory
30 Clock generator
31 bus
32 buses
33 External bus
34 Internal bus
36 External memory
40 Mini monitor unit (first monitor means)
42 Mini monitor ROM
44 Mini monitor RAM
46 Control register
48 SIO
49 Forced break controller
50 Trace part
60 Debug Tool
62 Main monitor section (second monitor means)
66 Host system
70 Send / Receive buffer
72 Transmission buffer
74 Receive buffer
76 Shift register
78 Transmission / reception switching unit
80 Clock controller
82 divider circuit
84 Control register
90 CPU
92 Transmission / reception switching unit
94 Clock controller
95 Frequency detector
96 divider circuit
98 Control register
100 address up counter
102 selector
104 Trace memory
106 Selector
108 ROM
110 Main monitor ROM
112 RAM
114 RS232C interface
116 Parallel interface
118 Clock generator
316 Main monitor section (second monitor means)

Claims (4)

There are a user mode in which a user program is executed and a debug mode in which a debug command is executed. In the debug mode, two or more such as a debug command stored in advance and a GO, a write, and a read are stored outside the microcomputer. Data with the second monitoring means for performing processing for converting the debug command issued by the host system into a combination of two or more primitive commands such as GO, write, and read in accordance with the correspondence of the combination of primitive commands A microcomputer configured to transmit and receive
A central processing unit formed to be switchable between user mode and debug mode;
First monitoring means for performing processing for performing on-chip debugging in debug mode;
A debugging terminal to which one communication line for transmitting / receiving data for performing on-chip debugging to / from external second monitoring means by half-duplex bidirectional communication is connected;
When a signal of a predetermined level is received through the debugging terminal in the user mode, it is determined that a forced break has been input, and a forced break signal for switching from the user mode to the debug mode is sent to the central processing unit. A break processing unit,
The first monitoring means includes
A memory storing a mini-monitor program for processing primitive commands such as GO, write, and read;
When execution instruction data for instructing execution of primitive commands such as GO, write, and read is received from the second monitor means provided outside the microcomputer in the debug mode, the mini monitor program stored in the memory is activated to Means for performing processing for executing a primitive command instructed by the execution instruction data;
The central processing unit is
When the forced break signal is received, the mode is switched from the user mode to the debug mode. In the debug mode, the memory storing the mini monitor program is allocated to the memory map, and the mini monitor program is executed to execute primitive commands such as GO, write, and read. The microcomputer which performs the process of. In claim 1,
In a state where no external debugging tool is connected, a circuit for holding the debugging terminal at a first level which is either high or low,
The central processing unit is
When it is detected that the debug terminal is at the first level at reset, execution starts in the user mode, and when it is detected at reset that the debug terminal is not at the first level, execution is started in debug mode. The microcomputer is configured as described above. A microcomputer according to claim 1;
An input source of data to be processed by the microcomputer;
And an output device for outputting data processed by the microcomputer. A debugging system for a target system including a microcomputer,
A debug command issued by the host system in accordance with a combination of a pre-stored debug command and a combination of two or more primitive commands such as GO, write, and read is converted into a combination of two or more primitive commands such as GO, write, and read. Second monitoring means for performing processing for conversion;
A central processing unit formed to be switchable between user mode and debug mode;
First monitoring means for performing processing for performing on-chip debugging in debug mode;
A debugging terminal to which one communication line for transmitting / receiving data for performing on-chip debugging to / from external second monitoring means by half-duplex bidirectional communication is connected;
When a signal of a predetermined level is received through the debugging terminal in the user mode, it is determined that a forced break has been input, and a forced break signal for switching from the user mode to the debug mode is sent to the central processing unit. A break processing unit,
The first monitoring means includes
A memory storing a mini-monitor program for processing primitive commands such as GO, write, and read;
When execution instruction data for instructing execution of primitive commands such as GO, write, and read is received from the second monitor means provided outside the microcomputer in the debug mode, the mini monitor program stored in the memory is activated to Means for performing processing for executing a primitive command instructed by the execution instruction data;
The central processing unit is
When the forced break signal is received, the mode is switched from the user mode to the debug mode. In the debug mode, the memory storing the mini monitor program is allocated to the memory map, and the mini monitor program is executed to execute primitive commands such as GO, write, and read. A debugging system characterized by performing the above process.

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