JP2005251217A - Microcomputer, electronic equipment and debugging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer, an electronic device and a debugging system capable of realizing an on-chip debugging function with a small instruction code size.
The microcomputer transmits and receives data between the central processing unit and the second monitor means, and determines a primitive command to be executed based on the received data from the second monitor means. First monitoring means 40 for performing processing for executing the primitive command. The first monitor means 40 includes a monitor ROM 42 in which a monitor program including the instruction code of the primitive command is stored, and the received data from the second monitor means 62 includes identification data for identifying the primitive command. When receiving the reception data from the second monitoring unit 62, the first monitoring unit 40 executes the primitive command of the instruction code specified by the identification data included in the reception data.
[Selection] Figure 3

Description

  The present invention relates to a microcomputer, an electronic device including the microcomputer, and a debugging system.

  In recent years, there has been an increasing demand for microcomputers that are incorporated in electronic devices such as game devices, car navigation systems, printers, and portable information terminals, and that can realize advanced information processing. Such an embedded microcomputer is usually mounted on a user board called a target system. A software development support tool called ICE (In-Circuit Emulator) is widely used to support the development of software for operating the target system.

  Conventionally, as such ICE, an ICE called a CPU replacement type as shown in FIG. In this CPU replacement type ICE, the microcomputer 302 is removed from the target system 300 during debugging, and the probe 306 of the debugging tool 304 is connected instead. Then, the debugging tool 304 is made to emulate the operation of the removed microcomputer 302. Further, the debug tool 304 is caused to perform various processes necessary for debugging.

  However, this CPU replacement type ICE has a drawback that the number of pins of the probe 306 increases and the number of lines 308 of the probe 306 increases. For this reason, it becomes difficult to emulate the high frequency operation of the microcomputer 302 (for example, about 33 MHZ is a limit). Also, the design of the target system 300 becomes difficult. Furthermore, the operating environment (signal timing and load condition) of the target system 300 changes between the actual operation in which the microcomputer 302 is mounted and operated and the debug mode in which the debugging tool 304 emulates the operation of the microcomputer 302. Resulting in. In addition, this CPU replacement type ICE has a problem that, if the microcomputer is different, even if it is a derivative product, it is necessary to use a debugging tool with a different design or a probe with a different number of pins or pin positions. there were.

  On the other hand, an ICE of the type in which the monitor program 310 is mounted on the target system 312 as shown in FIG. However, in the conventional monitor program mounting type ICE, all debug commands (program load, GO, step execution, memory read / write, internal register read / write, breakpoint setting / release are included in the monitor program 310. ) Must be provided. Therefore, the instruction code size of the monitor program 310 becomes very large (for example, 30 to 50 Kbytes). For this reason, there is a problem that the memory area that can be freely used by the user is reduced and the system is different between debugging and non-debugging. As a method for solving the problem of FIG. 1B, there is a method called on-chip debugging in which a monitor program is placed on a chip. If a monitor program having a large instruction code size is provided in the chip, the chip size is increased. There is a problem that it will.

  The present invention has been made in view of the above technical problems, and an object thereof is a microcomputer capable of realizing an on-chip debugging function with a small instruction code size or circuit scale, and an electronic apparatus including the microcomputer And providing a debugging system.

  In order to solve the above-described problems, the present invention is a microcomputer having an on-chip debugging function, and a central processing unit for executing instructions and a debugging command provided outside the microcomputer as at least one primitive command. To transmit / receive data to / from the second monitoring unit that performs processing for conversion, determine a primitive command to be executed based on the received data from the second monitoring unit, and execute the determined primitive command The first monitor means includes a monitor ROM that stores a monitor program for executing the process of the first monitor means, and the monitor program includes: Including the instruction code of the primitive command, and from the second monitor means The received data includes identification data for identifying the primitive command, and the first monitor means includes the identification data included in the received data when the received data is received from the second monitor means. A primitive command having an instruction code specified by is executed.

  The present invention also relates to a microcomputer having an on-chip debugging function, comprising: a central processing unit that executes instruction execution processing; and processing for converting a debug command into at least one primitive command provided outside the microcomputer. Data is transmitted / received to / from the second monitoring means to be executed, a primitive command to be executed is determined based on the received data from the second monitoring means, and a process for executing the determined primitive command is performed. And a control register which is used for instruction execution processing of the central processing unit and whose address is allocated on the memory map in the debug mode, wherein the second monitoring means is a step which is the debug command. Execute command, step execution enable bit A first primitive command that is a write command to the second command and a second primitive command that is a GO command, and the first monitoring means executes the first and second primitive commands, thereby performing a step. An execution process is performed.

  The present invention also relates to a microcomputer having an on-chip debugging function, comprising: a central processing unit that executes instruction execution processing; and processing for converting a debug command into at least one primitive command provided outside the microcomputer. Data is transmitted / received to / from the second monitoring means to be executed, a primitive command to be executed is determined based on the received data from the second monitoring means, and a process for executing the determined primitive command is performed. Monitoring means, a reception buffer for temporarily storing the reception data from the second monitoring means, and a transmission buffer for temporarily storing transmission data to the second monitoring means, The received data from the second monitor means identifies the primitive command. The first monitor means obtains a read address from the received data in the reception buffer when the identification data of the received data indicates a primitive command of a read command; When data is read from the acquired read address, the read data is written to the transmission buffer, and the identification data of the reception data indicates a primitive command of a write command, the data of the reception buffer A write address and write data are acquired from received data, and the process of writing the acquired write data to the acquired write address is performed.

  According to the present invention, when the received identification data indicates a primitive command of an external routine jump command, the first monitor means acquires a routine address from the received data in the reception buffer and externally A jump is made to the routine, and after the jump, a process of returning to the process of the first monitoring means is performed.

  Further, the present invention includes a monitor RAM in which the contents of the internal register of the central processing unit are saved and the address is assigned on the memory map in the debug mode. The first monitor means receives the identification data as GO If the command indicates a primitive command, the data saved in the monitor RAM is restored to the internal register, and the process of returning to the process of the user program after the restoration is performed.

  The present invention is also a debug system for a target system including a microcomputer, the second monitor means for performing processing for converting a debug command issued by a host system into at least one primitive command, A first monitor that transmits and receives data to and from the second monitoring means, determines a primitive command to be executed based on the received data from the second monitoring means, and performs processing for executing the determined primitive command The first monitor means includes a monitor ROM in which a monitor program for executing the processing of the first monitor means is stored, and the monitor program includes an instruction code of the primitive command. , The received data from the second monitor means is the primitive. Including identification data for identifying a command, and the first monitor means, when receiving the received data from the second monitor means, an instruction code specified by the identification data included in the received data The primitive command is executed.

  The present invention is also a debug system for a target system including a microcomputer, the second monitor means for performing processing for converting a debug command issued by a host system into at least one primitive command, A first monitor that transmits and receives data to and from the second monitoring means, determines a primitive command to be executed based on the received data from the second monitoring means, and performs processing for executing the determined primitive command And a control register which is used for instruction execution processing of the central processing unit and whose address is allocated on the memory map in the debug mode, the second monitoring means is a step execution command which is the debug command To the step execution enable bit. The first monitor command is converted into a first primitive command that is a command and a second primitive command that is a GO command, and the first monitoring means executes the first and second primitive commands, thereby performing step execution processing. It is characterized by performing.

  The present invention is also a debug system for a target system including a microcomputer, the second monitor means for performing processing for converting a debug command issued by a host system into at least one primitive command, A first monitor that transmits and receives data to and from the second monitoring means, determines a primitive command to be executed based on the received data from the second monitoring means, and performs processing for executing the determined primitive command Means, a reception buffer for temporarily storing the reception data from the second monitoring means, and a transmission buffer for temporarily storing transmission data to the second monitoring means, The received data from the second monitoring means is an identification data for identifying the primitive command. The first monitor means obtains a read address from the received data in the receive buffer, if the identification data of the received data indicates a primitive command of a read command, When data is read from the read address, the read data is written to the transmission buffer, and the identification data of the reception data indicates a primitive command of a write command, the reception data of the reception buffer The write address and the write data are acquired from the data, and the process of writing the acquired write data to the acquired write address is performed.

  The present invention also relates to a microcomputer having an on-chip debugging function, comprising: a central processing unit that executes instruction execution processing; and processing for converting a debug command into at least one primitive command provided outside the microcomputer. Data is transmitted / received to / from the second monitoring means to be executed, a primitive command to be executed is determined based on the received data from the second monitoring means, and a process for executing the determined primitive command is performed. And monitoring means.

  According to the present invention, the second monitoring means provided outside the microcomputer performs processing for converting (decomposing) a debug command issued by the host system or the like into a primitive command. The first monitor means receives data from the second monitor means and performs a process for executing the primitive command determined based on the received data. According to the present invention, the monitor program for executing the process of the first monitor means does not need to have a complicated routine for executing each debug command. Therefore, the instruction code size of the monitor program can be remarkably reduced, and an on-chip debugging function can be realized with a small hardware scale.

  In the present invention, the primitive command includes a command for starting execution of a user program, a command for writing data to an address on a memory map in a debug mode, and a command for reading data from an address on the memory map. It is characterized by that. Thus, by simplifying the primitive command, the instruction code size of the monitor program can be further reduced.

  The present invention is also characterized in that it includes a control register which is used for instruction execution processing of the central processing unit and whose address is allocated on a memory map in debug mode. In this way, it becomes possible to perform a debugging process using the control register in the debug mode, thereby simplifying the process and reducing the hardware scale.

  The present invention also includes a monitor RAM in which the contents of the internal register of the central processing unit are saved and the address is allocated on the memory map in the debug mode. In this way, it is possible to read the contents of the internal register in the debug mode, thereby realizing a wider variety of debug functions.

  The present invention also includes a terminal to which one bidirectional communication line for performing half-duplex bidirectional communication with the second monitoring means is connected, and the first monitoring means serving as a slave. On the condition that data has been received from the second monitoring means serving as a master, and performing processing corresponding to the received data and transmitting response data corresponding to the received data to the second monitoring means. Features. In this way, the number of terminals (pins) of the microcomputer can be reduced, and the cost of the microcomputer can be reduced. Further, the communication protocol between the first and second monitoring means can be simplified, and the instruction code size of the monitor program can be further reduced.

  Further, the invention is characterized in that the received data from the second monitor means includes identification data of a primitive command executed by the first monitor means. In this way, it is possible to easily transmit an instruction to execute a primitive command from the second monitor unit to the first monitor unit.

  Further, the present invention is characterized in that the first monitor means transmits and receives fixed-length data to and from the second monitor means. By doing so, it is possible to further reduce the instruction code size of the monitor program of the first monitor means.

  The present invention is also characterized in that a monitor program for executing the processing of the first monitor means is stored in a ROM. By doing so, the monitor program is stored in a ROM that occupies a smaller area than the RAM, and a logic circuit for loading the monitor program into the RAM becomes unnecessary. Therefore, the microcomputer can be further downsized.

  According to the present invention, the first monitor means divides the first clock and generates a first sampling clock for sampling each bit of data transmitted and received in an asynchronous manner. And a circuit for transmitting and receiving data based on the first sampling clock, wherein the first monitor means is a second frequency divider circuit included in the second monitor means is a second sampling clock. The first clock is supplied to the second monitor means as a signal for generating the signal. Thus, by sharing the first clock for generating the sampling clock between the first and second monitoring means, it is possible to significantly reduce the rate of occurrence of sampling errors in communication data, Communication speed can be optimized and increased.

  The present invention also includes a monitor RAM in which the first monitor means is readable and writable. When the first monitor means breaks the execution of the user program and shifts to the debug mode, the central processing unit The program counter value and the contents of the internal register are saved in the monitor RAM. By doing so, the user program can be properly executed when returning from the debug mode to the user program execution mode. Further, the first monitor means can perform various processes using the contents of the internal register.

  An electronic apparatus according to the present invention includes any one of the above microcomputers, an input source of data to be processed by the microcomputer, and an output device for outputting data processed by the microcomputer. It is characterized by that. In this way, it becomes possible to improve the efficiency of debugging work such as a program for operating the electronic device, thereby shortening the development period of the electronic device and reducing the cost.

  The present invention is also a debug system for a target system including a microcomputer, the second monitor means for performing processing for converting a debug command issued by a host system into at least one primitive command, A first monitor that transmits and receives data to and from the second monitoring means, determines a primitive command to be executed based on the received data from the second monitoring means, and performs processing for executing the determined primitive command According to the present invention, the instruction code size of the monitor program for executing the processing of the first monitor means can be remarkably reduced. This makes it possible to increase the memory area that the user can freely use. In addition, it is possible to provide a debugging system that can debug the target system in the same environment as the actual operating environment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

1. Features of this embodiment First, features of this embodiment will be described with reference to FIG.

  As shown in FIG. 2, in the present embodiment, the microcomputer 10 includes a CPU (central processing unit) 12 and a mini-monitor unit (first monitor means) 14 that is a main part of the present embodiment. A main monitor unit (second monitor means) 16 is provided outside the microcomputer 10. Here, the main monitor unit 16 performs processing for converting (decomposing) a debug command issued by, for example, a host system into a primitive command. The mini monitor unit 14 transmits and receives data to and from the main monitor unit 16. Then, the mini monitor unit 14 determines a primitive command to be executed based on the received data from the main monitor unit 16, and performs processing for executing the primitive command.

  Here, debug commands to be converted by the main monitor unit 16 include program load, GO, step execution, memory write, memory read, internal register write, internal register read, breakpoint setting, breakpoint release, etc. You can think of commands. The main monitor unit 16 sends these various complex debug commands to, for example, GO, write (write to a given address on the memory map in debug mode), read (from a given address on the memory map). (Read), etc., to convert to simple and primitive commands. In this way, the instruction code size of the mini monitor program that performs the processing of the mini monitor unit 14 can be significantly reduced. Thereby, the on-chip debugging function of the microcomputer 10 can be realized.

  That is, in the ICE of the type shown in FIG. 1B, the monitor program 310 has all processing routines for debug commands such as program load, GO, and step execution. For this reason, the instruction code size of the monitor program 310 becomes very large (for example, 30 to 50 Kbytes), and it becomes practically difficult to incorporate the monitor program 310 in the microcomputer 314.

  On the other hand, in the present embodiment, the mini monitor program that performs processing of the mini monitor unit 14 has only a simple primitive command processing routine such as GO, write, and read, and the instruction code size is very small (for example, 256 bytes). Therefore, the mini monitor program can be built in the microcomputer 10 and an on-chip debugging function can be realized. Further, it is possible to minimize the decrease in the memory area that can be freely used by the user or not to reduce it at all.

2. Detailed Configuration Example FIG. 3 shows a detailed configuration example of the microcomputer and debug system of the present embodiment. As shown in FIG. 3, the microcomputer 20 includes a CPU 22, a BCU (bus control unit) 26, an internal memory (an internal ROM and an internal RAM other than the mini monitor ROM 42 and the mini monitor RAM 44) 28, a clock generation unit 30, and a mini monitor unit 40 (first monitor). 1 monitoring means) and a trace unit 50.

  Here, the CPU 22 executes various instructions and includes an internal register 24. The internal registers 24 include general-purpose registers R0 to R15, special registers SP (stack pointer register), AHR (higher register of product-sum result data), ALR (lower register of product-sum result data), and the like.

  The BCU 26 controls the bus. For example, a Harvard architecture bus 31 connected to the CPU 22, a bus 32 connected to the internal memory 28, an external bus 33 connected to the external memory 36, an internal connected to the mini monitor unit 40, the trace unit 50, and the like. The bus 34 is controlled.

  The clock generation unit 30 generates various clocks used in the microcomputer 20. The clock generation unit 30 also supplies a clock to the external debug tool 60 via BCLK.

  The mini monitor unit 40 includes a mini monitor ROM 42, a mini monitor RAM 44, a control register 46, and an SIO 48.

  Here, the mini monitor ROM 42 stores a mini monitor program. In the present embodiment, this mini monitor program only processes simple and primitive commands such as GO, read, and write. For this reason, the memory capacity of the mini-monitor ROM 42 can be suppressed to, for example, about 256 bytes, and the microcomputer 20 can be reduced in size while having an on-chip debugging function.

  The content of the internal register 24 of the CPU 22 is saved in the mini monitor RAM 44 when the mode is shifted to the debug mode (when a break of the user program occurs). As a result, the execution of the user program can be restarted properly after the debug mode ends. In addition, reading of the contents of the internal register can be realized by a primitive read command etc. possessed by the mini monitor program.

  The control register 46 is a register for controlling various debugging processes, and includes a step execution enable bit, a break enable bit, a break address bit, a trace enable bit, and the like. Various debugging processes are realized by the CPU 22 operating by the mini-monitor program writing data to each bit of the control register 46 or reading the data of each bit.

  The SIO 48 is for transmitting and receiving data to and from the debug tool 60 provided outside the microcomputer 20. The SIO 48 and the debug tool 60 are connected by TXD / RXD (data transmission / reception line).

  The trace unit 50 is for realizing a real-time trace function. The trace unit 50 and the debug tool 60 are connected by four lines of 3-bit DST [2: 0] representing the instruction execution state of the CPU 22 and DPCO representing the branch destination PC (program counter) value. Has been.

  The debug tool 60 includes a main monitor unit 62 and is connected to a host system 66 realized by a personal computer or the like. When the host system 66 issues a debug command such as program load or step execution by a user operation, the main monitor unit 62 performs processing for converting (decomposing) the debug command into a primitive command. When the main monitor unit 62 transmits data instructing execution of a primitive command to the mini-monitor unit 40, the mini-monitor unit 40 performs processing for executing the instructed primitive command.

  FIG. 4 shows an example of a memory map in the debug mode. As indicated by D1, D2, and D3 in FIG. 4, in the debug mode, the addresses of the control register 46, mini monitor RAM 44, and mini monitor ROM 42 in FIG. 3 are also allocated on the memory map.

3. Conversion to Primitive Command FIGS. 5A, 5B, 5C, and 5D schematically show processing for converting various debug commands to primitive commands.

  For example, as shown in FIG. 5A, a 12-byte program (ADD ..., SUB ..., AND ..., OR ..., XOR ..., LD.W ...) Assume that a debug command for loading at address 80010h is issued. In this case, the program load command includes write (80010h, ADD ..., SUB), write (80013h, AND ..., OR ...), write (80018h, XOR ..., LD.W ... .) Is converted into three primitive write commands. That is, the program load command is realized by the mini monitor program executing these three primitive write commands.

  Assume that a debug command called a step execution command is issued as shown in FIG. Then, this step execution command is converted into a write command to the step execution enable bit of the control register 46 in FIG. 3 (write command to the address D1 in FIG. 4) and a GO command. That is, the mini monitor program executes the primitive write command and the GO command, thereby realizing a step execution command.

  Assume that a debug command called an internal register read command is issued as shown in FIG. Then, the internal register read command is converted into a read command (read command from the address D2 in FIG. 4) from the mini-monitor RAM 44 (a save destination of the contents of the internal register) on the memory map. That is, when the mini monitor program executes this primitive read command, the internal register read command is realized. The internal register write command, memory read command, and memory write command are also realized in the same manner.

  Assume that a debug command called a breakpoint setting command is issued as shown in FIG. Then, this breakpoint setting command is converted into a write command to the break enable bit and break address bit of the control register 46. That is, the breakpoint setting command is realized by the mini monitor program executing this primitive write command.

  As described above, in this embodiment, complicated and various debug commands are converted into primitive, simple read, write, and GO commands. Since the mini-monitor program only needs to execute these primitive read, write, and GO commands, the instruction code size of the mini-monitor program becomes very small. As a result, the memory capacity of the mini monitor ROM 42 can be reduced, and an on-chip debugging function can be realized with a small hardware scale.

4). Configuration Example of SIO FIG. 6 shows a configuration example of the SIO 48. The SIO 48 includes a transmission / reception buffer 70, a shift register 76, a transmission / reception switching unit 78, a clock control unit 80, and a control register 84.

  Here, the transmission / reception buffer 70 is for temporarily storing transmission data and reception data, and includes a transmission buffer 72 and a reception buffer 74. The shift register 76 has a function of converting transmission data from the transmission buffer 72 from parallel data to serial data and outputting it to the transmission / reception switching unit 78. Also, it has a function of converting received data from the transmission / reception switching unit 78 from serial data to parallel data and outputting it to the reception buffer 74. The transmission / reception switching unit 78 is for switching between transmission and reception of data. As a result, half-duplex data transmission / reception using TXD / RXD becomes possible.

  The clock control unit 80 divides BCLK by the built-in frequency dividing circuit 82, and outputs the sampling clock SMC 1 obtained by this frequency division to the shift register 76. The shift register 76 operates based on this SMC1. The clock control unit 80 supplies BCLK to the debug tool 60. As a result, the BCLK is shared by the microcomputer 20 and the debug tool 60.

  The frequency dividing ratio in the frequency dividing circuit 82 is set by the control register 84. That is, the mini monitor program executed by the CPU 22 writes a desired frequency dividing ratio in the control register 84, whereby the frequency dividing ratio in the frequency dividing circuit 82 is set. The address of the control register 84 is also assigned to the position D1 in FIG. 4 in the same manner as the control register 46 in FIG.

5). Configuration Example of Debug Tool FIG. 7 shows a configuration example of the debug tool 60.

  The CPU 90 executes a program stored in the ROM 108 and controls the entire debug tool 60. The transmission / reception switching unit 92 is for switching between transmission and reception of data. The clock control unit 94 controls a clock supplied to the SCLK terminal of the CPU 90, the address up counter 100, and the trace memory 104. The clock control unit 94 receives BCLK from the microcomputer 20 (SIO 48). The clock control unit 94 includes a frequency detection circuit 95 and a frequency dividing circuit 96. The frequency detection circuit 95 detects the frequency range to which the BCLK frequency belongs, and outputs the result to the control register 98. The frequency dividing ratio in the frequency dividing circuit 96 is controlled by the control register 98. That is, the main monitor program (stored in the main monitor ROM 110) executed by the CPU 90 reads the frequency range of BCLK from the control register 98. Then, the main monitor program determines an optimum frequency division ratio corresponding to this frequency range, and writes this frequency division ratio in the control register 98. Then, the frequency dividing circuit 96 divides BCLK by this frequency dividing ratio to generate SMC2, and outputs it to the SCLK terminal of the CPU 90.

  The address up counter 100 is for counting up the address of the trace memory. The selector 102 selects either the line 122 (address output from the address up counter 100) or the line 124 (address from the address bus 120), and outputs data to the address terminal of the trace memory 104. The selector 106 selects either the line 126 (DST [2: 0], DPCO which is the output of the trace unit 50 in FIG. 3) or the line 128 (data bus 118), and the data is input to the data terminal of the trace memory 104. Or retrieve data from the data terminal.

  The ROM 108 includes a main monitor ROM 110 (corresponding to the main monitor unit 62 in FIG. 3), and the main monitor ROM 110 stores a main monitor program. As described with reference to FIGS. 5A to 5D, the main monitor program performs processing for converting a debug command into a primitive command. The RAM 112 serves as a work area for the CPU 90.

  The RS232C interface 114 and the parallel interface 116 serve as an interface with the host system 66 of FIG. 3, and debug commands from the host system 66 are input to the CPU 90 via these interfaces. The clock generation unit 118 generates a clock for operating the CPU 90 and the like.

  Next, the real-time trace processing in this embodiment will be briefly described. In the present embodiment, 3-bit DST [2: 0] representing the instruction execution state of the CPU 22 in FIG. 3 and DPCO representing the branch destination PC value are stored in the trace memory 104. Then, the trace data is synthesized based on the data stored in the trace memory 104 and the source code of the user program. By doing so, it is possible to realize a real-time trace function while reducing the number of connection lines between the microcomputer 20 and the debug tool 60.

  In the user program execution mode, the line 122 is selected, and the output of the address up counter 100 is input to the address terminal of the trace memory 104 via the selector 102. In addition, the line 126 is selected, and DST [2: 0] and DPCO are input to the data terminal of the trace memory 105 via the selector 106. Here, in the address up counter 100, first, the start address as shown in FIG. 8A is set by the CPU 90 using the data bus 118 and the address bus 120. The ST / SP (start / stop) terminal of the address up counter 100 is connected to the DST [2] line for specifying the trace range. Then, as shown in FIG. 8B, when the first pulse 130 is input to the line DST [2], the address upcount of the address upcounter 100 starts. When the second pulse 132 is input to the DST [2] line, the address upcount of the address upcounter 100 is stopped and the trace operation is stopped. In this way, data (DST [2: 0], DPCO) in a desired trace range can be stored in the trace memory 104.

  On the other hand, when shifting from the user program execution mode to the debug mode, the line 124 is selected, and the address from the address bus 120 is input to the address terminal of the trace memory 104 via the selector 102. The line 128 is selected, and the data from the trace memory 104 is output to the data bus 118 via the selector 106. As a result, the data stored in the trace memory 104 (DST [2: 0], DPCO) can be read by the CPU 90 (main monitor program) in the debug mode. Then, it becomes possible to synthesize trace data based on the read data and the source code of the user program.

6). Transmission / Reception of Data As shown in FIG. 9A, as a method of communication of debug data between the mini monitor unit 40 and the main monitor unit 62, TXD (transmission) and RXD (reception) lines are separately set. A method of providing full duplex communication is conceivable.

  However, if two lines (terminals) are used for communication of debug data in this way, the number of terminals (number of pins) of the microcomputer increases accordingly, which is a high cost of the microcomputer. Invite

  Therefore, in the present embodiment, as shown in FIG. 9B, a single TXD / RXD line (bidirectional communication line) is provided between the mini monitor unit 40 and the main monitor unit 62, and a half duplex bidirectional operation is performed. Communicate. By doing so, an increase in the number of terminals of the microcomputer can be minimized, and the cost of the microcomputer can be reduced.

  Further, in the present embodiment, as shown in FIG. 9C, the processing corresponding to the received data is performed on condition that the mini-monitor unit 40 serving as the slave has received data from the main monitor unit 62 serving as the master. The response data corresponding to the received data is transmitted to the main monitor unit 62. That is, when the main monitor unit 62 transmits data (command) to the mini-monitor unit 40, the mini-monitor unit 40 in the wait state receives this, and performs processing corresponding to the received data. Then, data (reply) corresponding to the received data is transmitted to the main monitor unit 62. Thereafter, the mini monitor unit 40 waits until data is received from the main monitor unit 62. That is, the mini monitor unit 40 stops operating until data is received from the main monitor unit 62, and starts operating on the condition that the data has been received. In this way, data can be properly transmitted and received while the communication line between the mini monitor unit 40 and the main monitor unit 62 is single.

  The communication method of FIG. 9A has an advantage that data can be communicated at higher speed than FIG. 9B because TXD and RXD are on separate lines. There is also an advantage that when a communication error occurs in one of the mini monitor unit 40 and the main monitor unit 62, an error message can be immediately returned to the other. For example, when a communication error occurs in the mini monitor unit 40, an error message can be immediately returned to the main monitor unit 62 using TXD without waiting for the end of data reception by RXD.

  On the other hand, in the present embodiment, the BCLK is shared by the mini monitor unit 40 and the main monitor unit 62 as described later. As a result, as described later, data can be communicated at high speed at an optimum speed. Therefore, debug data can be transmitted and received at high speed without any problem even if only one communication line is provided as shown in FIG. 9B instead of the two communication lines as shown in FIG. 9A. It becomes like this.

  In this embodiment, as will be described later, transmission / reception data has a fixed length and a short data length (for example, 14 bytes). Therefore, for example, when a communication error occurs in the mini-monitor unit 40, even if an error message is transmitted after waiting for the end of the reception process, the time delay is not so great. In addition, since the data length of the transmission / reception data is short, the occurrence of a communication error itself can be minimized.

  As described above, the present embodiment has an advantage of reducing the number of terminals of the microcomputer by providing only one debug data communication line. Disadvantages (decrease in communication speed, error message delay) that occur in order to obtain this benefit are eliminated by sharing BCLK or making transmission / reception data short data of a fixed length.

7). Format and Type of Transmission / Reception Data FIG. 10A shows a format example of data transmitted / received through the TXD / RXD line. The transmission / reception data is 14-byte fixed length data composed of 1-byte ID (command identification data), 1-byte data size, 4-byte address, 4-byte data 1, and 4-byte data 2.

  As shown in FIG. 10B, when the main monitor unit 62 instructs the mini monitor unit 40 to execute the GO command, the ID of the data received by the mini monitor unit 40 is set to 00h which is identification data of the GO command. Is done. In this case, the mini monitor unit 40 does not transmit data to the main monitor unit 62.

  As shown in FIG. 10C, when the main monitor unit 62 instructs the execution of the write command, the ID of the received data of the mini monitor unit 40 is set to 01h that is the identification data of the write command. Further, the write address, the write data 1, and the write data 2 are set in the received data address, data 1, and data 2, respectively. Then, 01h is set in the data 1 of the transmission data of the mini monitor unit 40.

  A plurality of types of write commands, such as a byte data write command, a half word data write command, a word data write command, and a double word data write command, are prepared according to the length of data to be written. May be. In this case, a different ID is assigned to each write command.

  As shown in FIG. 10D, when the main monitor unit 62 instructs the execution of the read command, the received data ID of the mini monitor unit 40 is set to 02h, which is the identification data of the read command. A read address is set as the address of the received data. The read data 1 and the read data 2 obtained by the read command process are set in the data 1 and the data 2 of the transmission data of the mini monitor unit 40, respectively.

  In the present embodiment, commands such as an external routine jump and data fill are prepared as primitive commands to be executed by the mini monitor unit 62 in addition to GO, write, and read commands.

  Here, the external routine jump command is a command for instructing to jump to the external routine. By using such an external routine jump command, for example, it is possible to jump to a routine of an initialization program or a writing program of a flash memory (EEPROM). As shown in FIG. 11A, when the main monitor unit 62 instructs execution of the external routine jump command, the ID of the reception data of the mini monitor unit 40 is set to 03h which is identification data of the external routine jump command. Is done. Also, 18h (malfunction prevention check),% R12 (routine address),% R13 (write data), and% R14 (data address) are set in the data size, address, data 1 and data 2 of the received data, respectively. . Then,% R10 (return value. When the return value is 0, normal termination) is set in the data 1 of the transmission data of the mini-monitor unit 40.

  The data fill command is a command for filling the memory with a given value (for example, 0). For example, when all bits of a large-capacity memory are set to a value of 0, the processing time becomes very long if a write command is used. In such a case, the data fill command becomes valid. As shown in FIG. 11B, when the main monitor unit 62 instructs execution of the data fill command, the ID of the received data of the mini monitor unit 40 is set to 04h that is identification data of the data fill command. . The data size, address, data 1 and data 2 of the received data are set with data size 1, 2 or 4, start address, fill count and fill pattern, respectively.

  As described above, in this embodiment, the reception data from the main monitor unit 62 includes the identification data ID of the primitive command executed by the mini monitor unit 40. In this way, it is possible to easily transmit an instruction to execute a primitive command to the mini monitor unit 40.

8). In this embodiment, as shown in FIG. 10A, the transmission / reception data between the mini-monitor unit 40 and the main monitor unit 62 is 14-byte fixed-length data. In this way, the instruction code size of the mini monitor program can be further reduced.

  That is, when the transmission / reception data is variable length, the processing parts (instruction sequences) indicated by E1, E2, and E3 in FIG. 12A are necessary for almost all commands. These processing parts E1, E2, and E3 are parts for determining how many data processes are necessary. That is, when processing variable-length data, it is necessary to check the number of data to be processed based on the data size included in the transmission / reception data. Then, the number of data is held on, for example, a RAM that is a work area, and each time processing of one data is finished, the number of data is decremented or it is determined whether or not the number of data becomes zero. Processing is required. For this reason, as shown in FIG. 12A, the size of the source code of the mini monitor program is increased.

  On the other hand, in this embodiment, the transmission / reception data has a fixed length. For this reason, as can be seen by comparing FIG. 12A and FIG. 12B, the size of the source code of the mini monitor program can be reduced to, for example, about 2/3 as compared with the case of the variable length. Thereby, the size of the mini monitor ROM 42 of FIG. 3 can be further reduced, and an on-chip debugging function can be realized with a small hardware scale.

  Note that when the transmission / reception data is set to a fixed length, the communication efficiency is deteriorated, so that there is a problem that the communication speed is lowered as compared with the case where the length is variable. Therefore, in this embodiment, the BCLK is shared by the mini monitor unit 40 and the main monitor unit 62 as described later. As a result, data can be communicated at high speed at an optimum speed, and the above problem can be solved.

9. Mini monitor ROM
In the present embodiment, as shown in FIG. 3, a mini monitor ROM 42 is provided in the microcomputer 20, and a mini monitor program is stored in the mini monitor ROM 42. By doing so, it is possible to reduce the hardware scale and the cost of the microcomputer.

  For example, in the configuration illustrated in FIG. 13A, a loader logic circuit 332 and a RAM 334 are provided in the microcomputer 330. The loader logic circuit 332 is used to load a monitor program into the RAM 334 from the outside via the JTAG interface 336. However, in this configuration, it is necessary to provide the loader logic circuit 332 and the RAM 334 whose size is about 5 to 10 times that of the ROM in the microcomputer 330. For this reason, there arises a problem of an increase in scale and cost of the microcomputer 330.

  On the other hand, in this embodiment, as shown in FIG. 13B, the mini monitor program is stored in the mini monitor ROM 42 whose size is about 1/5 to 1/10 times the RAM. Also, no loader logic circuit is required. Therefore, the microcomputer 20 can be reduced in size and cost as compared with the configuration of FIG.

  In the configuration of FIG. 13A, it is necessary to stop the CPU once when power is turned on or reset, and then load the monitor program into the RAM 334 with the loader logic circuit 332, and then restart the CPU in the debug mode. is there. This complicates the processing and requires time for starting the debug mode.

  On the other hand, in the present embodiment shown in FIG. 13B, it is not necessary to load the mini monitor program into the RAM. For this reason, when the power is turned on or reset, the operation of the CPU in the debug mode can be started immediately without temporarily stopping the CPU.

10. Sharing BCLK As a data communication method between the microcomputer and the debug tool, a so-called synchronous method or a so-called asynchronous method can be adopted. In ICE, it is desired to reduce the number of communication lines between the microcomputer and the debug tool as much as possible. It is also desirable to prevent communication data sampling errors as much as possible.

  However, when performing communication in a synchronous manner, as shown in FIG. 14A, there are four cables between the microcomputer 340 (first information processing apparatus) and the debug tool 342 (second information processing apparatus). It is necessary to provide a communication line. That is, a TXD line as transmission data, a TCLK line as TXD sampling clock, an RXD line as reception data, and an RCLK line as RXD sampling clock are required. This unnecessarily increases the number of communication lines.

  On the other hand, in the case of performing asynchronous communication, as shown in FIG. 14B, the microcomputer 340 and the debug tool 342 separately have clocks having substantially the same frequency. For example, the microcomputer 340 has the clock CLK1, the debug system 342 has the clock CLK2, and the frequencies of CLK1 and CLK2 are substantially the same. Then, as shown in FIG. 15A, the microcomputer 340 generates the sampling clock SMC1 by dividing CLK1, and each bit (start bit, D0 to D7, stop bit) of data communicated in an asynchronous manner. Bit) is sampled by this SMC1. Further, as shown in FIG. 15B, the debug tool 342 generates the sampling clock SMC2 by dividing CLK2, and each bit (state bits, D0 to D7, stop bit) of data communicated in an asynchronous manner. Bit) is sampled by this SMC2.

  However, in this asynchronous system, when the operating frequency of the CPU included in the microcomputer 340 is increased and the frequencies of CLK1 and CLK2 are increased, the frequencies of SMC1 and SMC2 are also increased, and communication data sampling errors are likely to occur. . In other words, the frequency of CLK1 and CLK2 can be increased only to the extent that a sampling error of communication data does not occur. This means that debugging work cannot be performed in an environment where the microcomputer 340 operates at high speed. That is, at the time of debugging work, it is necessary to lower the clock frequency of the microcomputer.

  In order to solve such a problem, in this embodiment, as shown in FIG. 16, the microcomputer 140 and the debug tool 150 share BCLK for generating a sampling clock.

  More specifically, the microcomputer 140 (first information processing apparatus) includes a communication unit 142 (corresponding to the SIO 48 in FIG. 3). The communication unit 142 includes a transmission / reception circuit 144 (corresponding to the transmission / reception buffer 70, the shift register 76, and the transmission / reception switching unit 78 in FIG. 6) and a frequency dividing circuit 146 (corresponding to the frequency dividing circuit 82 in FIG. 6). As shown in FIG. 17A, the frequency dividing circuit 146 divides BCLK (first clock) and generates a sampling clock SMC1 for sampling each bit of data transmitted and received in an asynchronous manner. To do. The transmission / reception circuit 144 transmits / receives data based on the SMC1. Further, the microcomputer 140 supplies BCLK to the debug tool 150.

  The debug tool 150 (second information processing apparatus) includes a communication unit 152. The communication unit 152 includes a transmission / reception circuit 154 (corresponding to the CPU 90 and the transmission / reception switching unit 92 in FIG. 7) and a frequency dividing circuit 156 (corresponding to the frequency dividing circuit 96 in FIG. 7). As shown in FIG. 17B, the frequency dividing circuit 156 divides BCLK supplied from the microcomputer 140 and generates a sampling clock SMC2. The transmission / reception circuit 154 transmits / receives data based on the SMC2.

  As described above, in this embodiment, the microcomputer 140 and the debug tool 150 share BCLK for generating the sampling clocks SMC1 and SMC2 while being asynchronous. As a result, the rate of occurrence of communication data sampling errors can be significantly reduced as compared with the general asynchronous communication shown in FIG. Further, in the synchronous communication of FIG. 14A, four communication lines are necessary, but in this embodiment, two communication lines are sufficient as shown in FIG. 16 (in the case of full duplex). 3). Therefore, the number of communication lines between the microcomputer 140 and the debug tool 150 can be reduced as compared with FIG. As a result, the number of terminals of the microcomputer 140 can be reduced, and the cost of the microcomputer 140 can be reduced.

  In particular, in the configuration of FIG. 14B, the higher the frequency of CLK1 (and CLK2), the higher the incidence of communication data sampling errors. For this reason, the clock frequency of the microcomputer 340 cannot be increased during the debugging operation, and the debugging operation cannot be performed in an environment where the microcomputer 340 operates at high speed.

  On the other hand, in this embodiment of FIG. 16, both the microcomputer 140 and the debug tool 150 generate the sampling clock based on BCLK. For this reason, even if the frequency of BCLK increases, the occurrence rate of sampling errors does not increase so much. As a result, debugging work can be performed in an environment in which the microcomputer 140 operates at high speed, and debugging work can be performed in an environment closer to actual operation.

  Furthermore, in this embodiment, as shown in FIG. 18, the communication unit 142 includes a frequency division ratio control unit 148 (corresponding to the control register 84 in FIG. 6), and the communication unit 152 has a frequency division ratio control unit 158 (FIG. 18). 7 and a frequency detection circuit 159 (corresponding to the frequency detection circuit 95 of FIG. 7). This makes it possible to variably control the frequency dividing ratio FD1 when generating SMC1 and the frequency dividing ratio FD2 when generating SMC2. As a result, even if the frequency of BCLK changes, data can be communicated at an optimal and high communication speed.

  That is, as shown in FIG. 19A, when the frequency of BCLK is lowered, the frequency division ratios FD1 and FD2 that were 16 in FIGS. 17A and 17B are changed to 8, for example. As a result, the sampling clocks SMC1 and SMC2 are changed from a clock obtained by dividing BCLK by 16 to a clock obtained by dividing the clock by eight. As a result, the clock number of BCLK corresponding to 1-bit data is changed from 16 (16 clock mode) to 8 (8 clock mode).

  Further, as shown in FIG. 19B, when the frequency of BCLK is further lowered, the frequency division ratios FD1 and FD2 that were 8 in FIG. As a result, the sampling clocks SMC1 and SMC2 are changed from a clock obtained by dividing BCLK by 8 to a clock obtained by dividing the clock by four. As a result, the BCLK clock number corresponding to 1-bit data is changed from 8 (8 clock mode) to 4 (4 clock mode).

  In this way, even when the BCLK frequency is lowered, the data communication speed is not lowered. As a result, data can be communicated at an optimum and high communication speed.

  In particular, the clock frequency of the microcomputer is generally different for each user who uses the microcomputer. That is, one user operates the microcomputer with a clock of 60 MHZ, and another user operates the microcomputer with a clock of 20 MHZ.

  However, in the communication systems shown in FIGS. 14A and 14B, when the clock frequency of the microcomputer changes, the data communication speed also changes. That is, when the clock frequency is lowered, the data communication speed is also lowered. Therefore, data cannot be communicated at the maximum communication speed.

  On the other hand, in this embodiment, when the clock frequency of the microcomputer changes according to the user who uses the microcomputer, the frequency division ratios FD1 and FD2 also change, and the number of clocks corresponding to 1-bit data also changes. To do. That is, when the clock frequency is lowered, the frequency division ratios FD1 and FD2 are also reduced, and the number of clocks corresponding to 1-bit data is also reduced. As a result, the communication speed is not lowered after all, and communication can be performed at an optimal and high communication speed. That is, communication can be performed at an optimum communication speed according to a user who uses clocks having various frequencies.

  Next, processing in the communication units 142 and 152 will be described in more detail with reference to the flowcharts of FIGS.

  As shown in FIG. 20, first, the frequency detection circuit 159 in the communication unit 152 in FIG. 18 detects the frequency of BCLK supplied from the microcomputer 140 (step V1). Then, it is determined whether or not the frequency of BCLK is 30 MHZ or more (step V2). If it is 30 MHZ or more, the frequency division ratio control unit 158 sets the frequency division ratio FD2 to 16 (step V3). Then, frequency division ratio data notifying that FD2 is 16 is transmitted to the microcomputer 140 via the transmission / reception circuit 154 (step V4). Next, the frequency dividing circuit 156 divides BCLK by FD2 = 16 and generates SMC2 (step V5). Thereafter, data transmission / reception is performed by the SMC2.

  When the frequency of BCLK is lower than 30 MHZ, it is determined whether or not the frequency is 15 MHZ or higher (step V6). If the frequency is 15 MHZ or higher, FD2 = 8 is set (step V7), and processing similar to steps V4 and V5 is performed (steps V8 and V9). If the frequency of BCLK is lower than 15 MHZ, FD2 = 4 is set (step V10), and the same processing as steps V4 and V5 is performed (steps V11 and V12).

  On the other hand, the microcomputer 140 performs processing as shown in the flowchart of FIG. That is, first, frequency division ratio data is received from the debug tool 150 via the transmission / reception circuit 144 (step W1). Next, the frequency division ratio control unit 148 determines the frequency division ratio FD1 based on the received frequency division ratio data (step W2). Then, the frequency dividing circuit 146 divides BCLK by this FD1 to generate SMC1. Thereafter, data transmission / reception is performed by the SMC 1.

11. Detailed Processing Example of Mini Monitor Unit Next, a detailed processing example of the mini monitor unit will be described.

  As shown in FIG. 22, when a break occurs during execution of the user program, processing of the mini monitor program starts and shifts from the user program execution mode to the debug mode. When the mini monitor program executes a given command process and executes a return instruction, the program returns from the debug mode to the user program execution mode.

  23 and 24 are flowcharts showing the processing of the mini monitor program in the debug mode.

  When shifting to the debug mode, the mini-monitor program first saves the contents of the internal register 24 of the CPU 22 in FIG. 3 to the mini-monitor RAM 44 (step S1). Then, setting processing of the control register 46 used by the mini monitor program is performed (step S2).

  Next, the 14-byte data (see FIG. 10A) received from the debug tool 60 is written to the reception buffer 74 (see FIG. 6) (step S3). Then, the first byte (command identification data ID) of the data in the reception buffer 74 is checked (step S4).

  As shown in FIG. 24, when the ID indicates a read command (see FIG. 10D), a read address is acquired from the reception buffer 74 (steps S5 and S6). Then, data is read from the acquired read address and written to the transmission buffer 72 (step S7). Next, the data in the transmission buffer 72 is transmitted to the debug tool 60 (step S8). Then, the process returns to step S 3 in FIG. 23, and the next received data is written to the receiving buffer 74.

  If the ID indicates a write command (see FIG. 10C), the write address is acquired from the reception buffer 74 (steps S9 and S10). Then, write data is acquired from the reception buffer 74 and written to the write address acquired in step S10 (step S11).

  If the ID indicates an external routine jump command (see FIG. 11A), the routine address is acquired from the reception buffer 74 (steps S12 and S13). Then, after jumping to the external routine, the process returns to the mini monitor program (step S14).

  If the ID indicates a GO command (see FIG. 11B), the data saved in the mini monitor RAM 44 is restored to the internal register 24 (steps S15 and S16). Then, as shown in FIG. 22, the process returns to the user program and exits from the debug mode (step S17).

  On the other hand, if the ID is not any of read, write, external routine jump, and GO command, it is determined that no processing is required (steps S15 and S18). Then, dummy data is written to the transmission buffer 72 (step S19). In FIG. 24, processing of the data fill command is omitted.

  As described above, the primitive command obtained by converting the debug command is executed by the mini monitor program.

12 Next, an electronic device including the microcomputer according to the present embodiment will be described.

  For example, FIG. 25A shows an internal block diagram of a car navigation system which is one of electronic devices, and FIG. 26A shows an external view thereof. The operation of the car navigation system is performed using the remote controller 510, and the position detection unit 520 detects the position of the vehicle based on information from the GPS and the gyro. Information such as a map is stored in a CDROM 530 (information storage medium). The image memory 540 is a memory serving as a work area for image processing, and the generated image is displayed to the driver using the image output unit 550. The microcomputer 500 receives data from a data input source such as the remote controller 510, the position detection unit 520, and the CDROM 530, performs various processes, and outputs the processed data using an output device such as the image output unit 550.

  FIG. 25B shows an internal block diagram of a game device which is one of electronic devices, and FIG. 26B shows an external view thereof. In this game apparatus, based on the operation information of the player from the game controller 560, the game program from the CD ROM 570, the player information from the IC card 580, and the like, a game image and game sound are generated using the image memory 590 as a work area. Output is performed using the output unit 610 and the sound output unit 600.

  FIG. 25C shows an internal block diagram of a printer which is one of electronic devices, and FIG. 26C shows an external view thereof. In this printer, based on the operation information from the operation panel 620 and the character information from the code memory 630 and the font memory 640, a print image is generated using the bitmap memory 650 as a work area and is output using the print output unit 660. . The printer status and mode are communicated to the user using the display panel 670.

  According to the microcomputer or the debugging system of the present embodiment, it becomes possible to facilitate the development of a user program for operating the electronic devices of FIGS. 25A to 26C and shorten the development period. In addition, since the user program can be debugged in the same environment as the environment in which the microcomputer actually operates, the reliability of the electronic device can be improved. Further, since the hardware of the microcomputer incorporated in the electronic device can be reduced in size and cost, the cost of the electronic device can be reduced. Furthermore, since the instruction code size of the mini-monitor program is small, the user can secure the maximum memory area for storing programs and various data. In some cases, the memory area used by the user is not used at all. A monitor program can be loaded.

  In addition to the above, the electronic apparatus to which the microcomputer of the present embodiment can be applied includes, for example, a mobile phone (cellular phone), a PHS, a pager, an audio device, an electronic notebook, an electronic desk calculator, a POS terminal, and a touch panel. Various devices such as a projector, a word processor, a personal computer, a television, a viewfinder type or a monitor direct-view type video tape recorder can be considered.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  For example, as the primitive commands of the present invention, those described in this embodiment are particularly desirable, but the present invention is not limited to these.

  Further, the configuration of the microcomputer and the mini-monitor unit (first monitor means) is not limited to that described in the present embodiment, and various modifications can be made.

  Further, the configuration of the debug system is not limited to that shown in FIG.

FIG. 1A shows an example of a CPU replacement type ICE, and FIG. 1B shows an example of a monitor program mounting type ICE. It is a figure for demonstrating the characteristic of this embodiment. It is a functional block diagram which shows the structural example of the microcomputer of this embodiment, and a debugging system. It is a figure which shows the memory map at the time of debug mode. FIGS. 5A, 5 </ b> B, 5 </ b> C, and 5 </ b> D are diagrams for explaining processing for converting (decomposing) a debug command into a primitive command. It is a functional block diagram which shows the structural example of SIO. It is a functional block diagram which shows the structural example of a debug tool. 8A and 8B are diagrams for explaining the real-time trace processing. FIGS. 9A, 9B, and 9C are diagrams for explaining a communication method between the mini monitor unit and the main monitor unit. FIGS. 10A, 10B, 10C, and 10D are diagrams for explaining the format and type of transmission / reception data. FIGS. 11A and 11B are also diagrams for explaining the format and type of transmission / reception data. FIGS. 12A and 12B are diagrams for explaining the size of the source code of the mini-monitor program when the transmission / reception data has a variable length and a fixed length. FIGS. 13A and 13B are diagrams for explaining a method of storing the mini monitor program in the ROM. FIGS. 14A and 14B are diagrams for explaining synchronous and asynchronous communication methods. FIGS. 15A and 15B are diagrams illustrating timing waveforms of a clock, a sampling clock, and sampling data in a general asynchronous manner. It is a figure for demonstrating the communication method of this embodiment. 17A and 17B are diagrams showing timing waveforms of the clock, sampling clock, and sampling data in the method of FIG. It is a figure for demonstrating the communication method of this embodiment. FIGS. 19A and 19B are diagrams showing timing waveforms of the clock, sampling clock, and sampling data in the method of FIG. It is a flowchart for demonstrating the division ratio setting process by the debug tool side. It is a flowchart for demonstrating the division ratio setting process by the side of a microcomputer. It is a figure for demonstrating the transfer from user program execution mode to debug mode. It is a flowchart for demonstrating the detailed process example of this embodiment. It is a flowchart for demonstrating the detailed process example of this embodiment. 25A, 25B, and 25C are examples of internal block diagrams of various electronic devices. FIGS. 26A, 26B, and 26C are examples of external views of various electronic devices.

Explanation of symbols

10 microcomputer, 12 CPU (central processing unit), 14 mini monitor section (first monitoring means), 16 main monitor section (second monitoring means), 20 microcomputer, 22 CPU (central processing unit), 24 internal register , 26 BCU (bus control unit), 28 internal memory, 30 clock generation unit, 31 bus, 32 bus, 33 external bus, 34 internal bus, 36 external memory, 40 mini monitor unit (first monitor means), 42 mini monitor ROM , 44 Mini monitor RAM, 46 Control register, 48 SIO, 50 Trace unit, 60 Debug tool, 62 Main monitor unit (second monitor means), 66 Host system, 70 Transmit / receive buffer, 72 Transmit buffer, 74 Receive buffer, 76 Shift register, 8 transmission / reception switching unit, 80 clock control unit, 82 frequency dividing circuit, 84 control register, 90 CPU, 92 transmission / reception switching unit, 94 clock control unit, 95 frequency detection unit, 96 frequency dividing circuit, 98 control register, 100 address up counter , 102 selector, 104 trace memory, 106 selector, 108 ROM, 110 main monitor ROM, 112 RAM, 114 RS232C interface, 116 parallel interface, 118 clock generation unit, 140 microcomputer (first information processing apparatus), 142 communication unit 144 transmission / reception circuit, 146 frequency division circuit, 148 frequency division ratio control unit, 150 debug tool (second information processing device), 152 communication unit, 154 transmission / reception circuit, 156 frequency division circuit, 158 frequency division ratio control unit, 159 Frequency detection circuit

Claims (13)

A microcomputer having an on-chip debugging function,
A central processing unit for executing instructions,
Data is transmitted to and received from the second monitor means that is provided outside the microcomputer and performs processing for converting a debug command into at least one primitive command, and a primitive command to be executed is sent from the second monitor means. First monitoring means for determining based on received data and performing processing for executing the determined primitive command;
The first monitoring means includes
A monitor ROM for storing a monitor program for executing the processing of the first monitor means;
The monitor program is
Including an instruction code of the primitive command;
The received data from the second monitor means is
Including identification data for identifying the primitive command;
The first monitoring means includes
A microcomputer that executes a primitive command of an instruction code specified by the identification data included in the received data when the received data is received from the second monitor means. A microcomputer having an on-chip debugging function,
A central processing unit for executing instructions,
Data is transmitted to and received from the second monitor means that is provided outside the microcomputer and performs processing for converting a debug command into at least one primitive command, and a primitive command to be executed is sent from the second monitor means. First monitoring means for performing a process for executing the determined primitive command, based on the received data;
A control register that is used for instruction execution processing of the central processing unit and whose address is allocated on a memory map in debug mode;
The second monitor means includes
The step execution command which is the debug command is converted into a first primitive command which is a write command to a step execution enable bit and a second primitive command which is a GO command.
The first monitoring means includes
A microcomputer performing step execution processing by executing the first and second primitive commands. A microcomputer having an on-chip debugging function,
A central processing unit for executing instructions,
Data is transmitted to and received from the second monitor means that is provided outside the microcomputer and performs processing for converting a debug command into at least one primitive command, and a primitive command to be executed is sent from the second monitor means. First monitoring means for performing a process for executing the determined primitive command, based on the received data;
A reception buffer for temporarily storing the reception data from the second monitoring means;
A transmission buffer for temporarily storing transmission data to the second monitoring means,
The received data from the second monitor means is
Including identification data for identifying the primitive command;
The first monitoring means includes
When the identification data of the received data indicates a primitive command of a read command, a read address is acquired from the received data of the reception buffer, data is read from the acquired read address, and the read Write data to the transmit buffer;
If the identification data of the received data indicates a primitive command of a write command, a write address and write data are acquired from the received data in the reception buffer, and the acquired write address is acquired at the acquired write address. A microcomputer that performs a process of writing data. In claim 3,
The first monitoring means includes
If the received identification data indicates a primitive command of an external routine jump command, a routine address is acquired from the received data in the reception buffer and jumped to an external routine. After the jump, the first monitoring means A microcomputer characterized by performing a process returning to the process. In claim 3 or 4,
Including a monitor RAM in which the contents of the internal register of the central processing unit are saved and the address is assigned on the memory map in the debug mode;
The first monitoring means includes
When the received identification data indicates a GO command primitive command, the data saved in the monitor RAM is restored to the internal register, and the process of returning to the process of the user program after the restoration is performed. A microcomputer. In any one of Claims 1 thru | or 5,
The primitive command is
A microcomputer comprising: a command for starting execution of a user program; a command for writing data to an address on a memory map in a debug mode; and a command for reading data from an address on the memory map. In any one of Claims 1 thru | or 6.
A terminal to which one bidirectional communication line for performing half-duplex bidirectional communication with the second monitoring means is connected;
The first monitoring means to be a slave is
On the condition that data is received from the second monitor means serving as a master, processing corresponding to the received data is performed, and response data corresponding to the received data is transmitted to the second monitor means, A microcomputer. In any one of Claims 1 thru | or 7,
The first monitoring means includes
A microcomputer for transmitting and receiving fixed-length data to and from the second monitor means. In any one of Claims 1 thru | or 8.
The first monitor means includes a readable and writable monitor RAM;
The first monitoring means includes
A microcomputer characterized in that the program counter value of the central processing unit and the contents of an internal register are saved in the monitor RAM when execution of a user program breaks and shifts to a debug mode. A microcomputer according to any one of claims 1 to 9;
An input source of data to be processed by the microcomputer;
And an output device for outputting data processed by the microcomputer. A debugging system for a target system including a microcomputer,
Second monitoring means for performing processing for converting a debug command issued by the host system into at least one primitive command;
Data is transmitted / received to / from the second monitoring means, a primitive command to be executed is determined based on the received data from the second monitoring means, and processing for executing the determined primitive command is performed. Monitoring means,
The first monitoring means includes
A monitor ROM for storing a monitor program for executing the processing of the first monitor means;
The monitor program is
Including an instruction code of the primitive command;
The received data from the second monitor means is
Including identification data for identifying the primitive command;
The first monitoring means includes
A debug system characterized by executing a primitive command of an instruction code specified by the identification data included in the received data when the received data is received from the second monitor means. A debugging system for a target system including a microcomputer,
Second monitoring means for performing processing for converting a debug command issued by the host system into at least one primitive command;
Data is transmitted / received to / from the second monitoring means, a primitive command to be executed is determined based on the received data from the second monitoring means, and processing for executing the determined primitive command is performed. Monitoring means,
A control register that is used for instruction execution processing of the central processing unit and whose address is allocated on a memory map in debug mode;
The second monitor means includes
The step execution command which is the debug command is converted into a first primitive command which is a write command to a step execution enable bit and a second primitive command which is a GO command.
The first monitoring means includes
A debug system that performs step execution processing by executing the first and second primitive commands. A debugging system for a target system including a microcomputer,
Second monitoring means for performing processing for converting a debug command issued by the host system into at least one primitive command;
Data is transmitted / received to / from the second monitoring means, a primitive command to be executed is determined based on the received data from the second monitoring means, and processing for executing the determined primitive command is performed. Monitoring means,
A reception buffer for temporarily storing the reception data from the second monitoring means;
A transmission buffer for temporarily storing transmission data to the second monitoring means,
The received data from the second monitor means is
Including identification data for identifying the primitive command;
The first monitoring means includes
When the identification data of the received data indicates a primitive command of a read command, a read address is acquired from the received data of the reception buffer, data is read from the acquired read address, and the read Write data to the transmit buffer;
If the identification data of the received data indicates a primitive command of a write command, a write address and write data are acquired from the received data of the reception buffer, and the acquired write address is acquired at the acquired write address. A debugging system that performs a process of writing data.

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