JP3715551B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device having an array of memory cells using a complex oxide film as an insulating film of an information storage capacitor, and more particularly to a ferroelectric memory cell using a ferroelectric as a capacitor insulating film. Formation method and structure of cell transistor-cell capacitor connection wiring portion, bit line contact portion and memory cell in ferroelectric memory (FRAM) having an array, and dynamic type using high dielectric constant dielectric for capacitor insulating film The present invention relates to a method of forming a memory cell in a dynamic random access memory (DRAM) having an array of memory cells, and is applied to a semiconductor integrated circuit including FRAM or DRAM.
[0002]
[Prior art]
In recent years, nonvolatile ferroelectric memory cells (FRAM cells) using a ferroelectric thin film made of a material having a perovskite structure or a layered perovskite structure as an interelectrode insulating film of an information storage capacitor and an FRAM having an array thereof have attracted attention. ing.
[0003]
In the ferroelectric film, the electric polarization once generated when an electric field is applied remains even if the electric field is no longer applied, and when an electric field with a certain strength or more is applied in the direction opposite to the electric field. It has a characteristic that the direction of polarization is reversed.
[0004]
Focusing on this polarization characteristic that reverses the direction of polarization of the dielectric, a technique for realizing an FRAM cell using a ferroelectric as the insulating film of the information storage capacitor of the memory cell has been developed.
[0005]
This FRAM cell has a configuration in which a capacitor of a DRAM cell is replaced with a ferroelectric capacitor, and a method of taking out charges at the time of polarization inversion or non-inversion from a ferroelectric capacitor via a MOS transistor for switching (data). (Destructive read) is used, and the stored data written in the memory cell is not lost even when the operation power is turned off.
[0006]
Compared with a DRAM that is a representative of a large-capacity memory, the FRAM has a feature that since it is non-volatile, a refresh operation is unnecessary for data retention and power consumption during standby is unnecessary. In addition, the flash memory, which is another nonvolatile memory, has a feature that the number of data rewrites is large and the data rewrite speed is remarkably high. In addition, the power consumption is small and the cell area can be greatly reduced as compared with an SRAM used for a memory card or the like that requires battery backup.
[0007]
The expectation of FRAM having the above features is very high, such as replacement of existing DRAM, flash memory, and SRAM, and application to a logic embedded device. In addition, since FRAM is capable of high-speed operation without a battery, the development of contactless cards (RF-ID: Radio Frequency-Identification Data) is beginning. The structure of the memory cell of the FRAM includes a structure using a ferroelectric film instead of a paraelectric film in a storage capacitor for storing a charge capacity as information, as in a DRAM, and a silicon oxide film in a gate insulating film of a MOSFET. Are roughly classified into two types: a structure in which is replaced with a ferroelectric film. The latter is not feasible because there is no suitable ferroelectric film that can be formed directly on the Si interface, and since only proposals have been made so far, FRAM usually refers to the former structure.
[0008]
Further, as shown in FIG. 22, the FRAM cell includes a one-transistor / one-capacitor (abbreviated as 1T / 1C) type composed of one transistor and one ferroelectric capacitor, as shown in FIG. There are two transistors and two capacitors (abbreviated as 2T / 2C) type composed of two transistors and two ferroelectric capacitors.
[0009]
The 1T / 1C structure has the advantage that it can be integrated as high as a DRAM, but it must suppress variations in ferroelectric characteristics and deterioration in each memory cell, and increase yield and device reliability. Has the disadvantage of being difficult.
[0010]
The 2T / 2C structure has a defect that requires twice as much area as the 1T / 1C structure, but since the characteristic margin can be increased, it is easy to improve yield and device reliability.
[0011]
In any structure, an electrode / ferroelectric / electrode stack structure is formed on a base insulating film, and Al or Cu wiring is provided through a contact hole opened in an oxide film on the upper layer, and the film is protected by a passivation film. .
[0012]
By the way, as described above, the FRAM cell can operate at high speed and with low power consumption, and high integration is expected. Therefore, it is necessary to examine a manufacturing process with less memory cell area and less ferroelectric deterioration. It has become. In addition, when an existing FRAM device is mixed with other devices or a multilayer wiring technique indispensable for high integration has not yet been established.
[0013]
The reason why it is difficult to make a multi-layer wiring of a semiconductor integrated circuit mounted with an FRAM device is that a ferroelectric material is very weak in a reducing atmosphere (particularly a hydrogen atmosphere). In the existing LSI process, most of the processes are mixed with hydrogen, which is a serious problem in manufacturing FRAM.
[0014]
As an example of a process in which hydrogen is mixed, a process of filling a via hole in a multilayer wiring structure can be given. In particular, as a method for filling a via hole with a large aspect ratio, W filling by CVD is mainly used. However, since many hydrogen groups are generated in the step of filling this W, the ferroelectric is seriously damaged.
[0015]
Hereinafter, the above problem will be described in detail.
[0016]
Conventionally, as a structure of a ferroelectric memory cell, (1) a bit line post-fabrication structure in which a ferroelectric capacitor is disposed under a bit line, and (2) a bit line tip in which a bit line is disposed under a ferroelectric capacitor. There is a making structure.
[0017]
When manufacturing the ferroelectric memory cell having the bit line post-fabrication structure, a ferroelectric capacitor is disposed on the upper layer of the pass transistor (switching MOS transistor), and the lower electrode and the pass transistor are connected to the polysilicon plug. Then, a bit line is formed on the ferroelectric capacitor.
[0018]
When forming the ferroelectric capacitor, the ferroelectric thin film is formed after the lower electrode of the ferroelectric capacitor is usually formed on the polysilicon plug using Pt (platinum). When performing crystallization by forming a film, high-temperature oxygen annealing is required.
[0019]
Here, when PZT (lead zirconate titanate) is used as the ferroelectric material, when the oxidation is insufficient, the capacitor characteristics deteriorate due to the generation of defects due to the diffusion of Pb in the PZT. In order to avoid this, the oxygen annealing temperature necessary for sufficient oxidation is usually 600 ° C. to 700 ° C.
[0020]
When a bismuth layered compound such as SBT (strontium bismuth tantalate) is used as the ferroelectric material, the necessary oxygen annealing temperature is usually as high as ˜800 ° C.
[0021]
However, at the time of high-temperature oxygen annealing as described above, there arises a problem that the lower electrode using Pt reacts with the polysilicon plug to be silicided or the polysilicon plug is oxidized.
[0022]
On the other hand, when manufacturing a ferroelectric memory cell having the bit line prefabricated structure, a bit line is formed above the pass transistor, and a ferroelectric capacitor is formed above the bit line.
[0023]
At this time, when the lower electrode (for example, Pt) of the ferroelectric capacitor and the pass transistor are connected by the polysilicon plug, the same problem as that of the bit line post-fabrication structure described above arises.
[0024]
On the other hand, there has been proposed an upper electrode connection structure in which an upper electrode of a ferroelectric capacitor and a pass transistor are directly connected by a local electrode wiring made of a buried wiring. This structure has a feature that the degree of freedom of the pattern layout of the ferroelectric capacitor is relatively high, and a fine structure can be realized by arranging the ferroelectric capacitor on both the pass transistor region and the element isolation region. Is possible.
[0025]
When realizing the bit line pre-fabrication / upper electrode connection structure, after forming the ferroelectric capacitor from the lower electrode (plate electrode) to the upper electrode, a capacitor protective film is deposited. Thereafter, in order to form a local electrode wiring for directly connecting the upper electrode and the pass transistor, a contact portion with the upper electrode and a contact portion with the active layer of the pass transistor are opened in the capacitor protection film, and wiring is performed. After the film is deposited, it is patterned.
[0026]
When the bit line pre-fabrication / upper electrode connection structure is realized, as described above, when the lower electrode (for example, Pt) of the ferroelectric capacitor and the pass transistor are connected by the polysilicon plug, the lower electrode is made of polysilicon. There is no problem of silicidation by reacting with the plug.
[0027]
However, it is difficult to form a local electrode wiring for directly connecting the upper electrode and the pass transistor as described above in terms of aspect ratio and step coverage accompanying miniaturization.
[0028]
In addition, when PZT or BST is used as the ferroelectric material, the reducing atmosphere in various CVD (chemical vapor deposition) processes performed when forming the electrode wiring after forming the ferroelectric thin film becomes a problem. There is a problem that the dielectric material is deteriorated in characteristics by a reduction reaction.
[0029]
In other words, when forming a local electrode wiring for connecting the upper electrode and the pass transistor, W in a strong reducing atmosphere (hydrogen-based gas) using a metal CVD apparatus used in a DRAM is used. If an attempt is made to embed a W plug by (tungsten) film formation, the characteristics of the ferroelectric capacitor (electrical characteristics such as the amount of remanent polarization) are deteriorated, and therefore cannot be used.
[0030]
On the other hand, when forming the local electrode wiring for connecting the upper electrode and the pass transistor, even if the aluminum wiring film is formed using MO (Metal Organic) CVD, there is no reducing atmosphere. However, since the hydrogen group component including the source material cannot be completely removed, the characteristics of the ferroelectric capacitor are deteriorated.
[0031]
Further, when PZT or BST is used as the ferroelectric material, Pt, Ir, Ir oxide (IrO) is used as the electrode material of the ferroelectric capacitor. ₂ ), Ru, Ru oxide (RuO) ₂ ), Noble metals such as LSCO, SRO or conductive oxides are used.
[0032]
However, it is quite difficult to finely process these materials at a submicron level of about 0.5 μm by RIE (reactive ion etching), ion milling, ECR, etc., and in particular, Pt is very difficult. Miniaturization is not easy. However, miniaturization of the ferroelectric memory cell is indispensable for designing a highly integrated ferroelectric memory, and miniaturization of the upper electrode of the ferroelectric capacitor is an important issue for miniaturization of the memory cell. .
[0033]
On the other hand, the degree of integration of the memory has been improved year by year, but the electric capacity of the dielectric capacitor for accumulating charges must be maintained at about 30 fF or more even if the size is reduced. For this purpose, it is necessary to increase the effective area of the capacitor, reduce the thickness of the dielectric film, or increase the dielectric constant of the dielectric material. In the conventional DRAM technology, three-dimensional and thinner capacitors have been studied mainly by the improvement of the former two. However, conventional SiO ₂ In the type of dielectric film, the three-dimensionalization and thinning of the dielectric film are reaching the limit, and a technique for depositing a dielectric thin film having a large relative dielectric constant is required.
[0034]
By the way, when manufacturing a capacitor having an electrode / ferroelectric / electrode stack structure to be used in the FRAM as described above or an electrode / high dielectric constant dielectric / electrode stack structure to be used in a DRAM, As described above, the electrode material is Pt, Ir, Ru, IrO. ₂ , RuO ₂ , LSCO, SRO and other noble metals or conductive oxides are used.
[0035]
As described above, the ferroelectric substance of the FRAM cell capacitor is PZT (Pb (Zr, Ti) O ₃ ), SBT (SrBi ₂ Ta ₂ O ₉ ), BIT (Bi ₄ Ti ₃ O ₁₂ Or the like, or an oxide obtained by substituting a part of them with a substitution element. BST ((Ba, Sr) TiO 2 is used as a high dielectric constant dielectric of a DRAM cell capacitor. ₃ ) Etc. are used.
[0036]
These ferroelectric or high dielectric constant dielectric film formation methods include sputtering, laser ablation, CVD (Chemical Vapor Deposition), MOD (Metallo-Organic Decomposition) or spin coating such as sol-gel (Sol-gel) method, Furthermore, an LSMCD (Liquid Source Misted Chemical Deposition) method in which a mist MOD raw material is guided and deposited on a wafer by a carrier gas is known.
[0037]
Sputtering is an advantageous technique in terms of throughput because it is excellent in mass productivity as a film formation technique and two electrodes (metal or conductive oxide) sandwiching a dielectric are formed by the same sputtering technique.
[0038]
However, sputtering and laser ablation ₂ , Ar, Ar / O ₂ Therefore, it is inevitable that a gas component is taken into the film and formed into a complex oxide film (an oxide containing at least two kinds of metal elements). There is a problem that voids caused by the residual gas occur in the film), and a high-density oxide film cannot be formed.
[0039]
Actually, a sputtering gas such as Ar is detected from the film immediately after deposition. This is because gas molecules in the vicinity of the target are guided by the high energy of the plasma and enter the film, and are not a mechanism like diffusion. Easy to be driven in. Since the film immediately after deposition is an amorphous or low-density crystal film, this residual gas is dispersed and unnoticeable. It is left behind and becomes a clear gap.
[0040]
When this heat treatment is performed for a short time, large voids are generated not only at the grain boundaries and interfaces but also within the grains. Also in the film formation by CVD or LSMCD, since the carrier gas for introducing the raw material into the chamber is used, the carrier gas is taken into the film, resulting in the residual gas in the composite oxide film as in the case of sputtering. A void is produced.
[0041]
The size of such voids is determined when the film is crystallized or densified by annealing after film formation, but is particularly noticeable when annealing is rapid heat treatment with a high rate of temperature increase. . That is, in the crystallization annealing of the complex oxide film, rapid heat treatment is essential to minimize diffusion and evaporation, but there is a problem that a high-density film cannot be formed due to the above problems.
[0042]
However, in a ferroelectric film having a low film density, not only does the amount of polarization decrease and an operation margin cannot be obtained, but also it cannot be driven on the low voltage side, and short-circuiting easily occurs when the film is thinned. Furthermore, there is a problem that the characteristic change becomes large in the atmosphere in the subsequent process. For the same reason, if voids are generated in the electrode film and the density is lowered, there is a problem that the film resistance increases and the operation speed becomes slow.
[0043]
[Problems to be solved by the invention]
As described above, the conventional ferroelectric memory has been difficult to prevent deterioration of the characteristics of the ferroelectric capacitor and to integrate the process.
[0044]
The present invention has been made to solve the above-described problems, and in manufacturing a ferroelectric memory cell, manufacturing of a semiconductor device that prevents deterioration of the characteristics of the ferroelectric capacitor and enables process integration. It aims to provide a method.
[0045]
Another object of the present invention is to provide a dense and highly reliable strong when manufacturing an FRAM cell using a ferroelectric or a DRAM cell using a high dielectric constant dielectric as an insulating film of an information storage capacitor. A method of manufacturing a semiconductor device capable of forming a dielectric film or a high dielectric constant dielectric film is provided.
[0046]
[Means for Solving the Problems]
The method for manufacturing a semiconductor device according to the present invention includes forming a capacitor using a dielectric film made of a complex oxide film containing at least two or more metal elements between a pair of electrodes, and further insulating the capacitor. When manufacturing a semiconductor device in which an oxide film and a wiring layer are laminated, the capacitor forming step includes a first electrode forming step of forming a first electrode, and the dielectric film on the first electrode. A dielectric film forming step to be formed; a second electrode forming step of forming a second electrode on the dielectric film; and between the first electrode forming step and the dielectric film forming step And said And a step of performing a rapid heat treatment at a heating rate of 10 ° C./second or more under a reduced pressure of 0.5 × 133.322 Pa or more and 500 × 133.322 Pa or less at any time after the second electrode formation step. And
[0047]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0048]
First, an FRAM according to an example of a semiconductor device to which the present invention is to be applied will be briefly described.
[0049]
FIG. 22 shows an equivalent circuit of a 1-transistor 1-capacitor ferroelectric memory cell. In FIG. 22, C is a ferroelectric capacitor, Q is a MOS transistor for charge transfer, WL is a word line connected to the gate of the MOS transistor, BL is a bit line connected to one end of the MOS transistor, PL is a plate line connected to one end (plate) of the capacitor, and VPL is a plate line voltage.
[0050]
FIG. 23 shows an equivalent circuit of a part of a ferroelectric memory having a ferroelectric memory cell array having a bit line folded configuration, for example.
[0051]
In FIG. 23, MC is a unit cell in which a ferroelectric capacitor C for information storage using a ferroelectric as an interelectrode insulating film and a MOS transistor (pass transistor) Q for charge transfer are connected in series. The unit cells MC are arranged in a matrix to form a memory cell array 90.
[0052]
WLi (i = 1, 2, 3,...) Is a plurality of word lines commonly connected to the gates of the transistors Q of the unit cells in the same row in the cell array 90.
[0053]
PLi (i = 1, 2, 3,...) Is a plurality of plate lines commonly connected to the plates of the capacitors C of the unit cells in the same row in the cell array 90.
[0054]
BLi (i = 1, 2, 3, 4...) Is a bit line commonly connected to one end of the transistors of the unit cells in the same column in the cell array 90.
[0055]
The word line selection circuit 81 selects a part of the plurality of word lines WLi based on an address signal and supplies a word line voltage.
[0056]
The capacitor plate line selection circuit 82 selects a part of the plurality of plate lines PLi based on the address signal and controls the voltage of the plate line PLi.
[0057]
On the other hand, as shown in FIG. 24 or FIG. 25, the two-transistor / two-capacitor ferroelectric memory cell using two memory cells of FIG. 22 includes the first transistor Q1 and the second transistor Q2, The first capacitor C1 and the second capacitor C2 are connected in series corresponding to the first transistor Q1 and the second transistor Q2, respectively.
[0058]
A first bit line BL1 and a second bit line / BL1 are connected to one end (drain) of each of the first transistor Q1 and the second transistor Q2, and a common word is connected to each gate. A line WL is connected, and a plate line PL is commonly connected to the plates of the first capacitor C1 and the second capacitor C2.
[0059]
The word line WL and the plate line PL are provided in parallel, a word line signal is supplied to the word line WL selected by a word line row decoder (not shown), and a plate line row decoder (see FIG. The plate line voltage VPL is supplied to the plate line PL selected by (not shown).
[0060]
Further, a sense amplifier (not shown) for bit line potential sense amplification, a write circuit (not shown) and a precharge circuit (not shown) are connected to the two bit lines BL1 and / BL1. Yes.
[0061]
Next, the principle of the data write operation and the data read operation of the ferroelectric memory cell having the two-transistor / two-capacitor configuration will be described with reference to FIGS.
[0062]
FIGS. 24A to 24C show the applied electric field and the electric polarization state of the ferroelectric capacitor during the write operation, and FIGS. 25A to 25C show the state of the ferroelectric capacitor during the read operation. The state of applied electric field and electric polarization is shown.
[0063]
FIG. 26 shows the potential applied to the plate line during a data write operation and a read operation. At the time of writing / reading data to / from the ferroelectric memory cell, the direction of the dielectric polarization is controlled by changing the potential of the plate line PL of the selected memory cell from 0V → 5V → 0V, for example.
[0064]
(A) In the data write operation, in the initial state, the plate line PL is set to the ground potential Vss (0 V), and the two bit lines BL1 and / BL1 are precharged to 0 V, respectively.
[0065]
First, as shown in FIG. 24A, one of the two bit lines BL1 and / BL1 (for example, the second bit line / BL1) is set to 5 V, for example, and 5 V is applied to the word line WL. When the two transistors Q1 and Q2 are turned on, a potential difference is generated between both ends of the second capacitor C2 to generate, for example, downward polarization in the figure, but no polarization of the first capacitor C1 occurs.
[0066]
Next, as shown in FIG. 24B, when the plate line PL is set to 5 V, a potential difference is generated between both ends of the first capacitor C1, and upward polarization occurs in the figure, but the second capacitor The polarization of C2 is not reversed. As a result, the two capacitors C1 and C2 are brought into a state in which polarizations in opposite directions occur as shown in the figure, and this state corresponds to a writing state of data “1” or “0”.
[0067]
Next, as shown in FIG. 24C, the plate line PL is set to 0V, the word line WL is set to 0V, and the two transistors Q1 and Q2 are turned off.
[0068]
(B) In the data read operation, in the initial state, the plate line PL is set to 0V, and the two bit lines BL1 and / BL1 are precharged to 0V, respectively. Here, it is assumed that data in a state where polarizations in opposite directions are generated is written in the two capacitors C1 and C2, for example, as shown in FIG.
[0069]
First, as shown in FIG. 25 (b), when the plate line PL is set to 5V, for example, 5V is applied to the word line WL to turn on the two transistors Q1 and Q2, the second capacitor C2 is turned on. Although a potential difference is generated between both ends and the polarization direction is reversed, the polarization direction of the first capacitor C1 is not reversed. The read potentials from the two capacitors C1 and C2 are sense-amplified by a sense amplifier, and the two bit lines BL1 and / BL1 are correspondingly set to 0V and 5V by the output of the sense amplifier. Based on the output, “1” and “0” of the read data are discriminated.
[0070]
Subsequently, as shown in FIG. 25 (c), when the plate line PL is set to 0V, a potential difference is generated between both ends of the second capacitor C2, the direction of polarization is reversed, and the polarization of the first capacitor C1 is reversed. The direction of is not reversed and returns to the initial state.
[0071]
Next, an embodiment in which the present invention is applied to the FRAM as described above will be described in detail. FIG. 1 to FIG. 3 show an example of a planar pattern of a part of a cell array in the order of the cell array manufacturing process for a large-capacity ferroelectric memory employing a ferroelectric memory cell according to the first embodiment of the present invention. Shown schematically.
[0072]
4 to 7 schematically show a part of a cross-sectional structure of the cell array in the order of manufacturing steps. Specifically, the cross-section includes an SDG region and a cell capacitor along the line AA in FIG. The structure is shown.
[0073]
First, the structure of the cell array will be described. In the structure shown in FIG. 7, the connection structure between the pass transistor and the upper electrode 19 of the ferroelectric capacitor and the structure of the upper electrode 19 are different from the conventional bit line pre-fabrication / upper electrode connection structure described above.
[0074]
Here, a unit cell is a configuration in which one MOS transistor (pass transistor) for charge transfer and one ferroelectric capacitor for information storage are connected in series, and the unit cells are arranged in a matrix. An FRAM having a 1-transistor 1-capacitor ferroelectric memory cell constituting a memory cell array will be described as an example. For simplicity of explanation, each word line is indicated by WL, each bit line is indicated by BL and each plate line is indicated by PL.
[0075]
In FIG. 7, reference numeral 1 denotes a first conductivity type (for example, p-type) semiconductor substrate (for example, a silicon substrate), and a plurality of element regions (activation regions) SDG are formed on the surface layer portion thereof as shown in FIG. Each is formed in a substantially linear shape in a direction orthogonal to the word line WL formation direction (a direction parallel to the bit line BL formation direction) and in a matrix arrangement in plan view, and is formed between the element regions SDG. An oxide film 2 for an element isolation region is formed.
[0076]
Here, the position of each element region SDG is shifted by the length (one pitch) of one element region SDG for each column, and each element region SDG has a checkered arrangement ( Zigzag arrangement with respect to the regular lattice).
[0077]
Each element region SDG has a first drain / channel / source region constituting the first MOS transistor formed in a straight line in a region on one end side from the central portion, and a region on the other end side from the central portion. The second drain / channel / source region constituting the second MOS transistor is formed in a straight line, and the central portion is a drain region D common to the first and second MOS transistors. .
[0078]
A gate electrode portion G is formed on the channel region of the MOS transistor via a gate oxide film 3, and the gate electrode portions G of a plurality of MOS transistors in the same row are continuously connected to form a word line WL. The lines WL are formed in parallel to each other.
[0079]
In this case, each word line WL (gate electrode portion G) has a two-layer structure of, for example, P-doped polysilicon 4 and WSi (tungsten silicide) 5 and is protected by the surface insulating film 6 and the sidewall insulating film 7. ing.
[0080]
Further, an interlayer insulating film 9 and a surface planarizing interlayer insulating film 10 are formed on the surface insulating film 6 and the side wall insulating film 7. On the interlayer insulating film 10, the formation direction of the word lines WL and the respective directions are formed. Bit line BL groups are formed in the orthogonal direction.
[0081]
In this case, a contact hole is opened in the interlayer insulating film 10 so as to correspond to the second conductivity type (n-type in this example) impurity diffusion region (drain region) D in each central portion of the element region SDG. A bit line BL made of a barrier metal film 11 and a conductive film 12 is formed on the interlayer insulating film 10 at a position slightly deviated from the contact hole, and each bit line BL is in the same column in the contact hole. The drain regions D of the plurality of element regions SDG are contacted.
[0082]
4 to 7, the bit line BL is indicated by a solid line only in the contact hole, and the interlayer insulating film 10 located behind the illustrated cross section is indicated by a dotted line.
[0083]
Further, a planarization interlayer insulating film 13 and a cap insulating film 16 are formed on the bit line BL group. A ferroelectric capacitor having a stack structure is formed on the cap insulating film 16 for each unit cell. (Lower electrode 17, ferroelectric insulating film 18, upper electrode 19) are formed, and further, insulating film 20 for protecting the capacitor and passivation film 23 are formed.
[0084]
In this case, the lower electrodes 17 of the plurality of ferroelectric capacitors in the same row cover the central portion of the SDG region including the corresponding MOS transistor or the upper portion of the adjacent inter-element isolation oxide film 2, and The capacitor plate lines PL are continuously formed in a direction parallel to the formation direction of the word lines WL group (that is, in a direction orthogonal to the bit lines BL).
[0085]
Further, the upper electrode 19 of the ferroelectric capacitor for each unit cell is formed in a square shape, for example, via the ferroelectric insulating film 18 on the corresponding lower electrode 17 region.
[0086]
The upper electrode 19 of the ferroelectric capacitor is connected to the second conductivity type (in this example, n-type) impurity diffusion region (source region) S at one end of the corresponding MOS transistor via the electrode wiring 22 for local connection. Connected.
[0087]
In this case, contact holes corresponding to the source regions S at both ends of the element region SDG are formed in the interlayer insulating film 13 for surface planarization, the interlayer insulating film 10 for surface planarization, the interlayer insulating film 9 and the like. A conductive plug (capacitor contact plug) 15 is embedded in the contact hole. A contact hole is formed in the cap insulating film 16 so as to correspond to the capacitor contact plug 15. The inside of the contact hole, the capacitor protective film insulating film 20, and the upper electrode 19 are formed. For example, an aluminum-based wiring is formed as the electrode wiring 22 for local connection.
[0088]
In this example, the capacitor contact plug 15 and the electrode wiring 22 have a structure having barrier metal films 14 and 21 on the base side, respectively, similarly to the bit line BL.
[0089]
At this time, in this example, the capacitor contact plug 15 and the electrode wiring 22 are made of different materials. Specifically, the material of the capacitor contact plug 15 is preferably a refractory metal, and the material of the electrode wiring 22 is preferably an aluminum wiring material, a copper wiring material, or a conductive polysilicon wiring material.
[0090]
The lower end surface of the electrode wiring 22 has a larger area than the upper end surface of the capacitor contact plug 15, and the upper end surface of the capacitor contact plug 15 and the surrounding interlayer insulating film (in this example, the interlayer insulating film 13). I'm in contact. This makes it possible to reduce the contact resistance between the electrode wiring 22 and the capacitor contact plug 15 and to secure a margin for mask alignment when opening a contact hole corresponding to the capacitor contact plug 15. . Next, the manufacturing method of the cell array will be described in the order of steps with reference to the plane pattern shown in FIGS. 1 to 3 and the cross-sectional views shown in FIGS.
[0091]
First, as shown in FIGS. 1 and 4, an array of cell MOS transistors is formed on a silicon substrate 1 by a process similar to the process of forming a normal CMOS DRAM cell.
[0092]
Here, 2 is an oxide film which forms an element isolation region selectively formed in the substrate surface layer portion, and D and S are impurity diffusions having a conductivity type opposite to that of the substrate selectively formed in the element formation region of the substrate surface layer portion. A drain / source region composed of layers, 3 is a gate oxide film for a MOS transistor formed on the substrate surface, and G is a gate electrode portion for a MOS transistor formed on the gate oxide film 3 (part of a word line WL). It is.
[0093]
Next, the interlayer insulating film 10 is formed on the substrate including the gate electrode portion G, and a contact hole is formed in a portion corresponding to the drain region D of the interlayer insulating film 10. Further, the barrier metal film 11 and the conductive film 12 are sequentially formed inside the contact hole and on the interlayer insulating film 10, and the conductive film 12 and the barrier metal film 11 on the interlayer insulating film 10 are patterned to form the bit line BL. To do.
[0094]
Next, an interlayer insulating film (for example, a BPSG film) 13 for planarization is deposited on the substrate including the bit line by about 800 nm, and then is planarized by polishing by about 200 nm by chemical mechanical polishing (CMP). .
[0095]
Next, as shown in FIG. 5, an opening area of, for example, 0.8 × 0.8 μm □ is formed in a portion corresponding to the source region S of the interlayer insulating film 13 and the interlayer insulating film 10 by the lithography process and the etching process. Contact holes for capacitor plugs are selectively formed. In this case, the total insulating film thickness of the interlayer insulating film 13 and the interlayer insulating film 10 is 1500 nm, and the aspect ratio of the opening is 1.9.
[0096]
Further, after depositing a barrier metal film (for example, TiN film) 14 nm on the inner surface of the contact hole, tungsten is deposited on the entire surface of the contact hole by, for example, a metal CVD apparatus to a thickness of about 1700 nm which is equal to or greater than the total insulating film thickness. Embedded.
[0097]
Thereafter, the tungsten film and the barrier metal film on the planarization interlayer insulating film 13 are removed by etching back, whereby the capacitor contact plug 15 is obtained as shown in FIG.
[0098]
When the capacitor contact plug 15 is embedded, the barrier metal film 14 is formed on the inner wall of the contact hole, so that it is possible to prevent diffusion from the contact plug 15 to the impurity diffusion layer for the source region S.
[0099]
Further, as shown in FIG. 5, after sufficiently flattening the surface of the interlayer insulating film 13 by CMP, a cap insulating film 16 is deposited to a thickness of 150 nm.
[0100]
Next, as shown in FIGS. 2 and 6, a conductive film for the capacitor lower electrode 17 (capacitor plate line PL) and a ferroelectric film 18 for the capacitor insulating film are sequentially formed on the cap insulating film 16. Further, after forming the capacitor upper electrode 19 and patterning the conductive film for the ferroelectric film 18 and the lower electrode 17 to form the ferroelectric capacitor, the capacitor protection insulating film 20 is formed.
[0101]
At this time, as the ferroelectric film 18, PZT (PbZr _x Ti _1-x O ₃ ), PLZT ((Pb, La) (Zr, Ti) O ₃ ), SBT (SrBi ₂ Ta ₂ O ₉ ) Etc. can be used. Further, as the capacitor lower electrode 17 and the capacitor upper electrode 19, Pt or the like (Pt, Ir, IrOx, IrO ₂ , RuO ₂ , Or a combination thereof).
[0102]
Next, portions corresponding to the capacitor protection insulating film 20 and cap insulating film 16 on the capacitor contact plug 15 are opened, and portions corresponding to the capacitor upper electrode 19 of the capacitor protecting insulating film 20 are opened. . In this case, an opening (16a in FIG. 2) larger than the upper end area of the capacitor contact plug 15 and an opening (19a in FIG. 2) smaller than the area of the capacitor upper electrode 19 are formed.
[0103]
As shown in FIGS. 3 and 7, as an electrode wiring material for connecting the capacitor contact plug 15 and the capacitor upper electrode 19, for example, a TiN film 21 for a barrier metal film and Si.Cu (silicon / copper). A conductive film such as an Al (aluminum) wiring containing a component is sequentially deposited by, for example, a high-frequency sputtering method, a metal CVD method, or a MOCVD method so as to cover the insulating film 20 for protecting the capacitor. Then, a passivation film 23 is deposited thereon.
[0104]
In forming the ferroelectric film 18, in order to crystallize the ferroelectric material after the deposition of the ferroelectric material and enhance the ferroelectric properties, the ferroelectric film 18 is usually used in a high-temperature oxygen atmosphere at about 750 ° C. for about 10 seconds. , Fast heat treatment.
[0105]
In addition, annealing is performed in a high-temperature oxygen atmosphere at 600 ° C. for about 30 minutes in order to recover the deterioration of the ferroelectric characteristics that occurs when capacitor patterning is performed in the process after the deposition of the ferroelectric material.
[0106]
In the treatment in the high temperature oxygen atmosphere, the cap insulating film 16 is used as a contact for forming the electrode wiring until the thermal treatment process of the ferroelectric material in forming the ferroelectric film 18 is completed. Since the hole is not opened, the capacitor contact plug material has a function of preventing oxidation.
[0107]
However, even when the capacitor contact plug 15 is covered with the cap insulating film 16, mild partial oxidation of the surface of the capacitor contact plug material is unavoidable due to annealing in a high-temperature oxygen atmosphere.
[0108]
Therefore, preferably, when the electrode wiring material is deposited on the capacitor contact plug 15, an additional step of etching the surface oxide film of the capacitor contact plug 15 is added to the capacitor contact plug 15 and the electrode wiring material. Stable connection becomes possible. Etching at this time can be performed by reverse sputtering by replacing the normal metal sputtering electrode.
[0109]
In general, the 450 ° C. sintering process using a mixed gas of hydrogen and nitrogen, which is performed to lower the contact resistance between the MOSFET active layer and the contact plug, deteriorates the characteristics of the ferroelectric capacitor in the conventional process example. It was impossible to use. On the other hand, according to the manufacturing method of the above embodiment, the capacitor contact plug 15 is formed before the formation of the ferroelectric capacitor, so that it is the same as the normal MOS type LSI before the formation of the ferroelectric capacitor. It is possible to employ the sintering step, and specifically, sintering at about 400 to 500 ° C. using hydrogen, nitrogen, or a mixed gas thereof can be performed. Thereby, there is an advantage that various device parameters such as the gate threshold value Vth and substrate potential of the MOSFET can be controlled in common.
[0110]
In the manufacturing method of the above embodiment, the same material as that of the electrode wiring is not used as the material of the capacitor contact plug 15, which has oxidation resistance, heat resistance, low contact resistance, and has a high aspect ratio. It is desirable to use a material that can be embedded, and it is desirable to use a refractory metal such as tungsten, molybdenum, titanium, or palladium.
[0111]
This is because, when a material that is easily oxidized, such as a polysilicon material or an aluminum-based material, is used as the capacitor contact plug 15, an oxygen capacitor is formed when the ferroelectric capacitor is formed after the capacitor contact plug 15 is buried. This is because the high temperature heat treatment in the atmosphere is also applied to the capacitor contact plug 15, and the capacitor contact plug 15 is oxidized to increase its parasitic resistance.
[0112]
In this example, TiN is used as an interlayer between the AlSiCu electrode wiring material and the tungsten contact plug material, but a Ti / TiN laminated film may be used. Further, the electrode wiring material is not limited to AlSiCu wiring, and aluminum-based or copper-based wiring materials or conductive polysilicon-based wiring materials can be used.
[0113]
In the manufacturing method of the above embodiment, in order to reduce the contact resistance between the capacitor contact plug and the electrode wiring material, the electrode wiring is larger than the area of the upper end surface of the capacitor contact plug at the contact surface. A connection structure with a wiring area is adopted.
[0114]
That is, in this example, the electrode wiring (AlSiCu / TiN) on the capacitor contact plug has a structure in which both the upper end surface of the contact plug (W) and the peripheral insulating film (interlayer insulating film 13 in this example) are in contact. Adopted.
[0115]
Note that the charge transfer pass transistor is not limited to a MOS transistor in which the gate insulating film is made of an oxide, and the gate insulating film is made of nitride, nitride oxide, or a laminated structure of oxide and nitride. An MIS transistor can be formed.
[0116]
Next, a ferroelectric capacitor using Pt or another electrode material (Ir, Ir oxide, Ru oxide, etc.) as the upper electrode material of the ferroelectric capacitor using the PZT material or SBT material as described above. A method for finely forming the upper electrode of 0.1 to the micron level will be described with reference to FIGS. This process can also be applied to the formation of other than ferroelectric capacitor electrodes.
[0117]
First, as shown in FIG. 8A, a lower electrode film 17a of a ferroelectric capacitor and a ferroelectric thin film 18a are sequentially deposited on the cap insulating film 16. In this case, Pt is formed at 175 nm as the lower electrode film 17a, and a PZT film is formed at 300 nm as the ferroelectric thin film 18a.
[0118]
Next, as shown in FIG. 8B, a 300 nm TEOS (tetraethoxysilane) oxide film 20a is deposited on the ferroelectric thin film 18a.
[0119]
Next, as shown in FIG. 8C, an opening corresponding to a desired upper electrode area is selectively formed in the TEOS oxide film 20a by using PEP (photo etching process).
[0120]
Next, as shown in FIG. 8D, a Pt film 19a for forming an upper electrode is deposited to a thickness greater than that of the TEOS oxide film 20a.
[0121]
Next, as shown in FIG. 8E, the Pt film 19a on the TEOS oxide film 20a is removed by etch back or CMP. Then, using a normal photolithography technique, a strip-like resist pattern is formed, and the TEOS oxide film 20a / ferroelectric thin film 18a / lower electrode film 17a are formed by anisotropic etching using the resist pattern as a mask. Sequential patterning is performed.
[0122]
As a result, a desired strip-shaped ferroelectric thin film 18 and lower electrode 17 are obtained. At this time, the TEOS oxide film 20a, the ferroelectric thin film 18a, and the lower electrode film 17a are sequentially etched using the same mask pattern, so that the TEOS oxide film 20a, the ferroelectric thin film 18, and the lower electrode film 17 are self-aligned. Are formed in substantially the same planar shape.
[0123]
Next, as shown in FIG. 8F, the processing damage due to anisotropic etching at the pattern edges of the ferroelectric thin film 18 and the lower electrode 17 is alleviated, and the electrical withstand voltage of the ferroelectric thin film 18 is reduced. In order to suppress the decrease and the like, the capacitor protection insulating film 20 is formed so as to cover the surfaces of the TEOS oxide film 20a, the upper electrode 19, the ferroelectric thin film 18, and the lower electrode 17. As the capacitor protection insulating film 20, for example, SiO obtained by decomposition of TEOS by plasma CVD is used. ₂ Film or SiO by thermal oxidation method ₂ A film is formed.
[0124]
Then, an opening smaller than the area of the upper electrode 19 is provided in a portion corresponding to the upper electrode 19 of the capacitor protection insulating film 20, and then the electrode wiring 22 and the final protection passivation film 23 as described above are formed. .
[0125]
As described above, in the manufacturing method of the above embodiment, when forming a ferroelectric memory cell, a ferroelectric capacitor is formed after embedding the contact plug layer on the one end side region of the pass transistor, and the capacitor upper electrode and It is possible to form an electrode wiring for connecting the upper end portion of the contact plug, for example, by sputtering.
[0126]
As a result, the wiring film deposition process in a reducing atmosphere using a metal CVD apparatus or MOCVD apparatus after the formation of the ferroelectric memory cell can be avoided, and the electrical characteristics such as the residual polarization amount of the capacitor are deteriorated. Can be prevented.
[0127]
Also, since the capacitor upper electrode 19 is embedded in the opening of the insulating film 20a, the area of the capacitor upper electrode 19 can be reduced, the area of the unit cell can be reduced, and the FRAM can be highly integrated. Become.
[0128]
In the first embodiment, the capacitor contact plug is formed in one step. However, the capacitor contact plug may be formed in two stages, and a sectional view of the manufacturing method of such a modification example. Is shown in FIG. 9 and FIG.
[0129]
That is, as shown in FIGS. 9 and 10, the first capacitor contact plugs 11a and 12a are formed simultaneously with the formation of the bit lines BL (11 and 12), and the insulating layer 13 formed thereon is formed on the insulating layer 13 formed thereon. Second capacitor contact plugs 14 and 15 are formed so as to be connected to the upper end surfaces of first capacitor contact plugs 11a and 12a.
[0130]
By adopting such a structure, it is possible to reduce the aspect ratio of each contact hole when the contact plug layer is embedded, so that the contact hole can be easily embedded.
[0131]
The semiconductor device thus formed includes a MIS transistor having a drain region and a source region formed of an impurity diffusion region formed in a surface layer portion of a semiconductor substrate, and a first substrate formed on the semiconductor substrate including the MIS transistor. An insulating film is connected to one of the drain region and the source region via a bit line contact plug embedded in the first insulating film, and is formed on the first insulating film. A bit line, a first capacitor contact plug embedded in the first insulating film and having a lower end in contact with the other of the drain region and the source region, and a semiconductor substrate including the bit line A second insulating film formed on the first insulating film and embedded in the second insulating film; A second capacitor contact plug in contact with each other, a ferroelectric capacitor formed on the second insulating film and having a lower electrode, an interelectrode insulating film using a ferroelectric material, and an upper electrode, and the second capacitor And an electrode wiring for connecting between the upper end of the capacitor contact plug and the ferroelectric capacitor.
[0132]
In the first embodiment, the contact plug portion of the bit line BL (11, 12) and the capacitor contact plugs 14, 15 (first capacitor contact plugs 11a, 12a, second capacitor contact plug 14, 9 and 10), the upper opening width may be formed so as to have a reverse-tapered side surface wider than the opening width of the bottom surface.
[0133]
As a result, even if the distance between the word lines is reduced as the cell size is reduced, the distance between the word lines and the lower part of the contact plug is ensured as desired and the contact hole opening area (contact area with the electrode wiring) is desired. As a result, it is easy to secure the street, and the process margin can be increased.
[0134]
Next, FIG. 11 and FIG. 12 schematically show a part of a cross-sectional structure in the order of manufacturing steps of the FRAM cell and other elements in the large-capacity FRAM having the array of FRAM cells according to the second embodiment of the present invention. Is shown.
[0135]
FIG. 13 schematically shows an example of a planar pattern of a part of an array of FRAM cells according to the second embodiment.
[0136]
The manufacturing process shown in FIGS. 11 and 12 includes at least one of Al, AlCu, AlCuSi, and Cu in order to fill a via hole for connecting a second layer wiring (bit line or other wiring) in a two-layer wiring structure. It is characteristic that two materials (aluminum in this example) are reflowed. Here, the same parts as those in the manufacturing process shown in FIGS. 4 to 7 are denoted by the same reference numerals.
[0137]
11 and 12, a switching MOS transistor 31 for a memory cell and another MOS transistor 32 for an embedded device other than the memory cell are formed on a semiconductor substrate 1.
[0138]
In the first insulating layer 10 covering each of the transistors and having a flattened surface (that is, a flat base step), the drain region D and the source region S of the switching transistor 31 are connected. A bit line contact plug 33, a capacitor contact plug 34, and a contact plug 35 connected to the gate of another MOS transistor 32 for the embedded device are embedded.
[0139]
The second insulating layer 20 covering the substrate including the lower electrode 17, the ferroelectric film 18 and the upper electrode 19 formed in order on the surface of the first insulating layer 10 includes a bit line contact plug 33, a capacitor A hole is selectively formed above the contact plug 34, the mixed device contact plug 35, and the upper electrode 19. Then, a bit line buried plug connection wiring (bit line connection contact pattern) 36 connected to the bit line contact plug 33 through the hole portion, a capacitor contact plug 34 and an upper electrode lead-out wiring connected to the upper electrode 19 (Capacitor electrode wiring) 22 and a first layer wiring 37 connected to a contact plug 35 for a mixed device are formed.
[0140]
The upper electrode lead-out wiring 22 and the bit line embedded plug connection wiring 36 have at least one material of Al, AlCuSi, AlCu, W metal, TiN metal, and Ti metal. It is formed of the same wiring layer. A metal layer 11 ′ made of any one of W metal, TiN metal, and Ti metal is selectively formed on the upper surface side of the upper electrode lead-out wiring 22, the bit line embedded plug connection wiring 36, and the first layer wiring 37. These can be formed by sputtering or CVD that does not damage the ferroelectric film 18.
[0141]
In the third insulating layer 30 covering the upper surface of the substrate including the wirings and having a flat surface, via holes are selectively formed above the bit line embedded plug connection wirings 36 and the first layer wirings 37. Is formed. Then, at least one material (aluminum in this example) of Al, AlCu, AlCuSi, Cu is reflowed so as to fill the via hole, and is connected to the bit line buried plug connection wiring 36 through the via hole portion. A second layer wiring 38 connected to the first layer wiring 37 through the bit line BL and the via hole portion is formed. Further, a passivation film 39 is formed, and a hole is opened in the pad portion.
[0142]
A memory cell having an information storage capacitor and a switching transistor using a ferroelectric film made of a material having a perovskite or layered perovskite structure as described above, and a ferroelectric memory having a multilayer wiring structure of at least two layers or more In manufacturing, a step of reflowing at least one material (aluminum in this example) of Al, AlCu, AlCuSi, and Cu is used in order to fill the via hole in the multilayer wiring structure in the bit line forming step.
[0143]
At this time, when the underlying wiring is Al-based during Al reflow, the Al-based wiring may be melted and voids may occur depending on the temperature during sputter deposition. For this reason, as the base directly contacting with the via metal, after depositing any one of W metal, TiN metal, and Ti metal layer by sputtering or CVD method, the metal is selectively placed directly under the region to be the via portion of the multilayer wiring. Layer 11 'is formed and used as a melt void prevention film.
[0144]
Next, it demonstrates in detail in order of a process, referring sectional drawing and a plane pattern which are shown in FIG. 11 thru | or FIG.
[0145]
First, as shown in FIG. 11, a memory cell transistor 31 and a transistor 32 for another device are formed on the silicon substrate 1 by a process similar to a process for forming a normal CMOS DRAM cell.
[0146]
Here, 2 is an element isolation region selectively formed in the substrate surface layer portion, and D and S are drains made of impurity diffusion layers having a conductivity type opposite to that of the substrate selectively formed in the element formation region of the substrate surface layer portion. A source region 3 is a gate oxide film for a MOS transistor formed on the substrate surface, and G is a gate electrode portion (a part of the word line WL) for the MOS transistor formed on the gate oxide film 3.
[0147]
The element isolation region 2 may adopt an arbitrary structure such as a LOCOS film (selective oxide film) or STI (Shallow Trench Isolation).
[0148]
Next, a first interlayer insulating film (for example, a BPSG film) 10 for planarization is deposited on the substrate including the gate electrode portion G, and then the surface is planarized by CMP.
[0149]
Next, contact holes are selectively formed in the first interlayer insulating film 10. Specifically, a bit line contact hole is formed in a portion corresponding to the drain region D, and a capacitor plug contact hole and other wiring contact holes are formed in a portion corresponding to the source region S.
[0150]
Further, after depositing a barrier metal film (Ti, TiN) 11 on the inside of the contact hole and on the first interlayer insulating film 10 using a sputtering method, a W film is deposited using a CVD method, and the contact hole is formed. Contact plugs 33, 34, and 35 are formed inside.
[0151]
Next, etch back or CMP is performed to expose the surface of the first interlayer insulating film 10. Here, as in the first embodiment, if the contact plug is formed in a reverse taper shape, the process margin can be increased.
[0152]
Next, as shown in FIG. 12, Pt / Ti / TiN is sputter-deposited on the first interlayer insulating film 10 including the contact plugs as a conductive film for the capacitor lower electrode 17 (capacitor plate line PL). To do. Further, a PZT film is formed as the ferroelectric film 18 for the capacitor insulating film. Further, Pt is formed as the capacitor upper electrode 19. Then, using RIE, the capacitor upper electrode 19, the ferroelectric film 18, and the lower electrode 17 are patterned in this order to form a ferroelectric capacitor. At this time, if the ferroelectric film 18 is damaged, it can be recovered by heat treatment in an oxygen atmosphere at 500 to 600 ° C.
[0153]
Next, a second interlayer insulating film 20 is formed by plasma CVD, and contact holes for connection to the contact plugs 33, 34, 35 and the upper electrode 19 are formed by chemical dry etching (CDE) and RIE. To do.
[0154]
Then, Al and W are sequentially deposited by using the sputtering method to form the capacitor electrode wiring 22 for connecting the capacitor contact plug 34 and the capacitor upper electrode 19, and at the same time, the bit line connecting contact pattern 36 and the memory cell. First-layer wirings 37 for other mixed devices are formed.
[0155]
Further, after forming the third interlayer insulating film 30 and planarizing the surface by CMP, the first layer of the embedded device other than the via hole and the memory cell for connecting to the bit line connecting contact pattern 36. A via hole for connecting to the wiring 37 is formed, and the inside of the via hole is formed by a high-frequency magnetron sputtering method (Al reflow method in which Al is melted at a high temperature and the via hole is embedded in a migration manner) in an Ar atmosphere at a substrate temperature of 400 to 470 ° C. After the second wiring layer is deposited so as to be embedded, the second wiring layer is patterned to form the bit line BL and the second layer wiring 38 for the embedded device.
[0156]
As a result, the bit line BL is connected to the drain region D of the switching MOS transistor 31 of the memory cell via the via hole portion / bit line connecting contact pattern 36 and the bit line contact plug 33, and for the embedded device. The second layer wiring 38 is connected to the embedded device MOS transistor 32 other than the memory cell through the first layer wiring 37.
[0157]
The second layer wiring 38 may be patterned using the film deposited by Al reflow as it is, but the Al-based metal other than the via portion is polished, removed and planarized by metal CMP, and then the second layer wiring 38 again. A metal to be the layer wiring 38 may be deposited and patterned.
[0158]
Thereafter, in the case of a semiconductor integrated circuit having a two-layer wiring structure, a top passivation insulating film 39 is deposited and a pad portion is opened. In the case of a semiconductor integrated circuit having a wiring structure of three layers or four layers or more, after forming the interlayer insulating film 30 as described above, a wiring layer is deposited by Al reflow method, and a patterning process is repeated as many times as necessary. A top passivation insulating film 39 is deposited later, and the pad portion is opened.
[0159]
In the present embodiment, a part of the first wiring layer when the first layer wiring 37 is formed may be used as the pad portion.
[0160]
Further, FIG. 12 shows a case where holes are selectively opened above the bit line contact plug 33 in the third interlayer insulating film 30 and the bit line is brought into contact with the bit line connection contact pattern 36. Although shown, the bit line can be contacted at a position different from that by appropriately routing the bit line connection contact pattern 36 on the first insulating layer 10. Therefore, the process margin can be increased, which is particularly advantageous in improving the degree of freedom in designing the cell array. In exactly the same manner, the first layer wiring 37 of the mixed device other than the memory cell can be routed on the first insulating layer 10.
[0161]
A cell array having a structure (FCOB: Ferro Capacitor On Bit-line) in which the bit line BL is arranged below the ferroelectric capacitor as shown in FIG. 7 improves the degree of freedom in designing the memory cell portion. As a result, the insulating film thickness increases by the amount of the interlayer insulating film 13 formed on the bit line, and a structure that is disadvantageous for a mixed device other than a memory is forced.
[0162]
On the other hand, when the bit line BL is arranged on the upper layer side of the ferroelectric capacitor as shown in FIGS. 11 and 12, and the bit line BL is formed of the second wiring layer, the memory cell portion This greatly increases the degree of freedom in design, and this makes it possible to reduce the cell area.
[0163]
Here, description will be made with reference to the plane pattern shown in FIG.
[0164]
In the structure shown in FIG. 13, the bit line BL is formed with a constant width in the direction perpendicular to the word line WL above the word line WL as compared with the structure of FIGS. 1 to 3 described above. Since the arrangement, width, contact portion, and the like are the same and the others are the same, the same reference numerals as those in FIGS. 1 to 3 are assigned and detailed description thereof is omitted.
[0165]
That is, in FIG. 13, reference numeral 41 denotes a contact portion in which the bit line BL is connected to the bit line connection contact pattern (36 in FIG. 12), and reference numeral 42 denotes a stacked capacitor formed for each unit cell. Electrode wiring for local connection (see FIG. 12) formed in the intermediate layer between the word line WL and the bit line BL with respect to the upper electrode (19 in FIG. 12) and the capacitor contact plug (34 in FIG. 12). 12) of 12 is a contact part to which the connection is made. PL is a capacitor plate line formed so that the lower electrode (17 in FIG. 12) of the capacitor is continuous.
[0166]
That is, if a structure in which the bit line is arranged on the upper layer side of the ferroelectric capacitor as shown in FIGS. 11 and 12 is adopted, a cell array can be formed as shown in FIG. 13, and the FCOB structure is formed. As compared with the above, since the width of the bit line BL can be increased and the resistance of the bit line can be lowered, this is extremely advantageous in terms of memory operation.
[0167]
Therefore, when the FRAM memory and another LSI are mixedly mounted, it is more advantageous to form the bit line BL below the ferroelectric capacitor or after the second wiring layer rather than the FCOB structure in which the bit line BL is wired to the first layer.
[0168]
Furthermore, for comparison with the present invention, a case where via filling by Ti (sputter) / TiN (sputter) / W (CVD) is used instead of via filling by Al reflow in the second embodiment of the present invention. About (comparative example), the influence which it has on the polarization amount of the ferroelectric film of the ferroelectric capacitor by the difference in a process was investigated.
[0169]
As a result, the polarization amount of the ferroelectric film of the ferroelectric capacitor obtained by the second embodiment is 30 μC / cm. ² In contrast, in the comparative example, the amount of polarization is about 3 μC / cm. ² It deteriorated severely.
[0170]
In the FRAM device, the polarization amount of the ferroelectric is directly effective for the sense margin, and the larger value leads to the improvement of the reliability. Therefore, the superiority of the second embodiment is clear.
[0171]
Further, FIG. 14 schematically shows a part of a cross-sectional structure (including an SDG region and a cell capacitor) in a large-capacity FRAM having an array of FRAM cells according to a third embodiment of the present invention.
[0172]
The structure of the FRAM cell shown in FIG. 14 is basically substantially the same as that of the FRAM cell described above with reference to FIG. 12, but the first SiO 2 layer is formed on the first interlayer insulating film 10. ₂ The ferroelectric capacitor is formed through the film 51, and the second SiO is formed on the ferroelectric capacitor. ₂ The difference is that the film 52 is formed.
[0173]
Compared with the manufacturing process described above with reference to FIGS. 11 and 12, the manufacturing process of the FRAM cell shown in FIG. 14 is (1) after the surface of the first interlayer insulating film 10 is exposed by etch back. The first SiO 2 is deposited on the entire surface by sputtering. ₂ (2) After forming the ferroelectric capacitor as described above, the second SiO 2 is deposited on the entire surface by sputtering. ₂ The point that a film 52 is deposited to a thickness of about 100 nm is added. (3) Second SiO ₂ When the second interlayer insulating film 13 is deposited on the film 52 and a hole is selectively opened in the second interlayer insulating film 13, the lower second SiO 2 film is formed. ₂ Film 52 or second SiO ₂ Film 52 / first SiO ₂ The film 51 also differs in that holes are opened.
[0174]
SiO formed by sputtering as described above ₂ The films 51 and 52 do not contain a hydrogen group and are difficult to pass a hydrogen group. That is, in the subsequent process, even if the hydrogen group reaches the vicinity of the ferroelectric capacitor, it does not reach the ferroelectric capacitor directly, so that deterioration of the ferroelectric characteristics (polarization amount) is minimized. can do.
[0175]
FIG. 15 is a cross-sectional view of a semiconductor device according to the fourth embodiment of the present invention. The present embodiment provides a manufacturing method suitable for a semiconductor device in which an FRAM cell array and a logic circuit are mounted together.
[0176]
The manufacturing method of this embodiment is characterized in that contact plugs from the first layer wiring in the two-layer wiring structure to the semiconductor substrate or the gate electrode of the transistor are formed in two portions. That is, in the contact plug of this embodiment, the lower layer portion is first formed before the ferroelectric capacitor of the FRAM cell is formed, and then the remaining upper layer portion is formed after the ferroelectric capacitor is formed.
[0177]
By adopting such a contact plug formation method, the ratio of the depth to the contact hole opening diameter (aspect ratio) can be reduced, and the processing and filling of the contact hole is facilitated. This advantage is advantageous when mixed mounting with a logic product in which patterns are arranged using very strict rules in processing.
[0178]
The process in the first half of this example is the same as that in FIG. 11 described in the second embodiment. That is, on the semiconductor substrate 1, the MOS transistor 31 for switching the memory cell and the other MOS transistor 32 for the embedded device other than the memory cell are formed.
[0179]
A first bit line contact plug 33 and a first capacitor contact plug 34 connected to the drain / source region of the switching transistor 31 are provided in the flattened first interlayer insulating film 10 covering these transistors. A first contact plug 35 connected to the source or drain region or the gate electrode of another transistor 32 for a mixed device is embedded.
[0180]
Further, as shown in FIG. 15, a thin silicon nitride film layer 121 and a thin silicon oxide film layer 122 are formed on the surface of the first interlayer insulating film 10, and the lower electrode 17 and the ferroelectric film are further formed thereon. 18 and upper electrode 19 are sequentially formed to form a ferroelectric capacitor. This capacitor is covered with a second interlayer insulating film 13 whose surface is flattened. Further, a second bit line contact plug 133 and a second capacitor contact plug are formed inside the second interlayer insulating film 13. 134 and the second contact plug 135 connected to the other transistor 32 for the embedded device is embedded.
[0181]
Further, on the surface of the second interlayer insulating film 13, upper electrode lead-out wirings, bit line embedded plug connection wirings, and first wiring layers of first layer wirings 22, 36, and 37 for embedded devices are formed. .
[0182]
A bit line embedded plug connection wiring 36 and a first layer wiring 37 are formed on the third interlayer insulating film 30 formed on the second interlayer insulating film 13 so as to cover the first wiring layer and having a planarized surface. A via hole is formed directly above the top. This via hole is filled with at least one material of Al, AlCu, AlSiCu, and Cu. Further, second wiring layers 38 and BL are formed on the surface of the third interlayer insulating film 30, and a passivation film 39 is formed thereon.
[0183]
Next, the manufacturing method of this embodiment is demonstrated in order of a process. As described above, the first half of the process is the same as that of the second embodiment (FIG. 11). First, like a normal CMOS type DRAM, a memory cell transistor 31 and another device transistor 32 are formed on a silicon substrate 1. That is, the gate and diffusion layer region of the transistor are formed, and the first interlayer insulating film 10 and the contact hole are formed.
[0184]
Subsequently, a contact plug is embedded in this contact hole. As described above, in this embodiment, the contact plugs from the first wiring layer to the substrate surface are formed in two steps, but the first stage (lower layer portion) contact plugs are formed up to the stage shown in FIG. Complete.
[0185]
Next, as shown in FIG. 15, a thin silicon nitride film layer 121 is formed on the first interlayer insulating film 10 by LPCVD. This silicon nitride film layer 121 has a role of preventing oxidation of the contact plug material (for example, W) due to annealing in an oxygen atmosphere, which will be performed later in the formation process of the ferroelectric capacitor, and also preventing variation in transistor characteristics due to annealing. . Subsequently, a thin silicon oxide film layer 122 is formed on the silicon nitride film layer 121 by LPCVD, plasma CVD, or atmospheric pressure CVD.
[0186]
Next, TiN, Ti, and Pt are sequentially sputtered on the silicon oxide film layer 122 as a conductive film for the capacitor lower electrode 17. A PZT film is formed thereon as the ferroelectric film 18 for the capacitor insulating film. Further thereon, Pt is sputtered as the capacitor upper electrode 19.
[0187]
Subsequently, the upper electrode 19, the capacitor insulating film 18, and the lower electrode 17 are patterned in this order by RIE to form a ferroelectric capacitor. At this time, if the ferroelectric film 18 is damaged and has changed from its original characteristics, it can be recovered by annealing in an oxygen atmosphere at about 500 ° C.
[0188]
Next, a second interlayer insulating film 13 is formed by plasma CVD, and its surface is flattened by CMP or the like. Subsequently, contact holes for connecting the contact plugs 33, 34, 35 to the first wiring layer to be formed later are formed. At this time, a contact hole (not shown) for connecting the capacitor lower electrode 17 and the first wiring layer is simultaneously formed.
[0189]
Next, after a TiN film 111 is formed on the entire surface as a barrier layer by sputtering, Al is deposited by sputtering so as to fill the contact hole and reflowed at a temperature of about 400 ° C. Subsequently, the TiN film and Al other than the inside of the contact hole are removed by CMP or an etch back method. Thus far, both the lower layer portion and the upper layer portion of the contact plug are formed, and the characteristic structure of this embodiment is completed.
[0190]
Next, a contact hole is formed on the capacitor upper electrode 19 by RIE. This contact hole can be formed at the same time as the above contact hole and can be filled with Al or the like. However, in this embodiment, the contact hole is not formed at the same time and is formed separately after the previous contact hole is formed. The reason for this is that the aspect ratio of the contact hole to the upper electrode 19 is smaller than that of the other contact holes, so there is less need for embedding, and the condition for embedding is greatly different for contact holes with greatly different aspect ratios. For example, it is expected that simultaneous embedding is difficult, and further, it is desirable to prevent damage at the time of embedding from reaching the ferroelectric capacitor as much as possible.
[0191]
Next, Ti, TiN, AlCu, and TiN are sequentially deposited on the entire surface by sputtering to form a first wiring layer. By processing this by RIE, the capacitor wiring 22 that connects the capacitor contact plug 134 and the upper electrode 19, the bit line embedded plug connection wiring 36, and the first layer connection wiring 37 for the embedded device are formed. Here, the uppermost TiN of the first wiring layer functions as an antireflection film for preventing reflection of light from Al when forming a resist pattern for lithography.
[0192]
Subsequently, a third interlayer insulating film 30 is formed and the surface thereof is planarized by CMP, and then a via hole for connecting the first wiring layer described above and a second wiring layer described later is opened. Further, the via hole is filled with Al by using the same Al reflow technique as in the case of the contact hole formed in the second interlayer insulating film 13, and then Ti, TiN, and Al are sputtered in order to obtain the second wiring. Form a layer. The second wiring layer is processed by RIE to form the second layer wiring 38, the bit line BL, and the like.
[0193]
Thereafter, in the case of a device having a two-layer wiring structure, a top passivation film 39 is deposited and a pad portion is selectively opened. In the case of a device having a multi-layer wiring structure, a wiring layer and an insulating layer are formed by repeating the above-described method, and finally a top passivation film 39 is deposited, and a pad portion is selectively opened.
[0194]
FIG. 16 is a cross-sectional view of a semiconductor device according to the fifth embodiment of the present invention. The present embodiment provides another structure suitable for a semiconductor device in which an FRAM cell array, a logic circuit, and the like are mixedly mounted, and a manufacturing method thereof. Basically, it is similar to that of the third embodiment. The same parts as those in FIG.
[0195]
The process in the first half of the present example is almost the same as FIG. 11 described in the second embodiment. That is, on the semiconductor substrate 1, a switching transistor 31 of a memory cell, another transistor 32 for an embedded device other than the memory cell, and an STI
An element isolation oxide film 2 is formed by (shallow trench isolation).
[0196]
A silicon oxide film layer 10 is deposited so as to cover these transistors, and the surface is flattened using a CMP method. On top of that, Si _x N _y A film 121 is deposited by LPCVD, for example, 150 nm (FIG. 16). This Si _x N _y The film 121 reduces damage to the transistor (threshold fluctuation) due to oxygen annealing during the formation of the ferroelectric capacitor.
[0197]
Next, contact holes to the source region S and drain region D of the transistor are formed by RIE. Ti and TiN are sequentially deposited as the barrier layer 11 by sputtering, and then W is buried as contact plugs 33, 34, and 35 by the CVD method. Further, Ti, TiN, and W on the insulating film 10 are removed using, for example, a CMP method.
[0198]
Next, a silicon oxide film layer (SiO ₂ ) 122 is deposited to 100 nm. A Pt layer 17, a PZT layer 18, and a Pt layer 19 constituting a ferroelectric capacitor are sequentially deposited thereon by sputtering. These layers are heat-treated in oxygen, and the PZT layer is crystallized to form a perovskite structure. These layers are then processed by RIE into the shape of the capacitor.
[0199]
Next, a silicon oxide film 13 is deposited on the entire surface by plasma CVD, and an opening is formed above the contact plugs 33, 34, and 35 and above the upper electrode 19 of the capacitor. Thereafter, Ti and TiN to be the barrier layer 111, Al to be the wiring layers 22, 36 and 37, and W to be the metal layer 11 ′ are sequentially deposited on the entire surface by sputtering and processed by RIE to wire between the capacitor and the contact plug 34. In addition, a first wiring layer including a contact plug extraction electrode and the like is formed.
[0200]
Next, a silicon oxide film layer 30 is deposited on the entire surface by plasma CVD. An opening is formed in the silicon oxide film layer 30 immediately above the contact plugs 33 and 35, and a portion corresponding to 36 in the first wiring layer is exposed. Subsequently, Ti and TiN serving as the barrier layer 112 and Al serving as the wiring 38 are sequentially deposited by sputtering. Thereafter, Al is reflowed by a heat treatment at about 400 ° C., and the opening having a high aspect ratio formed in the silicon oxide film 30 is buried. At this time, the reason why the W is not buried by the CVD method is to eliminate damage to the ferroelectric capacitor due to hydrogen. If Al reflow is used, hydrogen is not generated and damage to the ferroelectric capacitor can be avoided.
[0201]
Subsequently, the Ti, TiN, and Al layers are processed by RIE to form a second wiring layer. Thereafter, a silicon oxide film 39 is deposited by the CVD method to complete the semiconductor structure shown in FIG.
[0202]
FIG. 17 is a sectional view of a semiconductor device according to the sixth embodiment of the present invention. The present embodiment provides still another structure suitable for a semiconductor device in which an FRAM cell array, a logic circuit, and the like are mixedly mounted, and a manufacturing method thereof. Basically, it is similar to the fourth embodiment, and the same parts as those in FIG.
[0203]
The process up to the step of forming the silicon oxide film 122 is performed in the same manner as in the fifth embodiment. Subsequently, a Pt layer 17, a PZT layer 18, and a Pt layer 19 constituting a ferroelectric capacitor are sequentially deposited on the entire surface by sputtering. These layers are heat-treated in oxygen, and the PZT layer is crystallized to form a perovskite structure. These layers are then processed by RIE into the shape of the capacitor.
[0204]
Next, a silicon oxide film 13 is deposited on the entire surface by plasma CVD, and openings are formed above the contact plugs 33, 34, and 35. Thereafter, Ti and TiN to be the barrier layer 111 and Al to be the wiring layers 22, 36 and 37 are sequentially deposited on the entire surface by sputtering, and Al is reflowed by heat treatment at about 400 ° C. to fill the opening. Thereafter, a W metal layer 11 ′ serving as a barrier is deposited using a CVD method. These Ti, TiN, Al, and W layers are processed by RIE to form a first wiring layer including via contacts with contact plugs 33, 34, 35, and the like. The feature of this embodiment is that the opening (via hole) formed in the silicon oxide film layer 13 is filled with reflowed Al. Here, as in the second embodiment, TiN metal or Ti metal can be used for the metal layer 11 ′.
[0205]
Next, a silicon oxide film layer 30 is deposited on the entire surface by plasma CVD. An opening is formed in the silicon oxide film layer 30 immediately above the drain region D of the transistor, and the corresponding W metal layer 11 ′ on the first wiring layers 36 and 37 is exposed. Subsequently, similarly to the fifth embodiment, Ti and TiN serving as the barrier layer 111 and Al serving as the wiring 38 are sequentially deposited by sputtering. Thereafter, Al is reflowed by a heat treatment at about 400 ° C., and an opening (via hole) formed in the silicon oxide film 30 with a high aspect ratio is buried. Note that the W metal layer 11 ′ formed on the first wiring layer functions to prevent dissolution of Al in the first wiring layer when reflowing Al in the second wiring layer.
[0206]
Subsequently, the Ti, TiN, and Al layers are processed by RIE to form a second wiring layer. Thereafter, a silicon oxide film 39 is deposited by the CVD method to complete the semiconductor structure shown in FIG.
[0207]
FIG. 18 is a cross-sectional view of a semiconductor device according to the seventh embodiment of the present invention. The present embodiment provides still another structure suitable for a semiconductor device in which an FRAM cell array, a logic circuit, and the like are mixedly mounted, and a manufacturing method thereof. The structure of this embodiment is basically similar to that of the third embodiment, and the same parts as those in FIG.
[0208]
The process in the first half of the present example is almost the same as FIG. 11 described in the second embodiment. That is, on the semiconductor substrate 1, a switching transistor 31 of a memory cell, another transistor 32 for a mixed device other than the memory cell, and an element isolation oxide film 2 by STI are formed.
[0209]
A silicon oxide film layer 10 is deposited so as to cover these transistors, and the surface is flattened using a CMP method. On top of that, Si _x N _y A film 121 is deposited by LPCVD, for example, 150 nm (FIG. 18). This Si _x N _y The film 121 reduces damage to the transistor (threshold fluctuation) due to oxygen annealing during the formation of the ferroelectric capacitor.
[0210]
Next, a silicon oxide film layer (SiO ₂ ) 122 is deposited to 100 nm. A Pt layer 17, a PZT layer 18, and a Pt layer 19 constituting a ferroelectric capacitor are sequentially deposited thereon by sputtering. These layers are heat-treated in oxygen, and the PZT layer is crystallized to form a perovskite structure. These layers are then processed by RIE into the shape of the capacitor.
[0211]
Next, a silicon oxide film 13 is deposited on the entire surface by plasma CVD, and contact holes to the source region S and drain region D of the transistor are formed by RIE. Ti and TiN as the barrier layer 11 and Al as the wirings 22, 36 and 37 are sequentially deposited by sputtering, Al is reflowed by a heat treatment at about 400 ° C., and the contact hole is buried. Subsequently, a W metal layer 11 ′ as a barrier layer is deposited by CVD. These Ti, TiN, Al, and W layers are processed by RIE to form a first wiring layer that includes contacts with the source region S and drain region D of the transistor. The feature of this embodiment is that an opening (contact hole) formed through the insulating layers 10, 121, 122, and 13 is filled with reflowed Al.
[0212]
Next, a silicon oxide film layer 30 is deposited on the entire surface by a plasma CVD method and planarized by CMP. An opening is formed in the silicon oxide film layer 30 immediately above the drain region D of the transistor, and the corresponding W metal layer 11 ′ on the first wiring layers 36 and 37 is exposed. Subsequently, similarly to the fifth embodiment, Ti and TiN to be the barrier layer 112 and Al to be the wiring 38 are sequentially deposited by sputtering. Thereafter, Al is reflowed by a heat treatment at about 400 ° C., and the opening having a high aspect ratio formed in the silicon oxide film 30 is buried. The W metal layer 11 ′ formed on the first wiring layer functions to prevent dissolution of Al in the first wiring layer when reflowing Al in the second wiring layer. Similarly to the sixth embodiment, TiN or Ti can be used.
[0213]
Subsequently, the Ti, TiN, and Al layers are processed by RIE to form a second wiring layer. Thereafter, a silicon oxide film 39 is deposited by the CVD method to complete the semiconductor structure shown in FIG.
[0214]
Next, as an eighth embodiment of the method for manufacturing a semiconductor device of the present invention, for example, a ferroelectric film and an electrode film of a charge storage capacitor of an FRAM cell as shown in FIG. 19 or as shown in FIG. A plurality of embodiments will be described with respect to steps for realizing high density and high reliability of the high dielectric constant dielectric film and the electrode film of the charge storage capacitor of the DRAM cell.
[0215]
That is, a capacitor using a dielectric film made of a complex oxide film containing at least two or more metal elements is formed between a pair of electrodes, and an insulating oxide film and a wiring layer are further stacked on the capacitor. When manufacturing a semiconductor device
(A) The capacitor forming step includes a step of forming a first electrode, a step of forming a dielectric film, and RTA under a reduced pressure of 0.5 Torr (= 0.5 × 133.322 Pa) to 500 Torr. A step of performing a treatment (Rapid Thermal Anneal) and a step of forming a second electrode thereafter.
[0216]
(B) The capacitor forming step includes a step of forming a first electrode, a step of forming a dielectric film, a step of forming a second electrode, and a reduced pressure of 0.5 Torr to 500 Torr thereafter. And performing a RTA process below.
[0217]
(C) The capacitor forming step includes a step of forming a first electrode, a step of performing an RTA treatment under a reduced pressure of 0.5 Torr or more and 500 Torr or less, a step of forming a dielectric film, Forming a second electrode.
[0218]
(D) In any of the steps (a) to (c), a composite oxide film containing at least two kinds of metal elements is formed on the first electrode by sputtering, CVD (Chemical Vapor Deposition; It is formed by a chemical vapor deposition method or an LSMCD (Liquid Source Misted Chemical Deposition) method.
[0219]
(E) In any of the steps (a) to (c), the RTA treatment under reduced pressure is performed under an oxygen partial pressure of 0.5 Torr to 500 Torr.
[0220]
(F) In any of the steps (a) to (c), the RTA treatment under reduced pressure is performed under an ozone partial pressure of 0.5 Torr to 500 Torr.
[0221]
(G) In any of the steps (a) to (c), the RTA treatment is performed in an atmosphere having an ozone partial pressure ratio of 1% or more.
[0222]
Here, the RTA treatment refers to a heat treatment at a temperature increase rate of 10 ° C./second or more. This heat treatment rate significantly increases the crystallinity of the film. In particular, a lead-based dielectric film such as PZT can avoid generation of a low-permittivity pyrochlore phase and is an advantageous method for crystallization. However, the heat treatment by RTA has a problem that since the temperature rise rate is fast, crystallization proceeds with insufficient volatilization of the intake gas.
[0223]
In the dielectric film forming method according to the eighth embodiment, since the RTA treatment is performed under a reduced pressure of 0.5 Torr or more and 500 Torr or less, the residue taken into the deposition film even in a short crystallization process. Crystallization can proceed while eliminating gas, and a dielectric film with good crystallinity can be formed at a high density. When the dielectric film is crystallized, the electrode film is also crystallized at the same time. However, the trapped gas in the electrode film can also be eliminated by this heat treatment, and the resistance value of the electrode film can be lowered.
[0224]
RTA treatment proceeds with crystallization, but if the oxygen supply is insufficient, the dielectric film may become a semiconductor. In particular, Pb-based dielectric films such as PZT, barium titanate films, and the like are easily converted into semiconductors, and the film resistance is significantly reduced.
[0225]
As heat treatment in such a case, it is desirable to perform annealing under reduced pressure under an oxygen partial pressure of 0.5 Torr or more and 500 Torr or less. IrO ₂ And RuO ₂ , ITO, SnO ₂ If the supply of oxygen is insufficient, the resistance of the film will change drastically in the subsequent process and the characteristics will become unstable. Annealing is effective.
[0226]
Furthermore, if annealing under reduced pressure is performed under an ozone partial pressure of 0.5 Torr or more and 500 Torr or less, the leakage current of the film can be reduced, which is particularly important for forming a capacitor in a memory such as a DRAM that requires a refresh operation. Yes, power consumption can be saved.
[0227]
These RTA treatments under reduced pressure are particularly performed in the step of forming a dielectric film made of a complex oxide film containing at least two or more metal elements on the first electrode, by sputtering, CVD, or This is particularly effective when the LSMCD method is adopted. This is because when the film is formed by these film forming methods, the influence of the intake gas is inevitable.
[0228]
On the other hand, it is possible to apply a sol-gel method or a MOD method to the dielectric film forming method according to the eighth embodiment of the present invention. Since the amount of volatilization is large, if the heat treatment is performed under reduced pressure from the beginning, the surface of the film may become rough. Therefore, in these cases, it is desirable to perform a heat treatment at a temperature of 350 ° C. or higher in advance under atmospheric pressure and then perform an RTA treatment under reduced pressure as described above.
[0229]
Next, a method and effect of ozone annealing will be described. An ozone / oxygen mixed gas generated using an ozone generator is introduced into a heat treatment section heated to 100 to 400 ° C. For example, an ozone / oxygen mixed gas is introduced while the back surface of the wafer is heated to 300 ° C., and 100 mW / cm is introduced into the heat treatment portion. ² Of low pressure mercury light for 30 to 200 minutes. Mercury light has an effective wavelength of 320 nm or less.
[0230]
In this case, if heat treatment is performed in a mixed gas atmosphere having an ozone partial pressure ratio of 1% or more, oxygen vacancies existing during film formation are reduced, and leakage current can be reduced. Furthermore, if a heat treatment in oxygen at 600 ° C. or higher is added thereafter, variations in the wafer surface can be reduced, which is more effective.
[0231]
(Example 1)
FIG. 19 shows a cross-sectional structure of an FRAM cell having a capacitor formed by the manufacturing method according to the eighth embodiment of the present invention.
[0232]
19, the inter-element isolation insulating film 2 is formed on the semiconductor substrate 1 by LOCOS, and then the diffusion layer for the source S / drain D region, the gate insulating film 3, and the gate electrode portion G are formed. Thus, the MOS transistor 70 is formed. After this, using the CVD method, SiO ₂ An interlayer insulating film 71 made of is deposited.
[0233]
Next, the information storage capacitor 72 of the memory cell is formed. First, a lower electrode film made of Ti / Pt is formed on the interlayer insulating film 71 by continuous DC sputtering in 2.5 mTorr Ar.
[0234]
Next, a PZT film having a thickness of 180 nm, 210 nm, or 240 nm is formed by RF (radio frequency) sputtering in 2.5 mTorr of Ar. Thereafter, the first RTA treatment is performed at a heating rate of 100 ° C./second in oxygen at 10 Torr at 800 ° C. for 10 seconds, and then a Pt film as an upper electrode film is formed on the PZT film by DC sputtering, and then diffusion The second annealing is performed slowly at 600 ° C. using a furnace.
[0235]
Next, the laminated lower electrode film, PZT film, and upper electrode film are etched by RIE and patterned into a desired shape, whereby the capacitor 72 composed of the lower electrode 17, the dielectric film 18, and the upper electrode 19 is formed. Form. Here, in order to remove etching damage, a third annealing was slowly performed at 600 ° C. using a diffusion furnace.
[0236]
Next, an insulating film 73 is deposited by the CVD method so as to cover the capacitor 72, and one of the source S / drain D diffusion layers of the MOS transistor 70 and the upper electrode 19 and the lower electrode 17 of the capacitor 72 are formed by RIE. After the contact hole to be exposed was formed by etching, a fourth annealing was slowly performed at 600 ° C. using a diffusion furnace.
[0237]
Next, an internal wiring 74a for connecting one of the source S / drain D diffusion layers of the MOS transistor 70 and the upper electrode 19 and an internal wiring 74b serving as an extraction electrode from the lower electrode 17 are formed, and the entire element is formed. Then, a passivation film 75 is deposited. Thereafter, a contact hole is formed in the passivation film 75 by RIE, and an aluminum wiring 77 is formed through the barrier layer 76. The gate electrode portion G of the MOS transistor 70 is used as a word line, and the internal wiring 74b, the barrier layer 76, and the aluminum wiring 77 are used as plate lines.
[0238]
Here, of the four annealings described above, the first is a heat treatment for crystallization of the dielectric film, and the second is the interface state between the ferroelectric film 18 and the upper electrode 19 and the lower electrode 17 and the ferroelectric. The heat treatment is performed in the same manner as that of the body film 18, and the third and fourth times are for recovering the process damage.
[0239]
The above example is referred to as Example 1, and examples corresponding to three types of PZT films having thicknesses of 180, 210, and 240 nm are referred to as Examples 1-1, 1-2, and 1-3, respectively.
[0240]
Examples in which the following steps are changed are referred to as Examples 2 to 6, and those in which the dielectric film thickness is changed are referred to as Examples n-1, n-2, and n-3 from the thin ones. The comparative example was formed in the same manner.
[0241]
(Example 2)
The semiconductor device of Example 2 was formed by forming the information storage capacitor 72 of Example 1 as follows. First, a lower electrode film made of Ti / Pt is formed on the interlayer insulating film 71 by continuous DC sputtering in 2.5 mTorr Ar. Next, the PZT film was formed at a substrate temperature of 500 ° C. and Ar / O ₂ It is formed by RF sputtering in an atmosphere. After the Pt film was formed on the PZT film by DC sputtering, the first RTA annealing was performed at 800 ° C. for 10 seconds in oxygen at a temperature rising rate of 100 ° C./second and 10 Torr.
[0242]
(Example 3)
The semiconductor device of Example 3 was formed by forming the information storage capacitor 72 of Example 1 as follows. First, a lower electrode film made of Ti / Pt is formed on the interlayer insulating film 71 by continuous DC sputtering in 2.5 mTorr Ar. The first RTA annealing is performed at a heating rate of 100 ° C./second in oxygen at 10 Torr at 800 ° C. for 10 seconds, and then a PZT film is formed by RF sputtering in Ar at a substrate temperature of 500 ° C. and 2.5 mTorr. Thereafter, after a Pt film is formed on the PZT film by DC sputtering, the second annealing is performed slowly at 600 ° C. using a diffusion furnace.
[0243]
(Example 4)
The semiconductor device of Example 4 was formed by forming the information storage capacitor 72 of Example 1 as follows. First, Ir resinate is spin-coated on the interlayer insulating film 71 and heat-treated at 800 ° C. in an atmosphere of 760 Torr. ₂ The lower electrode film is formed. Next, the SBT film is formed using the LSMCD method in which the organic metal compound mixed raw material is atomized and deposited on the rotating substrate. Subsequently, after heat treatment at 450 ° C. in an atmosphere of 760 Torr in advance, RTA annealing was performed at a temperature increase rate of 50 ° C./second and 800 ° C. for 10 seconds in 500 Torr oxygen. Thereafter, again, Ir resinate is spin-coated on the SBT film, and heat-treated at 800 ° C. in the atmosphere of 760 Torr. ₂ The upper electrode film is formed.
[0244]
(Example 5)
The semiconductor device of Example 5 was formed by forming the information storage capacitor 72 of Example 4 as follows. First, Ir resinate is spin-coated on the interlayer insulating film 71 and heat-treated at 800 ° C. in an atmosphere of 760 Torr. ₂ The lower electrode film is formed. Next, the SBT film is formed using the LSMCD method in which the organic metal compound mixed raw material is atomized and deposited on the rotating substrate. Subsequently, after heat treatment at 450 ° C. in an atmosphere of 760 Torr in advance, RTA annealing was performed at 800 ° C. for 10 seconds in a mixed atmosphere of 5% Torr ozone 10% and oxygen 90% at a temperature rising rate of 80 ° C./second. . Thereafter, again, Ir resinate is spin-coated on the SBT film, and heat-treated at 800 ° C. in the atmosphere of 760 Torr. ₂ The upper electrode film is formed.
[0245]
(Example 6)
The semiconductor device of Example 6 was formed by forming the information storage capacitor 72 of Example 1 as follows. First, a lower electrode film made of Ti / Pt is formed on the interlayer insulating film 71 by continuous DC sputtering in 2.5 mTorr Ar. A PZT film is then formed by RF sputtering in 2.5 mTorr Ar. The first RTA annealing is performed at a heating rate of 100 ° C./second in oxygen at 10 Torr at 800 ° C. for 10 seconds, and after that, a Pt film is formed on the PZT film by DC sputtering, and then the second annealing is performed this time. Is slowly performed at 550 ° C. in a mixed atmosphere of ozone 10% and oxygen 90%.
[0246]
(Comparative Example 1)
The information storage capacitor of Example 1 was formed as follows to form the semiconductor device of Comparative Example 1. First, a lower electrode film made of Ti / Pt is formed on the interlayer insulating film by continuous DC sputtering in 2.5 mTorr Ar. A PZT film is then formed by RF sputtering in 2.5 mTorr Ar. The first RTA annealing is performed at a heating rate of 100 ° C./second in oxygen at 760 Torr at 800 ° C. for 10 seconds, and then a Pt film is formed on the PZT film by DC sputtering. Slowly at 600 ° C.
[0247]
(Comparative Example 2)
The information storage capacitor of Example 4 was formed as follows to form the semiconductor device of Comparative Example 2. First, Ir resinate is spin-coated on the interlayer insulating film, and heat-treated at 800 ° C. in an atmosphere of 760 Torr. ₂ The lower electrode film is formed. Next, a PZT film having a thickness of 180 nm is formed using the LSMCD method in which the organometallic compound mixed raw material is deposited in the form of a mist on a rotating substrate. Subsequently, after heat treatment at 450 ° C. in an atmosphere of 760 Torr, RTA annealing was performed at 800 ° C. for 10 seconds in oxygen at 760 Torr and a temperature increase rate of 50 ° C./second. Thereafter, again, Ir resinate is spin-coated on the PZT film, and heat-treated at 800 ° C. in the atmosphere of 760 Torr. ₂ The upper electrode film is formed.
[0248]
(Evaluation of Examples and Comparative Examples)
FIG. 20 shows the relationship between the film thickness (dielectric thickness) t and the reciprocal of the capacitance C (1 / C) by measuring the capacitance of the capacitors in Examples 1 to 6 and Comparative Examples 1 and 2. ing.
[0249]
The following relationship holds between the capacitance C, the dielectric constant ε of the dielectric, and the dielectric thickness t.
[0250]
C = εo × ε × S / t
Where εo is the dielectric constant of vacuum and S is the electrode area. If you rewrite this,
1 / C = k × (1 / ε) × t
However, k is a constant of 1 / (εo × S). In the actual graph,
1 / C = k × (1 / ε) × t + n
When n = 1 / C ′, a circuit in which capacitors for C ′ are connected in series is expected.
[0251]
In the example according to the eighth embodiment of the present invention, the capacitor component corresponding to the C ′ is small, and therefore, an extra low dielectric constant layer does not exist at the interface with the electrode, and it corresponds to thinning. It can be seen that a dielectric film is formed.
[0252]
On the other hand, in the comparative example, the capacitor component corresponding to C ′ is large, so that sufficient capacitance cannot be obtained, and it is not possible to cope with thinning. In order to drive the device at a low voltage, it is necessary to use it in a region where the dielectric is sufficiently saturated, that is, to make a thin film and to apply a sufficiently large electric field. Then, it cannot respond to thin film formation.
[0253]
When the cross sections of the dielectric portions of Examples 1 to 6 and Comparative Examples 1 and 2 were examined with a transmission electron microscope, a large gap corresponding to a film thickness of 1/10 to 1/5 was found at the dielectric and electrode interface of the comparative example. Although many were seen, in the Example, it was few, and it turned out that this space | gap made a part of film | membrane low density, and became the cause of the low dielectric constant layer.
[0254]
In addition, the operating speed characteristics and fatigue characteristics of each element were examined. In Example 3, the highest operating speed was achieved, and no defective bits were generated even when the write time was shortened to 140 ns. In other embodiments, if it was not set to 150 ns or more, a defective bit was generated in the reliability test. In the fourth and fifth embodiments, the number of rewrites is 10 ¹² More than once, but in other embodiments 10 ¹⁰ Bad bits appeared from the first time. 10 ⁷ In Examples 5 and 6, no defective bit was produced when the imprint characteristics were examined after being left for a long time after the fatigue test.
[0255]
(Other examples)
In the step of forming a trench type DRAM cell shown in FIG. 21, an element isolation region 81, a source S / drain D region of a MOS transistor for a transfer gate of a memory cell, and a capacitor 82 having a trench structure of the memory cell are formed on a semiconductor substrate 80. To do. When the capacitor 82 is formed, Ru of the lower electrode 83 is formed by DC sputtering, and then the BST film 84 is deposited to a thickness of 100 nm at a substrate temperature of 450 ° C. by a CVD method using an organometallic compound as a raw material source and an Ar carrier gas. Obtained as a membrane. After this, N ₂ RTA annealing was performed at 600 ° C. in a partial pressure of 450 Torr, and Ru of the upper electrode 85 was formed by DC sputtering to obtain a three-dimensional laminated structure. After that, SiO ₂ The insulating film 86 and the word lines WL and bit lines BL were formed to form a DRAM structure. In this case, a dense BST dielectric film having a dielectric constant of 250 was obtained.
[0256]
Next, an example in which the above-described FRAM is applied to an RF-ID system is shown.
[0257]
The RF-ID system is a non-contact type tag system (identifier) using radio waves, and is generally called a non-contact data carrier system. The system configuration is shown in FIG.
[0258]
The RF-ID system is composed of a host side composed of a personal computer, a controller, an antenna, and the like, and a data carrier called a transponder. The transponder has a simple configuration including a monolithic RF-ID chip in which FRAM and ASIC are integrated into one chip, and an antenna serving both for power reception and data reception / transmission.
[0259]
From the host side, commands and data are transmitted on a carrier wave as necessary. On the transponder side, necessary power is generated by the carrier wave, and information is returned to the host side for data writing, reading, and transmission. .
[0260]
The non-contact type tag does not require a battery, and can be used for management such as entry / exit of a person by reading the content stored in the FRAM in a non-contact manner using radio waves and rewriting the content. For example, a ticket gate with a non-contact tag for a commuter pass in the pocket of clothes, a non-contact tag attached to a car and running so that it is not necessary to stop at the toll gate on the highway. It is aimed at applications such as monitoring and managing parking lot entry and exit without human intervention. It can also be used to manage the behavior of livestock and migratory fish.
[0261]
FIG. 28 shows the details of the internal circuit of the transponder.
[0262]
That is, an LC circuit that detects an electromagnetic wave input from the outside, a circuit 58 that generates a signal from the electromagnetic wave detected by the LC circuit, a circuit 59 that generates a power supply voltage from the electromagnetic wave detected by the LC circuit, and a rise of the power supply voltage A plurality of memory cells including a power-on circuit 60 that detects a power-on signal and outputs a power-on signal, a ferroelectric capacitor having a ferroelectric substance between electrodes, and a MOS transistor for charge transfer; For example, the MOS transistors of the memory cells belonging to the same row are commonly connected by the same word line, and one electrode of the ferroelectric capacitor of the memory cell belonging to the same row is commonly connected by the same capacitor plate line, respectively. FRA formed by commonly connecting one terminal of MOS transistors of memory cells belonging to the same bit line through the same bit line It consists of the cell array 61 and the like.
[0263]
The present invention is not limited to the FRAM as described above, but a ferroelectric memory that is used in a small amount for a logic program storage unit in a logic LSI mounted with an FPGA (Field Programmable Gate Array) or a static RAM. It is also possible to apply to a cell formation method.
[0264]
The present invention is not limited to the case where the ferroelectric memory cell is formed on the semiconductor substrate as described above, but also when the ferroelectric memory cell is formed on the semiconductor layer on the insulating substrate such as SOI. It is possible to apply.
[0265]
Furthermore, the charge transfer switching transistor is not limited to a MOS transistor whose gate insulating film is made of an oxide, and the gate insulating film is made of nitride, nitride oxide, or a laminated structure of oxide and nitride. A MIS transistor can also be formed.
[0266]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device of the present invention, when a ferroelectric memory cell is formed, a ferroelectric capacitor is formed after embedding a contact plug layer on one end side region of the pass transistor. Since the upper electrode and the upper end of the contact plug are connected by electrode wiring, the influence of processing in a reducing atmosphere after the formation of the ferroelectric capacitor can be avoided, and the ferroelectric capacitor can be easily formed. it can.
[0267]
In addition, according to the method for manufacturing a semiconductor device of the present invention, it is possible to realize fine processing of the capacitor upper electrode (Pt or the like), and further miniaturization of the pattern of the ferroelectric memory cell.
[0268]
Therefore, according to the semiconductor device manufactured by the method for manufacturing a semiconductor device of the present invention, the reliability of the electrode wiring for connecting the capacitor upper electrode and the upper end of the contact plug is high, and the ferroelectric capacitor is miniaturized. Has a possible structure.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing an example of a planar pattern of a part of a cell array in a cell array manufacturing process for a large capacity FRAM employing a ferroelectric memory cell according to a first embodiment of the present invention;
FIG. 2 is a diagram showing a part of a planar pattern in a process following the process of FIG. 1;
FIG. 3 is a diagram showing a part of a planar pattern in a process following the process of FIG. 2;
4 is a diagram showing a part of a cross section in an example of a manufacturing process of the cell shown in FIGS. 1 to 3; FIG.
FIG. 5 is a diagram showing a part of a cross section in a step that follows the step of FIG. 5;
6 is a diagram showing a part of a cross section in a step following the step of FIG. 5. FIG.
7 is a diagram showing a part of a cross section in a step following the step of FIG. 6;
8 is a cross-sectional view showing a part of the cross section in detail by taking out part of the process in FIG. 7;
FIG. 9 is a diagram showing a part of a cross section for a manufacturing method of a modified example of the cell shown in FIGS. 4 to 8;
10 is a diagram showing a part of a cross section of a manufacturing method of a modified example of the cell shown in FIGS. 4 to 8; FIG.
FIG. 11 is a diagram showing a part of a cross section in an example of a cell array manufacturing process for a large-capacity FRAM that employs an FRAM cell according to a second embodiment of the present invention;
12 is a view showing a part of a cross section in a step following the step of FIG. 11;
13 is a view showing a part of a planar pattern of an FRAM including the FRAM cell shown in FIGS. 11 and 12. FIG.
FIG. 14 is a cross-sectional view showing the structure of an FRAM cell according to a third embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 15 is a cross-sectional view showing the structure of an FRAM cell according to a fourth embodiment of the method for manufacturing a semiconductor device of the present invention.
FIG. 16 is a cross-sectional view showing the structure of an FRAM cell according to a fifth embodiment of the method for manufacturing a semiconductor device of the present invention.
FIG. 17 is a cross-sectional view showing the structure of an FRAM cell according to a sixth embodiment of the method for manufacturing a semiconductor device of the present invention.
FIG. 18 is a cross-sectional view showing the structure of an FRAM cell according to a seventh embodiment of the method for manufacturing a semiconductor device of the present invention.
FIG. 19 is a sectional view showing the structure of an FRAM cell according to an eighth embodiment of the method for manufacturing a semiconductor device of the present invention.
FIG. 20 is a graph showing capacitor characteristics of examples and comparative examples according to the eighth embodiment.
FIG. 21 is a sectional view showing the structure of a DRAM cell according to an eighth embodiment of the method for manufacturing a semiconductor device of the present invention.
FIG. 22 is a circuit diagram showing an equivalent circuit of a ferroelectric memory cell having a one-transistor / one-capacitor configuration.
23 is a circuit diagram showing an equivalent circuit of a part of the array of ferroelectric memory cells of FIG. 22 and its peripheral circuit.
24 shows the applied electric field and the electric polarization state of the ferroelectric capacitor in order to explain the principle of the write operation of the two-transistor / two-capacitor ferroelectric memory cell using two memory cells of FIG. Figure.
FIG. 25 shows the applied electric field and electric polarization state of a ferroelectric capacitor in order to explain the principle of read operation of a two-transistor / two-capacitor ferroelectric memory cell using two memory cells of FIG. Figure.
26 is a waveform diagram showing an example of a voltage waveform applied to the plate line PL during the write operation shown in FIG. 24 and the read operation shown in FIG. 25;
FIG. 27 is a diagram showing an overall system configuration of an RF-ID system.
FIG. 28 is a diagram showing details of an internal circuit of the transponder.
[Explanation of symbols]
1 ... Semiconductor substrate,
2 ... Inter-element isolation oxide film,
3 ... Gate oxide film,
4 ... P-doped polysilicon,
5 ... WSi,
6, 7 ... Insulating film for protecting the gate electrode,
9, 10 ... insulating film,
11 ... barrier metal film,
13 ... Insulating film for planarization,
14 ... barrier metal film,
15: Capacitor contact plug,
16 ... Insulating film for cap,
17 ... lower electrode,
18 ... Ferroelectric thin film,
19 ... Upper electrode,
16a, 19a ... openings for electrode wiring connection,
20a: insulating film for embedding the upper electrode,
20 ... Insulating film for protecting the capacitor,
21 ... Barrier metal film,
22 ... electrode wiring,
23 ... Passivation film,
SDG ... active region,
D: Impurity diffusion layer (drain region),
G: Gate electrode part,
S: Impurity diffusion layer (source region),
BL ... bit line,
WL ... word line,
PL ... Plate wire

Claims (4)

A semiconductor formed by forming a capacitor using a dielectric film made of a complex oxide film containing at least two or more metal elements between a pair of electrodes, and further laminating an insulating oxide film and a wiring layer on the capacitor When manufacturing equipment
The capacitor forming step includes:
A first electrode forming step of forming a first electrode;
A dielectric film forming step of forming the dielectric film on the first electrode;
A second electrode forming step of forming a second electrode on the dielectric film;
The first electrode forming step and a dielectric film forming step between the heating rate under a reduced pressure below 0.5 × 133.322 Pa or 500 × 133.322 Pa either after the second electrode forming step of 10 A step of performing a rapid heat treatment of at least ° C / second;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
The rapid heat treatment under reduced pressure is performed in an atmosphere having an oxygen partial pressure of 0.5 × 133.322 Pa or more and 500 × 133.322 Pa or less, an ozone partial pressure, or an ozone partial pressure ratio of 1% or more. Production method.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the dielectric film is a ferroelectric film, and the capacitor is a charge storage capacitor of a memory cell of an FRAM. Production method.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the dielectric film is a high dielectric constant dielectric film, and the capacitor is a charge storage capacitor of a DRAM memory cell. Device manufacturing method.

Images