JP3714087B2 - Sample data reproducing apparatus and sample data recording / reproducing apparatus - Google Patents

Description

【００３４】
チップ０（ＳＤＲＡＭ６４，６６の一方）、１（ＳＤＲＡＭ６４，６６の他方）はそれぞれ０〜３の４バンクに構成されている。チップ０には演奏音用に０〜２３のチャンネルが均等の容量の領域に割り当てられている。隣接するチャンネル番号どうしは別々のバンクに割り当てられている。チップ１のバンク０には、小節の１発目のメトロノーム音の波形全体、サンプラーの領域が割り当てられている。バンク２，３全体にはサンプラーの領域が割り当てられている。バンク４には、サンプラー、小節の２発目以降に共用されるメトロノーム音の波形全体の領域が割り当てられている。録音・再生モード時に演奏音用の０〜２３チャンネルの領域内の音データは演奏の進行に応じて順次更新されるが、メトロノーム音およびサンプラー音は繰り返し読み出して用られるので（メトロノーム音は操作者によりメトロノーム音再生がオンに設定されているときに、操作者によって指示されたテンポで自動的に繰り返し読み出され、サンプラー音は操作者の操作に基づきレコーダＣＰＵ１４から発音が指令されるごとに繰り返し読み出される。）、１つのソング中では特に必要のない限り更新されない。つまり、メトロノーム音およびサンプラー音については、ＳＤＲＡＭ６４または６６に、再生する波形データ全体が保存されているので、再生中にＳＤＲＡＭ６４または６６への書き込みは必要なく、ＳＤＲＡＭ６４または６６からの読み出しのみ行われる。ＳＤＲＡＭ６４または６６からのメトロノーム音およびサンプラー音の読み出しは、サンプリング周期１／ｆｓごとに１サンプルずつ（複数種類のサンプラーが指定されている場合は、その種類ごとに１サンプルずつ）、演奏音の再生チャンネルの音データの読み出し処理および録音チャンネルの音データの書き込み処理と時分割で行われる。なお、サンプラー音は、操作者が予め任意のサンプラー音を任意の数だけ録音しておき、録音・再生モードでソングを指定して録音をするに先立ち、操作者が録音されているサンプラー音の中から任意のサンプラー音を選択して（最大８種類まで選択可能）、ＨＤＤ６０から該当するサンプラー音の音データを読み出して、ＳＤＲＡＭ６４，６６の任意のチャンネル（サンプラー０〜７）に書き込んでおく。そして、録音開始後の任意のタイミングで任意のチャンネルのサンプラーの発音をボタン操作等で指示することにより該当するサンプラー音が発音され、その発音タイミングおよび発音チャンネルがソング管理データに記録される。録音が終了してそのソングの再生を行うと、ソング管理データに基づき、該当するタイミングで該当するサンプラー音がＳＤＲＡＭ６４，６６から読み出されて発音される。
【００３５】
表１のチャンネル割り当てをする際の、ＳＤＲＡＭ６４，６６（一方がチップ０，他方がチップ１）のアドレスマップ例を図１１に示す。チップ０には各演奏チャンネル０〜２３にそれぞれＡ領域（１クラスタ）、Ｂ領域（１クラスタ）の合計２クラスタ分の連続したアドレス領域が割り当てられている。チップ０のバンク２の後尾にはバンク０，２に割り当てられたチャンネル用の無音領域が、またバンク３の後尾にはバンク１，３に割り当てられたチャンネル用の無音領域が、それぞれ適宜の大きさ（１〜２クラスタ程度）で割り当てられ、録音・再生モードの投入とともに、無音データがそれぞれ書き込まれて保持される。チップ１の先頭にはメトロノーム（１発目）に適宜の大きさ（１クラスタ程度）の領域が割り当てられている。チップ１の後尾にはメトロノーム（２発目以降）に適宜の大きさ（１クラスタ程度）の領域が割り当てられている。メトロノーム（１発目）、メトロノーム（２発目以降）の領域には、録音・再生モードの投入とともに、フラッシュＲＯＭ５８（図３）から読み出されたメトロノーム（１発目）、メトロノーム（２発目以降）の音データがそれぞれ保持される。チップ１の先頭および後尾の領域に挟まれた連続した中間の領域にサンプラーの領域が割り当てられている。サンプラーの領域に割り当てるサンプラーの数は操作者が任意に設定することができる（ただし、最大で０〜７の８種類、合計約８０秒）。
【００３６】
ＳＤＲＡＭ６４，６６を日立製ＨＭ５２６４１６５−Ｂ６０で構成し、該ＳＤＲＡＭ６４，６６の各バンクに図１１のようにチャンネルを割り当て、１サンプリング周期（全５１２タイムスロット）の開始から１／４の期間（０〜１２７タイムスロット）（すなわち、図６の区間Ａ）で各チャンネルのデータを１サンプルずつＳＤＲＡＭ６４，６６に書き込みあるいはＳＤＲＡＭ６４，６６から読み出す場合の、通常の録音、再生時におけるＤＲＣ６８によるＳＤＲＡＭ６４，６６の書き込み、読み出し制御シーケンスの一例を表２に示す。表２において，各記号はそれぞれ次を表す。
ＡＣＴ：選択したバンクを活性化させるコマンド。このとき、ロー（行）アドレスが指定される。
ＲＤｗＡＰ：Read with auto pre-charge（読み出しを行い、それが終了後自動的にプリチャージするコマンド）。このとき、コラム（列）アドレスが指定される。）
ＷＴｗＡＰ：Write with auto pre-charge（書き込みを行い、それが終了後自動的にプリチャージするコマンド）。このとき、コラム（列）アドレスが指定される。
Ｒ／ＷｗＡＰ：Read or write with auto pre-charge（読み出しまたは書き込みを行い、それが終了後自動的にプリチャージするコマンド）。このとき、コラム（列）アドレスが指定される。
Ｒ：読み出しモード
Ｗ：書き込みモード
【００３７】

【００３８】
表２の例では、演奏音用の０〜２３チャンネルのうちチャンネル０〜７を再生専用チャンネル、チャンネル８〜１５を録音再生兼用チャンネル、チャンネル１６〜２３を録音専用チャンネルに設定している。ただし、チャンネル８〜１５は録音のみ（ＡＬＬ ＲＥＣ）のモードでのみ録音用チャンネルとして使用できるもので、再生同時録音（ＳＹＮＣ ＤＵＢＢＩＮＧ）のモードでは再生用チャンネルとしてのみ使用することができる。表２ではチャンネル８〜１５を読み出しモードに設定した場合のこれら各チャンネル８〜１５のサンプルデータの出力タイミングをそれぞれカッコ書きで示している。また、表２において、タイムスロット１２７で読み出しを指令されたサンプラー７のデータは、区間Ａが終了後（つまり、メインＣＰＵ１４がバス権を明け渡した後）のタイムスロット１２９で出力されるが、このデータの出力にはメインＣＰＵ１４は関与しないので、該データの出力は支障なく行うことができる。なお、ミックスダウンを行うときは、チャンネル０〜１５を再生チャンネルとしてミックスダウン元のパートのトラックを割り当て、チャンネル１６，１７をミックスダウン先の録音チャンネルＭＩＸＬ，ＭＩＸＲ（左右２チャンネル）として割り当てて、チャンネル０〜１５で再生した音をＤＳＰ３８で左右２チャンネルにミックスダウンして、チャンネル１６，１７を経てＨＤＤ６０に録音する。ＨＤＤ６０に録音されたミックスダウン信号を再生するときは、左右２チャンネルのミックスダウン信号を再生専用チャンネル０〜１５のうちの任意のチャンネルに割り当てて再生する。ミックスダウン信号ＭＩＸＬ，ＭＩＸＲは２４ビットで構成されるので、それぞれ上位ワード、下位ワードに分けて伝送する。表２のシーケンスを実行する際のＳＤＲＡＭ６４，６６の制御信号のタイムチャートの一部を図１２に示す。
【００３９】
バッファメモリを構成するＳＤＲＡＭ６４，６６の、録音・再生モードのパンチイン、パンチアウト時における各バンクに対する各チャンネルの割り当て例を表３に示す。

【００４０】
表３のチャンネル割り当てをする際の、ＳＤＲＡＭ６４，６６のアドレスマップ例を図１３に示す。パンチイン、パンチアウト時は、操作者がパンチイン、パンチアウト区間を含むように適当に設定したリピート区間を自動的にリピート再生するため、演奏チャンネル０〜２３には通常の録音、再生時の倍のＡ〜Ｄ（それぞれ１クラスタずつ）の連続した４クラスタ分の領域が割り当てられている。また、チップ０のバンク２の後尾にはチップ０のバンク０，２に割り当てられたチャンネル用の無音領域が、チップ０のバンク３の後尾にはチップ０のバンク１，３に割り当てられたチャンネル用の無音領域が、チップ１のバンク０の後尾にはチップ１のバンク０，２に割り当てられたチャンネル用の無音領域が、チップ１のバンク１の後尾にはチップ１のバンク１，３に割り当てられたチャンネル用の無音領域がそれぞれ適宜の大きさ（１〜２クラス程度）で割り当てられ、パンチイン、パンチアウトモードの投入とともに無音データがそれぞれ書き込まれて保持される。また、チップ１のバンク２の後尾には、メトロノーム（１発目）に適宜の大きさ（１クラスタ程度）の領域が割り当てられ、チップ１のバンク３の後尾にはメトロノーム（２発目以降）に適宜の大きさ（１クラスタ程度）の領域が割り当てられている。メトロノーム（１発目）、メトロノーム（２発目以降）の領域には、パンチイン、パンチアウトの投入とともに、フラッシュＲＯＭ５８（図３）から読み出されたメトロノーム（１発目）、メトロノーム（２発目以降）の音データがそれぞれ保持される。なお、パンチイン、パンチアウト時はサンプラーは使用しないものとし、サンプラーは割り当てられない。ＳＤＲＡＭ６４，６６の各バンクに図１３のようにチャンネルを割り当てた場合の、パンチイン、パンチアウト時におけるＤＲＣ６８によるＳＤＲＡＭ６４，６６の制御シーケンスは、前記表２からサンプラーおよびミックスダウンに関するシーケンスを除いたものとすることができる。
【００４１】
ＳＤＲＡＭ６４，６６のチャンネル割り当てを、通常の録音、再生時は図１１のように設定し、パンチイン、パンチアウト時は図１３のように設定した場合の、該ＳＤＲＡＭ６４，６６のアドレス制御について説明する。図１０のトラックアドレスジェネレータ１００の構成例を図１に示す。トラックアドレスＲＡＭ１１８は、各チャンネルについて、現在のサンプリング周期で読み出しあるいは書き込みを行うＳＤＲＡＭ６４，６６のアドレス情報（現アドレス）を記憶するとともに、次のサンプリング周期で読み出しあるいは書き込みを行うＳＤＲＡＭ６４，６６のアドレスを計算するために必要な、ＳＤＲＡＭ６４，６６の各種アドレス情報を順次更新しながら記憶するものである（トラックアドレスＲＡＭ１１８に記憶されるＳＤＲＡＭ６４，６６のアドレス情報を以下まとめて「アドレスパラメータ」という。）。トラックアドレスＲＡＭ１１８のアドレスマップ例を図１４に示す。トラックアドレスＲＡＭ１１８には演奏チャンネル０〜２３、サンプラー０〜７、メトロノーム（１発目）、メトロノーム（２発目以降）用の領域がそれぞれ設けられている。演奏チャンネル０〜２３用の領域にはそれぞれ次の８つの領域内アドレスが割り当てられて、それぞれ１ワードずつ該当するアドレスパラメータデータを保持する。
【００４２】
▲１▼領域内アドレス０｛領域始端アドレス（ＴＳ）保持用アドレス｝：当該チャンネルに割り当てられたＳＤＲＡＭ６４，６６のアドレス領域の始端アドレス。すなわち、図１１、図１３のアドレスマップの領域Ａの先頭のアドレス。
▲２▼領域内アドレス１｛領域終端アドレス（ＴＥ）保持用アドレス｝：当該チャンネルに割り当てられたＳＤＲＡＭ６４，６６のアドレス領域の終端アドレス。すなわち、通常の録音、再生時あるいはミックスダウン時は図１１の領域Ｂの後尾のアドレス、パンチイン、パンチアウト時は図１３の領域Ｄの後尾のアドレス。▲３▼領域内アドレス２｛読み出し開始アドレス（ＲＳ）保持用アドレス｝：当該チャンネルに割り当てられたＳＤＲＡＭ６４，６６のアドレス領域の読み出しを開始するアドレス。再生開始当初にＨＤＤ６０から読み出される最初のクラスタの音データは領域Ａに格納されるので、通常は領域Ａの先頭のアドレス（領域始端アドレスＴＳ）を読み出し開始アドレスＲＳに設定してそこから読み出しを開始すればよいが、特殊なファイルでは曲の最初の部分に音楽データでない例えばサンプリング周波数等が記入されている場合があり、この部分を再生したくない場合は音楽データが開始されるアドレスを読み出し開始アドレスＲＳに設定することができる。
▲４▼領域内アドレス３｛割り込み要求発生アドレス（ＲＴ）保持用アドレス｝：当該チャンネルについて音データのＤＭＡ転送のための割り込み要求をレコーダＣＰＵ１４に向けて発生するＳＤＲＡＭ６４，６６のアドレス。ＳＤＲＡＭ６４，６６の書き込みまたは読み出しアドレスが割り込み要求発生アドレスに達するごとに該割り込み要求が発せられる。通常の録音、再生時は割り込み要求発生アドレスは各演奏チャンネル０〜２３のアドレス領域の領域Ａ，Ｂ（図１１）の各後尾のアドレスに設定され、１クラスタ分の音データが書き込まれまたは読み出されるごとに割り込み要求が発生される。無音領域を再生する場合やパンチイン、パンチアウト等のために適宜設定された区間をリピート再生する場合はこれ以外のアドレスにも割り込み要求発生アドレスＲＴが設定される。これについては後述する。
▲５▼領域内アドレス４｛現アドレス（ＣＲ）保持用アドレス｝：当該チャンネルについて現在のサンプリング周期で書き込みまたは読み出しを行うＳＤＲＡＭ６４，６６のアドレス。通常はサンプリング周期ごとに１アドレスずつインクリメントされていく。
▲６▼領域内アドレス５｛ジャンプ元アドレス（ＪＴ）保持用アドレス｝：当該チャンネルについて読み出し中にアドレスジャンプを行うＳＤＲＡＭ６４，６６のジャンプ元のアドレス。ソング管理データにより指示されるジャンプ開始時刻または操作者により指示されるジャンプ開始時刻にアドレスポインタが到達するＳＤＲＡＭ６４，６６のアドレスを、レコーダＣＰＵ１４が現アドレス（ＣＲ）を参照して演算で求めて設定する。
▲７▼領域内アドレス６｛ジャンプ先アドレス（ＪＤ）保持用アドレス｝：当該チャンネルについて読み出し中にアドレスジャンプを行うＳＤＲＡＭ６４，６６のジャンプ先のアドレス。ジャンプ先のサンプルデータが格納されるＳＤＲＡＭ６４，６６のアドレスをレコーダＣＰＵ１４が演算で求めて設定する。現アドレスＣＲの１つ先のアドレスがジャンプ元アドレスＪＴに到達すると、現アドレスについて書き込みまたは読み出しを行った後、アドレスジャンプを行い、次のサンプリング周期からはジャンプ先アドレスＪＤから読み出しが続行される。
▲８▼領域内アドレス７：未使用
【００４３】
また、トラックアドレスＲＡＭ１１８のサンプラー０〜７、メトロノーム（１発目）、メトロノーム（２発目以降）用の領域には、それぞれ次の４つの領域内アドレスが割り当てられて、それぞれ１ワードずつ該当するアドレスパラメータデータを保持する。
▲１▼領域内アドレス０｛読み出し開始アドレス（ＲＳ）保持用アドレス｝：当該チャンネルの読み出しを開始するＳＤＲＡＭ６４，６６のアドレス。
▲２▼領域内アドレス１｛読み出し終了アドレス（ＲＥ）保持用アドレス｝：当該チャンネルの読み出しを終了するＳＤＲＡＭ６４，６６のアドレス
▲３▼領域内アドレス２｛現アドレス（ＣＲ）保持用アドレス｝：当該チャンネルについて現在のサンプリング周期で書き込みまたは読み出しを行うＳＤＲＡＭ６４，６６のアドレス。サンプリング周期ごとに１アドレスずつインクリメントされていく。
▲４▼領域内アドレス４：未使用
【００４４】
なお、サンプラー０〜７およびメトロノーム（１発目）、メトロノーム（２発目以降）については、読み出し開始アドレスＲＳで指定されるＳＤＲＡＭ６４，６６のアドレスに無音データが格納され、その次のアドレスから有効な音データが格納される。そして、ＳＤＲＡＭ６４，６６のアドレスポインタは、発音開始が指示されるまで、該読み出し開始アドレスＲＳに停まっている。発音開始の指示（サンプラーの場合は操作者による発音指示操作またはソング管理データに基づくレコーダＣＰＵ１４からの発音指令、メトロノーム音については指定されたテンポに対応した周期ごとにレコーダＣＰＵ１４から発せられる発音指令）があると、アドレスポインタがサンプリング周期ごとに１ずつ進められていき、サンプラー音あるいはメトロノーム音が発音される。アドレスポインタが読み出し終了アドレスＲＥに到達すると発音を終了し、次に発音開始の指示が与えられるまで、アドレスポインタは読み出し開始アドレスＲＳに停まる。
【００４５】
本ハードディスクレコーダ１０において録音・再生モードが選択されると、レコーダＣＰＵ１４からは、ソング指定前にわかっていて予めトラックアドレスＲＡＭ１１８に格納できるアドレスパラメータのデータとして、演奏チャンネル０〜２３の領域始端アドレスＴＳ、領域終端アドレスＴＥ、メトロノーム（１発目）、メトロノーム（２発目以降）の読み出し開始アドレスＲＳ、読み出し終了アドレスＲＥ等の各データが、それらを格納するトラックアドレスＲＡＭ１１８のアドレス情報とともに送出される。レコーダＣＰＵ１４は、送出したアドレスパラメータのデータおよびトラックアドレスＲＡＭ１１８のアドレス情報を、自身のクロックで図１のレジスタ１２０，１２２にそれぞれ書き込む。レジスタ１２０，１２２に書き込まれた情報は、ＤＲＣ６８が自身のクロックで読み出して、セレクタ１２４，１２６を介してトラックアドレスＲＡＭ１１８に転送される。これにより、各演奏チャンネル０〜２３の領域始端アドレスＴＳ、領域終端アドレスＴＥおよびメトロノーム（１発目）、メトロノーム（２発目以降）の読み出し開始アドレスＲＳ、読み出し終了アドレスＲＥ等の情報がトラックアドレスＲＡＭ１１８のそれぞれ割り当てられたアドレスに書き込まれる。
【００４６】
続いてソングが指定されると、ＨＤＤ６０から読み出されるソング管理データに基づき、レコーダＣＰＵ１４からは演奏チャンネル０〜２３のうち再生が指示されたチャンネルの読み出し開始アドレスＲＳ、最初の割り込み要求発生アドレスＲＴ、各サンプラーの読み出し開始アドレスＲＳ、読み出し終了アドレスＲＥ等のデータが、それらを格納するトラックアドレスＲＡＭ１１８のアドレス情報とともに送出され、レジスタ１２０，１２２およびセレクタ１２４，１２６を介してトラックアドレスＲＡＭ１１８に入力され、これら各アドレスパラメータデータがトラックアドレスＲＡＭ１１８のアドレス情報で指示されたアドレスにそれぞれ書き込まれる。ジャンプ元アドレスＪＴおよびジャンプ先アドレスＪＤのデータは、ソング管理データに基づき、アドレスジャンプを発生させる時刻の直前にレコーダＣＰＵ１４からそれらを格納するトラックアドレスＲＡＭ１１８のアドレス情報とともに送出され、レジスタ１２０，１２２およびセレクタ１２４，１２６を介してトラックアドレスＲＡＭ１１８の該当するアドレスに保持される。なお、録音・再生モードにおいてパンチイン、パンチアウトが指示されると、演奏チャンネル０〜２３およびメトロノーム（１発目）、メトロノーム（２発目以降）に割り当てられるＳＤＲＡＭ６４，６６のアドレス領域を前記図１３に示すように変更する必要があるので、レコーダＣＰＵ１４からは各演奏チャンネル０〜２３の領域始端アドレスＴＳおよび領域終端アドレスＴＥのデータがそれらを格納するトラックアドレスＲＡＭ１１８のアドレス情報とともに送出され、レジスタ１２０，１２２およびセレクタ１２４，１２６を介してトラックアドレスＲＡＭ１１８に送られ、トラックアドレスＲＡＭ１１８の該当するアドレスに書き込まれて、該アドレス内のデータが更新される。
【００４７】
録音、再生が行われている際には、レコーダＣＰＵ１４からは演奏チャンネル０〜２３のうち再生が指示されたチャンネルについて、割り込み要求発生アドレスＲＴ、ジャンプ元アドレスＪＴ、ジャンプ先アドレスＪＤが、それらを格納するトラックアドレスＲＡＭ１１８の情報とともに、該割り込みあるいは該アドレスジャンプを発生させる直前の適宜の時点で送出され（録音が指示されたチャンネルについては、割り込み要求発生アドレスＲＴに関する情報のみ送出される。）、レジスタ１２０，１２２にそれぞれ書き込まれる。セレクタ１２４，１２６は、毎サンプリング周期で、５１２分割クロックの８ｎ＋４／０〜５１１（ｎ＝０，１，２，…，６３）のタイミング（すなわち８クロックに１回のタイミング）ごとに入力Ａ側を選択し、該レジスタ１２０，１２２に書き込まれているデータを読み出す。トラックアドレスＲＡＭ１１８はこの読み出しタイミングごとに書き込みモードに切り換えられる。その結果、レジスタ１２０に保持されたアドレスパラメータデータは、レジスタ１２２に保持されたデータで指示されるトラックアドレスＲＡＭ１１８のアドレスに格納される。このようにして、録音、再生が行われている際に、トラックアドレスＲＡＭ１１８内の割り込み要求発生アドレスＲＴ、ジャンプ元アドレスＪＴ、ジャンプ先アドレスＪＤの各アドレスパラメータデータがその都度必要な内容に更新される。なお、ジャンプ終了後は、次のジャンプをすぐに発生させる必要がない限り、レコーダＣＰＵ１４からはジャンプ元アドレスＪＴ、ジャンプ先アドレスＪＤのアドレスパラメータデータとして、当該チャンネルの領域外のアドレス情報が送出されて、トラックアドレスＲＡＭ１１８の該当するアドレスに格納される。当該チャンネルの領域外のアドレスであるので、アドレスポインタのインクリメント動作でそのアドレスに到達することはなく、したがってアドレスジャンプは発生しない。次のジャンプが近づくと、レコーダＣＰＵ１４からそのジャンプを行わせるための有効なジャンプ元アドレスＪＴ、ジャンプ先アドレスＪＤのパラメータデータが送出されて、トラックアドレスＲＡＭ１１８の該当するアドレスに格納される。なお、ＤＭＡ転送が行われている間は、レコーダＣＰＵ１４がバス権を取得するサンプリング周期の開始から１／４の区間でのみレジスタ１２０，１２２に対するデータの書き込みが行われることになるが、レコーダＣＰＵ１４はその区間だけ使っても、更新が必要なトラックアドレスＲＡＭ１１８のアドレスパラメータデータおよび該データを格納するトラックアドレスＲＡＭ１１８のアドレス情報を、その都度遅滞なくレジスタ１２０，１２２に書き込むことができる。なお、トラックアドレスＲＡＭ１１８の各チャンネルの現アドレスＣＲ保持用アドレスには、後述するように、図１のアドレス演算回路１３４において演算で求められた値が格納される。
【００４８】
図１において、ＳＤＲＡＭ読み書き用アドレス発生回路１２８は、録音・再生モードにおいて、毎サンプリング周期の開始から１／４の区間で各チャンネルの１サンプルの音データをＳＤＲＡＭ６４，６６から時分割で読み出しあるいはＳＤＲＡＭ６４，６６に書き込むために、トラックアドレスＲＡＭ１１８の現アドレスＣＲが記憶されているアドレスの情報を前記表２のタイムスロットで規定されるタイミングに従って、録音あるいは再生を指示されたチャンネルごとに発生する。計算用アドレスパラメータ読み出し用アドレス発生回路１３０は、録音・再生モードにおいて、毎サンプリング周期の残り３／４の区間で、各チャンネルの次のサンプルのデータの読み出しあるいは書き込みを行うＳＤＲＡＭ６４，６６のアドレスを各チャンネルごとに時分割で計算するために、トラックアドレスＲＡＭ１１８から各チャンネルのアドレスパラメータを読み出すための該トラックアドレスＲＡＭ１１８のアドレス情報を、５１２分割クロックに同期して、予め規定されたタイミングに従って時分割で発生する。両アドレス発生回路１２８，１３０から発生されるトラックアドレスＲＡＭ１１８のアドレス情報はセレクタ１３２に入力され、毎サンプリング周期の開始から１／４の区間ではＳＤＲＡＭ読み書き用アドレス発生回路１２８の出力アドレス情報が選択され、残りの３／４の区間では計算用アドレスパラメータ読み出し用アドレス発生回路１３０の出力アドレスが選択される。
【００４９】
セレクタ１３２で選択されたアドレス情報は、レジスタ１２０，１２２のデータをトラックアドレスＲＡＭ１１８に書き込む５１２分割クロックの８クロックごとのタイミング｛８ｎ＋４／０〜５１１（ｎ＝０，１，２，…，６３）のタイミング｝を除いた区間でセレクタ１２４から出力され、トラックアドレスＲＡＭ１１８のアドレス端子に入力され、トラックアドレスＲＡＭ１１８の該当するアドレスから該当するパラメータデータが読み出される。なお、レジスタ１２０，１２２のデータをトラックアドレスＲＡＭ１１８に書き込むタイミングでは、アドレス発生回路１２８，１３０から有効なデータが発生されないように、５１２分割クロックに同期した該アドレス発生回路１２８，１３０のデータ発生シーケンスが設定されている。毎サンプリング周期の開始から１／４の区間でトラックアドレスＲＡＭ１１８から読み出される各チャンネルの現アドレスＣＲは、ＳＤＲＡＭ６４，６６に送られ、その書き込みまたは読み出しアドレスとして用いられる。また、該現アドレスＣＲは、レコーダＣＰＵ１４に送られ、レコーダＣＰＵ１４に各チャンネルの現アドレスＣＲが通知される。
【００５０】
アドレス演算回路１３４は、トラックアドレスＲＡＭ１１８に格納されているアドレスパラメータに基づき、毎サンプリング周期の残り３／４の区間で、各チャンネルの次のサンプルのデータの読み出しあるいは書き込みを行うＳＤＲＡＭ６４，６６のアドレス（次のサンプリング周期の現アドレスＣＲ）を、５１２分割を動作クロックとして用いて時分割で計算する。該演算を行うために、各チャンネルに割り当てられたアドレス演算回路１３４の使用時間の分割例を図１５に示す。各演算チャンネル０〜２３，サンプラー０〜７，メトロノーム（１発目）、メトロノーム（２発目以降）は、それぞれに割り当てられた時間内でアドレス演算回路１３４を専有して、次のサンプリング周期の現アドレスＣＲを計算し、トラックアドレスＲＡＭ１１８の該当するアドレスに格納する。演算するチャンネルの順序は、例えば前記図１４に示されたトラックアドレスＲＡＭ１１８のアドレス配列と同じ順序とすることができる。
【００５１】
図１のアドレス演算回路１３４内の構成について説明する。セレクタ１３６はトラックアドレスＲＡＭ１１８の書き込みタイミング（５１２分割クロックの８クロックごとに１クロック分）を除いたタイミングで該トラックアドレスＲＡＭ１１８から時分割で読み出される現在演算を行っているチャンネルの各アドレスパラメータまたはレジスタ１３８（レジスタＢ）のデータを選択する。選択されたデータはレジスタ１４０（レジスタＡ）に書き込まれる。レジスタＡに書き込まれたデータはセレクタ１２６およびＡＬＵ（演算部）１４２に送出される。ＡＬＵ１４２はレジスタＡのデータおよびレジスタＢのデータを用いて適宜の演算を行い、その結果に応じてレジスタＡのデータ書き込み、計算用アドレスパラメータ読み出し用アドレス発生回路１３０からのアドレス情報の発生、ＤＭＡ転送のための割り込み要求発生の各制御を行う。ＡＬＵ１４２の計算は必要に応じてＡＣＣ（アキュムレータ）１４４に保持される。
【００５２】
アドレス演算回路１３４における１つの演奏チャンネル（再生チャンネル）のアドレス計算手順を説明する。図１６は、再生操作（または再生同時録音操作）がされて再生が起動した時の最初のサンプリング周期で行われる計算である。再生操作がされると（Ｓ１）、トラックアドレスＲＡＭ１１８から、当該再生チャンネルの読み出し開始アドレスＲＳが読み出され（Ｓ２）、セレクタ１３６、レジスタＡ、セレクタ１２６を介して、トラックアドレスＲＡＭ１１８の当該再生チャンネルの現アドレスＣＲ保持用アドレスに格納される（Ｓ３）。図１７は、その次のサンプリング周期から停止操作がされるまでの間にサンプリング周期ごとに繰り返される計算である。トラックアドレスＲＡＭ１１８から現アドレスＣＲを読み出して、レジスタＡに書き込む（Ｓ１０）。ＡＬＵ１４２でレジスタＡのデータ（現アドレスＣＲ）＋１を計算して、計算結果をＡＣＣ１４４に格納する（Ｓ１１）。トラックアドレスＲＡＭ１１８から割り込み要求発生アドレスＲＴを読み出して、レジスタＡへ書き込む。これを並行してＡＣＣ１４４のデータ（現アドレスＣＲ＋１）をレジスタＢへ書き込む。これと並行して、ＡＬＵ１４２で｛レジスタＡのデータ（割り込み要求アドレスＲＴ）｝−｛レジスタＢのデータ（現アドレスＣＲ＋１）｝を計算する。レジスタＡのデータ＝レジスタＢのデータであれば、ＤＭＡ転送のための割り込みを発生する（Ｓ１２）。トラックアドレスＲＡＭ１１８からジャンプ元アドレスＪＴを読み出して、レジスタＡへ書き込む。これと並行して、ＡＬＵ１４２で｛レジスタＡのデータ（ジャンプ元アドレスＪＴ）｝−｛レジスタＢのデータ（現アドレスＣＲ＋１）｝を計算する（Ｓ１３）。トラックアドレスＲＡＭ１１８から領域終端アドレスＴＥを読み出して、レジスタＡへ書き込む。これと並行して、ＡＬＵ１４２で｛レジスタＡのデータ（領域終端アドレスＴＥ）｝−｛レジスタＢのデータ（現アドレスＣＲ＋１）｝を計算する（Ｓ１４）。
【００５３】
ステップＳ１３の計算結果が｛レジスタＡのデータ（ジャンプ元アドレスＪＴ）｝＝｛レジスタＢのデータ（現アドレスＣＲ＋１）｝の場合は、トラックアドレスＲＡＭ１１８からジャンプ先アドレスＪＤを読み出して、レジスタＡへ書き込む。ステップＳ１４の計算結果が｛レジスタＡのデータ（領域終端アドレスＴＥ）｝＜｛レジスタＢのデータ（現アドレスＣＲ＋１）｝の場合は、トラックアドレスＲＡＭ１１８から領域始端アドレスＴＳを読み出してレジスタＡに書き込む。計算結果がそれ以外の場合はレジスタＢのデータ（現アドレスＣＲ＋１）をレジスタＡに書き込む（Ｓ１５）。そして、これら計算結果に応じてレジスタＡに書き込まれたデータをトラックアドレスＲＡＭ１１８の該当チャンネルの現アドレスＣＲ保持用アドレスに書き込む（Ｓ１６）。その結果、次のサンプリング周期では、この現アドレスＣＲ保持用アドレスに書き込まれたＳＤＲＡＭ６４，６６のアドレスについてサンプルデータの書き込みまたはサンプルデータの読み出しが行われる。
【００５４】
録音チャンネルについても、アドレス演算回路１３４で同様の計算が行われる。すなわち、録音操作（または再生同時録音操作）がされて、録音が起動した時の最初のサンプリング周期でトラックアドレスＲＡＭ１１８から領域始端アドレスＴＳが読み出されて、該トラックアドレスＲＡＭ１１８の現アドレスＣＲ保持用アドレスに格納され、次のサンプリング周期で該現アドレスＣＲで指示されるＳＤＲＡＭ６４，６６のアドレスにサンプルデータの書き込みが行なわれ、以後サンプリング周期ごとに現アドレスＣＲが１ずつインクリメントされていく。その途中で割り込み要求アドレスに一致すると、ＤＭＡ転送のための割り込み要求が発生される。現アドレスＣＲが領域終端アドレスＴＥに到達すると、次のサンプリング周期では領域始端アドレスＴＳが現アドレスＣＲとして設定され、以後アドレス循環が繰り返される。録音チャンネルについてはアドレスジャンプは行われない。
【００５５】
また、サンプラー０〜７については、再生操作（または再生同期録音操作）がされて再生が起動されると、最初のサンプリング周期でトラックアドレスＲＡＭ１１８のサンプラー０〜７の読み出し開始アドレスＲＳが読み出されて、該トラックアドレスＲＡＭ１１８の該当チャンネルの現アドレスＣＲ保持用アドレスに格納され、操作者によりサンプラー発音操作がされるまでまたはソング管理データに基づきレコーダＣＰＵ１４から発音指令が発せられるまでその状態が保持される。ＳＤＲＡＭ６４，６６のサンプラー０〜７の読み出し開始アドレスＲＳには無音データが格納されているので、この状態では発音されない。操作者が任意のサンプラーについて発音操作をするとまたはソング管理データに基づきレコーダＣＰＵ１４から発音指令が発せられると、該当するサンプラーについてサンプリング周期ごとに現アドレスＣＲが１ずつインクリメントされて、該当するサンプラー音が発音される。現アドレスＣＲが読み出し終了アドレスＲＥに到達すると、次のサンプリング周期以降トラックアドレスＲＡＭ１１８の現アドレスＣＲ保持用アドレスには読み出し開始アドレスＲＳが保持されて、次にそのサンプラーについて発音操作がされるまでまたはソング管理データに基づきレコーダＣＰＵ１４から発音指令が発せられるまで、そのサンプラー音は発音されない。
また、メトロノーム（１発目）、メトロノーム（２発目以降）については、録音・再生モードの投入によってトラックアドレスＲＡＭ１１８からメトロノーム（１発目）、メトロノーム（２発目以降）の読み出し開始アドレスＲＳが読み出されて、該トラックアドレスＲＡＭ１１８のメトロノーム（１発目）、メトロノーム（２発目以降）の現アドレスＣＲ保持用アドレスに格納されて、操作者によりメトロノーム音の発音指示操作がされるまで、その状態が保持される。ＳＤＲＡＭ６４，６６のメトロノーム（１発目）、メトロノーム（２発目以降）の読み出し開始アドレスＲＳには無音データが格納されているので、この状態では発音されない。操作者がメトロノーム音の発音指示操作をすると、レコーダＣＰＵ１４からメトロノーム（１発目）の発音が指令され、メトロノーム（１発目）についてサンプリング周期ごとに現アドレスＣＲが１ずつインクリメントされて、小節の１拍目のメトロノーム音が発音される。現アドレスＣＲが読み出し終了アドレスＲＥに到達すると、次のサンプリング周期以降トラックアドレスＲＡＭ１１８の現アドレスＣＲ保持用アドレスには読み出し開始アドレスＲＳが保持されて発音が停止される。小節の２拍目のタイミングに達すると、レコーダＣＰＵ１４からメトロノーム（２発目以降）の発音が指令され、メトロノーム（２発目以降）についてサンプリング周期ごとに現アドレスが１ずつインクリメントされて、小節の２拍目のメトロノーム音が発音される。現アドレスＣＲが読み出し終了アドレスＲＥに到達すると、次のサンプリング周期以降トラックアドレスＲＡＭ１１８の現アドレスＣＲ保持用アドレスには読み出し開始アドレスＲＳが保持されて発音が停止される。メトロノーム（２発目以降）は該小節内で、曲の拍子に応じて必要な数だけ発音が繰り返し指令されて、発音が繰り返される。次の小節以降もメトロノーム音（１発目）、メトロノーム（２発目以降）、…が繰り返し発音される。
【００５６】
なお、チャンネル数が多くアドレス演算回路１３４で１サンプリング周期内に全チャンネルのアドレス計算ができない場合には、トラックアドレスＲＡＭ１１８およびアドレス演算回路１３４を複数組並列に設けて、チャンネルを振り分けて計算するかあるいはアドレス演算回路１３４の動作クロック周波数を上げて計算速度を速めるようにすればよい。
【００５７】
トラックアドレスジェネレータ１００によるＳＤＲＡＭ６４，６６のアドレス制御例について説明する。図１８は通常の録音、再生時の１つの演奏チャンネル（再生チャンネル）についてのＳＤＲＡＭ６４または６６のアドレスポインタの移動を示したものである。この例ではアドレスジャンプは含まれていない。当該チャンネルには、ＳＤＲＡＭ６４または６６のＡ領域、Ｂ領域の連続した２クラスタ分の音データを格納するメモリ空間（アドレス領域）が割り当てられ、現アドレスＣＲに相当する読み出しアドレスポインタがサンプリング周期ごとに１アドレスずつインクリメントされていく。Ａ領域の先頭に領域始端アドレスＴＳが設定され、Ｂ領域の後尾に領域終端アドレスＴＥが設定されている。また、この例では、読み出し開始アドレスＲＳが領域始端アドレスＴＳとは別のアドレスに設定されている。割り込み要求発生アドレスＲＴはＡ領域、Ｂ領域のうちアドレスポインタが存在する領域の後尾のアドレスに交互に設定される。
【００５８】
選択されたソングについて再生（または録音同時再生）が指示されると、ＨＤＤ６０から各再生チャンネルの最初のクラスタの音データが読み出されて、ＤＭＡ転送でＳＤＲＡＭ６４，６６の各再生チャンネルに割り当てられた領域のＡ領域に格納され、読み出し開始アドレスＲＳからサンプリング周期ごとにアドレスポインタが１アドレスずつ進められて、該当する音データが読み出されて再生が行われる。アドレスポインタがＡ領域を移動している間に次のクラスタの音データがＨＤＤ６０から読み出されて、Ｂ領域に格納される。アドレスポインタがＡ領域を移動している際には、割り込み要求発生アドレスＲＴはＡ領域の後尾のアドレスに設定される。アドレスポインタがＡ領域を移動中に、Ｂ領域のＤＭＡ転送による音データの書き込みは終了する。アドレスポインタがＡ領域の後尾のアドレスに到達すると、割り込み要求が発生される。この割り込み要求はレコーダＣＰＵ１４に通知され、ＤＭＡ転送が起動されてＨＤＤ６０からさらに次のクラスタの音データが読み出され、Ａ領域にＤＭＡ転送で書き込まれる。アドレスポインタはＡ領域の後尾に達した後も引き続きＢ領域の先頭アドレスからサンプリング周期ごとに１アドレスずつ進められて、音データは途切れることなく再生される。アドレスポインタがＢ領域に入ると、割り込み要求発生アドレスＲＴはＢ領域の後尾のアドレスに変更される。アドレスポインタが該Ｂ領域を移動中に、Ａ領域のＤＭＡ転送による音データの書き込みは終了する。アドレスポインタは、Ｂ領域の後尾のアドレスに到達すると、次のサンプリング周期ではＡ領域の先頭のアドレスに戻され、さらにサンプリング周期ごとに１アドレスずつインクリメントされていき、音データは途切れることなく再生される。アドレスポインタがＡ領域を移動中にＢ領域のＤＭＡ転送による音データの書き込みが行われる。アドレスポインタがＡ領域を移動中は割り込み要求発生アドレスＲＴはＡ領域の後尾のアドレスに設定される。以上のようにして、再生が停止されるまでアドレスポインタはＡ領域の先頭からＢ領域の後尾までの区間を繰り返し移動する。
【００５９】
なお、録音が指示された演奏チャンネルについては、録音（または録音同時再生）の開始が指示されると、書き込みアドレスポインタが領域始端アドレスＴＳからサンプリング周期ごとに１アドレスずつ進められ、入力されるサンプリングデータが１サンプルずつＡ領域に格納されていく。このとき、割り込み要求発生アドレスＲＴはＡ領域の後尾に設定される。アドレスポインタが該割り込み要求発生アドレスＲＴに到達すると、割り込み要求が発生され、ＤＭＡ転送が起動されて、Ａ領域に蓄積された１クラスタ分の音データがＨＤＤ６０にＤＭＡ転送されて記録される。アドレスポインタはＡ領域の後尾に達した後も引き続きＢ領域の先頭アドレスからサンプリング周期ごとに１アドレスずつ進められて、入力される音データはＢ領域に格納されていく。このとき、割り込み要求発生アドレスＲＴはＢ領域の後尾に設定される。アドレスポインタが該割り込み要求発生アドレスＲＴに到達すると、割り込み要求が発生され、ＤＭＡ転送が起動されて、Ｂ領域に蓄積された１クラスタ分の音データがＨＤＤ６０に転送されて記録される。アドレスポインタはＡ領域の先頭に戻されて、サンプリング周期ごとに１アドレスずつ進められる。録音または再生同時録音が停止されるまで以上の動作が繰り返されて、入力される音データは１クラスタずつＨＤＤ６０に記録される。
【００６０】
次に、無音区間を設定して録音した場合のアドレス制御例について説明する。ここでは、図１９に示すように、ある演奏チャンネルについて時刻ｔ１〜ｔ２（ｔ１，ｔ２は録音開始からの経過時間）の区間に無音区間が設定されているものとする。ｍ１〜ｍ６はＨＤＤ６０に記録されているそれぞれ１クラスタ分の音データである。録音中に時刻ｔ１で無音区間の開始が指示されると、その時点で録音は休止され、その直前に作成されていた音データｍ３のクラスタ（そのクラスタの時刻ｔ１以降には無効な音データが作成される）のデータがＨＤＤ６０に記録された後は、そのチャンネルについてのＨＤＤ６０への音データの記録は休止される。時刻ｔ２に無音区間の終了が指示されると録音が再開され、音データｍ４，ｍ５，…が１クラスタずつ作成されてＨＤＤ６０に記録される。録音を終了して保存操作をすると、ソング管理データにそのパートの演奏の時刻ｔ１〜ｔ２が無音区間であることが記録される。
【００６１】
図１９のように無音区間を含んで録音されたパートを再生するときのアドレスジェネレータ１００によるＳＤＲＡＭ６４，６６のアドレス制御例を図２０の手順図に従って説明する。（ｉ）はＳＤＲＡＭ６４または６６の領域Ａに格納された音データｍ１を読み出している状態、（ii）はそれに続いて領域Ｂに格納された音データｍ２を読み出している状態である。音データｍ２を読み出している間に領域Ａが音データｍ３に書き換えられ、時刻ｔ１に相当するアドレスがジャンプ元アドレスＪＴとして設定され、無音領域の先頭のアドレスがジャンプ先アドレスＪＤとして設定される。アドレスポインタＡＰが領域Ｂの後尾のアドレスに達すると、(iii) のようにアドレスポインタＡＰが領域Ａに戻されて、その先頭のアドレスから再び移動していく。また、割り込み要求発生アドレスＲＴがジャンプ元アドレスＪＴと同じアドレスに設定される。アドレスポインタＡＰはジャンプ元アドレスＪＴに到達すると、ジャンプ先アドレスＪＤにジャンプし、（iv）に示すようにジャンプ先アドレスＪＤからサンプリング周期ごとに１アドレスずつ移動していく。これにより当該チャンネルについて無音が再生される。また、アドレスポインタＡＰがジャンプ元アドレスＪＴで割り込み要求発生アドレスＲＴに到達することにより、割り込み要求が発生され、無音再生されている間に領域Ｂが音データｍ４に書き換えられ、領域Ａが音データｍ５に書き換えられる。無音区間の終了時刻ｔ２の直前まで、無音区間の後尾のアドレスがシャンプ元アドレスＪＴ、該無音区間の先頭のアドレスがジャンプ先アドレスＪＤに設定され、アドレスポインタＡＰは無音領域を循環して、無音が再生される。この間ＨＤＤ６０からの当該チャンネルの音データの読み出しは休止される。無音区間の終了時刻ｔ２の直前に達すると、（ｖ）に示すように、無音区間の終了時刻ｔ２に相当する無音領域のアドレスがジャンプ元アドレスＪＴとして設定され、領域Ｂの先頭のアドレスがジャンプ先アドレスＪＤとして設定される。アドレスポインタＡＰは無音領域のジャンプ元アドレスＪＴに到達すると、（vi）に示すようにジャンプ先アドレスＪＤにジャンプし、領域Ｂの先頭から音データｍ４の読み出しを再開する。これにより、無音区間は終了し、当該チャンネルの演奏音が再生される。また、領域Ｂの後尾の領域終端アドレスＴＥが割り込み要求発生アドレスＲＴとして設定される。アドレスポインタＡＰは領域終端アドレスＴＥに到達すると、(vii) に示すように領域Ａに戻されて、その先頭のアドレスから再び移動していき、音データｍ５が読み出されて再生される。また、割り込み要求が発生されて、領域Ｂが音データｍ６に書き替えられ、音データｍ５の読み出し終了後に音データｍ６が読み出されて再生される。
【００６２】
次に、リピート再生する場合のアドレス制御例について説明する。ここでは、図２１に示すように、録音されているソングのｔ３〜ｔ４の区間をリピート再生し、この区間内の時刻ｔ５〜ｔ６でパンチイン、パンチアウトを行うものとする。ｍ１〜ｍ６はそれぞれ１クラスタずつの音データである。リピート再生の開始時刻ｔ３は音データｍ１の途中の時刻であり、リピート再生の終了時刻ｔ４は音データｍ６の途中の時刻である。図２１のようにリピート再生する場合のアドレスジェネレータ１００によるＳＤＲＡＭ６４，６６のアドレス制御例を図２２の手順図に従って説明する。録音・再生モードにおいてパンチイン、パンチアウトモードが選択されると、前記図１３で示したように、各演奏チャンネル０〜２３にＳＤＲＡＭ６４，６６の４クラスタ分の領域Ａ〜Ｄが割り当てられる。操作者の操作によりリピート区間ｔ３〜ｔ４およびパンチイン、パンチアウト区間ｔ５〜ｔ６が指示されると、ＨＤＤ６０が読み出されて、図２２の（ｉ）に示すように、時刻ｔ３が含まれるクラスタの音データｍ１が領域Ａに格納され、時刻ｔ４が含まれるクラスタの音データｍ６が領域Ｄに格納される。これらリピート区間の両端の音データｍ１，ｍ６はリピート再生を行っている間書き換えられない。領域Ｂ，Ｃには、最初に（ｉ）に示すように、音データｍ２，ｍ３がそれぞれ格納される。領域Ａの先頭アドレスに領域始端アドレスＴＳ、領域Ａの時刻ｔ３に相当するアドレスに読み出し開始アドレスＲＳ、領域Ａの後尾にジャンプ先アドレスＪＤ、領域Ｂの後尾に割り込み要求発生アドレスＲＴ、領域Ｃの後尾にジャンプ元アドレスＪＴ、領域Ｄの後尾に領域終端アドレスＴＥがそれぞれ設定される。
【００６３】
リピート再生開始が指示されると、（ii）に示すように、アドレスポインタＡＰが読み出し開始アドレスＲＳからサンプリング周期ごとに１アドレスずつ進行していき、音データｍ１のうち時刻ｔ３以降の音データが読み出されて再生される。アドレスポインタＡＰが領域Ａの後尾アドレスに到達すると、(iii) に示すように、領域Ｂの音データｍ２がそのまま続けて再生される。音データｍ２を再生している途中の時刻ｔ５に到達すると、パンチイン、パンチアウトが指示されたチャンネルが録音モードに切り換えられて、パンチインが実行される。アドレスポインタＡＰが領域Ｂの後尾アドレスに到達すると、割り込み要求が発生し、ＨＤＤ６０から音データｍ４が読み出され、（iv）に示すように、領域Ｂが該音データｍ４で書き換えられる。アドレスポインタＡＰはそのまま領域Ｂを移動して音データｍ３の再生および入力音の録音が続行される。割り込み要求発生アドレスＲＴは領域Ｃの後尾アドレスに変更される。アドレスポインタＡＰが領域Ｃの後尾アドレスに到達すると、ジャンプが発生し、（ｖ）に示すようにアドレスポインタＡＰが領域Ｂの先頭アドレスに戻されて、音データｍ４の読み出しが行われる。また、割り込み要求が発生されて、ＨＤＤ６０から音データｍ５が読み出され、領域Ｃが該音データｍ５で書き換えられる。割り込み要求発生アドレスＲＴは、領域Ｂの後尾アドレスに設定される。アドレスポインタＡＰが領域Ｂの後尾アドレスに到達すると、割り込み要求が発生され、（vi）に示すように、領域Ｂが音データｍ２で書き換えられる。アドレスポインタＡＰはそのまま領域Ｃを移動し、音データｍ５の再生が行われる。割り込み要求発生アドレスＲＴは領域Ｃの後尾アドレスに変更される。また、領域Ｄの時刻ｔ４に相当するアドレスがジャンプ元アドレスＪＴ、領域Ａの時刻ｔ３に相当するアドレスがジャンプ先アドレスＪＤとして設定される。音データｍ５を再生している途中の時刻ｔ６に到達すると、パンチイン、パンチアウトが指示されたチャンネルが再生モードに戻されて、パンチアウトが実行される。アドレスポインタＡＰが領域Ｃの後尾アドレスに到達すると、割り込み要求が発生し、(vii) に示すように、領域Ｃが音データｍ３で書き換えられる。アドレスポインタＡＰはそのまま領域Ｄを移動し、音データｍ６の再生が行われる。割り込み要求発生アドレスＲＴは領域Ｂの後尾アドレスに変更される。アドレスポインタＡＰがリピート区間の終了時刻ｔ４に相当するアドレスに到達すると、ジャンプが発生し、(viii)に示すように、アドレスポインタＡＰが領域Ａのリピート区間の開始時刻ｔ３に相当するアドレスに戻され、そこから再び再生が行われて、以上のリピート再生およびパンチイン、パンチアウト動作が繰り返される。なお、時刻ｔ３に相当するアドレスから再生を再開する前にわずかな無音時間を形成して、リピート区間の開始位置に戻ったことが容易に認識されるようにしてもよい。
【００６４】
最後に、図１０のＤＭＡアドレスジェネレータ１０２による、ＤＭＡ転送におけるＳＤＲＡＭ６４，６６の書き込み、読み出しアドレス制御について説明する。１つのチャンネルについてのＤＭＡアドレスジェネレータ１０２の構成例を図２３に示す。ＤＭＡアドレスジェネレータ１０２はカウンタ１４６で構成される。ＤＭＡ転送のための割り込み要求が発生されると、レコーダＣＰＵ１４はＳＤＲＡＭ６４，６６の該当チャンネルの領域Ａ，Ｂ（リピート再生の場合は領域Ｂ，Ｃ）のうち、今回ＤＭＡ転送を行う側の領域の先頭アドレスをカウンタ１４６に設定する。カウンタ１４６のインクリメント入力ＩＮＣには、図７のオア回路９６から出力されるサンプリング周期の残り３／４の区間（すなわちＤＭＡ転送を行う区間）を示す信号が入力され、クロック入力ＣＫには、５１２分割クロックを１／４に分周したクロックが入力される。これによりカウンタ１４６はＤＭＡ転送を行う区間で５１２分割クロックの４クロックごとにカウントアップされ、そのカウント値がＳＤＲＡＭ６４，６６にアドレス情報として入力されて該当するアドレスからサンプルデータが読み出されてＨＤＤ６０にＤＭＡ転送され、あるいはＨＤＤ６０からＤＭＡ転送されたサンプルデータがそのアドレスに書き込まれる。
【００６５】
なお、上記実施の形態ではバッファメモリをＳＤＲＡＭで構成した場合について説明したが、他の形式のメモリを用いることもできる。また、上記実施の形態では外部記憶装置をＨＤＤとしたが、光ディスク装置、光磁気ディスク装置、その他の外部記憶装置を使用することもできる。また、上記実施の形態では外部記憶装置が内蔵されている記録再生装置にこの発明を適用した場合について説明したが、外部記憶装置をＳＣＳＩ等のインタフェースボードを介して外付けして使用する記録再生装置にもこの発明を適用することができる。また、上記実施の形態ではディジタルミキシングレコーダ（ハードディスクレコーダ）にこの発明を適用した場合について説明したが、ミキシング機能を具えていないディジタルレコーダ、その他各種のサンプルデータ再生装置にこの発明を適用することができる。
【図面の簡単な説明】
【図１】 この発明の実施の形態を示す図で、図１０のトラックアドレスジェネレータの構成例を示すブロック図である。
【図２】 ハードディスクレコーダにおけるリピート再生の説明図である。
【図３】 この発明を適用したハードディスクレコーダ全体の主要部のシステム構成を示すブロック図である。
【図４】 図３のＨＤＤ６０のアドレス領域の分割例を示す図である。
【図５】 図３のハードディスクレコーダ全体のシステム構成のうち、音データ、システム管理データ、ソング管理データの授受に関与する主な部分を抽出して示したブロック図である。
【図６】 図３のハードディスクレコーダにおけるバス５６の使用権の分割例および録音・再生モード時のサンプリング周期内のＳＤＲＡＭの書き込み、読み出し処理の分割例を示すタイムチャートである。
【図７】 図３のハードディスクレコーダにおけるバス５６の使用権の時分割制御の制御系統ブロック図である。
【図８】 図７の制御系統の動作を示すタイムチャートである。
【図９】 図７の制御系統による１つの再生チャンネルについてのＤＭＡ転送の手順（プロトコル）を示す図である。
【図１０】 図３のＤＲＣ６８内におけるサンプルデータの信号経路構成およびＳＤＲＡＭ６４，６６のアドレス情報の信号経路構成の具体例を示すブロック図である。
【図１１】 通常の録音、再生時におけるＳＤＲＡＭ６４，６６のアドレスマップ例を示す図である。
【図１２】 表２のシーケンスを実行する際のＳＤＲＡＭ６４，６６の制御信号の一部を示すタイムチャートである。
【図１３】 パンチイン、パンチアウト時におけるＳＤＲＡＭ６４，６６のアドレスマップ例を示す図である。
【図１４】 図１のトラックアドレスＲＡＭ１１８のアドレスマップを示す図である。
【図１５】 各チャンネルに割り当てられたアドレス演算回路１３４の使用時間の分割例を示すタイムチャートである。
【図１６】 再生が起動した時の最初のサンプリング周期におけるアドレス演算回路１３４よる１つの演奏チャンネル（再生チャンネル）のアドレス計算手順を示すフローチャートである。
【図１７】 再生が起動した時の最初のサンプリング周期の次のサンプリング周期から停止操作がされるまでの間にサンプリング周期ごとに繰り返されるアドレス演算回路１３４よる１つの演奏チャンネル（再生チャンネル）のアドレス計算手順を示すフローチャートである。
【図１８】 通常の録音、再生時の１つの演奏チャンネル（再生チャンネル）についてのＳＤＲＡＭ６４または６６のアドレスポインタの移動例を示す図である。
【図１９】 無音区間が設定された演奏例を示すタイムチャートおよび該演奏音を録音したＨＤＤの記録データを示す図である。
【図２０】 図１９の無音区間を含んで録音されたパートを再生するときのアドレスジェネレータ１００によるＳＤＲＡＭ６４，６６のアドレス制御例を示す手順図図である。
【図２１】 パンチイン、パンチアウトにおけるリピート再生区間の設定例を示すタイムチャートである。
【図２２】 図２１のリピート再生するときのアドレスジェネレータ１００によるＳＤＲＡＭ６４，６６のアドレス制御例を示す手順図である。
【図２３】 図１０のＤＭＡアドレスジェネレータ１０２の構成例を示すブロック図である。
【符号の説明】
１０…ハードディスクレコーダ（サンプルデータ再生装置）、６４，６６…ＳＤＲＡＭ（バッファメモリ）、６０…ＨＤＤ（外部記憶装置）、１００…トラックアドレスジェネレータ（バッファメモリ制御回路）１１８…トラックアドレスＲＡＭ（ジャンプアドレス設定回路、アドレスメモリ）、１３４…アドレス演算回路（読み出しアドレス演算回路）。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for reproducing sample data recorded on an external storage device (referred to as data sampled at an appropriate sampling frequency) and an apparatus for recording / reproduction, which enable efficient reading of sample data. is there.
[0002]
[Prior art]
In a digital mixing recorder (hard disk recorder) using a hard disk device (hereinafter referred to as “HDD”) as an external storage device, sound data is distributed and recorded at appropriate addresses for each predetermined unit section (for example, for each cluster of data). During playback, based on the chain information of the recording positions of the sound data included in the separately recorded management data, the recording positions are sequentially accessed to obtain a series of sound data, and the acquired sound data Are sequentially stored in the buffer memory, and reproduction is performed by sequentially reading out one sample of sample data from the buffer memory at each sampling period.
[0003]
[Problems to be solved by the invention]
Conventional hard disk recorders , Pa In order to perform repeat playback (an operation that automatically repeats playback of a specified section) by specifying an arbitrary section in order to perform punch-in, punch-out, etc., each of the sections included in the specified section It is necessary to repeatedly access the recording position on the HDD where the sound data of the unit section is recorded in order and repeatedly acquire the sound data of each unit section. As shown in FIG. When a section from the time close to the end of section 1 to the time immediately after the start of another unit section 5 is designated, the playback of unit section 4 ends and the start portion of unit section 5 and unit section 1 It is necessary to access unit sections 5, 1, and 2 in order within a short time from playback of a short part of the end part to transition to unit section 2, and the playback sound is interrupted in the middle of the song because access is not in time. There was a Rukoto. The possibility of the occurrence was high especially when the number of tracks was large. To prevent the playback sound from being interrupted in the middle of a song, wait for a long time after the playback of the unit section 5 is finished (after the sound data of the unit sections 1 and 2 are stored in the buffer memory). It was necessary to adjust the time to start, and when there were many tracks, the wait time was long.
The present invention has been made in view of the above points, and an object of the present invention is to provide a sample data reproducing apparatus and a sample data recording / reproducing apparatus that enable efficient reading of sample data.
[0007]
[Means for Solving the Problems]
This The sample data reproducing apparatus of the invention reads sample data stored in an external storage device sequentially in predetermined unit intervals and writes them to a buffer memory, and reads the sample data from the buffer memory sample by sample for each sampling period. In a sample data reproducing apparatus that reproduces sample data that has been read from the buffer memory and sequentially updates the unit data with new sample data that is read from the external storage device, and continuously reproduces the sample data. In the case of repeatedly reproducing sample data of an arbitrary section spanning the unit section, at least the unit section including at least the head portion of the repeat section and the sample data of the unit section including the tail portion of the repeat section are stored in the external storage. The buffer memory read from the device Stored in a predetermined area, during reproduction, the sample data of the unit section of the intermediate portion is sequentially read out from the external storage device, sequentially updated and stored in another area of the buffer memory, and the sample data from the buffer memory is 1 At an appropriate time during the reading of each sample, the jump source address and the jump destination address of the address jump necessary for continuous and repeated playback of the repeat section are sequentially set, and the read address of the buffer memory is set. A buffer memory control circuit that detects that the set jump source address has been reached, jumps a read address to the jump destination address, and continues reading sample data from the jump destination address It is. According to this, each sample data of the unit interval including at least the beginning portion of the repetition interval and the unit interval including the tail portion of the repetition interval is read from the external storage device and stored in a predetermined area of the buffer memory, During repeat playback, the sample data of the unit section of the intermediate portion is sequentially read out from the external storage device and played back. Therefore, during repeat playback, at least the unit section including the head portion and the unit section including the tail portion are included. There is no need to read from the external storage device, and even when the head portion of the unit section including the head portion and the tail portion of the unit section including the tail portion are short, the access of the external storage device cannot be made in time. It is possible to prevent the playback sound from being interrupted in the middle of the song. Further, it is possible to eliminate the waiting time from the end of the reproduction of the repeat section to the restart of the reproduction of the repeat section, or to set an arbitrarily short time.
[0008]
This The sample data recording / reproducing apparatus of the present invention sequentially reads sample data stored in an external storage device by a predetermined unit interval and writes the sample data to a buffer memory, and reads the sample data from the buffer memory sample by sample at every sampling period. The sample data that has been read and reproduced from the buffer memory is updated sequentially for each unit interval with new sample data that is read from the external storage device, and the sample data is continuously reproduced, in parallel with the reproduction. In this way, sample data that is separately input is written into the buffer memory one sample at a time in a time-sharing manner, and the sample data written in the buffer memory is read out from the buffer memory in predetermined unit intervals to the external storage device. Write, read from the buffer memory In a sample data recording / reproducing apparatus that sequentially updates sample data that has been completed with newly input sample data and continuously records the sample data, while repeatedly reproducing the sample data in an arbitrary interval across a plurality of unit intervals , When recording separately input sample data in a section designated as appropriate in the repetition section, a unit section including at least a head portion of the repetition section and a unit section including a tail portion of the repetition section in advance. Each sample data is read from the external storage device and stored in a predetermined area of the buffer memory, and during reproduction, the sample data of the unit section of the intermediate portion is sequentially read from the external storage device to another area of the buffer memory. Sequentially update and store, and read sample data from the buffer memory one sample at a time The jump source address and the jump destination address of the address jump necessary to continuously and repeatedly reproduce the repeated section are set in order at an appropriate time during the output, and the read address of the buffer memory is set to the set Detecting that the jump source address has been reached, jumping the read address to the jump destination address, continuing to read sample data from the jump destination address, and instructing the recording during the playback In the reproduction operation and time division, sample data input separately is written into the buffer memory one sample at each sampling period, and the sample data written in the buffer memory is read out from the buffer memory in predetermined unit intervals. Write to external storage device and finish reading buffer memory A buffer memory control circuit for sequentially updating the sample data with newly inputted sample data. According to this, for example, when performing punch-in and punch-out while repeat playback, each sample data of the unit section including at least the beginning portion of the repeated section and the unit section including the tail portion of the repeated section is stored in the external section. Since it is read from the storage device, stored in a predetermined area of the buffer memory, and the sample data of the unit section of the intermediate portion is sequentially read out from the external storage device during the repeat reproduction, it is reproduced at least at the head portion during the repeat reproduction. When the unit section including the tail part and the unit part including the tail part are not read from the external storage device, the head part of the unit section including the head part and the tail part of the unit section including the tail part are short. However, access to the external storage device will not be in time, and the playback sound will be interrupted in the middle of the song. Punch-in and punch-out operations can be performed, or the waiting time from the end of playback of a repeat section to the restart of playback of the repeat section can be eliminated or set to any short time. Can be performed smoothly.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment in which the present invention is applied to a digital mixing recorder (hard disk recorder) using an HDD as an external storage device will be described. FIG. 3 shows the system configuration of the main part of the entire hard disk recorder. This hard disk recorder 10 has a plurality of channels {signal paths for performing signal processing on sound data of individual tracks (not only signal paths physically divided for each channel but also time-division processing of sound data of each channel). Physically includes a common signal path) or sound data itself flowing through the signal path. } Signal path, simultaneous recording of multiple tracks (for example, simultaneous recording of up to 16 tracks) or simultaneous playback of multiple tracks (for example, simultaneous playback of up to 16 tracks) or simultaneous recording and playback of multiple tracks (for example, up to 16 tracks) It is possible to record up to 8 tracks simultaneously while playing back simultaneously. The sound data of one sample of each channel is composed of 16 bits (2 bytes) except that the mixed down signal is composed of 24 bits (3 bytes).
[0010]
The hard disk recorder 10 is provided with a total of three one-chip CPUs (microcomputers) {for example, SH7042 (single-chip RISC microcomputer) manufactured by Hitachi} including a main CPU 12, a recorder CPU 14, and a sub CPU 16. Each of the CPUs 12, 14, and 16 is independently driven by mutually prepared operation clocks that are asynchronous with each other. The main CPU 12 mainly performs mixing control. The recorder CPU 14 performs recording and reproduction control of the HDD 60, waveform editing control, and the like based on a command from the main CPU 12. The sub CPU 16 performs control to transmit various types of operation information by the operator to the main CPU 12, and performs motor drive control of each fader operator based on commands from the main CPU 12.
[0011]
Connected to the bus 18 of the sub CPU 16 are various operators 20 composed of switches, rotary knobs, mice, jogs, shuttles, etc., a flash ROM 22 storing a program of the sub CPU 16, a motor driver interface 24, and the like. Yes. A plurality of motor drive type fader operators 26 are connected to the motor driver interface 24 via a motor driver 28. The operation position information of each motor drive type fader operator 26 is transmitted to the sub CPU 16. In the various controls 20, a mixing parameter {routing (which signal route channel is used to record each input channel and which track is recorded) and each track reproduction signal is routed via which signal route channel by the operator's operation. Allocation of output channels), equalizer characteristics, effect characteristics, panning (PAN), etc.}, recording / playback / stop / pause / slow playback / fast forward / rewind, etc. Selection of a song (a unit of music to be recorded and reproduced, for example, one song = one music), operation mode switching such as recording / playback mode / editing mode, waveform editing, and the like are performed. The recording / playback mode includes normal recording and playback mode for each part (recording only (ALL REC), playback only, or recording simultaneously with playback (SYNC DUBBING)), punch-in, punching There are modes for out, mixdown, etc. Operation information of the various controls 20 is transmitted to the sub CPU 16 and is transmitted to the main CPU 12 via the signal line 30. Each fader operator 26 performs level adjustment for each input channel and each output channel, stereo output level adjustment, etc., by the operator's operation. The operation information is transmitted to the sub CPU 16 via the signal line 30. This is transmitted to the main CPU 12. In the recording / playback mode, regarding the fader level adjustment of each playback track, the operation position command of each fader operator 26 is sequentially transmitted from the main CPU 12 to the sub CPU 16 via the signal line 30 according to the progress of the song. Each fader operator 26 is automatically controlled to move to the commanded operation position via the motor 24 and the motor driver 28. As a result, the operation position of each fader operator 26 set at the time of recording is reproduced, and the playback level of each track is automatically adjusted to the state set at the time of recording and playback is performed.
[0012]
The bus 32 of the main CPU 12 has a flash ROM 34 storing the program of the main CPU 12 and a mixing function (routing, equalizing, effect addition, fader level adjustment) for a song currently designated for recording, playback, editing, etc. Sequence data relating to the setting values of these parameters in accordance with the progress of time, DRAM 36 functioning as a work area of the main CPU 12, DSP 38 realizing a mixing function, An LCD (Liquid Crystal Display) 43 is connected via an LCD control circuit 41, and an FL (fluorescence) display 47 is connected via an interface 45. Information corresponding to the operation mode is displayed on the LCD 43. For example, in the recording / playback mode, a display for routing, channel on / off, virtual track selection, and the like is performed. In the waveform editing mode, a waveform editing portion is graphically displayed. The FL display 47 displays time information (time code) as numerical values and the level of the input signal or reproduction signal of each channel as a bar graph. A virtual track is a virtual track that is assigned to each track (real track). During playback or simultaneous recording and playback, each track (real track) to be played is selected from a plurality of assigned virtual tracks. You can select and play virtual tracks one by one. For example, if the number of tracks is 16 and the number of virtual tracks is 8 for each track, a total of 128 virtual tracks can be created.
[0013]
The DSP 38 forms a multi-channel mixing processing unit, and commands the main CPU 12 based on operations of various operators 20 and fader operators 26 by the operator or according to sequence data relating to the mixing function stored in the DRAM 36. Thus, processing (mixing processing) for realizing the instructed contents is performed for the mixing functions such as routing, equalizing, effect application, fader level adjustment, and localization adjustment for the recording input and reproduction output.
[0014]
A plurality of channels (for example, a maximum of 16 channels) of analog audio signals (recording inputs) input from the analog input terminal 40 are gain-adjusted to an appropriate signal level during A / D conversion by a gain control (not shown). After that, it is converted into a digital signal by the A / D converter 42 and input to the DSP 38, where mixing processing is performed. Also, digital audio signals (recording inputs) of a plurality of channels (for example, a maximum of 16 channels) input from the digital input terminal 44 are input to the DSP 38 via the interface 46 and subjected to mixing processing. The recording input subjected to the mixing process is recorded in the HDD 60 described later. Further, digital audio signals (reproduction output) of a plurality of channels (for example, a maximum of 16 channels) reproduced from the HDD 60 are mixed by the DSP 38 and output from the digital output terminal 54 via the interface 52. A signal obtained by mixing the digital audio signal into a 2-channel stereo signal by the DSP 38 is converted to an analog signal by the D / A converter 48 and output from the analog output terminal 50 as a monitor signal or the like.
[0015]
The bus 56 of the recorder CPU 14 has a flash ROM 58 storing a program for the recorder CPU 14, a DRAM 62, an HDD 60 corresponding to the external storage device of the present invention, an SDRAM (synchronous DRAM) 64 corresponding to the buffer memory of the present invention, 66, a DRAM controller (hereinafter referred to as “DRC”) 68 that controls the writing and reading of sound data to and from 66, an optical disk device 72 such as a CD-RW via an interface 70, and data of the current date and time via a parallel interface 74. A real-time clock 76 is connected. The HDD 60 is connected to the bus 56 through an interface such as IDE. The optical disk device 72 backs up a song recorded on the HDD 60 to a CD-R disk or CD-RW disk, or plays back a CD-ROM or the like storing a version upgrade program, and updates the programs in the flash ROMs 22, 34, and 58. Used to do.
[0016]
An example of division of the address area of the HDD 60 is shown in FIG. The address area of the HDD 60 is divided into a fixed capacity system management data address area 84 followed by a shared address area 86 extending to the end. In the shared address area 86, the sound data for each channel is recorded and stored sequentially as digital signals in the order of take (recording unit, one take = one recording) from the front end, and the sound data area 86- 0 is sequentially enlarged, and song management data of each song is sequentially recorded from the rear end portion, so that song management data areas 86-1, 86-2,. Sound data is recorded in units of clusters (128 Kbytes). Once recorded, the sound data is not erased unless an explicit delete instruction for the corresponding take is given by the operator. When recording multiple tracks at the same time, the sound data of each track is sequentially switched and recorded in the common address area 86, and the sound data added later by punch-in, punch-out, etc. Since the sound data of the initial recording of the track is separated from the address at which the sound data is recorded, it is continuously recorded at the end of the recorded sound data in the shared address area 86 at the time when they are recorded. The sound data is distributed and recorded in cluster units in the shared address area 86. When there is a long pause in the middle of a song in the performance part being recorded, the operator performs a silent interval instruction operation for the corresponding channel, and the recording of that channel is paused at that point. After the data for one cluster including the previous sound data is recorded in the shared address area 86, the sound data for the channel is not recorded. When the operator performs an instruction operation to end the silent period for the corresponding channel, recording is resumed for the corresponding channel, and sound data of the corresponding channel is sequentially recorded in the shared address area 86 in units of clusters.
[0017]
In the song management data areas 86-1, 86-2,... Of each song, in order to reproduce the sound data of each virtual track included in the song recorded in a distributed manner as continuous music. Necessary sequence data indicating a chain of recording addresses of sound data for each virtual track is recorded. For a virtual track in which a silent section is designated, information on the start time and end time of the silent section is also recorded. In addition, sequence data relating to the mixing function for each virtual track included in the song is also recorded in the song management data areas 86-1, 86-2,. The song management data areas 86-1, 86-2,... Of each song have a fixed capacity (for example, 1.5 Mbytes per song), and every time the operator instructs to create a new song file. The song management data area for the song is newly initialized and secured, and each time recording sound data is added for the song, the song management data is updated accordingly. The song management data areas 86-1, 86-2,... Of each song are fixed once determined, and are not erased unless an explicit song erase command is given by the operator. In the system management data address area 84, system management data including data for knowing the recording position of the song management data for each song is recorded.
[0018]
Song management data is recorded in units of songs in order from the rear end of all address areas of the HDD 60. However, in the individual song management data areas 86-1, 86-2,... From the side in the positive direction (address increasing direction). } Moreover, since the capacity of each song management data area 86-1, 86-2,... Is fixed, the last address information of all the address areas of the HDD 60 is recorded in the system management data address area 84. Thus, the start positions of the song management data areas 86-1, 86-2,... Can be obtained by calculation. For example, the start position of the song management data area 86-1 of the first song is obtained by the calculation of [the last address of all address areas of the HDD 60]-[capacity of one song management data area]. Instead of obtaining by calculation, the address information of the start positions of the song management data areas 86-1, 86-2,... Of each song can be recorded in the system management data address area 84. In the above example, the last address in the shared address area is matched with the last address in the entire address area of the HDD 60, but the present invention is not limited to this.
[0019]
According to the file structure as described above, when the power of the hard disk recorder 10 is turned on, the system management data is automatically accessed by reading the head address of the HDD 60, and when the song is designated, the system management is performed. Based on the data, when the song management data is read by accessing the address area (song management data area) where the song management data of the designated song is recorded, Based on the management data, the sound data of the virtual track can be reproduced by sequentially accessing and reading the address where the sound data is recorded for each currently selected virtual track of the song.
[0020]
In FIG. 3, the DRAM 62 has a sequence indicating a chain of recording positions in the HDD 60 among the system management data read from the HDD 60 and the song management data relating to the song currently designated for recording, reproduction, editing, and the like. Data is stored. The DRAM 62 functions as a work area for the recorder CPU 14. The sound data is transmitted between the DSP 38 and the DRC 68 via a signal line 69 that does not pass through the buses 32 and 56.
The bus 32 of the main CPU 12 and the bus 56 of the recorder CPU 14 are connected to each other via a dual port RAM 78 (hereinafter referred to as “DPRAM”), and various commands to be exchanged between the main CPU 12 and the recorder CPU 14 and information such as song management data are transmitted. Is done. A sampling clock oscillator 80 oscillates a sampling period clock and is input to the AND circuit 82. The recorder CPU 14 outputs an operation section instruction signal that rises in synchronization with the start of recording or reproduction, and falls in synchronization with the end of the recording or reproduction, and is input to the AND circuit 82. As a result, the AND circuit 82 outputs a sampling clock during the period from the start to the end of recording or playback. This sampling clock is input to the external clock input terminals of the main CPU 12 and the recorder CPU 14. In both the CPUs 12 and 14, counters for counting clocks input from the external clock input terminal are respectively arranged. Both counters are reset in synchronization with the start of recording or playback, and then count the sampling clock that is input thereafter. The main CPU 12 executes mixing processing in units of sampling clocks according to the count value. Further, the recorder CPU 14 executes writing or reading control of the HDD 60 and the SDRAMs 64 and 66 in sampling clock units according to the count value. As a result, the main CPU 12 and the recorder CPU 14 operate in synchronization with each other in units of sampling periods (48 kHz, 44.1 kHz, etc.) while operating with individual operation clocks (for example, 28 MHz) for recording or reproduction. Control can be performed independently and in parallel.
[0021]
Transfer of data (sound data, system management data, song management data) in the recording / playback mode in the hard disk recorder 10 of FIG. 3 will be described with reference to FIG. When the power of the hard disk recorder 10 is turned on, the system management data is read from the system management data address area of the HDD 60 and held in the DRAM 62 via the bus 56. When a song is designated, the recorder CPU 14 refers to the system management data stored in the DRAM 62, accesses the song management data area in the HDD 60 where the song management data of the designated song is recorded, and manages the corresponding song management. Read data. Of the read song management data, sequence data relating to the mixing function of the song is transferred to the DRAM 36 via the bus 56, DPRAM 78 and bus 32. Among the read song management data, sequence data indicating a chain of recording positions of a series of sound data of the song in the HDD 60 is transferred to the DRAM 62 via the bus 56. As a result, the designated song can be recorded, played back, edited in waveform, and the like according to instructions from the operator. For a song to be recorded for the first time, a new song file is created in advance by the operator's operation (one new song management data area is secured in the HDD 60), and the song management data is recorded. Are held in the DRAMs 36 and 62 and recording is possible.
[0022]
In the recording / playback mode, processing is performed as follows for the track {recording (recording) channel} instructed to record. The recording signal (sound data) of the track input from the analog input terminal 40 or the digital input terminal 44 is input to the DSP 38 via the A / D converter 42 or the interface 46, and various operators 20 and faders by the operator. Mixing processing is performed by the DSP 38 in accordance with the operation of the operator 26, and the data is sequentially stored from the DRC 68 to the SDRAMs 64 and 66 constituting the buffer memory via the signal line 69 not passing through the bus 56. The sound data stored in the SDRAMs 64 and 66 is periodically DMA-transferred to the HDD 60 via the bus 56 and recorded. Of the system management data and song management data newly generated at this time, sequence data indicating the chain of playback positions is sequentially stored in the DRAM 62, and among the song management data, sequence data relating to the mixing function is sequentially stored in the DRAM 36. . When the recording operation is finished and the storing operation is performed, the sequence data related to the mixing function stored in the DRAM 36 is transmitted to the bus 56 via the DPRAM 78, and together with data indicating a chain of recording positions of sound data in the HDD 60 stored in the DRAM 62, The song management data area of the HDD 60 for saving the song management data is overwritten and saved. The system management data stored in the DRAM 62 is also overwritten and saved in the system management data address area of the HDD 60.
[0023]
In the recording / playback mode, the following processing is performed for the track (playback channel) for which playback has been instructed. The recorder CPU 14 refers to the sequence data indicating the chain of reproduction positions of the track stored in the DRAM 62 and sequentially reads out the sound data of the corresponding track from the HDD 60. The read sound data is DMA-transferred and stored in the SDRAMs 64 and 66 via the bus 56 and the DRC 68. The DRC 68 sequentially reads out the sound data stored in the SDRAMs 64 and 66 at a sampling period. The sound data read from the SDRAMs 64 and 66 is transferred from the DRC 68 to the DSP 38 via a signal line that does not pass through the bus 56. The main CPU 12 refers to sequence data relating to the mixing function stored in the DRAM 36, sets the parameters of the DSP 38, and performs mixing processing on the transferred sound data. The sound data subjected to the mixing process is output from the digital output terminal 54 via the interface 52. The signal mixed into the 2-channel stereo signal in the DSP 38 is converted into an analog signal by the D / A converter 48 and output from the analog output terminal 50. In the recording / playback mode, the signals of the tracks to be recorded and played are time-sequentially processed in order, and the SDRAMs 64 and 66 are time-divisionally operated (write / read) depending on whether they are recording tracks or playback tracks. Can be switched.
[0024]
A specific example of the right to use (bus right) control of the bus 56 and the transfer control of sample data (write / read control of the SDRAMs 64 and 66) in the recording / playback mode will be described. In the recording / playback mode, as shown in FIG. 6, at predetermined intervals A (first time) and B (second time) every sampling period 1 / fs (fs = 48 kHz, 44.1 kHz, etc.). Divided. The length of the sections A and B is A <B. The right to use the bus 56 is assigned to the recorder CPU 14 in the section A, and is assigned to the DMA transfer between the SDRAMs 64 and 66 and the HDD 60 in the section B. Within the section A, the recorder CPU 14 accesses the program stored in the flash ROM 58 and the song management data stored in the DRAM 62 via the bus 56 and executes the program. Sample data transfer control is performed as follows. With respect to the recording channel (input channel), sound data is written to the SDRAM 64 or 66 in a time-division manner for each sample via the signal line 69 that does not pass through the bus 56 in the section A, and a plurality of recording channels are recorded in the section B. Sample sound data is read from the SDRAM 64 or 66, and DMA-transferred to the HDD 60 via the bus 56 for writing. With respect to the playback channel (output channel), sound data is read out from the SDRAM 64 or 66 in a time division manner in a time division manner in the section A, and is output via the signal line 69 that does not pass through the bus 56. A plurality of samples of sound data are read out from the HDD 60 and DMA-transferred to the SDRAM 64 or 66 via the bus 56 for writing.
[0025]
The DMA transfer from the SDRAMs 64 and 66 to the HDD 60 is newly accumulated (or earlier than that) when sample data for one cluster is newly accumulated in the SDRAMs 64 and 66 for each channel. The sample data for one cluster is grouped and divided into sections B for every sampling period, and DMA transfer of the sample data for one cluster is completed for one channel. Similarly, another channel newly accumulated in the SDRAMs 64 and 66 is DMA-transferred for one cluster in a similar manner, and each channel is clustered for one cluster and each channel is time-divisionally performed. Also, in the DMA transfer from the HDD 60 to the SDRAMs 64 and 66, when sample data for one cluster is newly read from the SDRAMs 64 and 66 for each channel, the sample data for one cluster is collectively collected for the channel. DMA transfer is performed by dividing each section B of the sampling cycle, and when DMA transfer of sample data for one cluster is completed for one channel, another channel in which sample data for one cluster is newly read from the SDRAMs 64 and 66 is obtained. In the same manner, the data is transferred by one cluster for one cluster in a similar manner, and each channel is performed for one cluster and each channel is time-divisionally performed. For any channel, when there is no need to move data by DMA transfer, that is, when input data from the input / output signal line 69 is not newly written to the SDRAMs 64 and 66 by one cluster, the input / output signal line If the output data to 69 is not newly read out from the SDRAMs 64 and 66 for one cluster, the DMA transfer is suspended and the right to use is assigned to the recorder CPU 14 throughout each sampling period. In the SDRAMs 64 and 66, the address area is divided for each channel, and the address area of each channel has a capacity capable of storing sample data for at least two clusters. When attention is paid to one channel, while the sample data for one cluster is DMA-transferred by using the address area for one cluster out of at least two available addresses by DRC 68 address control, Using the address area for the cluster, new recording input or reproduction output sample data of the same channel is written or read one sample at each sampling period. By alternately switching the address area for performing DMA transfer and the address area for writing or reading sample data for recording input or reproduction output one sample at a time for each cluster, DMA transfer and recording input or reproduction output for the same channel are performed. Sample data can be written or read in parallel.
[0026]
A specific example of time-sharing control of the right to use the bus 56 in the recording / playback mode will be described. FIG. 7 shows a control system for time division control of the right to use the bus 56, and FIG. 8 shows the operation of the DRC 68 of the control system in the recording / playback mode. 8, (A) to (F) are signal waveforms at locations indicated by the same reference numerals in FIG. Here, it is assumed that the SH7042 manufactured by Hitachi is used as the recorder CPU 14 and is controlled by a clock obtained by dividing one sampling period by 512. The SH 7042 incorporates a DMA controller for controlling DMA transfer. Here, the DMA controller 63 provided in the IDE interface 61 built in the HDD 60 is used instead of the DMA controller in the recorder CPU 14. Assume that the DMA transfer is controlled.
[0027]
In FIG. 7, in the recording / reproducing mode, the recorder CPU 14 stores the recording input sample data for one cluster in the SDRAMs 64 and 66 for any recording channel or reproducing channel (or from the SDRAMs 64 and 66 to 1). A command to start DMA operation is issued to the DRC 68 and the HDD 60 (each time reproduction output sample data for the cluster is read). In response to this command, the HDD 60 issues a DMA request signal DMARQ = “H” {FIG. 8A}. The DRC 68 inverts the signal DMARQ with the inverter 88 and inputs the inverted signal to the D flip-flop circuit 90. The counter 92 is reset at every start timing of the sampling period, and a clock (hereinafter referred to as 512) divided into one period (1 / fs) of the sampling clock (48 kHz, 44.1 kHz, etc.) oscillated by the sampling clock oscillator 80 of FIG. “512 divided clocks”). In accordance with the count value of the counter 92, the timing generator 94 becomes “H” level in a section from 0 to 127 (a quarter from the start of the sampling period), and a section from 128 to 521 (sampling). A bus right division signal {FIG. 8 (D)} that becomes “L” level in the remaining 3/4 period of the cycle) is output. In addition, the timing generator 94 becomes “H” level in the interval where the count value is 0 to 255 (interval in the first half of the sampling cycle), and in the interval 256 to 521 (interval in the second half of the sampling cycle). ) Together with the clock signal {FIG. The D flip-flop circuit 90 takes in the inverted signal of the input DMA request signal DMARQ (a signal synchronized with the clock in the HDD 60) with the clock signal of the DRC 68, and the DMA request signal IDMARQ = “L” {FIG. 8 (C)} Is output. The OR circuit 96 receives the DMA request signal IDMARQ and the bus right division signal, and outputs the bus right division signal for the interval of the DMA request signal IDMARQ = “L”. The OR circuit 98 inputs the output signal of the OR circuit 96 and the inverted signal of the DMA request signal DMARQ, and outputs a signal for stopping the output of the bus right division signal in synchronization with the end of the DMA request signal DMARQ = “H”. The right request signal BREQ {FIG. 8 (E)} is output. Upon receiving the bus right request signal BREQ = “L”, the recorder CPU 14 releases the bus right and outputs the bus right request acceptance signal BACK = “L” {FIG. 8 (F)}. Upon receipt of the bus right request acceptance signal BACK, the DRC 68 transmits it directly to the HDD 60 as a DMA acceptance signal DMACK. The HDD 60 and the DRC 68 perform DMA transfer using the bus 56 exclusively in a section where BACK (DMACK) = “L”. In addition, during the DMA operation period, the DRC 68 sets the bus right request signal BREQ to “H” and returns the bus right every quarter of the sampling period from the start of the sampling period. As a result, the recorder CPU 14 obtains the bus right only for the section, accesses the DRAM 62 and the flash ROM 58 exclusively using the bus 56, and executes programs necessary for recording and reproduction.
[0028]
While the recorder CPU 14 occupies the bus 56, the DMA transfer between the HDD 60 and the DRC 68 is suspended, and the DRC 68 passes through the signal line 69 not passing through the bus 56 and the SDRAM 64 for each recording channel for each sampling period. 66, input sample data (one sample for each channel) is written or output sample data (one sample for each channel) is read from the SDRAMs 64, 66. As described above, the recorder CPU 14 serves as the bus master in the quarter interval from the start of the sampling cycle, and the recorder CPU 14 accesses the DRAM 62 and the flash ROM 58 via the bus 56 as shown by symbol I in FIG. The HDD 60 (IDE) is the bus master in the remaining 3/4 interval of the sampling period, and the HDD 60 and the DRC 68 execute DMA transfer via the bus 56 as shown by reference numeral II in FIG. The right is divided.
[0029]
A DMA transfer procedure (protocol) for one reproduction channel by the control system of FIG. 7 will be described with reference to FIG. When reading of reproduction output sample data for one cluster from the SDRAMs 64 and 66 is completed in the recording / reproduction mode, the DRC 68 is set to an operation mode for performing DMA transfer in accordance with a command from the recorder CPU 14 (S1). Further, the recorder CPU 14 gives a command for requesting the start of DMA reading to the HDD 60 (IDE) (S2). In response to this, the HDD 60 issues a DMA request signal DMARQ = "H" and transfers it to the DRC 68 (S3). In response, the DRC 68 issues a bus right request signal BREQ = "L" and transfers it to the recorder CPU 14 (S4). When the recorder CPU 14 receives the bus right request signal BREQ = “L”, the strobe terminal is set to “H” level output, and the strobe terminal, the address terminal, and the data terminal are set to high impedance, and the bus right request is accepted. A signal BACK = "L" is issued (S5). In response, the DRC 68 issues a DMA acceptance signal DMACK = “L” and transfers it to the HDD 60 (S6). The DRC 68 sends a signal DIOR for prompting data transmission to the HDD 60 (S7). In response to this, the DRC 68 performs data transmission (DMA transfer) for each section allocated to the DMA transfer (during DMARQ = “H”, new data is transmitted from the HDD 60 each time DIOR falls). . The transmitted data is received by the DRC 68 (S8) and transferred to the SDRAMs 64 and 66. When the DMA transfer of data for one cluster is completed, the HDD 60 causes the DMA request signal DMARQ to fall. At the same time, the HDD 60 issues an interrupt request signal IDEIRQ (S9). The interrupt request signal IDEIRQ is transferred to the recorder CPU 14 via the DRC 68. Accordingly, the recorder CPU 14 recognizes the end of the DMA transfer and performs a DMA transfer end process. When the DMA transfer end process ends, the end of the process is notified to the HDD 60 via the DRC 68 (S10), and the HDD 60 cancels the issuance of the interrupt request signal IDEIRQ. The recorder CPU 14 returns the bus acceptance signal BACK to the “H” level and transfers it to the DRC 68 (S11). In response, the DRC 68 returns the DMA acceptance signal DMACK to the “H” level and transfers it to the HDD 60 (S12). The DMA transfer is completed as described above, and the bus 56 is exclusively used by the recorder CPU 14 until the next DMA transfer is requested for any channel.
[0030]
Note that the address areas of the SDRAMs 64 and 66 are divided into channel units, the address areas of each channel are assigned to a single bank, and channels with different banks are alternately specified within a quarter of the sampling period. Then, the data of each channel is written to the SDRAMs 64, 66 in time division by one sample or read from the SDRAMs 64, 66, so that data of about 3-4 samples is written to the SDRAMs 64, 66 every 8 clocks of the 512 divided clocks or SDRAM 64 66, and the number of input / output channels is about 24 tracks (8 tracks simultaneous recording while simultaneously playing 16 tracks), within a quarter interval (time of 128 clocks) from the start of the sampling period. ) Tunnel 1 sample each of the sample data can be read from the write or SDRAM64,66 to SDRAM64,66. In addition, since DMA transfer of sample data for one sample can be performed with 4 clocks of 512 divided clocks, about 90 samples are required within the remaining 3/4 period (time for 384 clocks) of one sampling period. Data can be DMA transferred. Therefore, when handling data in the CD format (16 bits, 44.1 kHz), sample data for one cluster (128 Kbytes) in one channel (64 Ksamples. In the case of the CD format, 64 Ksamples / 44.1 kHz) Thus, DMA transfer of about 1.45 seconds of data) can be sufficiently performed within a time of about 800 sampling periods (about 20 msec) by 64000/90.
[0031]
A specific example of the signal path configuration of the sample data in the DRC 68 and the signal path configuration of the address information of the SDRAMs 64 and 66 is shown in FIG. The track address generator 100 is an address of the SDRAMs 64 and 66 for writing input 1 sample data or reading output 1 sample data of each channel in a quarter interval from the start of each sampling period in the recording / playback mode. Generate information. Further, in the remaining 3/4 section, the write or read address of the SDRAMs 64 and 66 of each channel in the next sampling period is calculated. The DMA address generator 102 stores address information of the SDRAMs 64 and 66 for writing or reading the DMA transfer data of each channel in the remaining 3/4 section of each sampling period of the section in which DMA transfer is performed in the recording / playback mode. Generate. As this address information, information on the start address of the SDRAMs 64 and 66 to be written or read by DMA transfer is given from the recorder CPU 14, and thereafter the address value is sequentially incremented from the start address in the DMA address generator 102 in a predetermined cycle. It is generated by going. The multiplexer 104 uses the bus reception signal BACK {FIG. 8 (F)} as a switching signal, for example, and the track address generator 100 generates a quarter interval from the start of every sampling period during the DMA transfer period. The selected address information is selected and output, and the address information generated by the DMA address generator 102 is selected and output for the remaining 3/4 of the sampling period of the period during which the DMA transfer is performed. The address information output from the multiplexer 104 is time-divided into a row (row) address and a column (column) address by the SDRAM address converter 105 and supplied to the address input terminals of the SDRAMs 64 and 66.
[0032]
The sample data of each input channel supplied from the DSP 38 (FIGS. 5 and 3) is converted into parallel data by the serial / parallel converter 103, and one sample of each channel is latched by the latch circuit 106, via the multiplexer 112. Are written in the SDRAMs 64 and 66. The sample data of each output channel read out from the SDRAMs 64 and 66 is latched by one sample in each latch circuit 108 through the multiplexer 112, converted into serial data by the parallel / serial converter 110, and output to the DSP 38. The The sample data of the latch circuits 106 and 108 is rewritten every sampling period. The DMA transfer data is DMA transferred between the SDRAMs 64 and 66 and the HDD 60 via the multiplexer 112, the signal line 114, and the bus 56. The multiplexer 112 uses the bus reception signal BACK as a switching signal, for example, selects a signal line 69 during a quarter period from the start of every sampling period during the period of DMA transfer, and selects each input / output channel 1 sample. Input / output is performed one by one, and the signal line 114 is selected to input / output DMA transfer data in the remaining 3/4 period of each sampling period during the period of DMA transfer. The write / read control circuit 116 performs control to set the SDRAMs 64 and 66 to the write mode at the timing of writing data to the SDRAMs 64 and 66, and to set to the read mode at the timing of reading data from the SDRAMs 64 and 66.
[0033]
Table 1 shows an example of assignment of each channel to each bank at the time of normal recording and reproduction in the recording / reproducing mode of the SDRAMs 64 and 66 constituting the buffer memory.

[0034]
Chips 0 (one of the SDRAMs 64 and 66) and 1 (the other of the SDRAMs 64 and 66) are configured in 4 banks of 0 to 3, respectively. On chip 0, channels 0 to 23 for performance sounds are assigned to areas of equal capacity. Adjacent channel numbers are assigned to different banks. The entire waveform of the first metronome sound of the measure and the sampler area are allocated to bank 0 of chip 1. Sampler areas are allocated to the entire banks 2 and 3. Bank 4 is assigned the entire area of the metronome sound waveform shared after the second sampler and measure. The sound data in the 0-23 channel area for performance sound in the recording / playback mode is updated sequentially as the performance progresses, but the metronome sound and sampler sound are repeatedly read and used (the metronome sound is When the metronome sound playback is turned on, the tempo instructed by the operator is automatically and repeatedly read out, and the sampler sound is repeated each time the sound generation is commanded from the recorder CPU 14 based on the operation of the operator. It is not updated unless it is particularly necessary in one song. That is, for the metronome sound and the sampler sound, since the entire waveform data to be reproduced is stored in the SDRAM 64 or 66, writing to the SDRAM 64 or 66 is not necessary during reproduction, and only reading from the SDRAM 64 or 66 is performed. Reading of metronome sound and sampler sound from SDRAM 64 or 66 is performed by one sample per sampling period 1 / fs (one sample for each type if multiple types of samplers are specified). The sound data of the channel is read out and the sound data of the recording channel is written in time division. Note that the sampler sound is recorded in advance by the operator, recording an arbitrary number of sampler sounds, and specifying the song in the record / playback mode before recording. An arbitrary sampler sound is selected from among them (up to eight types can be selected), and sound data of the corresponding sampler sound is read from the HDD 60 and written in arbitrary channels (samplers 0 to 7) of the SDRAMs 64 and 66. Then, by instructing the sound generation of a sampler of an arbitrary channel at an arbitrary timing after the start of recording by button operation or the like, the corresponding sampler sound is generated, and the sounding timing and the sound generation channel are recorded in the song management data. When the recording is finished and the song is played back, the corresponding sampler sound is read from the SDRAMs 64 and 66 at the corresponding timing based on the song management data and sounded.
[0035]
FIG. 11 shows an example of an address map of SDRAMs 64 and 66 (one is chip 0 and the other is chip 1) when assigning the channels shown in Table 1. On chip 0, consecutive performance areas corresponding to a total of two clusters of area A (one cluster) and area B (one cluster) are assigned to each performance channel 0-23. The silent area for the channels assigned to banks 0 and 2 is at the tail of bank 2 of chip 0, and the silent area for the channels assigned to banks 1 and 3 is at the tail of bank 3, respectively. When the recording / playback mode is turned on, silence data is written and held. An area of an appropriate size (about one cluster) is allocated to the top of the chip 1 for the metronome (first one). An area of an appropriate size (about one cluster) is allocated to the rear end of the chip 1 for the metronome (second and subsequent shots). In the metronome (first shot) and metronome (second shot and later) areas, the metronome (first shot) and metronome (second shot) read from the flash ROM 58 (Fig. 3) when the recording / playback mode is turned on. The subsequent sound data is held. A sampler area is assigned to a continuous intermediate area sandwiched between the leading and trailing areas of the chip 1. The number of samplers to be assigned to the sampler area can be arbitrarily set by the operator (however, eight types of 0 to 7 at maximum, about 80 seconds in total).
[0036]
The SDRAMs 64 and 66 are configured by Hitachi HM5264165-B60, channels are assigned to the banks of the SDRAMs 64 and 66 as shown in FIG. 11, and the period (0 to 0) from the start of one sampling period (all 512 time slots) is assigned. 127 time slots (that is, section A in FIG. 6), when data of each channel is written to or read from the SDRAMs 64 and 66 one sample at a time, the writing of the SDRAMs 64 and 66 by the DRC 68 during normal recording and reproduction is performed. An example of the read control sequence is shown in Table 2. In Table 2, each symbol represents the following.
ACT: A command for activating the selected bank. At this time, a row (row) address is designated.
RDwAP: Read with auto pre-charge (command to read and automatically precharge after completion). At this time, a column address is designated. )
WTwAP: Write with auto pre-charge (command to write and automatically precharge after completion). At this time, a column address is designated.
R / WwAP: Read or write with auto pre-charge (command to read or write and automatically precharge after completion). At this time, a column address is designated.
R: Read mode
W: Write mode
[0037]

[0038]
In the example of Table 2, among the 0 to 23 channels for performance sound, channels 0 to 7 are set as playback dedicated channels, channels 8 through 15 are set as recording / playback channels, and channels 16 through 23 are set as recording dedicated channels. However, channels 8 to 15 can be used as recording channels only in the recording only (ALL REC) mode, and can be used only as playback channels in the simultaneous playback recording (SYNC DUBING) mode. In Table 2, the output timing of the sample data of each of the channels 8 to 15 when the channels 8 to 15 are set to the read mode is shown in parentheses. In Table 2, the data of the sampler 7 that is instructed to be read in the time slot 127 is output in the time slot 129 after the section A ends (that is, after the main CPU 14 gives up the bus right). Since the main CPU 14 is not involved in data output, the data output can be performed without any problem. When mixing down, channels 0 to 15 are assigned as playback channels, the tracks of the parts to be mixed down are assigned, channels 16 and 17 are assigned as recording channels MIXL and MIXR (two channels on the left and right) of the mixdown, The sound reproduced on channels 0 to 15 is mixed down to the left and right channels by DSP 38 and recorded on HDD 60 via channels 16 and 17. When reproducing the mixdown signal recorded in the HDD 60, the left and right channel mixdown signals are assigned to any one of the reproduction-only channels 0 to 15 and reproduced. Since the mixdown signals MIXL and MIXR are composed of 24 bits, they are transmitted separately in the upper word and the lower word. FIG. 12 shows a part of a time chart of control signals of the SDRAMs 64 and 66 when the sequence of Table 2 is executed.
[0039]
Table 3 shows an example of assigning each channel to each bank at the time of punch-in / punch-out in the recording / reproducing mode of the SDRAMs 64 and 66 constituting the buffer memory.

[0040]
An example of an address map of the SDRAMs 64 and 66 when assigning the channels shown in Table 3 is shown in FIG. At the time of punch-in and punch-out, a repeat section appropriately set so that the operator includes a punch-in and punch-out section is automatically played back repeatedly, so that the performance channels 0 to 23 are double the normal recording and playback times. Areas for four consecutive clusters A to D (one cluster each) are allocated. The silent area for the channels assigned to the banks 0 and 2 of the chip 0 is located at the tail of the bank 2 of the chip 0, and the channels assigned to the banks 1 and 3 of the chip 0 are located at the tail of the bank 3 of the chip 0. The silent area for the channel is the silent area for the channels assigned to the banks 0 and 2 of the chip 1 at the tail of the bank 0 of the chip 1, and the silent areas for the channels 1 and 3 of the chip 1 at the tail of the bank 1 of the chip 1. Silent areas for the assigned channels are assigned with appropriate sizes (about 1 to 2 classes), and silent data is written and held as the punch-in and punch-out modes are turned on. In addition, an area of an appropriate size (about one cluster) is allocated to the tail of bank 2 of chip 1 and the metronome (second and subsequent) is allocated to the tail of bank 3 of chip 1. An area of an appropriate size (about one cluster) is assigned to the. In the metronome (first shot) and metronome (second shot and later) area, the metronome (first shot) and metronome (second shot) read out from the flash ROM 58 (Fig. 3) as well as punch-in and punch-out are inserted. The subsequent sound data is held. Note that the sampler is not used during punch-in and punch-out, and no sampler is assigned. The control sequence of the SDRAMs 64 and 66 by the DRC 68 at the time of punch-in and punch-out when channels are assigned to the banks of the SDRAMs 64 and 66 as shown in FIG. can do.
[0041]
Address control of the SDRAMs 64 and 66 when the channel assignments of the SDRAMs 64 and 66 are set as shown in FIG. 11 during normal recording and reproduction and as shown in FIG. 13 during punch-in and punch-out will be described. A configuration example of the track address generator 100 of FIG. 10 is shown in FIG. The track address RAM 118 stores address information (current address) of the SDRAMs 64 and 66 that are read or written in the current sampling cycle for each channel, and stores the addresses of the SDRAMs 64 and 66 that are read or written in the next sampling cycle. Various address information of the SDRAMs 64 and 66 necessary for calculation is stored while being sequentially updated (the address information of the SDRAMs 64 and 66 stored in the track address RAM 118 is hereinafter collectively referred to as “address parameter”). An example of an address map of the track address RAM 118 is shown in FIG. The track address RAM 118 is provided with areas for performance channels 0 to 23, samplers 0 to 7, a metronome (first shot), and a metronome (second shot and later). The following eight in-area addresses are assigned to the areas for the performance channels 0 to 23, respectively, and corresponding address parameter data is held for each word.
[0042]
(1) In-area address 0 {area start address (TS) holding address}: start address of the address area of the SDRAMs 64 and 66 assigned to the channel. That is, the top address of the area A in the address map of FIGS.
{Circle around (2)} Intra-area address 1 {area end address (TE) holding address}: end address of the address area of the SDRAMs 64 and 66 assigned to the channel. That is, at the time of normal recording, playback or mixdown, the tail address of the area B in FIG. 11, and at the time of punch-in and punch-out, the tail address of the area D in FIG. {Circle around (3)} Intra-area address 2 {Read start address (RS) holding address}: Address to start reading of the address areas of the SDRAMs 64 and 66 assigned to the channel. Since the sound data of the first cluster read from the HDD 60 at the beginning of reproduction is stored in the area A, usually, the head address (area start end address TS) of the area A is set as the read start address RS and read from there. If you do not want to play this part, you may read the address where the music data starts. The start address RS can be set.
(4) In-area address 3 {address for holding interrupt request generation address (RT)}: Address of SDRAMs 64 and 66 for generating an interrupt request for DMA transfer of sound data to recorder CPU 14 for the channel. Each time the write or read address of the SDRAMs 64 and 66 reaches the interrupt request generation address, the interrupt request is issued. During normal recording and playback, the interrupt request generation address is set to the last address of each of the performance areas 0 to 23 in the address areas A and B (FIG. 11), and sound data for one cluster is written or read. Each time an interrupt request is generated. When a silent area is reproduced, or when a period appropriately set for punch-in, punch-out, etc. is repeated, the interrupt request generation address RT is set for other addresses. This will be described later.
(5) In-area address 4 {Address for holding current address (CR)}: Address of SDRAM 64 or 66 to which writing or reading is performed in the current sampling period for the channel. Normally, it is incremented by one address every sampling period.
(6) In-area address 5 {Jump source address (JT) holding address}: Jump source address of SDRAMs 64 and 66 that perform address jump during reading for the channel. The recorder CPU 14 refers to the current address (CR) and calculates and sets the address of the SDRAMs 64 and 66 at which the address pointer reaches the jump start time indicated by the song management data or the jump start time indicated by the operator. To do.
(7) In-area address 6 {Jump destination address (JD) holding address}: Jump destination address of SDRAMs 64 and 66 that perform an address jump during reading for the channel. The recorder CPU 14 calculates and sets the addresses of the SDRAMs 64 and 66 where the jump destination sample data is stored. When the next address of the current address CR reaches the jump source address JT, the current address is written or read, then the address jump is performed, and reading is continued from the jump destination address JD from the next sampling period. .
(8) Area address 7: Not used
[0043]
In addition, the following four addresses in the area are assigned to the areas for the samplers 0 to 7 of the track address RAM 118, the metronome (first), and the metronome (second and subsequent), respectively, and correspond to one word each. Holds address parameter data.
(1) In-area address 0 {Read start address (RS) holding address}: Address of SDRAMs 64 and 66 that start reading the channel.
{Circle around (2)} In-area address 1 {reading end address (RE) holding address}: address of SDRAM 64, 66 that finishes reading the channel
{Circle around (3)} In-area address 2 {Address for holding current address (CR)}: Address of SDRAM 64 or 66 to which writing or reading is performed for the channel in the current sampling period. Each address is incremented by one address.
(4) Area address 4: Unused
[0044]
For samplers 0 to 7, metronome (first), and metronome (second and later), silence data is stored in the addresses of SDRAMs 64 and 66 specified by the read start address RS, and is effective from the next address. Sound data is stored. The address pointers of the SDRAMs 64 and 66 remain at the read start address RS until the start of sound generation is instructed. Sound generation start instruction (in the case of a sampler, sound generation instruction operation by the operator or sound generation command from the recorder CPU 14 based on song management data, and for the metronome sound, a sound generation command issued from the recorder CPU 14 at intervals corresponding to the specified tempo) If there is, the address pointer is advanced by 1 every sampling period, and a sampler sound or a metronome sound is generated. When the address pointer reaches the read end address RE, the sound generation ends and the address pointer stops at the read start address RS until the next sound start instruction is given.
[0045]
When the recording / playback mode is selected in the hard disk recorder 10, the recorder CPU 14 determines the area start address TS of the performance channels 0 to 23 as address parameter data that is known before the song designation and can be stored in the track address RAM 118 in advance. , Area end address TE, metronome (first), metronome (second and subsequent) read start address RS, read end address RE, and the like are sent together with address information of track address RAM 118 for storing them. . The recorder CPU 14 writes the address parameter data and the address information stored in the track address RAM 118 in the registers 120 and 122 shown in FIG. Information written in the registers 120 and 122 is read by the DRC 68 with its own clock and transferred to the track address RAM 118 via the selectors 124 and 126. As a result, the information such as area start address TS, area end address TE, metronome (first), metronome (second and subsequent) read start address RS, read end address RE, etc. of each performance channel 0-23 is track address. The data is written to each assigned address in the RAM 118.
[0046]
Subsequently, when a song is designated, based on the song management data read from the HDD 60, the read start address RS of the channel instructed to be played out of the performance channels 0 to 23, the first interrupt request generation address RT, Data such as the read start address RS and the read end address RE of each sampler is sent together with the address information of the track address RAM 118 for storing them, and is input to the track address RAM 118 via the registers 120 and 122 and the selectors 124 and 126. Each of these address parameter data is written to the address indicated by the address information in the track address RAM 118. Based on the song management data, the data of the jump source address JT and the jump destination address JD is sent from the recorder CPU 14 together with the address information of the track address RAM 118 for storing them immediately before the time when the address jump is generated. It is held at a corresponding address in the track address RAM 118 via the selectors 124 and 126. When punch-in / punch-out is instructed in the recording / playback mode, the address areas of the SDRAMs 64 and 66 assigned to the performance channels 0 to 23 and the metronome (first) and metronome (second and subsequent) are shown in FIG. Therefore, the recorder CPU 14 sends out the data of the area start address TS and area end address TE of the performance channels 0 to 23 together with the address information of the track address RAM 118 for storing them. , 122 and the selectors 124, 126 are sent to the track address RAM 118 and written to the corresponding address in the track address RAM 118, and the data in the address is updated.
[0047]
When recording and playback are being performed, the interrupt request generation address RT, jump source address JT, and jump destination address JD for the channels for which playback is instructed from the performance channels 0 to 23 from the recorder CPU 14 Along with the information in the track address RAM 118 to be stored, it is sent at an appropriate time immediately before the occurrence of the interrupt or the address jump (for the channel for which recording is instructed, only information relating to the interrupt request generation address RT is sent). They are written in the registers 120 and 122, respectively. The selectors 124 and 126 input the input A side at every sampling cycle at every 8n + 4/0 to 511 (n = 0, 1, 2,..., 63) timings of 512 divided clocks (that is, once every 8 clocks). And the data written in the registers 120 and 122 are read out. The track address RAM 118 is switched to the write mode at each read timing. As a result, the address parameter data held in the register 120 is stored at the address of the track address RAM 118 indicated by the data held in the register 122. Thus, when recording and playback are performed, the address parameter data of the interrupt request generation address RT, the jump source address JT, and the jump destination address JD in the track address RAM 118 are updated to necessary contents each time. The After the jump is completed, unless the next jump needs to be generated immediately, the recorder CPU 14 sends address information outside the area of the channel as address parameter data of the jump source address JT and the jump destination address JD. And stored in the corresponding address of the track address RAM 118. Since the address is outside the channel area, the address pointer is not reached by the increment operation of the address pointer, and therefore no address jump occurs. When the next jump approaches, the recorder CPU 14 sends out valid jump source address JT and jump destination address JD parameter data for performing the jump, and stores the parameter data in the corresponding address of the track address RAM 118. Note that while DMA transfer is being performed, data is written to the registers 120 and 122 only in a quarter interval from the start of the sampling period in which the recorder CPU 14 acquires the bus right. Even if only that section is used, the address parameter data of the track address RAM 118 that needs to be updated and the address information of the track address RAM 118 that stores the data can be written to the registers 120 and 122 without delay each time. Note that, as will be described later, a value obtained by calculation in the address calculation circuit 134 of FIG. 1 is stored in the current address CR holding address of each channel of the track address RAM 118.
[0048]
In FIG. 1, the SDRAM read / write address generation circuit 128 reads sound data of one sample of each channel from the SDRAMs 64 and 66 in a time-division manner in a quarter interval from the start of each sampling period, or SDRAM64. , 66, the information of the address where the current address CR of the track address RAM 118 is stored is generated for each channel instructed to be recorded or reproduced in accordance with the timing specified by the time slot in Table 2. The calculation address parameter read address generation circuit 130 obtains the addresses of the SDRAMs 64 and 66 for reading or writing the data of the next sample of each channel in the remaining 3/4 section of each sampling period in the recording / playback mode. In order to calculate by time division for each channel, the address information of the track address RAM 118 for reading the address parameter of each channel from the track address RAM 118 is time-divided according to a predetermined timing in synchronization with the 512-division clock. Occurs. The address information of the track address RAM 118 generated from both the address generation circuits 128 and 130 is input to the selector 132, and the output address information of the SDRAM read / write address generation circuit 128 is selected in a quarter interval from the start of every sampling period. In the remaining 3/4 section, the output address of the calculation address parameter read address generation circuit 130 is selected.
[0049]
The address information selected by the selector 132 is the timing of every eight divided 512 clocks for writing the data of the registers 120 and 122 to the track address RAM 118 {8n + 4/0 to 511 (n = 0, 1, 2,..., 63). Are output from the selector 124 in a section excluding the timing of), input to the address terminal of the track address RAM 118, and the corresponding parameter data is read from the corresponding address of the track address RAM 118. It should be noted that the data generation sequence of the address generation circuits 128 and 130 synchronized with the 512-divided clock so that valid data is not generated from the address generation circuits 128 and 130 at the timing of writing the data of the registers 120 and 122 to the track address RAM 118. Is set. The current address CR of each channel read from the track address RAM 118 in the quarter interval from the start of every sampling period is sent to the SDRAMs 64 and 66 and used as the write or read address. The current address CR is sent to the recorder CPU 14, and the recorder CPU 14 is notified of the current address CR of each channel.
[0050]
The address calculation circuit 134 is based on the address parameter stored in the track address RAM 118, and addresses of the SDRAMs 64 and 66 that read or write data of the next sample of each channel in the remaining 3/4 section of each sampling period. (Current address CR of the next sampling period) is calculated by time division using 512 division as an operation clock. FIG. 15 shows an example of dividing the usage time of the address calculation circuit 134 assigned to each channel in order to perform the calculation. Each computation channel 0-23, sampler 0-7, metronome (first shot), metronome (second shot and later) occupies the address computation circuit 134 within the time allotted to each of them, and the next sampling cycle The current address CR is calculated and stored in the corresponding address in the track address RAM 118. The order of channels to be calculated can be the same as the address array of the track address RAM 118 shown in FIG. 14, for example.
[0051]
A configuration in the address arithmetic circuit 134 of FIG. 1 will be described. The selector 136 reads each address parameter or register of the channel that is currently being read from the track address RAM 118 in a time division manner at a timing excluding the write timing of the track address RAM 118 (one clock for every 8 divided 512 clocks). The data of 138 (register B) is selected. The selected data is written to the register 140 (register A). The data written in the register A is sent to the selector 126 and the ALU (arithmetic unit) 142. The ALU 142 performs an appropriate operation using the data of the register A and the data of the register B, and according to the result, writing of the data of the register A, generation of address information from the calculation address parameter reading address generation circuit 130, DMA transfer Each control of interrupt request generation for. The calculation of the ALU 142 is held in an ACC (accumulator) 144 as necessary.
[0052]
An address calculation procedure for one performance channel (playback channel) in the address calculation circuit 134 will be described. FIG. 16 shows calculations performed in the first sampling cycle when playback is started after playback operation (or playback simultaneous recording operation) is performed. When a reproduction operation is performed (S1), the read start address RS of the reproduction channel is read from the track address RAM 118 (S2), and the reproduction channel of the track address RAM 118 is transmitted via the selector 136, the register A, and the selector 126. Is stored in the current address CR holding address (S3). FIG. 17 shows a calculation repeated every sampling period from the next sampling period until the stop operation is performed. The current address CR is read from the track address RAM 118 and written to the register A (S10). The ALU 142 calculates the data (current address CR) +1 of the register A, and stores the calculation result in the ACC 144 (S11). The interrupt request generation address RT is read from the track address RAM 118 and written to the register A. In parallel with this, the data of ACC 144 (current address CR + 1) is written to register B. In parallel with this, {data of register A (interrupt request address RT)}-{data of register B (current address CR + 1)} is calculated by the ALU 142. If register A data = register B data, an interrupt for DMA transfer is generated (S12). The jump source address JT is read from the track address RAM 118 and written to the register A. In parallel with this, {data of register A (jump source address JT)}-{data of register B (current address CR + 1)} is calculated by the ALU 142 (S13). The area end address TE is read from the track address RAM 118 and written to the register A. In parallel with this, {data of register A (region end address TE)}-{data of register B (current address CR + 1)} is calculated by the ALU 142 (S14).
[0053]
If the calculation result of step S13 is {register A data (jump source address JT)} = {register B data (current address CR + 1)}, the jump destination address JD is read from the track address RAM 118 and written to the register A. . If the calculation result in step S14 is {register A data (region end address TE)} <{register B data (current address CR + 1)}, the region start end address TS is read from the track address RAM 118 and written to the register A. Otherwise, the data in register B (current address CR + 1) is written into register A (S15). Then, the data written in the register A according to these calculation results is written in the current address CR holding address of the corresponding channel in the track address RAM 118 (S16). As a result, in the next sampling period, sample data is written or sample data is read from the addresses of the SDRAMs 64 and 66 written to the current address CR holding address.
[0054]
For the recording channel, the address calculation circuit 134 performs the same calculation. That is, when the recording operation (or simultaneous reproduction recording operation) is performed and the recording is started, the area start end address TS is read from the track address RAM 118 at the first sampling period, and the current address CR in the track address RAM 118 is held. Sample data is written to the addresses of the SDRAMs 64 and 66 stored in the address and indicated by the current address CR in the next sampling cycle, and thereafter, the current address CR is incremented by 1 every sampling cycle. If it matches the interrupt request address in the middle, an interrupt request for DMA transfer is generated. When the current address CR reaches the region end address TE, the region start address TS is set as the current address CR in the next sampling period, and the address circulation is repeated thereafter. Address jumps are not performed for recording channels.
[0055]
For the samplers 0 to 7, when a reproduction operation (or reproduction synchronous recording operation) is performed and reproduction is started, the read start addresses RS of the samplers 0 to 7 in the track address RAM 118 are read out in the first sampling cycle. The current address CR holding address of the corresponding channel in the track address RAM 118 is stored until the sampler sounding operation is performed by the operator or a sound generation command is issued from the recorder CPU 14 based on the song management data. The Since silence data is stored in the read start addresses RS of the samplers 0 to 7 of the SDRAMs 64 and 66, no sound is generated in this state. When the operator performs a sound generation operation on an arbitrary sampler or a sound generation command is issued from the recorder CPU 14 based on the song management data, the current address CR is incremented by 1 for each sampling period for the corresponding sampler, and the corresponding sampler sound is output. Pronounced. When the current address CR reaches the read end address RE, the read start address RS is held in the current address CR holding address of the track address RAM 118 from the next sampling period until the next sound generation operation is performed on the sampler or The sampler sound is not generated until a sound generation command is issued from the recorder CPU 14 based on the song management data.
For the metronome (first shot) and metronome (second shot and later), the read start address RS of the metronome (first shot) and metronome (second shot and later) is read from the track address RAM 118 when the recording / playback mode is turned on. Until it is read and stored in the address for holding the current address CR of the metronome (first one) and metronome (second and later) in the track address RAM 118, and the metronome sound is instructed to be operated by the operator. That state is maintained. Since silence data is stored in the read start address RS of the metronome (first one) and the metronome (second and later) of the SDRAMs 64 and 66, no sound is generated in this state. When the operator performs a sound generation instruction operation for the metronome sound, the recorder CPU 14 issues a sound for the metronome (first sound), and the current address CR is incremented by 1 for each sampling period for the metronome (first sound), The first beat of the metronome sound is produced. When the current address CR reaches the read end address RE, the read start address RS is held in the address for holding the current address CR in the track address RAM 118 after the next sampling period, and the sound generation is stopped. When the timing of the second beat of the measure is reached, the recorder CPU 14 instructs the metronome (second and subsequent) to sound, and the current address of the metronome (second and subsequent) is incremented by one for each sampling period, A second metronome sound is produced. When the current address CR reaches the read end address RE, the read start address RS is held in the address for holding the current address CR in the track address RAM 118 after the next sampling period, and the sound generation is stopped. In the metronome (second and later), a required number of pronunciations are repeatedly commanded within the measure according to the time signature of the song, and the pronunciation is repeated. The metronome sound (first sound), metronome (second sound and later), and so on are repeated repeatedly after the next measure.
[0056]
If there are a large number of channels and the address calculation circuit 134 cannot calculate addresses for all channels within one sampling period, a plurality of sets of track address RAM 118 and address calculation circuits 134 are provided in parallel, and the channels are distributed and calculated. Alternatively, the operation speed of the address arithmetic circuit 134 may be increased to increase the calculation speed.
[0057]
An example of address control of the SDRAMs 64 and 66 by the track address generator 100 will be described. FIG. 18 shows the movement of the address pointer of the SDRAM 64 or 66 for one performance channel (reproduction channel) during normal recording and reproduction. In this example, address jump is not included. The channel is assigned a memory space (address area) for storing sound data for two consecutive clusters in the A area and B area of the SDRAM 64 or 66, and a read address pointer corresponding to the current address CR is set for each sampling period. It is incremented by one address. An area start address TS is set at the head of the A area, and an area end address TE is set at the tail of the B area. In this example, the read start address RS is set to a different address from the area start address TS. The interrupt request generation address RT is alternately set to the last address of the area where the address pointer exists in the A area and the B area.
[0058]
When playback (or simultaneous recording / playback) is instructed for the selected song, the sound data of the first cluster of each playback channel is read from the HDD 60 and assigned to each playback channel of the SDRAMs 64 and 66 by DMA transfer. In the area A, the address pointer is advanced by one address for each sampling period from the read start address RS, and the corresponding sound data is read and reproduced. While the address pointer moves in the A area, the sound data of the next cluster is read from the HDD 60 and stored in the B area. When the address pointer is moving in the A area, the interrupt request generation address RT is set to the last address of the A area. While the address pointer is moving in the A area, the writing of the sound data by the DMA transfer in the B area is completed. When the address pointer reaches the tail address of the A area, an interrupt request is generated. This interrupt request is notified to the recorder CPU 14, DMA transfer is activated, sound data of the next cluster is further read from the HDD 60, and is written to the A area by DMA transfer. Even after reaching the tail of the A area, the address pointer is continuously advanced by one address from the start address of the B area every sampling period, and the sound data is reproduced without interruption. When the address pointer enters the B area, the interrupt request generation address RT is changed to the tail address of the B area. While the address pointer is moving in the area B, the writing of the sound data by the DMA transfer in the area A is completed. When the address pointer reaches the tail address of the B area, it is returned to the top address of the A area in the next sampling period, and further incremented by one address every sampling period, so that the sound data is reproduced without interruption. The While the address pointer is moving in the A area, sound data is written by DMA transfer in the B area. While the address pointer is moving in the A area, the interrupt request generation address RT is set to the last address of the A area. As described above, the address pointer repeatedly moves from the head of the A area to the tail of the B area until reproduction is stopped.
[0059]
For the performance channel for which recording has been instructed, when the start of recording (or simultaneous playback of recording) is instructed, the write address pointer is advanced by one address for each sampling period from the area start end address TS, and the input sampling is performed. Data is stored in the A area sample by sample. At this time, the interrupt request generation address RT is set at the end of the A area. When the address pointer reaches the interrupt request generation address RT, an interrupt request is generated, DMA transfer is started, and the sound data for one cluster stored in the A area is DMA transferred to the HDD 60 and recorded. Even after the address pointer reaches the end of the A area, the address data is continuously advanced from the head address of the B area by one address every sampling period, and the input sound data is stored in the B area. At this time, the interrupt request generation address RT is set at the tail of the B area. When the address pointer reaches the interrupt request generation address RT, an interrupt request is generated, DMA transfer is activated, and sound data for one cluster stored in the B area is transferred to the HDD 60 and recorded. The address pointer is returned to the beginning of the A area and advanced by one address every sampling period. The above operation is repeated until recording or playback simultaneous recording is stopped, and input sound data is recorded in the HDD 60 one cluster at a time.
[0060]
Next, an example of address control when recording is performed with a silent section set. Here, as shown in FIG. 19, it is assumed that a silent section is set in a section between times t1 and t2 (t1 and t2 are elapsed times from the start of recording) for a certain performance channel. m1 to m6 are sound data for one cluster recorded in the HDD 60, respectively. When the start of a silent section is instructed at time t1 during recording, recording is paused at that time, and a cluster of sound data m3 created immediately before that (invalid sound data is present after time t1 of the cluster). Recording of the sound data to the HDD 60 for that channel is suspended. When the end of the silent section is instructed at time t2, recording is resumed, and sound data m4, m5,... Are created one by one and recorded on the HDD 60. When the recording is finished and the storing operation is performed, it is recorded in the song management data that the performance time t1 to t2 of the part is a silent section.
[0061]
An example of address control of the SDRAMs 64 and 66 by the address generator 100 when reproducing a part recorded including a silent section as shown in FIG. 19 will be described with reference to a procedure diagram of FIG. (I) is a state in which the sound data m1 stored in the area A of the SDRAM 64 or 66 is read out, and (ii) is a state in which the sound data m2 stored in the area B is subsequently read out. While the sound data m2 is being read, the area A is rewritten with the sound data m3, the address corresponding to the time t1 is set as the jump source address JT, and the head address of the silent area is set as the jump destination address JD. When the address pointer AP reaches the tail address of the area B, the address pointer AP is returned to the area A as shown in (iii) and moved again from the head address. The interrupt request generation address RT is set to the same address as the jump source address JT. When the address pointer AP reaches the jump source address JT, the address pointer AP jumps to the jump destination address JD and moves from the jump destination address JD by one address every sampling period as shown in (iv). As a result, silence is reproduced for the channel. In addition, when the address pointer AP reaches the interrupt request generation address RT at the jump source address JT, the interrupt request is generated, and the area B is rewritten with the sound data m4 while the sound is being reproduced, and the area A is the sound data. Rewritten to m5. Immediately before the end time t2 of the silent section, the tail address of the silent section is set as the shampoo source address JT, the leading address of the silent section is set as the jump destination address JD, and the address pointer AP circulates through the silent area, Is played. During this time, reading of the sound data of the channel from the HDD 60 is suspended. When reaching just before the end time t2 of the silent section, as shown in (v), the address of the silent area corresponding to the end time t2 of the silent section is set as the jump source address JT, and the top address of the area B is jumped. Set as the destination address JD. When the address pointer AP reaches the jump source address JT of the silent area, it jumps to the jump destination address JD as shown in (vi), and the reading of the sound data m4 is restarted from the head of the area B. As a result, the silent period ends, and the performance sound of the channel is reproduced. In addition, the region end address TE at the tail of the region B is set as the interrupt request generation address RT. When the address pointer AP reaches the area end address TE, the address pointer AP is returned to the area A as shown in (vii) and moved again from the head address, and the sound data m5 is read and reproduced. Also, when an interrupt request is generated, the area B is rewritten with the sound data m6, and the sound data m6 is read and reproduced after the reading of the sound data m5 is completed.
[0062]
Next, an example of address control in the case of repeat reproduction will be described. Here, as shown in FIG. 21, it is assumed that a section of t3 to t4 of a recorded song is repeatedly reproduced, and punch-in and punch-out are performed at times t5 to t6 in this section. m1 to m6 are sound data of one cluster each. The repeat reproduction start time t3 is a time in the middle of the sound data m1, and the repeat reproduction end time t4 is a time in the middle of the sound data m6. An example of address control of the SDRAMs 64 and 66 by the address generator 100 in the case of repeat reproduction as shown in FIG. 21 will be described with reference to the procedure diagram of FIG. When the punch-in / punch-out mode is selected in the recording / playback mode, areas A to D of four clusters of SDRAMs 64 and 66 are assigned to the performance channels 0 to 23 as shown in FIG. When repeat sections t3 to t4 and punch-in and punch-out sections t5 to t6 are instructed by the operator's operation, the HDD 60 is read out, and as shown in FIG. 22 (i), the cluster including time t3 is included. The sound data m1 is stored in the area A, and the cluster sound data m6 including the time t4 is stored in the area D. The sound data m1 and m6 at both ends of the repeat section are not rewritten during the repeat reproduction. In areas B and C, sound data m2 and m3 are respectively stored as shown in (i). The start address TS of the area A at the start address of the area A, the read start address RS at the address corresponding to the time t3 of the area A, the jump destination address JD at the end of the area A, the interrupt request generation address RT at the end of the area B, The jump source address JT is set at the tail and the area end address TE is set at the tail of the area D.
[0063]
When the repeat reproduction start is instructed, as shown in (ii), the address pointer AP advances one address at every sampling period from the read start address RS, and the sound data after the time t3 in the sound data m1. It is read and played. When the address pointer AP reaches the tail address of the area A, as shown in (iii), the sound data m2 of the area B is continuously reproduced as it is. When the time t5 in the middle of reproducing the sound data m2 is reached, the channel instructed to punch-in and punch-out is switched to the recording mode, and punch-in is executed. When the address pointer AP reaches the tail address of the area B, an interrupt request is generated, the sound data m4 is read from the HDD 60, and the area B is rewritten with the sound data m4 as shown in (iv). The address pointer AP moves as it is in the area B, and the reproduction of the sound data m3 and the recording of the input sound are continued. The interrupt request generation address RT is changed to the tail address of the area C. When the address pointer AP reaches the tail address of the area C, a jump occurs, and the address pointer AP is returned to the head address of the area B as shown in (v), and the sound data m4 is read. Also, an interrupt request is generated, the sound data m5 is read from the HDD 60, and the area C is rewritten with the sound data m5. The interrupt request generation address RT is set to the tail address of the area B. When the address pointer AP reaches the tail address of the area B, an interrupt request is generated, and the area B is rewritten with the sound data m2, as shown in (vi). The address pointer AP moves in the area C as it is, and the sound data m5 is reproduced. The interrupt request generation address RT is changed to the tail address of the area C. Further, the address corresponding to the time t4 in the area D is set as the jump source address JT, and the address corresponding to the time t3 in the area A is set as the jump destination address JD. When the time t6 in the middle of reproducing the sound data m5 is reached, the channel for which punch-in / punch-out has been instructed is returned to the reproduction mode, and punch-out is executed. When the address pointer AP reaches the tail address of the area C, an interrupt request is generated, and the area C is rewritten with the sound data m3 as shown in (vii). The address pointer AP moves in the area D as it is, and the sound data m6 is reproduced. The interrupt request generation address RT is changed to the tail address of the area B. When the address pointer AP reaches the address corresponding to the end time t4 of the repeat section, a jump occurs, and the address pointer AP returns to the address corresponding to the start time t3 of the repeat section of the area A as shown in (viii). Then, reproduction is performed again, and the above repeat reproduction, punch-in and punch-out operations are repeated. Note that a slight silence period may be formed before resuming playback from the address corresponding to time t3, and it may be easily recognized that the position has returned to the start position of the repeat section.
[0064]
Finally, write and read address control of the SDRAMs 64 and 66 in the DMA transfer by the DMA address generator 102 of FIG. 10 will be described. A configuration example of the DMA address generator 102 for one channel is shown in FIG. The DMA address generator 102 includes a counter 146. When an interrupt request for DMA transfer is generated, the recorder CPU 14 selects one of the areas A and B of the corresponding channels of the SDRAMs 64 and 66 (areas B and C in the case of repeat reproduction) on the side that performs the DMA transfer this time. The start address is set in the counter 146. The increment input INC of the counter 146 receives a signal indicating the remaining 3/4 period of the sampling period output from the OR circuit 96 of FIG. 7 (that is, the period in which DMA transfer is performed), and 512 is input to the clock input CK. A clock obtained by dividing the divided clock by 1/4 is input. As a result, the counter 146 counts up every 4 divided 512 clocks during the DMA transfer period, and the count value is input to the SDRAMs 64 and 66 as address information, and sample data is read from the corresponding address to the HDD 60. Sample data DMA-transferred or DMA-transferred from the HDD 60 is written at the address.
[0065]
In the above embodiment, the case where the buffer memory is configured by SDRAM has been described. However, other types of memories can be used. In the above embodiment, the external storage device is an HDD. However, an optical disk device, a magneto-optical disk device, and other external storage devices can also be used. In the above-described embodiment, the case where the present invention is applied to a recording / reproducing apparatus incorporating an external storage device has been described. However, the recording / reproduction using the external storage device externally via an interface board such as SCSI is used. The present invention can also be applied to an apparatus. In the above embodiment, the case where the present invention is applied to a digital mixing recorder (hard disk recorder) has been described. However, the present invention can be applied to a digital recorder that does not have a mixing function and other various sample data reproduction apparatuses. it can.
[Brief description of the drawings]
1 is a diagram showing an embodiment of the present invention, and is a block diagram showing a configuration example of a track address generator of FIG.
FIG. 2 is an explanatory diagram of repeat reproduction in a hard disk recorder.
FIG. 3 is a block diagram showing a system configuration of a main part of the entire hard disk recorder to which the present invention is applied.
4 is a diagram illustrating an example of division of an address area of the HDD 60 in FIG. 3;
5 is a block diagram showing extracted main parts involved in the exchange of sound data, system management data, and song management data in the entire system configuration of the hard disk recorder of FIG. 3;
6 is a time chart showing an example of dividing the right to use bus 56 in the hard disk recorder of FIG. 3 and an example of dividing write / read processing of SDRAM within a sampling period in the recording / playback mode.
7 is a control system block diagram of time-sharing control of the right to use bus 56 in the hard disk recorder of FIG. 3. FIG.
8 is a time chart showing the operation of the control system of FIG.
9 is a diagram showing a DMA transfer procedure (protocol) for one playback channel by the control system of FIG. 7; FIG.
10 is a block diagram showing a specific example of the signal path configuration of sample data and the signal path configuration of address information of SDRAMs 64 and 66 in the DRC 68 of FIG. 3;
FIG. 11 is a diagram showing an example of an address map of SDRAMs 64 and 66 during normal recording and reproduction.
12 is a time chart showing a part of control signals of SDRAMs 64 and 66 when executing the sequence of Table 2. FIG.
FIG. 13 is a diagram showing an example of an address map of SDRAMs 64 and 66 at the time of punch-in and punch-out.
14 is a diagram showing an address map of the track address RAM 118 of FIG. 1. FIG.
FIG. 15 is a time chart showing an example of dividing the usage time of the address calculation circuit 134 assigned to each channel;
FIG. 16 is a flowchart showing the address calculation procedure of one performance channel (reproduction channel) by the address calculation circuit 134 in the first sampling period when reproduction is started.
FIG. 17 shows the address of one performance channel (playback channel) by the address calculation circuit 134 that is repeated every sampling cycle from the sampling cycle next to the first sampling cycle when playback is started until the stop operation is performed. It is a flowchart which shows a calculation procedure.
FIG. 18 is a diagram showing an example of movement of the address pointer of the SDRAM 64 or 66 for one performance channel (reproduction channel) during normal recording and reproduction.
FIG. 19 is a diagram showing a time chart showing an example of performance in which a silent section is set, and recording data of an HDD that records the performance sound.
20 is a procedure diagram showing an example of address control of the SDRAMs 64 and 66 by the address generator 100 when a recorded part including the silent section of FIG. 19 is reproduced.
FIG. 21 is a time chart showing an example of setting a repeat playback section in punch-in and punch-out.
22 is a procedure diagram showing an example of address control of the SDRAMs 64 and 66 by the address generator 100 at the time of repeat reproduction of FIG.
23 is a block diagram illustrating a configuration example of the DMA address generator 102 of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Hard disk recorder (sample data reproduction device), 64, 66 ... SDRAM (buffer memory), 60 ... HDD (external storage device), 100 ... Track address generator (buffer memory control circuit) 118 ... Track address RAM (jump address setting) Circuit, address memory), 134... Address arithmetic circuit (read address arithmetic circuit).

Claims (2)

The sample data stored in the external storage device is sequentially read out in predetermined unit intervals and written into the buffer memory. The sample data is read out from the buffer memory one sample at a time for each sampling period and reproduced. In the sample data reproduction device for sequentially updating the sample data by successively updating the unit data with the new sample data read out from the external storage device for each unit interval,
When repeatedly reproducing sample data of an arbitrary section spanning a plurality of unit sections, each sample data of a unit section including at least a head portion of the repeated section and a unit section including the tail portion of the repeated section is stored in the external Read from the storage device and store it in a predetermined area of the buffer memory. During playback, the sample data of the unit section of the intermediate part is sequentially read from the external storage device and sequentially updated and stored in another area of the buffer memory. The jump source address and the jump destination address of the address jump necessary to continuously and repeatedly reproduce the repeated section are sequentially set at an appropriate time when sample data is read from the buffer memory one sample at a time. And the read address of the buffer memory is the set jump source address And detecting the arrival, to jump the read address to the jump destination address, sample data reproducing apparatus comprising comprises a buffer memory control circuit to continue the reading of sample data from the jump destination address. The sample data stored in the external storage device is sequentially read out in predetermined unit intervals and written into the buffer memory. The sample data is read out from the buffer memory one sample at a time for each sampling period and reproduced. The sample data that has been completed is updated sequentially for each unit interval with new sample data that is read from the external storage device, the sample data is reproduced continuously, and the sample is input separately in a time-sharing manner in parallel with the reproduction. Data is written to the buffer memory one sample at each sampling period, the sample data written to the buffer memory is read from the buffer memory in predetermined unit intervals, written to the external storage device, and the reading of the buffer memory is completed. New sample data entered That the sample data are sequentially updated, the sample data recording and reproducing apparatus for continuously recording the sample data,
When repetitively reproducing sample data of an arbitrary section across a plurality of unit sections and recording separately input sample data in an appropriately designated section within the repeated section, at least a head portion of the repeated section is previously stored. Each sample data of the unit interval including the unit interval included and the tail portion of the repetition interval is read from the external storage device and stored in a predetermined area of the buffer memory, and the sample data of the unit interval of the intermediate portion during reproduction Are sequentially read from the external storage device, sequentially updated and stored in another area of the buffer memory, and the repetition interval is continuously performed at an appropriate time during reading of sample data sample by sample from the buffer memory. And the jump source address and jump destination address of the address jump necessary for repeated playback The buffer memory read address reaches the set jump source address, jumps the read address to the jump destination address, and reads the sample data from the jump destination address. In the interval instructed to record during the playback, the sampled data, which is input separately, is written into the buffer memory for each sampling period by the playback operation and time division, and written to the buffer memory. A buffer memory control circuit for reading sample data from the buffer memory in predetermined unit intervals and writing them to the external storage device and sequentially updating the sample data that has been read from the buffer memory with newly input sample data; A sample data recording / reproducing apparatus.

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