JP3692761B2 - Printed circuit board manufacturing method and printed circuit board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a printed board such as a so-called multilayer printed board (built-up board) on which an electronic component such as a bare chip is mounted, and the printed board.
[0002]
[Prior art]
In general, in electronic devices, printed circuit boards for mounting circuit elements such as various electronic components are used. Due to recent demands for downsizing and higher integration of devices and circuit elements, printed circuit boards are used. There is a demand for miniaturization of itself and miniaturization of wiring patterns.
At present, the line width and inter-line width of the wiring pattern of the printed circuit board are on the order of about 100 μm. However, as a future trend, the above-mentioned line width and inter-line width are 20 to 50 μm for further miniaturization. Something of the order is required. Here, a conventional method for manufacturing a printed circuit board will be described with reference to FIGS.
[0003]
First, as shown in FIG. 8A, a predetermined wiring pattern 2 is formed by forming a copper foil or the like on the surface of an insulating core material 1 made of, for example, a glass epoxy resin and patterning it. At present, the line width L1 and the line width L2 of the wiring pattern 2 are at least about 100 μm, and the thickness W1 is about 20 μm. The surface of the wiring pattern 2 is oxidized and blackened to increase the degree of adhesion with the epoxy resin layer in the subsequent process.
[0004]
Next, as shown in FIG. 8B, the first insulating layer 3 and the second insulating layer 4 as shown in FIG. 8C are applied to the entire surface of the core material 1 by screen printing or the like. Are sequentially applied and formed.
FIG. 9 shows an enlarged view of a portion A in FIGS. 8C and 8D, and the main material of the insulating layers 3 and 4 is made of, for example, an epoxy resin. As shown in FIG. 9, in the first insulating layer 3, an appropriate amount of SiO ₂ filler 5 having a particle diameter L3 of approximately 1 μm is mixed as an inorganic filler in order to improve the insulating characteristics, and its thickness is increased. T1 is set to about 50 μm (see FIG. 8C). The second insulating layer 4 is mixed with an appropriate amount of CaCO ₃ filler 6 having a particle size L4 of approximately 10 μm as an inorganic filler to be dissolved in the roughening step described later, and its thickness T2 is It is set to about 20 μm.
[0005]
Next, as shown in FIG. 8D, the connection holes 8 are selectively formed so as to penetrate the first and second insulating layers 3 and 4 using, for example, carbon dioxide laser light 7 in the electrical connection portion. Then, the internal wiring pattern 2 is exposed. The diameter D1 of the hole 8 is about 100 μm.
Next, as shown in FIG. 8E, an alkaline roughening solution such as a potassium permanganate solution is allowed to act on the surface of the second insulating layer 4 so that the CaCO ₃ exposed on the surface is exposed. The inorganic filler 6 is dissolved to form a large number of uneven portions 9 to roughen the surface of the insulating layer 4. FIG. 10 is an enlarged view showing a portion B in FIG.
Further, in the connection hole 8, scrap generated when drilling with the laser beam 7 remains as a residue 10 (see FIG. 8D), but due to the action of the potassium permanganate solution, This residue 10 is cleaned and removed.
[0006]
Next, as shown in FIG. 8 (F), in order to make a base for electroless plating in the next step, for example, a solution obtained by dissolving tin and palladium is allowed to act on the surface of the insulating layer 4 to adhere the catalysis 12. The conduction of the entire surface of the insulating layer is intended.
Next, as shown in FIG. 8G, an electroplating conductive film 13 made of copper or the like is formed over the entire surface of the insulating layer 4 by electroless plating, for example, until the thickness becomes about 0.3 μm.
Further, as shown in FIG. 8H, a conductive film 14 made of, for example, copper is formed on the electroplating conductive film 13 by electroplating to a thickness of about 20 μm. Thereby, conduction between the conductor film 14 and the lower wiring pattern 2 can be achieved. In a normal process, after this, after forming an insulating layer, patterning of wiring is performed again, and the printed circuit board of each layer is manufactured by repeating the above-mentioned process.
[0007]
[Problems to be solved by the invention]
Incidentally, in the manufacturing method described above, in order to reduce the line width or the line width of the wiring pattern 2 to 50 μm or less, it is necessary to make the insulating layers 3 and 4 thinner and accordingly the diameter of the connection hole 8 to be smaller. Thus, it was very difficult to form a good printed circuit board. The reason is that since the diameter L4 of the inorganic filler 6 contained in the second insulating layer 4 is about 10 μm, this dimension is too large compared to the line width and the like, and it is very easy to form a pattern in a straight line with high accuracy. It becomes difficult.
On the other hand, it is conceivable to reduce the diameter of the inorganic filler 6, but in this case, the catalysis solution cannot sufficiently enter the concavo-convex portion 9 and cannot be employed.
[0008]
In addition, as described above, it is desirable that the diameter of the connection hole 8 is set to 50 μm or less as the size of the hole is reduced. When the hole diameter is reduced, potassium permanganate liquid or catalysis liquid is contained in the hole 8. In some cases, it becomes difficult to penetrate and the residue 10 cannot be sufficiently removed, and the conductive film 14 formed by plating and the underlying pattern 2 may not be sufficiently connected.
Furthermore, in the manufacturing method described above, not only the two insulating layers 3 and 4 are required, but also a wet process using a large amount of alkaline potassium permanganate solution or catalysis solution is employed. A cleaning process is necessary, and the number of processes increases as a whole, resulting in high costs. In addition, since the inorganic filler 6 made of CaCO ₃ has a strong hygroscopic property, there is a possibility that the moisture is absorbed every time wet processing is performed and the insulating performance is deteriorated.
[0009]
The present invention focuses on the above-described problems and was devised to effectively solve this problem. Its purpose is to form a fine pattern with a small number of steps by using dry etching or sputter deposition. Another object of the present invention is to provide a printed circuit board manufacturing method and a printed circuit board.
[0010]
[Means for Solving the Problems]
The present invention, in order to solve the above problems, forming a surface pattern width 100μm or less of the wiring pattern including the wiring pattern of the core material, the surface in the following 1μm of the core material containing the wiring pattern A step of forming an insulating layer made of an organic resin mixed with an inorganic filler , a step of selectively forming a connection hole reaching the wiring pattern in the insulating layer, and an oxygen partial pressure of 0.05 to 0.1 Torr. The step of removing the organic resin on the surface of the insulating layer by dry etching with a range of 1 to roughen the surface of the inorganic filler into a convex rough surface protruding, and the inorganic filler by vacuum film formation. A step of forming a conductive film for electroplating on the surface of the insulating layer, and a step of forming a conductive film on the conductive film for electroplating by electroplating. is there.
[0011]
As a result, it is possible to form a printed circuit board in which the line width and the line-to-line width are miniaturized with fewer steps than in the conventional method, without increasing the number of steps. In this case, if a filler removing step for removing the inorganic filler exposed on the surface of the insulating layer is included between the roughening step and the electroplating conductive film forming step, The free filler that is about to fall off from the surface of the insulating layer can be eliminated, and the adhesiveness between the electroplating conductive film and the surface of the insulating layer can be improved accordingly.
[0012]
Furthermore, after the roughening step, the surface of the insulating layer is further finely roughened by performing a fine roughening step of roughening the surface of the insulating layer by dry etching. It is possible to further improve the adhesion between this and the electroplating conductive film.
[0013]
For example, reactive ion etching under a high oxygen partial pressure can be used for the dry etching, and the fine roughening step can be performed by reactive ion etching under a low oxygen partial pressure.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, an embodiment of a printed circuit board manufacturing method and a printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings.
The same components as those of the conventional printed circuit board described with reference to FIGS. 8 to 10 will be described with the same reference numerals.
FIG. 1 is a process diagram showing a method of manufacturing a printed circuit board according to the present invention, FIG. 2 is an enlarged view showing a portion C in FIG. 1, and FIG. 3 is an enlarged view showing a portion D in FIG. The feature of the method of the present invention is that the wet process is only an electroplating process and a free filler removing process, and the other processes are performed using dry etching or sputtering.
[0015]
First, as shown in FIG. 1A, a predetermined wiring pattern 2 is formed by forming a copper foil or the like on the surface of an insulating core material 1 made of, for example, a glass epoxy resin and patterning it. The line width L5 and the line-to-line width L6 of the wiring pattern 2 are about 25 to 50 μm, respectively, and are made finer than the conventional printed circuit board. The thickness W2 of the pattern 2 is about 20 μm. The surface of the wiring pattern 2 is oxidized and blackened to increase the degree of adhesion with the epoxy resin layer in the subsequent process. The line width L5 and the inter-line width L6 of the wiring pattern 2 may be set to the line width L1 and the inter-line width L2 shown in the prior art without being set to the above-mentioned widths, and the dimensions are not limited. .
[0016]
Next, as shown in FIG. 1B, the insulating layer 3 is applied and formed on the entire surface of the core material 1 using a method such as screen printing. The insulating layer 3 is made of the same material as the first insulating layer 3 described above. That is, as shown in FIG. 2, the main material of the insulating layer 3 is made of, for example, an epoxy resin. In this insulating layer 3, an appropriate amount of SiO ₂ filler 5 having a particle diameter L 3 of approximately 1 μm is mixed as an inorganic filler in order to improve the insulating characteristics, and its thickness T 3 is set to about 20 to 30 μm. It is formed to be considerably thinner than about 50 μm of the conventional printed circuit board.
[0017]
Next, as shown in FIG. 1C, a connection hole 8 is selectively formed in the electrical connection portion so as to penetrate the insulating layer 3 using, for example, a laser beam 7, and the internal wiring pattern 2 is formed. Expose. The diameter D2 of the hole 8 is about 20 to 50 μm, and is set to be considerably smaller than that of the conventional printed circuit board.
[0018]
Next, the entire core material is introduced into a dry etching apparatus and subjected to a dry etching process as shown in FIG. 1 (D), whereby the surface of only the insulating layer 3 which is an organic material is scraped and removed by a slight thickness. To do. In this case, as shown in FIG. 3, the inorganic filler 5 which is an inorganic substance is not removed by dry etching but remains partly exposed, and as a result, irregularities appear on the entire surface and are roughened. Become.
In order to perform the etching process at this time, an ordinary RIE (reactive ion etching) apparatus using a high-frequency power source for plasma formation may be used, and O ₂ gas is used as an etching gas to dry-etch organic substances. Further, in order to increase the etching rate, it is performed under a high oxygen partial pressure. Although this oxygen partial pressure depends on the target etching rate, it may be set, for example, to about 0.05 to 0.1 Torr.
[0019]
Further, in the connecting hole 8 debris generated during the drilling by a laser beam 7 remains becomes residue 10 (see FIG. 1 (C)) but, H ₂ O and CO by the dry etching process is decomposed into _two, the residue 10 is removed.
[0020]
Next, the entire core material is introduced into a sputtering film forming apparatus using a vacuum film forming method to perform sputtering film formation, and the surface of the insulating layer 3 and the inner wall surface of the hole 8 as shown in FIG. The electroconductive film 13 for electroplating made of copper or the like is formed over the entire surface until, for example, the thickness becomes about 0.3 μm. As this sputtering apparatus, for example, a DC magnetron sputtering film forming apparatus can be used, and Ar gas can be used as the plasma gas. The film formation of the electroplating conductive film 13 is not limited to the case where it is performed using a sputtering film forming apparatus, and any film forming method may be used as long as it is a vacuum film forming method.
Next, as shown in FIG. 1 (F), a conductive film 14 made of, for example, copper is formed on the electroplating conductive film 13 by electroplating to a thickness of about 10 μm. Thereby, conduction between the conductor film 14 and the lower wiring pattern 2 can be achieved. In a normal process, after this, after forming an insulating layer, patterning of wiring is performed again, and a multilayer printed board (built-up board) is manufactured by repeating the above-described process.
[0021]
As described above, according to the method of the present invention, the wet process is performed only by the electroplating process shown in FIG. 1 (F) and the free filler removing process (FIG. 4) described later, and no liquid is used in other processes. Since it is a dry process, many washing steps and neutralization steps required in the conventional method can be eliminated.
In addition, although the conventional method uses two or more insulating layers, one insulating layer can be used in the method of the present invention.
Accordingly, it is possible to manufacture a printed circuit board having a miniaturized wiring pattern without increasing the number of processing steps as compared with the case of the conventional method, but rather reducing it.
[0022]
Furthermore, since it is not necessary to use the water-absorbing CaCo ₃ filler used in the conventional method, the insulating property can be improved accordingly.
In the above embodiment, the electroconductive film 13 for electroplating is formed as shown in FIG. 1 (E) with the inorganic filler 5 partially exposed on the surface of the insulating layer 3 as shown in FIG. In this case, it is considered that the partially exposed inorganic filler 5 is detached from the surface of the insulating layer 3 in a later step or the like, and is released, and when this free filler is generated, the insulating layer 3 and the upper layer are separated. The adhesiveness of the electroplating conductive film 13 may deteriorate. Therefore, before forming the electroplating conductive film 13, it is preferable to incorporate a free filler removing step of removing the inorganic filler 5 from which part of the conductive film 13 is exposed. In this free filler removing step, as shown in FIG. 4, the entire core material after the dry etching step is immersed in pure water, and ultrasonic cleaning is performed by applying ultrasonic waves thereto. FIG. 5 is an enlarged view showing a portion E in FIG. As a result, the inorganic filler 5 that is partially exposed on the surface of the insulating layer 3 falls off and is removed as free filler 5A. Moreover, the recessed part 15 will be formed in the part from which the inorganic type filler 5 fell, and, thereby, the whole surface of the insulating layer 3 becomes uneven | corrugated and is maintained in the roughened state.
[0023]
In this state, if the electroconductive film 13 for electroplating as shown in FIG. 1E is formed on the surface of the insulating layer 3 by a sputtering film forming apparatus, the deterioration of the adhesion due to the above-described free filler 5A can be prevented. And higher adhesion can be obtained.
Furthermore, in order to further improve the adhesion, the removal of the free filler 5A as shown in FIG. 6 is not performed, instead of the above-described process in which the electroplating conductive film 13 is directly formed on the insulating layer 5 shown in FIG. You may make it perform the fine roughening process which roughens the surface of the subsequent insulating layer 3 further finely. FIG. 7 is an enlarged view showing a portion F in FIG. Note that this fine roughening step may be performed after the step shown in FIG.
[0024]
In this fine roughening step, the surface of the insulating layer 3 made of an organic substance is described with reference to FIG. 1D in order to perform a dry etching process at a smaller etching rate than the dry etching shown in FIG. Reactive ion etching similar to the above is performed. In this dry etching, in order to reduce the etching rate, the O ₂ gas partial pressure is lowered and the treatment is performed under a low oxygen partial pressure. The oxygen partial pressure at this time is set to a pressure of 0.05 Torr or less, and the lower limit value is a limit value at which plasma is generated, for example, about 0.003 Torr.
Thus, by performing reactive ion etching under a low oxygen partial pressure, very fine uneven portions, that is, fine uneven portions 16 are formed on the surface of the insulating layer 3. Therefore, when the electroplating conductive film 13 is directly formed on the fine irregularities 16 by the sputtering film forming apparatus, the adhesion between the two can be further improved.
[0025]
In the above-described embodiment, the case where SiO ₂ particles are used as the inorganic filler 5 has been described as an example. However, the inorganic filler 5 is not limited to this as long as it is a material that cannot be scraped off by dry etching, and other inorganic materials may be used. Of course. In addition, the dimensions of the respective members are merely examples, and of course are not limited thereto.
[0026]
【The invention's effect】
As described above, according to the printed circuit board manufacturing method and the printed circuit board of the present invention, the following excellent operational effects can be exhibited.
By using dry etching or vacuum film formation (sputtering), a printed circuit board having a miniaturized wiring pattern can be manufactured without increasing the number of steps or with the number of steps reduced. Therefore, it is possible to provide an inexpensive fine pattern printed circuit board that does not cause an increase in cost.
Further, by removing the inorganic filler exposed on the surface of the insulating layer to eliminate the free filler, the adhesion between the insulating layer and the upper conductor film can be improved.
Furthermore, the adhesion between the insulating layer and the upper conductor film can be further improved by performing a fine roughening step for finely roughening the surface of the insulating layer.
[Brief description of the drawings]
FIG. 1 is a process diagram showing a method for producing a printed circuit board according to the present invention.
FIG. 2 is an enlarged view showing a portion C in FIG.
FIG. 3 is an enlarged view showing a D portion in FIG. 1;
FIG. 4 is a diagram for explaining a modification of the method of the present invention.
FIG. 5 is an enlarged view showing an E portion in FIG. 4;
FIG. 6 is a diagram for explaining another modification of the method of the present invention.
7 is an enlarged view showing a portion F in FIG. 6. FIG.
FIG. 8 is a diagram for explaining a conventional method of manufacturing a printed circuit board.
FIG. 9 is an enlarged view showing a portion A in FIGS. 8C and 8D.
FIG. 10 is an enlarged view showing a portion B in FIG.
[Explanation of symbols]
1 ... core material, 2 ... wiring pattern, 3: insulating layer (first insulating layer), 5 ... SiO ₂ filler (inorganic filler), 7 ... laser light, 8 ... connecting hole, for conduction 13 ... electroplating Membrane, 14 ... conductor membrane.

Claims (4)

Forming a wiring pattern including a wiring pattern having a pattern width of 100 μm or less on the surface of the core material;
Forming an insulating layer made of an organic resin mixed with an inorganic filler of 1 μm or less on the surface of the core material including the wiring pattern;
Selectively forming connection holes reaching the wiring pattern in the insulating layer;
A step of removing the organic resin on the surface of the insulating layer by dry etching with an oxygen partial pressure in the range of 0.05 to 0.1 Torr to roughen the surface to a convex rough surface from which a part of the inorganic filler protrudes. When,
Forming a conductive film for electroplating on the surface of the insulating layer containing the inorganic filler by vacuum film formation;
Forming a conductor film on the electroconductive film for electroplating by electroplating. Performing a filler removing step of removing the inorganic filler released from the surface of the insulating layer by ultrasonic cleaning between the roughening step and the step of forming the electroplating conductive film. The method for producing a printed circuit board according to claim 1. After the roughening step, the surface of the insulating layer is subjected to a fine roughening step of further finely roughening by dry etching with an oxygen partial pressure in the range of 0.003 to 0.05 Torr. A method for producing a printed circuit board according to claim 1 or 2. Core material,
  A wiring pattern including a wiring pattern having a pattern width of 100 μm or less formed on the surface of the core material;
  An insulating layer made of a resin mixed with an inorganic filler of 1 μm or less formed on the surface of the core material including the wiring pattern;
  A connection hole selectively formed so as to reach the wiring pattern in the insulating layer;
  A conductive film for electroplating formed on the insulating layer including the connection hole;
  A conductive film formed on the electroconductive film for electroplating,
  The boundary surface of the insulating layer in contact with the electroplating conductive film is a convex rough surface in which a part of the inorganic filler protrudes from the insulating layer and contacts the electroplating conductive film. Printed circuit board.

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