JP2013149810A - Manufacturing method of multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a multilayer wiring board which enables a gap between the outermost layer of a resin insulation layer and an IC chip to be unfailingly sealed with an underfill material.SOLUTION: A resin insulation layer 25 on the outermost layer, forming a multilayer wiring board, is composed mainly of the same resin insulation material as resin insulation layers on the inner layer side and includes a silica filler 57. In a drilling step, laser hole processing is performed to the resin insulation layer 25 on the outermost layer thereby forming openings 43 exposing connection terminals 41. In a desmear process, smears in each opening 43 are removed. In a subsequent filler increase process, the silica filler 57 exposed on a surface of the resin insulation layer 25 is increased.

Description

  The present invention relates to a method for manufacturing a multilayer wiring board in which a plurality of resin insulation layers and a plurality of conductor layers are alternately laminated to form a multilayer.

  In recent years, IC chips used as computer microprocessors have become increasingly faster and more functional, and this has been accompanied by an increase in the number of terminals and a narrower pitch between terminals. In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a semiconductor package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the semiconductor package is mounted on a motherboard.

  As an IC chip mounting wiring board constituting this type of package, a multilayer wiring board in which build-up layers are formed on the front surface and the back surface of a core substrate has been put into practical use. In this multilayer wiring substrate, for example, a resin substrate (such as a glass epoxy substrate) in which a reinforcing fiber is impregnated with a resin is used as a core substrate. Then, by utilizing the rigidity of the core substrate, a buildup layer is formed by alternately laminating a resin insulating layer and a conductor layer on the front surface and the back surface of the core substrate. That is, in this multilayer wiring board, the core board plays a role of reinforcement and is formed much thicker than the build-up layer. In addition, wiring (specifically, a through-hole conductor or the like) is formed through the core substrate for conduction between buildup layers formed on the front surface and the back surface.

  In recent years, with the increase in the speed of semiconductor integrated circuit elements, the signal frequency used has become a high frequency band. In this case, the wiring penetrating the core substrate contributes as a large inductance, leading to transmission loss of high-frequency signals and circuit malfunction, which hinders speeding up. In order to solve this problem, it has been proposed that the multilayer wiring board is a board that does not have a core board (see, for example, Patent Document 1). Since the multilayer wiring board described in Patent Document 1 is obtained by shortening the entire wiring length by omitting a relatively thick core board, the transmission loss of high-frequency signals is reduced, and the IC chip is operated at high speed. It becomes possible.

  By the way, in the multilayer wiring board of Patent Document 1, the outermost resin insulation layer on the IC chip mounting surface side is formed using the same resin material as the resin insulation layer on the inner layer side. In addition, in this type of multilayer wiring board, silica filler is used in the resin material for the purpose of improving the adhesion to the electroless plating layer formed on the resin insulating layer or reducing the coefficient of thermal expansion. A resin insulation layer formed by adding may be used. Further, in the multilayer wiring board, a connection terminal for connecting an IC chip is formed on the outermost resin insulation layer, and the IC chip is flip-chip connected to the connection terminal via a solder bump. The gap between the outermost resin insulation layer and the IC chip is filled with an underfill material, which is a liquid thermosetting resin, in order to improve the thermal fatigue life of the solder bumps.

  Here, since the resin insulating material and the underfill material constituting the resin insulating layer are mainly organic materials, they are basically hydrophobic. On the other hand, since the silica filler which comprises a resin insulating layer is an inorganic oxide material, it has hydrophilicity fundamentally. The underfill material supplied on the outermost resin insulating layer tends to flow when the insulating layer surface has high hydrophobicity, and conversely, when the hydrophilicity of the insulating layer surface is high, it tends to be difficult to flow. Incidentally, the flowability of the underfill material on the surface of the insulating layer depends on the amount of silica filler exposed on the surface of the insulating layer, for example. That is, if the amount of the silica filler is small, the hydrophobicity of the insulating layer surface is increased, and as a result, the flowability is improved. On the other hand, when the amount of the silica filler is large, the hydrophilicity of the insulating layer surface is increased, resulting in poor flowability.

JP 2009-117703 A

  By the way, in the conventional method of manufacturing a multilayer wiring board, in order to form a via conductor in the outermost resin insulation layer, a drilling process for forming an opening is usually performed by laser drilling, followed by a desmear liquid treatment. A desmear process for removing smear in the opening is performed. However, when such desmear treatment is performed, the outermost resin insulation layer is also affected by the chemical solution at the same time, and therefore, silica filler exposed on the surface of the insulation layer is often easily dropped off. As a result, the abundance of the silica filler decreases, and the hydrophobicity of the insulating layer surface may become excessively high. And in this case, the flow of the underfill material becomes too good, and as a result of the underfill material spreading out wet beyond the sealing range, the gap between the outermost resin insulation layer and the IC chip is reliably filled, There is a possibility that sealing cannot be performed. Therefore, in order to ensure the sealing property of the underfill material, it is necessary to make the surface of the insulating layer an appropriate hydrophilic surface. In this case, in order to adjust the surface of the insulating layer to a desired state, a method capable of accurately controlling the abundance of the silica filler exposed on the surface of the outermost resin insulating layer is indispensable.

  The present invention has been made in view of the above problems, and its purpose is to manufacture a multilayer wiring board capable of reliably sealing a gap between the outermost resin insulation layer and a chip component with an underfill material. It is to provide a method.

  As means (means 1) for solving the above-mentioned problem, a multilayer structure in which a plurality of resin insulation layers and a plurality of conductor layers are alternately stacked to form a multilayer structure is provided. The outermost resin insulation layer formed on the chip mounting surface side on which the substrate is mounted is composed mainly of the same resin insulation material as the inner resin insulation layer and includes a filler made of an inorganic oxide, A method for manufacturing a multilayer wiring board in which a gap between a resin insulating layer and the chip component is sealed with an underfill material, and by applying laser hole processing to the outermost resin insulating layer, a conductor portion is formed. A hole forming step for forming an opening to be exposed, a desmear step for removing smear in the opening after the hole forming step, and a surface of the outermost resin insulation layer after the desmear step. There are a method of manufacturing the multilayer wiring board, which comprises a filler increasing step of increasing the serial filler.

  Therefore, according to the invention described in the means 1, the opening is formed in the outermost insulating resin layer in the drilling process, and the smear in the opening is removed in the desmear process. Thereafter, by performing the filler increasing step, it is possible to increase the amount of filler exposed on the surface of the outermost resin insulating layer. Therefore, even if the amount of filler exposed on the surface of the insulating layer after passing through the desmear process is small, it can be adjusted by increasing it appropriately, and the surface of the insulating layer is made an appropriate hydrophilic surface. be able to. Therefore, the flowability of the underfill material is easily optimized, and the gap between the outermost resin insulating layer and the chip component can be reliably sealed with the underfill material.

  In the manufacturing method described above, a laser drilling process is performed on the outermost resin insulation layer to partially remove the resin insulation layer, thereby forming an opening that exposes the conductor in the inner layer. Do. There are various kinds of such conductor parts, and there is no particular limitation. For example, a connection terminal for connecting an IC chip can be cited as a preferred example. The conductor portion may be a connection terminal for connecting a chip component (for example, a chip resistor, a chip capacitor, a chip inductor, a chip coil, etc.) other than the IC chip. A columnar terminal may be formed on such a connection terminal so that a part of the connection terminal protrudes from the outermost resin insulating layer. The conductor portion is not limited to the one intended for electrical connection with the electronic component, and may be one not intended for electrical connection (for example, a positioning conductor portion).

  After the drilling process, a desmear process is performed to remove smear in the opening caused by laser irradiation. Specifically, the smear is dissolved and removed by wet etching with a desmear solution.

  After the desmear process, a filler increasing process for increasing the filler exposed on the surface of the outermost resin insulation layer is performed. As a preferable specific example of the filler increasing step, for example, a dry etching process in which the resin insulating material forming the surface of the outermost resin insulating layer is selectively removed to expose the filler can be mentioned. This is because, generally, the dry etching process is easier to control the processing conditions than the wet etching process. Accordingly, it is possible to set appropriate processing conditions, and as a result, it is possible to selectively remove the resin insulating material while suppressing the dropout of the filler. As another filler increasing step, filler fixing treatment for fixing a filler on the surface of the outermost resin insulating layer can be mentioned. However, when the filler fixing process and the dry etching process are compared, the latter is preferable in that the process can be reliably and easily performed compared to the former. The latter is also preferable in that the surface of the filler itself can be activated and hydrophilized.

  The dry etching process is a technique of etching a material with a reactive gas or an ionized / radicalized gas, and a preferable specific example thereof is a plasma process. Other examples include reactive ion etching (RIE) and ion milling.

  When dry etching treatment is performed, conditions may be set such that the etching amount of the outermost resin insulation layer is about half the average particle diameter of the filler, specifically, 40% to 60%. Good. If it is less than 40%, the processing conditions become too weak and the resin insulating material around the filler cannot be sufficiently removed. Therefore, it may be difficult to sufficiently increase the filler exposed on the surface of the insulating layer. However, if it exceeds 60%, the processing conditions become too strong and the resin insulating material around the filler is excessively removed. Therefore, the exposed filler tends to fall off, and as a result, it may be difficult to increase the filler sufficiently. Here, for example, assuming that the average particle diameter of the filler is about 2 μm, the etching amount of the outermost resin insulating layer is preferably set so that the thickness is 0.8 μm or more and 1.6 μm or less. . In addition, assuming that the average particle size of the filler is about 0.5 μm, the etching amount of the outermost resin insulating layer is preferably set to have a thickness of 0.2 μm or more and 0.3 μm or less. .

  The filler increasing step may be performed immediately after the desmear process, but for example, high-pressure water washing may be performed after the desmear process and before the filler increasing process. When the high-pressure water washing treatment is performed, not only the desmear liquid is washed away, but also the filler exposed on the surface of the insulating layer that has a weak adhesion can be washed off. For this reason, there exists an advantage that a filler becomes difficult to drop | omit in the process after a filler increase process.

  When the high-pressure water washing treatment is performed, surface plating may be performed at a stage after the high-pressure water washing treatment and before the filler increasing step. If surface plating is performed at a stage before the high-pressure water washing treatment, the plating solution is deteriorated at an early stage due to mixing of the filler that has fallen off from the surface of the insulating layer. Further, when surface plating is performed in a situation where the filler has fallen off, problems such as plating depositing at unintended locations are likely to occur, making it difficult to obtain a highly reliable plating layer. On the other hand, if surface plating is performed at a stage after the high-pressure water washing treatment and before the filler increasing process, early deterioration of the plating solution is avoided and the cost is improved, and the reliability of the formed plating layer is also improved. .

  Since the plating layer formed by surface plating is made of metal such as copper, nickel / gold, etc., in order to improve the adhesion between the plating layer and the insulating layer surface, the insulating layer surface must be If anything, it is preferable to have a hydrophobic surface. If surface plating is performed at a stage after the filler increasing step, many fillers are exposed on the surface of the insulating layer and hydrophilicity is increased, which is disadvantageous for improving the adhesion. On the other hand, if surface plating is performed before the filler increasing step, the amount of filler exposed on the surface of the insulating layer is still small, so that the plating can be performed on the hydrophobic surface. Therefore, it is possible to form a highly reliable plating layer with excellent adhesion to the insulating layer surface. Moreover, in such a procedure, since the filler increasing step is performed in a state where a part of the insulating layer surface is covered with the plating layer, only the uncovered area is selectively made an appropriate hydrophilic surface. It is possible and convenient.

  The plurality of resin insulation layers constituting the laminated structure can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Preferred examples of the polymer material for forming each resin insulation layer include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, polyimide resins, polycarbonate resins, acrylic resins, polyacetal resins, polypropylene resins. And other thermoplastic resins. Moreover, as a filler contained in a resin insulating layer, the filler which consists of inorganic oxides, such as a silica, a titania, an alumina, is mentioned. In particular, since the silica filler has a low dielectric constant and a low coefficient of linear expansion, the quality of the multilayer wiring board can be further improved by adding the silica filler to the resin insulating layer.

  When the resin insulating layer is formed using a thermosetting resin, a heat curing step of heating and curing the outermost resin insulating layer may be further performed after the filler increasing step. The reason is that the resin treatment layer before being completely cured is relatively soft, so that the plasma treatment can be performed efficiently.

1 is a schematic cross-sectional view showing a semiconductor package of the present embodiment. The schematic sectional drawing for demonstrating the manufacturing procedure of the multilayer wiring board which comprises the said semiconductor package. The schematic sectional drawing for demonstrating the manufacturing procedure of the said multilayer wiring board. The schematic sectional drawing for demonstrating the manufacturing procedure of the said multilayer wiring board. The schematic sectional drawing for demonstrating the manufacturing procedure of the said multilayer wiring board. The schematic sectional drawing for demonstrating the manufacturing procedure of the said multilayer wiring board. The principal part expansion schematic sectional drawing for demonstrating the state which formed the outermost resin insulation layer in the manufacturing procedure of the said multilayer wiring board. The principal part expansion schematic sectional drawing for demonstrating the state which formed the opening part by the laser hole process in the manufacturing procedure of the said multilayer wiring board. The principal part expansion schematic sectional drawing for demonstrating the state after a desmear process in the manufacturing procedure of the said multilayer wiring board. The principal part enlarged view which shows notionally the state of the insulating layer surface from the formation of the outermost resin insulation layer to the completion of the filler increasing step in the manufacturing procedure of the multilayer wiring board. The schematic diagram which shows the SEM photograph in the insulating layer surface. The schematic sectional drawing for demonstrating the manufacturing procedure of the said multilayer wiring board. The schematic sectional drawing for demonstrating the manufacturing procedure of the said multilayer wiring board. The schematic sectional drawing for demonstrating the manufacturing procedure of the said multilayer wiring board. The schematic sectional drawing for demonstrating the manufacturing procedure of the said multilayer wiring board. The schematic sectional drawing which shows the multilayer wiring board in another embodiment. The principal part expansion schematic sectional drawing for demonstrating the state after a desmear process in the manufacturing procedure of the said multilayer wiring board. The principal part expansion schematic sectional drawing for demonstrating the state after performing the filler increase process and the plating process in the manufacturing procedure of the said multilayer wiring board. The principal part expansion schematic sectional drawing for demonstrating the state which formed the etching resist in the manufacture procedure of the said multilayer wiring board. The principal part expansion schematic sectional drawing for demonstrating the state which removed the dummy plating layer by the etching in the manufacturing procedure of the said multilayer wiring board.

  Hereinafter, an embodiment embodying a method for producing a multilayer wiring board according to the present invention will be described in detail with reference to FIGS.

  As shown in FIG. 1, the semiconductor package 10 of the present embodiment is a BGA (ball grid array) composed of a multilayer wiring board 11 and an IC chip 12. Note that the form of the semiconductor package 10 is not limited to BGA alone, and may be PGA (pin grid array), LGA (land grid array), or the like.

  The multilayer wiring board 11 is a coreless wiring board formed without including a core board, and includes resin insulating layers 21, 22, 23, 24, 25 mainly composed of the same resin insulating material, a conductor layer 26 made of copper, The wiring laminated portion 30 (laminated structure) is formed by alternately laminating layers. Each of the resin insulation layers 21 to 25 is formed using a build-up material mainly composed of a resin insulation material not imparted with photocurability, specifically, a cured product of a thermosetting epoxy resin. Moreover, the silica filler is added to each resin insulating layers 21-25.

  In the multilayer wiring substrate 11, a plurality of connection terminals 41 for connecting the IC chip 12 are arranged in an array on the upper surface 31 (chip mounting surface) side of the wiring laminated portion 30. The resin insulating layer 25 that is the outermost layer on the upper surface 31 side in the wiring laminated portion 30 is an insulating layer that functions as a solder resist. In the resin insulating layer 25, openings 43 for exposing the plurality of connection terminals 41 are formed. A plurality of solder bumps 44 are provided on the surface of the connection terminal 41. Each solder bump 44 is electrically connected to the surface connection terminal 28 of the IC chip 12. In the upper surface 31 of the wiring laminated portion 30, the region where the connection terminals 41 and the solder bumps 44 are formed is an IC chip mounting region 29 in which the IC chip 12 can be mounted.

  On the other hand, a plurality of connection terminals 45 for connecting a mother board are arranged in an array on the lower surface 32 of the wiring laminated portion 30. A plurality of solder bumps 47 are disposed on the surface of each connection terminal 45, and the multilayer wiring board 11 is mounted on a mother board (not shown) by the solder bumps 47.

  Each resin insulating layer 21 to 24 is provided with a via hole 33 and a via conductor 34. Each via hole 33 has a truncated cone shape and is formed by performing laser processing on each resin insulating layer 21 to 25. Each via conductor 34 is a conductor whose diameter increases toward the upper surface 31 side, and electrically connects each conductor layer 26, connection terminal 41, and connection terminal 45 to each other.

  In the multilayer wiring board 11 of the present embodiment, the gap between the outermost resin insulation layer 25 and the IC chip 12 is filled with the underfill material 49, and the connection parts (connection terminals 41, solder bumps 44) of the IC chip 12 are filled. , And the surface connection terminal 28) are sealed with an underfill material 49. Furthermore, in the multilayer wiring board 11, the silica filler 57 is exposed from the surface in the outermost resin insulating layer 25 (see FIG. 10).

  Hereinafter, the manufacturing method of the multilayer wiring board 11 in this Embodiment is demonstrated.

  First, a support substrate 50 (such as a glass epoxy substrate) having sufficient strength is prepared, and the resin insulating layers 21 to 25 and the conductor layer 26 are built up on the support substrate 50 to form the wiring laminated portion 30.

  More specifically, as shown in FIG. 2, a base resin insulating layer 51 is formed by attaching a sheet-like insulating resin base material made of an epoxy resin on the support substrate 50, thereby forming the support substrate 50 and the base resin. A base material 52 made of the insulating layer 51 is obtained. Then, the laminated metal sheet body 54 is disposed on the upper surface of the base resin insulating layer 51 of the base material 52. Here, by arranging the laminated metal sheet body 54 on the base resin insulating layer 51, the adhesiveness to the extent that the laminated metal sheet body 54 is not peeled off from the base resin insulating layer 51 in the subsequent manufacturing process is ensured. The laminated metal sheet body 54 is formed by closely attaching two copper foils 55 and 56 (a pair of metal foils) in a peelable state. Specifically, the laminated metal sheet body 54 in which the copper foil 55 and the copper foil 56 are disposed is formed through metal plating (for example, chromium plating, nickel plating, titanium plating, or a composite plating thereof).

  Then, on the base material 52, the sheet-like resin insulating layer 21 is disposed so as to wrap the laminated metal sheet body 54, and the resin insulating layer 21 is attached (see FIG. 3). The resin insulating layer 21 is in close contact with the laminated metal sheet body 54, and in close contact with the base resin insulating layer 51 in the peripheral region of the laminated metal sheet body 54, thereby sealing the laminated metal sheet body 54.

Then, a via hole 33 is formed at a predetermined position of the resin insulating layer 21 by performing laser processing using, for example, an excimer laser, a UV laser, a CO ₂ laser, or the like (see FIG. 4). Next, a desmear process is performed to remove smear in each via hole 33 using an etching solution such as a potassium permanganate solution.

  After the desmear process, via conductors 34 are formed in the via holes 33 by performing electroless copper plating and electrolytic copper plating according to a conventionally known method. Further, the conductor layer 26 is patterned on the resin insulating layer 21 by performing etching by a conventionally known method (for example, a semi-additive method) (see FIG. 5). Further, the other resin insulation layers 22 to 25, the conductor layer 26, and the connection terminal 41 are also formed by the same method as the resin insulation layer 21 and the conductor layer 26 described above and laminated on the resin insulation layer 21 ( (See FIGS. 6 and 7).

  Then, laser hole machining is performed on the outermost resin insulating layer 25 to form an opening 43 that exposes the connection terminal 41 for connecting the IC chip 12 (drilling step: see FIG. 8). Next, a desmear process for removing smear in each opening 43 with a potassium permanganate solution or the like is performed (see FIG. 9). When this desmear process is performed, the surface of the outermost resin insulation layer 25 and the wall surface of the opening 43 are roughened to form a roughened surface consisting of fine irregularities. In FIG. 10, the state before the desmear process is drawn on the first stage, and the state after the desmear process is drawn on the second stage. As can be understood from this figure, after the desmear process, the silica filler 57 is exposed from the upper surface 31 as a result of the resin insulating material in the outermost resin insulating layer 25 being selectively dissolved. At this time, the amount (remaining amount) of the silica filler 57 exposed from the surface (that is, the upper surface 31) of the resin insulating layer 25 is once reduced.

In the stage after the desmear process and before the filler increasing process, high-pressure water washing is performed. Specifically, to set the pressure to about ^{100kgf / cm 2 ~500kgf / cm 2} , performing the blowing continued 10 seconds to 2 minutes high pressure water at room temperature to the surface of the resin insulating layer 25. In the third row of FIG. 10, the state after the high-pressure water washing step is depicted. As can be seen from this figure, by performing this treatment, among the silica fillers 57 exposed from the surface of the resin insulating layer 25 and the wall surface of the opening 43, unstable ones that are easily removed are washed away. . That is, here, the silica filler 57 whose surface is more exposed (more than half of the surface area is exposed) is removed, and the silica filler 57 embedded in the resin insulating layer 25 remains in the resin insulating layer 25. At this time, the amount of silica filler 57 exposed from the surface of the insulating layer is further reduced as compared with the state immediately after the desmear process.

In the subsequent filler increasing step, plasma processing which is a kind of dry etching processing is performed. When this treatment is performed, the resin insulating material that forms the surface (upper surface 31) of the outermost resin insulating layer 25 is selectively removed, resulting in an increase in the amount of silica filler 57 exposed on the upper surface 31. (Refer to the fourth row in FIG. 10). As a result of this treatment, even if the amount of the silica filler 57 exposed on the surface of the insulating layer after the desmear process is small, it can be adjusted to a desired value by appropriately increasing it. In the present embodiment, plasma treatment is performed by irradiating the surface of the outermost resin insulation layer 25 with O ₂ plasma using an O ₂ plasma apparatus. Here, since the average particle diameter D1 of the silica filler 57 is 1 [mu] m, the etching amount T1 of the resin insulating layer 25 is set to 0.4 [mu] m to 0.6 [mu] m, which is about half that thickness.

  The inventor took SEM photographs of the surface of the resin insulating layer 25 before and after the filler increasing step, and confirmed that the abundance of the silica filler 57 was increased based on these SEM photographs. Specifically, a diagonal line L1 is drawn in the SEM photograph 59 (see FIG. 11) on the surface of the resin insulating layer 25, and the length of the silica filler 57 that occupies on the diagonal line L1 (the width of each silica filler 57 overlapping the diagonal line L1). ) Is measured. Then, the value of “(the added distance / the length of the diagonal L1) × 100 (%)” was defined as “abundance (presence rate) of the silica filler 57”. And based on this measurement result, it confirmed that the abundance of the silica filler 57 was increasing.

  According to the measurement results, before the filler increasing step (but immediately after the desmear step), the amount of filler 57 present in the resin insulating layer 25 was about 83%. On the other hand, the abundance of the silica filler 57 exposed on the surface of the resin insulating layer 25 was reduced to about 30% to 40%. Further, the contact angle (CA) of the underfill material 49 with respect to the surface of the resin insulating layer 25 at this time was about 8 ° to 12 °. Therefore, the surface of the resin insulating layer 25 has changed from a hydrophilic surface to a hydrophobic surface. Further, immediately after the high-pressure water washing step, the amount of the silica filler 57 exposed on the surface of the resin insulating layer 25 is further reduced, and the contact angle tends to be reduced.

  And in the stage which passed through the filler increase process, the abundance of the silica filler 57 exposed on the surface of the resin insulation layer 25 increased to about 55% to 65%. At this time, the contact angle of the underfill material 49 was about 17 ° to 18 °. Therefore, finally, after the filler increasing step, the surface of the resin insulating layer 25 can be made an appropriate hydrophilic surface, and the flowability of the underfill material 49 can be brought into a suitable state.

  After the filler increasing step as described above, a heat curing step is performed in which each of the resin insulating layers 21 to 25 is heated and cured. In the present embodiment, each of the resin insulating layers 21 to 25 is subjected to a pre-curing process for curing to some extent each time each layer is formed, and finally cured in a thermal curing process.

  By the build-up process described above, the wiring laminate 60 in which the laminated metal sheet body 54, the resin insulating layers 21 to 25, and the conductor layer 26 are laminated on the base material 52 is formed. As shown in FIG. 11, a region located on the laminated metal sheet body 54 in the wiring laminate 60 is a portion that becomes the wiring laminated portion 30 of the multilayer wiring board 11.

  After the build-up process, the wiring laminate 60 is cut by a dicing apparatus (not shown), and the peripheral region of the wiring laminate 30 is removed. At this time, as shown in FIG. 12, the base material 52 (the supporting substrate 50 and the base) located below the wiring laminated portion 30 at the boundary between the wiring laminated portion 30 and the peripheral portion P1 (boundary indicated by an arrow in FIG. The whole resin insulating layer 51) is cut. By this cutting, the outer edge portion of the laminated metal sheet 54 sealed with the resin insulating layer 21 is exposed. That is, due to the removal of the peripheral portion P1, the adhesion portion between the base resin insulating layer 51 and the resin insulating layer 21 is lost. As a result, the wiring laminated portion 30 and the base material 52 are connected via the laminated metal sheet body 54 only.

  Here, as shown in FIG. 13, by peeling at the interface between the pair of copper foils 55 and 56 in the laminated metal sheet body 54, the substrate 52 is removed from the wiring laminated portion 30, and the wiring laminated portion 30 ( The copper foil 55 on the lower surface 32 of the resin insulating layer 21) is exposed. Then, as shown in FIG. 14, the connection terminals 45 are formed on the resin insulating layer 21 by performing patterning by etching on the copper foil 55 on the lower surface 32 of the wiring laminated portion 30 (resin insulating layer 21). Form.

  In the subsequent solder bump forming step, solder bumps 44 for connecting IC chips are formed on the plurality of connection terminals 41 formed on the resin insulating layer 24 (see FIG. 15). Specifically, after solder balls are arranged on each connection terminal 41 using a solder ball mounting device (not shown), the solder balls are heated to a predetermined temperature and reflowed, whereby solder bumps are formed on each connection terminal 41. 44 is formed. Similarly, solder bumps 47 are formed on the plurality of connection terminals 45 formed on the resin insulating layer 21. The multilayer wiring board 11 is manufactured through the above steps.

  Thereafter, the IC chip 12 is placed in the IC chip mounting area 29 of the multilayer wiring board 11. At this time, the surface connection terminals 28 on the IC chip 12 side and the solder bumps 44 on the multilayer wiring board 11 side are aligned. Then, by heating and reflowing the solder bumps 44, the surface connection terminals 28 and the solder bumps 44 are joined, and the IC chip 12 is mounted on the multilayer wiring board 11.

  Further, an underfill material 49 that is a liquid thermosetting resin is poured into the gap between the outermost resin insulation layer 25 and the IC chip 12. At this time, the surface of the resin insulating layer 25 is an appropriate hydrophilic surface as described above, and the flowability of the underfill material 49 is in a suitable state. Therefore, the underfill material 49 does not spread out beyond the sealing range, and the entire gap between the outermost resin insulating layer 25 and the IC chip 12 can be reliably filled and sealed without excess or deficiency. As a result, as shown in FIG. 1, the semiconductor package 10 in which the connecting portion between the multilayer wiring board 11 and the IC chip 12 is sealed with the underfill material 49 is manufactured.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) According to the manufacturing method of this embodiment, since the filler increasing process is performed after the desmear process, the abundance of the silica filler 57 exposed on the surface of the outermost resin insulation layer 25 can be increased. . Therefore, even if the amount of silica filler 57 exposed on the surface of the insulating layer after passing through the desmear process is small, it can be adjusted by increasing it appropriately, and the surface of the insulating layer can be adjusted to an appropriate hydrophilic surface. It can be. Therefore, the flowability of the underfill material 49 is easily optimized, and the gap between the outermost resin insulating layer 25 and the IC chip 12 can be reliably sealed with the underfill material 49.

  (2) In the filler increasing step of the manufacturing method of the present embodiment, plasma processing, which is a kind of dry etching processing, is employed, so that the processing conditions can be controlled more easily and reliably than wet etching processing. Accordingly, the resin insulating material can be selectively removed while suppressing the filler from falling off, and the filler can be reliably exposed. In addition, the surface of the filler itself can be activated and hydrophilized.

  (3) In the manufacturing method of this embodiment, the high pressure water washing process is performed in the stage after a desmear process and before a filler increase process. According to this treatment, not only the desmear liquid is washed out, but also the silica filler 57 exposed on the surface of the insulating layer can be washed out with weak adhesion. For this reason, there exists an advantage that the silica filler 57 becomes difficult to drop | omit in the process after a filler increase process. In addition, foreign matters (resin residue etc.) adhering to the surface of the resin insulating layer 25 and the inner wall of the opening 43 can also be removed.

  (4) In the manufacturing method of the present embodiment, since the filler increasing step is performed before the heat curing step for curing the resin insulating layer 25, the relatively incompletely cured resin is etched instead of the completely cured state. be able to. Therefore, plasma processing can be performed efficiently and in a short time, and it becomes easy to achieve improvement in productivity.

  In addition, you may change embodiment of this invention as follows.

  In the above embodiment, the dry etching process is performed as the filler increasing process. Instead, a filler fixing process for fixing the silica filler 57 on the surface of the outermost resin insulating layer 25 is performed. Also good. Specifically, the outermost resin insulation layer 25 is in an incompletely cured state, and the silica filler 57 is uniformly applied on the surface thereof. Thereafter, thermal curing is performed to completely cure the resin insulating layer 25, and the silica filler 57 is fixed.

  -In the said embodiment, although the high pressure water washing process was performed in the stage after a desmear process and a filler increase process, since this process is not essential, you may abbreviate | omit if unnecessary.

  In the above embodiment, the present invention is embodied in the multilayer wiring board 11 having no core, but the present invention is embodied in a multilayer wiring board in which build-up layers (wiring laminated portions) are formed on both surfaces of the core board. May be used.

  The present invention may be embodied as, for example, a multilayer wiring board 11A in another embodiment shown in FIGS. In this multilayer wiring board 11A, the structure of the conductor portion is different from that of the above embodiment. That is, the conductor part in the said embodiment was the some connection terminal 41 arrange | positioned under the resin insulating layer 25 which functions as a soldering resist. A plurality of columnar terminals 61 (copper posts) formed by copper plating are formed on the surfaces of the plurality of connection terminals 41. Some of these columnar terminals 61 protrude from the outermost resin insulating layer 25 through the opening 43. The outer surface of the columnar terminal 61 is covered with a nickel / gold plating layer 62. A plurality of connection terminals 71 for chip capacitor connection made of copper plating are formed on the outer peripheral portion of the outermost resin insulation layer 25. The outer surface of the connection terminal 71 is also covered with the nickel / gold plating layer 62.

  Hereinafter, the manufacturing method will be described. First, according to the procedure of the said embodiment, the desmear process with respect to the opening part 43 of the resin insulation layer 25 of the outermost layer is performed (refer FIG. 17). Next, after performing high-pressure water washing treatment, a plating step is performed to form the columnar terminals 61 and the connection terminals 71 (see FIG. 18). Specifically, the following procedure is followed. First, electroless copper plating (surface plating) is performed to form an entire plating layer that covers the inner wall of the opening 43 of the resin insulating layer 25 and the resin insulating layer 25. Then, a dry film for forming a plating resist is laminated on the upper surface 31 of the resin insulating layer 25, and a plating resist (not shown) is formed by exposing and developing the dry film. Thereafter, after electrolytic copper plating is selectively performed in a state where the plating resist is formed, the exposed portions of the plating resist and the entire plating layer that are no longer needed are removed, and the columnar terminals 61, the connection terminals 71, and the dummy conductor layers 72 are removed. Form. At this stage, since the amount of silica filler 57 exposed on the surface of the insulating layer is still small (about 30% to 40%), the surface of the insulating layer is a hydrophobic surface. Therefore, it is possible to ensure suitable adhesion with the insulating layer surface for the columnar terminals 61 and the connection terminals 71 made of copper plating. Thereafter, an etching resist is formed on the columnar terminal 61 and the connection terminal 71 (see FIG. 19). Etching is performed in this state to remove only the dummy conductor layer 72, and then the etching resist is removed (see FIG. 20). At this stage, plasma processing is performed as a filler increasing step as in the above embodiment. As a result, the abundance of the silica filler 57 exposed on the insulating layer surface is increased (about 55% to 65%). In such a procedure, the filler increasing step is performed in a state where a part of the surface of the insulating layer is covered with the columnar terminal 61 and the connection terminal 71. Therefore, only the uncovered area can be selectively made into an appropriate hydrophilic surface, and the sealing property of the underfill material 49 can be ensured. Then, the columnar terminal 61 and the connection terminal 45 are sequentially subjected to electroless nickel plating and electroless gold plating. As a result, nickel / gold plating layers 62 are formed on the surfaces of the columnar terminals 61 and the connection terminals 45, respectively, so that the multilayer wiring board 11A of FIG. 16 is completed.

DESCRIPTION OF SYMBOLS 11, 11A ... Multilayer wiring board 12 ... IC chip 21-25 as a chip component ... Resin insulating layer 26 ... Conductive layer 30 ... Wiring laminated part as laminated structure 31 ... Upper surface 41, 71 ... Conductor part as chip mounting surface Connection terminal 43 as an opening 49 Underfill material 57 Silica filler as a filler 61 Columnar terminal D1 Average particle diameter of filler T1 Etching amount

Claims (9)

It has a multilayer structure in which a plurality of resin insulation layers and a plurality of conductor layers are alternately laminated to form a multilayer structure, and in the multilayer structure, the outermost resin insulation formed on the chip mounting surface side on which chip components are mounted The layer is mainly composed of the same resin insulating material as that of the resin insulating layer on the inner layer side and includes a filler made of an inorganic oxide. The gap between the outermost resin insulating layer and the chip component is sealed with an underfill material. A method of manufacturing a multilayer wiring board to be stopped,
A drilling step for forming an opening exposing the conductor by laser drilling the outermost resin insulation layer;
After the drilling process, a desmear process for removing smear in the opening,
And a filler increasing step of increasing the filler exposed on the surface of the outermost resin insulating layer after the desmearing step.   The method for manufacturing a multilayer wiring board according to claim 1, wherein the conductor portion is a connection terminal for connecting the chip component.   3. The method of manufacturing a multilayer wiring board according to claim 2, wherein a columnar terminal is formed on the connection terminal so that a part thereof protrudes from the outermost resin insulating layer.   The said filler increase process performs the dry etching process which selectively removes the said resin insulation material which makes | forms the surface among the said resin insulation layers of the outermost layer, and exposes the said filler. The manufacturing method of the multilayer wiring board of any one of Claims 1.   The method of manufacturing a multilayer wiring board according to claim 4, wherein the dry etching process is a plasma process.   5. The dry etching treatment is characterized in that the etching amount of the outermost resin insulation layer is set so that the thickness is 40% or more and 60% or less of the average particle diameter of the filler. 6. A method for producing a multilayer wiring board according to 5.   6. The method for manufacturing a multilayer wiring board according to claim 1, wherein high-pressure water washing is performed after the desmear process and before the filler increasing process.   8. The method of manufacturing a multilayer wiring board according to claim 7, wherein surface plating is performed at a stage after the high-pressure water washing treatment and before the filler increasing step. The resin insulation layer is formed using a thermosetting resin,
9. The method for manufacturing a multilayer wiring board according to claim 1, further comprising a thermal curing step of heating and curing the outermost resin insulating layer after the filler increasing step. 10.

Images