JP3692063B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a high breakdown voltage and a low current loss using a wide forbidden band width semiconductor (wide gap semiconductor) material.
[0002]
[Prior art]
Semiconductor materials having normal forbidden band width Eg, such as silicon (forbidden band width Eg = about 1.1 eV) and gallium arsenide (forbidden band width Eg = about 1.4 eV), which have been researched early in the semiconductor industry and have been put into practical use. In contrast, a semiconductor material having a wider forbidden band width Eg is called a wide forbidden band width semiconductor (wide gap semiconductor). For example, zinc telluride (ZnTe) with forbidden band width Eg = about 2.2 eV, cadmium sulfide (CdS) with forbidden band width Eg = about 2.4 eV, zinc selenide (ZnSe) with forbidden band width Eg = about 2.7 eV. ), Gallium nitride (GaN) with forbidden band width Eg = about 3.4 eV, zinc sulfide (ZnS) with forbidden band width Eg = about 3.7 eV, and diamond with forbidden band width Eg = about 5.5 eV. It is given as. Silicon carbide (SiC) is also an example of a wide gap semiconductor. Forbidden band width Eg of SiC is reported to be about 2.23 eV for 3C-SiC, 2.93 eV for 6H-SiC, and about 3.26 eV for 4H-SiC.
[0003]
Wide gap semiconductors are generally thermally, chemically and mechanically stable and resistant to radiation.
Excellent linearity. In particular, SiC is excellent in these characteristics, and power semiconductor devices (power devices) exhibiting high reliability and stability under severe conditions such as high temperature, high power, and radiation irradiation as well as light emitting elements and high frequency devices. As such, it is expected to be applied in various industrial fields.
[0004]
In such a wide gap semiconductor, the wider the forbidden band width Eg, the closer to the properties as an insulator, and it becomes difficult to obtain a low resistivity by doping impurities. In general, in wide gap semiconductors, it is difficult to obtain a “good conductive” material with high reproducibility and reliability. For example, as materials for blue light emitting diodes, GaN, a group III-V semiconductor having a wurtzite structure, ZnSe of group II-VI, and the like have been vigorously studied as promising materials. The research subject was to realize p-type conductivity control. It has been considered that the p-type valence electron control in a wide gap semiconductor is difficult due to the self-compensation effect. For example, when donor impurities are introduced into ZnSe, Zn vacancies that act as double acceptors are naturally formed when donor impurities are introduced, and the electrons in the conduction band formed by the introduction of donor impurities are spontaneously compensated. This is a phenomenon. In order for this phenomenon to occur, the enthalpy of generation of Zn vacancies ΔHv (Zn) should be smaller than the total energy ΔEv released when two electrons fall into the acceptor. Now, ignoring the binding energy of carriers to donors and Zn vacancies, ΔE is approximately twice the forbidden band width Eg. For this reason, it is considered that the self-compensation effect is more noticeable as the semiconductor has a wider gap (forbidden band width Eg). For this reason, it has long been considered that there is an essential difficulty in realizing p-type conduction in a wide gap semiconductor material. On the other hand, such a problem does not become a problem at all in a semiconductor material such as Si having a forbidden band width Eg = about 1.1 eV or GaAs having a forbidden band width Eg = 1.4 eV. Accordingly, semiconductor materials such as Si and GaAs have been put into practical use as materials for various semiconductor devices.
[0005]
In particular, it has been reported that a high-voltage power semiconductor device (power device) using SiC has a lower on-resistance than a power device using Si. It has also been reported that the forward voltage drop of a Schottky diode using SiC is low. As is well known, the on-resistance of a power device and the switching speed are in a trade-off relationship. However, according to a power device using SiC, there is a possibility that low on-resistance and high switching speed can be achieved at the same time.
[0006]
[Problems to be solved by the invention]
However, the diffusion coefficient of impurities with respect to SiC is very small, about one thousandth of the diffusion coefficient of impurities in Si. For this reason, not only with predeposition (vapor phase diffusion) technology, but with ion implantation technology, it is simply p.⁺It is difficult to design the region to the desired impurity concentration and geometric shape.
[0007]
One of semiconductor power devices is a junction barrier Schottky diode (hereinafter referred to as “JBS diode”). This JBS diode is a normal n-type Schottky diode.⁺It has a structure in which the area is embedded. The feature of JBS diodes is that each p⁺The depletion layer extends from the region and is pinched off, thereby relaxing the electric field applied to the Schottky interface and suppressing the reverse leakage current. However, on the other hand, in the forward characteristics, a plurality of p's are formed under the Schottky electrode.⁺Since the region is buried, there is a problem that the region through which the carrier passes effectively decreases, and as a result, the forward resistance increases.
[0008]
Therefore, there is a demand for a novel structure for sufficiently reducing the forward resistance without impairing the reverse characteristics such as withstand voltage and leakage current. However, in SiC, as described above, since the process technology, particularly the diffusion technology, has not been developed, it is not easy to realize the structure of the JBS diode in a desired structure. Therefore, in the JBS diode using SiC, it is strongly demanded to realize a structure that satisfies the above requirements without increasing the number of processes if possible and at a low manufacturing cost.
[0009]
Moreover, the problem of the JBS diode using SiC described above is common with the problem related to the shape of the gate region of a static induction transistor (SIT) which is another semiconductor power device. Various structures such as a buried gate type, a surface gate type, and a cut gate type are known for SIT. Among these, in the surface gate type SIT, a pair of gate regions are formed to face each other with a source region sandwiched between the substrate surfaces. A region sandwiched between the pair of gate regions is a channel region. The main current flowing between the source region and the drain region is electrostatically controlled by the voltage applied to the gate region, the height of the potential barrier formed in the channel region in front of the source region. Also in this surface gate type SIT, a structure for improving the characteristics is being studied in the same manner as the JBS diode described above. Adopting a new structure effectively extends the depletion layer to the drift region with a smaller gate voltage, making it easier to obtain normally-off characteristics, and sufficiently reducing the forward resistance between the source and drain. The structure which can do is awaited. However, even in the surface gate type SIT using SiC, there is currently no sufficient technology for realizing a desired device structure without increasing the number of processes and at a low manufacturing cost.
[0010]
In view of the above problems, an object of the present invention is to provide a semiconductor device having a high breakdown voltage, a low reverse leakage current, and a small forward voltage drop, and a method for manufacturing the same.
[0011]
[Means for Solving the Problems]
In view of the above object, the first feature of the present invention is that a first conductivity type ohmic contact region, a first conductivity type drift region made of a wide band gap material provided on the ohmic contact region, and the drift A semiconductor device comprising a plurality of second-conductivity-type deep expansion diffusion regions provided inside the region, and a Schottky electrode forming a Schottky junction with a drift region provided in contact with the surface of the drift region. Is the gist. The plurality of deep expansion diffusion regions of the second conductivity type form a JBS diode structure. In other words, by providing a plurality of deep expansion type diffusion regions of the second conductivity type, depletion layers from each deep expansion type diffusion region extend into the drift region and pinch off each other in reverse characteristics, thereby forming a Schottky interface. The applied electric field is relaxed. For this reason, the reverse leakage current can be suppressed. Although the same applies to the following second to fifth characteristics, in the present invention, the “wide forbidden band width material” means a semiconductor material having a wider forbidden band than 2.2 eV. The drift region has a lower impurity concentration than the ohmic contact region. Each of the deep-expansion diffusion regions has a horizontal cross-sectional area that gradually increases from the surface of the drift region toward the ohmic contact region. For example, it has a trapezoidal cone shape or a mirror shape. The deep expansion type diffusion region has its top exposed at the surface of the drift region. The first conductivity type and the second conductivity type are opposite to each other. That is, if the first conductivity type is n-type, the second conductivity type is p-type. If the first conductivity type is p-type, the second conductivity type is n-type.
[0012]
According to the first feature of the present invention, the horizontal cross-sectional area of the deep inflatable diffusion region is increased as it deepens in the drift region. Therefore, in the JBS diode, reverse characteristics such as breakdown voltage and leakage current are obtained. The forward resistance can be sufficiently reduced without impairing the resistance.
[0013]
In the first feature of the present invention, each of the plurality of deep inflatable diffusion regions is preferably composed of an upper region and a lower region located below the upper region. The upper region includes the first impurity element. On the other hand, the lower region includes a second impurity element having a larger diffusion coefficient in the wide forbidden band width material than the first impurity element.
[0014]
The second feature of the present invention is that the first main electrode region, a first conductivity type drift region made of a wide forbidden band width material provided above the first main electrode region, and provided inside the drift region. A plurality of second conductivity type deep expansion diffusion regions, and a first conductivity type second main electrode region provided inside the drift region sandwiched between the plurality of deep expansion diffusion regions. The gist is that it is a semiconductor device. Similar to the first feature of the present invention, each of the deep-expanded diffusion regions has a three-dimensional shape in which the horizontal cross-sectional area gradually increases from the surface of the drift region toward the first main electrode region. Each of the deep expansion diffusion regions functions as a control electrode region that controls a current flowing between the first and second main electrode regions. The “first main electrode region” means a semiconductor region that is either an emitter region or a collector region in a bipolar transistor (BJT) or an insulated gate bipolar transistor (IGBT). In a field effect transistor (FET) and a static induction transistor (SIT), it means a semiconductor region that is either a source region or a drain region. In an electrostatic induction thyristor (SI thyristor) and a gate turn-off thyristor (GTO thyristor), it means a semiconductor region that is either an anode region or a cathode region. The “second main electrode region” means a semiconductor region that is either an emitter region or a collector region that is not the first main electrode region in BJT, IGBT, etc., and the first main electrode region in FET, SIT. It means a semiconductor region that is either a source region or a drain region that is not to be. In the SI thyristor and the GTO thyristor, the “second main electrode region” means a semiconductor region that is either the anode region or the cathode region that is not the first main electrode region. That is, if the first main electrode region is an emitter region, the second main electrode region is a collector region. If the first main electrode region is a source region, the second main electrode region is a drain region. If one main electrode region is a cathode region, the second main electrode region means an anode region. Further, the “control electrode region” means a semiconductor region, a Schottky junction region, or an insulated gate structure region or structure that controls current flowing between the first main electrode region and the second main electrode region. For example, IGBT, FET, SIT, SI thyristor, and GTO thyristor mean a gate region or a gate structure, and BJT means a base region including an external base region (base electrode extraction region).
[0015]
The first conductivity type and the second conductivity type are opposite to each other. That is, if the first conductivity type is n-type, the second conductivity type is p-type. If the first conductivity type is p-type, the second conductivity type is n-type. The first main electrode region may be the first conductivity type or the second conductivity type. The drift region has a lower impurity concentration than the first main electrode region. The deep expansion type diffusion region and the second main electrode region are arranged so that the top portion is exposed on the surface of the drift region.
[0016]
According to the second feature of the present invention, the width of the deep expansion type diffusion region, that is, the cross-sectional area in the horizontal direction in three dimensions, is gradually expanded as the depth increases inside the drift region. The forward resistance can be sufficiently reduced without impairing the breakdown voltage characteristics of the control electrode region.
[0017]
In the second aspect of the present invention, a base region of the second conductivity type may be further provided between the plurality of deep expansion diffusion regions. If the impurity concentration of the base region of the second conductivity type is lowered so that the first and second main electrode regions are almost punched through. It functions as a bipolar mode SIT (BSIT) or normally-off SI thyristor. On the other hand, if the impurity concentration of the base region of the second conductivity type is set high so that a neutral region remains between the first and second main electrode regions, it functions as a BJT or GTO thyristor.
[0018]
In the second feature of the present invention, each of the plurality of deep expansion diffusion regions is located in an upper region containing the first impurity element and in a lower portion of the upper region, and is wider than the first impurity element. What is necessary is just to make it consist of the lower region containing the 2nd impurity element with a large diffusion coefficient in a forbidden bandwidth material.
[0019]
The third feature of the present invention is that the first main electrode region of the first conductivity type or the second conductivity type is provided on the upper portion of the first main electrode region, and has a lower impurity concentration than the first main electrode region. A drift region of a first conductivity type made of a wide band gap material, a plurality of second conductivity type body regions disposed on the surface of the drift region, and a first conductivity type disposed on the surface of the body region The second main electrode region, a plurality of trenches dug from the surface of the second main electrode region toward the first main electrode region, and a gate insulating film formed on the inner walls of the plurality of trenches, Inside the plurality of trenches, a gate electrode disposed on the surface of the gate insulating film and a drift region below the plurality of trenches are provided in the inside of the drift region, and horizontally from the bottom of the trench toward the first main electrode region region, respectively. Directional cross section gradually widens Is made as to, and summarized in that a semiconductor device including a plurality of second conductivity type deep expansion-type diffusion regions serving as electric-field relaxation region. Here, the “first main electrode region” means a semiconductor region serving as either an emitter region or a collector region in an insulated gate bipolar transistor (IGBT). In an insulated gate FET or an insulated gate SIT, it means a semiconductor region that is either a source region or a drain region. The “second main electrode region” refers to a semiconductor region that is either an emitter region or a collector region that is not the first main electrode region in an IGBT or the like, an insulating gate type FET, and an insulating gate type SIT. 1 means a semiconductor region that is either a source region or a drain region that does not become a main electrode region.
[0020]
According to the third feature of the present invention, the deep expansion type diffusion region significantly relaxes the electric field strength of the gate insulating film in the vicinity of the bottom of the trench, and an insulated gate semiconductor device having a higher breakdown voltage can be realized. . This is because the deep expansion type diffusion region equally shares the voltage applied to the gate insulating film. As a result, the reliability of the insulated gate semiconductor device is also improved.
[0021]
Further, in the third feature of the present invention, each of the plurality of deep expansion diffusion regions is located in an upper region containing the first impurity element and in a lower portion of the upper region and is wider than the first impurity element. It is the same as the first and second features that the lower band containing the second impurity element having a large diffusion coefficient in the forbidden bandwidth material may be used.
[0022]
According to a fourth aspect of the present invention, there is provided a first conductivity type drift region made of a wide forbidden band width material, a plurality of second conductivity type body regions disposed on the surface of the drift region, and spaced from the body region. The first conductivity type or the second conductivity type first main electrode region disposed on the surface of the drift region at a higher impurity concentration than the drift region, and the first conductivity type disposed on the surface of the body region. A second main electrode region; a plurality of trenches that penetrate the body region from the surface of the second main electrode region to reach the drift region; a gate insulating film formed on the inner wall of the plurality of trenches; The gate electrode disposed on the surface of the gate insulating film and the drift region at the bottom of the plurality of trenches are provided in the drift region, and the water is directed away from the body region from the bottom of the trench. Is to a direction cross-sectional area is gradually wider, and summarized in that a semiconductor device including a plurality of second conductivity type deep expansion-type diffusion regions serving as electric-field relaxation region. Here, the “first main electrode region” means a semiconductor region that is either an emitter region or a collector region in an insulated gate bipolar transistor (IGBT), and is an insulated gate FET or insulated gate SIT. As in the third feature, it means a semiconductor region which is either a source region or a drain region. Therefore, the “second main electrode region” means an emitter region or a collector region that is not the first main electrode region in the IGBT or the like, an insulating gate type FET, or an insulating gate type SIT. It means a semiconductor region that is either a source region or a drain region that does not become the first main electrode region.
[0023]
According to the fourth feature of the present invention, similar to the third feature, the deep expansion type diffusion region significantly relaxes the electric field strength of the gate insulating film in the vicinity of the bottom of the trench, and the lateral insulated gate having a higher breakdown voltage. Type semiconductor device can be realized. This is because the deep expansion type diffusion region equally shares the voltage applied to the gate insulating film. As a result, the reliability of the lateral insulated gate semiconductor device is also improved. In the lateral insulated gate semiconductor device according to the fourth feature of the present invention, since the first and second main electrode regions are provided on the same side surface, it is easy to integrate as a monolithic IC. It is. In addition, wiring work is simplified even when incorporated in a hybrid IC or the like. In addition, the degree of freedom of surface wiring and connection increases, and the design becomes easy.
[0024]
In the fourth feature of the present invention, each of the plurality of deep-expanded diffusion regions is located in an upper region containing the first impurity element and in a lower portion of the upper region and is wider than the first impurity element. It is the same as the first to third features that the lower band containing the second impurity element having a large diffusion coefficient in the forbidden bandwidth material may be used.
[0025]
The fifth feature of the present invention is that (a) a step of forming an ion implantation mask on the surface of the first conductivity type semiconductor region made of a wide forbidden band width material, and (b) using the ion implantation mask, A deep ion implantation step of implanting the first impurity ions having the second conductivity type into the semiconductor region a plurality of times while changing acceleration energy; (c) using the mask for ion implantation in the semiconductor region rather than the first impurity ions; A shallow ion implantation process in which second impurity ions having a small diffusion coefficient are implanted a plurality of times while changing the acceleration energy at a position shallower than the projected range of the first impurity ions, and (d) the first and first by the heat treatment process. The present invention is summarized as a method of manufacturing a semiconductor device including a step of electrically activating two impurity ions and forming a deep expansion type diffusion region inside the semiconductor region.
[0026]
According to the method for manufacturing a semiconductor device according to the fifth feature of the present invention, the semiconductor device according to the first to fourth features can be easily manufactured.
[0027]
For example, if the wide band gap material is silicon carbide (SiC), boron (B) may be selected as the first impurity ion and aluminum (Al) may be selected as the second impurity ion.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Next, first to eighth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it goes without saying that the drawings include portions having different dimensional relationships and ratios.
[0029]
(First embodiment)
As shown in FIG. 2 (f), the JBS diode according to the first embodiment of the present invention includes a first conductivity type ohmic contact region (n-type low resistance SiC substrate) 11 and an upper portion of the ohmic contact region 11. A first conductivity type drift region (n-type epitaxial growth layer) 12 made of a wide forbidden band width material provided in the first region, and a plurality of second conductivity type deep expansion diffusion regions 15a provided in the drift region 12 15b and a Schottky electrode 17 which forms a Schottky junction with the drift region 12 provided in contact with the surface of the drift region 12. An ohmic electrode 16 is formed on the entire surface of the ohmic contact region (n-type low resistance SiC substrate) 11. The plurality of second-conductivity-type deep expansion diffusion regions 15a and 15b shown in FIG. 2 (f) form a JBS diode structure.
[0030]
The drift region 12 has a lower impurity concentration than the ohmic contact region 11. Each of the deep-expanded diffusion regions 15a and 15b has a horizontal cross-sectional area that gradually increases from the surface of the drift region 12 toward the ohmic contact region 11. According to the structure shown in FIG. 2 (f), the horizontal cross-sectional area of the deep inflatable diffusion regions 15a and 15b is increased in the drift region 12 as it becomes deeper. The forward resistance can be sufficiently reduced without deteriorating the reverse characteristics such as the above. That is, the area of the Schottky junction is made sufficiently large, and at the same time, a favorable pinch-off characteristic between the deep expansion diffusion regions 15a and 15b is realized.
[0031]
A method for manufacturing the JBS diode according to the first embodiment of the present invention shown in FIG. 2 (f) will be described with reference to FIGS.
(A) First, as shown in FIG. 1A, the impurity concentration is 1 × 10¹⁹cm^-3An impurity concentration of 3 × 10 3 is formed on an n-type low resistance SiC substrate 11 having a thickness of 300 μm by an epitaxial growth method.¹⁵cm^-3Then, an n-type epitaxial growth layer 12 having a thickness of 10 μm is formed. However, nitrogen (N) is used as the n-type impurity here, but another impurity such as phosphorus (P) may be used.
[0032]
(B) Next, a metal film 13 is deposited on the surface of the n-type epitaxial growth layer 12 by vacuum evaporation or sputtering. As the metal film 13, for example, molybdenum (Mo) can be used. Then, a photoresist film (hereinafter simply abbreviated as “resist”) 14 is spin-coated on the metal film 13. Then, the resist 14 is patterned by photolithography as shown in FIG. Then, using the resist 14 patterned as shown in FIG. 1B as an etching mask, the metal film 13 is patterned to form an ion implantation mask 13M as shown in FIG. For patterning the metal film 13, reactive ion etching (RIE) may be used. Then, using this ion implantation mask 13M, as shown in FIG. 1C, a substrate temperature T is formed at a position deep from the surface of the n-type epitaxial growth layer 12._SUB= Boron at around 700 ℃¹¹B⁺) Selective ion implantation (deep ion implantation step). Here, boron is acceleration energy E_ACC= 100-200 keV, total dose Φ = 3 × 10¹⁵cm^-2Impurity concentration of 1 × 10 in a region having a depth of 0.25 to 0.5 μm from the surface.²⁰cm^-3The boron implantation layer is formed. For example:
First ion implantation: Φ = 6 × 10^{1 Four}cm^-2/ E_ACC= 100 keV;
Second ion implantation: Φ = 6 × 10^{1 Four}cm^-2/ E_ACC= 130 keV;
Third ion implantation: Φ = 6 × 10^{1 Four}cm^-2/ E_ACC= 150 keV;
Fourth ion implantation: Φ = 1.2 × 10¹⁵cm^-2/ E_ACC= 200 keV;
Ion implantation is performed as follows.
[0033]
(C) Further, using the ion implantation mask 13M, as shown in FIG. 2D, aluminum (from the surface of the n-type epitaxial growth layer 12 to a position shallower than the projected range of boron (²⁷Al⁺) Selective ion implantation (shallow ion implantation step). Aluminum is the substrate temperature T_SUB= Acceleration energy E at around 700 ° C_ACC= 10 to 180 keV, total dose Φ = 2 × 10¹⁵cm^-2Of multistage injection. As a result, an impurity concentration of 1 × 10 6 is formed in a region having a depth of 0.25 μm from the surface.²⁰cm^-3An aluminum injection layer is formed.
[0034]
(D) Thereafter, the substrate temperature T_SUBAs shown in FIG. 2E, p-type deep expansion diffusion regions 15a and 15b are selectively formed by activation heat treatment at about = 1600 ° C. At this time, the width of each surface of the deep expansion diffusion regions 15a and 15b is about 2 μm, and the width of the Schottky junction near the surface sandwiched between the deep expansion diffusion region 15a and the deep expansion diffusion region 15b facing each other. Was about 2 μm.
[0035]
(E) Nickel (Ni) is deposited on the back surface of the n-type low-resistance SiC substrate 11 to a thickness of about 1 μm. Furthermore, the substrate temperature T_SUBAn ohmic electrode (cathode electrode) 16 is formed by a sintering process at about 1000 ° C. as shown in FIG.
[0036]
(F) Next, as shown in FIG. 2 (f), on the surfaces of the n-type epitaxial growth layer 12 and the deep expansion type diffusion regions 15a and 15b, titanium (Ti) is about 200 nm thick and Al is about 1 μm thick. Then, a Schottky electrode (anode electrode) 17 is formed to complete a JBS diode.
[0037]
The results of evaluating the electrical characteristics of the JBS diode manufactured as described above are as follows. JBS diode with a withstand voltage of 1000V, the reverse current when reverse voltage 700V is applied is 1 × 10^-6A / cm²And forward current density 100 A / cm²In this case, the forward voltage was 1.7V. On the other hand, the JBS diode according to the prior art has a forward voltage of about 2.5V when compared with the same withstand voltage of 1000V. Therefore, the forward voltage reduction of about 0.8V can be obtained with the JBS diode of the present invention. Here, the reason why the forward voltage can be reduced by about 0.8 V according to the present invention is that the depletion layer extending from the pn junction between the deep expansion diffusion regions 15a and 15b and the n-type epitaxial growth layer 12 to the n-type epitaxial growth layer 12 is used. This is because the area of an effective Schottky junction can be expanded at the same time as realizing pinch-off characteristics. It can be seen that by increasing the effective Schottky junction area, the forward voltage drop of the diode of the same chip area can be reduced by about 0.8V.
[0038]
Further, as shown in FIG. 2 (f), when realizing a structure in which the horizontal cross-sectional area of the deep expansion type diffusion regions 15a and 15b is deepened toward the inside of the substrate, boron having a lighter mass has a deep projection range. Because of the injection, the damage during injection can be greatly reduced. As a result, in the JBS diode of the present invention, the forward resistance can be sufficiently reduced without impairing the reverse characteristics such as withstand voltage and leakage current.
[0039]
(Second Embodiment)
The semiconductor device according to the second embodiment of the present invention is a surface gate type SIT as shown in FIG. That is, the surface gate type SIT according to the second embodiment of the present invention includes a first main electrode region (n-type low-resistance SiC substrate) 11 and a wide forbidden band provided on the first main electrode region 11. A first conductivity type drift region (n-type epitaxial growth layer) 21 made of a width material, a plurality of second conductivity type deep expansion diffusion regions 25a and 25b provided in the drift region 21, and a plurality of deep portions It is composed of a first conductivity type second main electrode region 35 provided inside the drift region 21 between the expansion type diffusion regions 25a and 25b. As in the first embodiment of the present invention, each of the deep-expanded diffusion regions 25a and 25b has a horizontal cross-sectional area that gradually increases as it approaches the first main electrode region 11 from the surface of the drift region 21. 3D shape.
[0040]
More preferably, the curvature of the outer peripheral surface of the second main electrode region 35 is equal to the curvature of the outer peripheral surface of the deep inflatable diffusion regions 25a and 25b facing the second main electrode region 35 in a male / female relationship. It ’s good. More preferably, the deep expansion diffusion is performed so that the potential profile of the second main electrode region 35 and the potential profiles of the deep expansion diffusion regions 25a and 25b facing the second main electrode region 35 are uniformly continuous. The curvatures of the regions 25a and 25b may be selected.
[0041]
Each of the deep expansion type diffusion regions 25a and 25b functions as a control electrode region (gate region) that controls a current flowing between the first and second main electrode regions 35. The first main electrode region 11 functions as a drain region of the surface gate type SIT. The second main electrode region 35 functions as a source region of the surface gate type SIT. Each of the plurality of deep-expanded diffusion regions 25a and 25b is located in the upper region made of the first impurity element, and in the lower portion of the upper region, and the diffusion coefficient in the wider forbidden band width material than the first impurity element. And a lower region made of a large second impurity element.
[0042]
A drain electrode 43 is in ohmic contact with the first main electrode region (drain region) 11, and a source electrode 41 is in ohmic contact with the second main electrode region (source region) 35. Further, gate electrodes 45a and 45b are in ohmic contact with the deep expansion type diffusion regions (gate regions) 25a and 25b, respectively.
[0043]
SIT can be interpreted as a transistor in the limit of shortening the FET channel. That is, it can be defined as a device in which the channel is made short enough to punch through between the source region and the drain region of the FET, and there is a potential barrier that can be controlled by the drain voltage and the gate voltage in the channel. Specifically, it is a device in which the height of a potential barrier (potential) that is a saddle point in a two-dimensional space of a potential between a source and a drain and a potential in a channel due to a gate voltage is controlled by the drain voltage and the gate voltage. The potential barrier (potential) is formed in front of the second main electrode region (source region) 35 under the influence of the potential of the deep expansion type diffusion regions (gate regions) 25a and 25b. Since the drain current flows depending on the height of the potential barrier (potential), the drain current / drain voltage characteristics of the SIT exhibit characteristics according to the exponential law similar to the triode characteristics of the vacuum tube.
[0044]
As will be described later, each of the deep-expanded diffusion regions 25a and 25b should have a three-dimensional shape in which the horizontal cross-sectional area gradually increases as it approaches the first main electrode region 11 from the surface of the drift region 21. For example, the forward voltage drop can be reduced while the reverse breakdown voltage of the surface gate type SIT is maintained high.
[0045]
The surface gate type SIT shown in FIG. 5 (i) can be manufactured by the following procedure:
(A) First, the impurity concentration is 1 × 10.¹⁹cm^-3Impurity concentration of 3 × 10 5 by epitaxial growth on an n-type low resistance SiC substrate 11 having a thickness of 300 μm¹⁵cm^-3Then, an n-type epitaxial growth layer 21 having a thickness of 10 μm is formed. However, nitrogen is used as the n-type impurity here, but another impurity such as phosphorus may be used.
[0046]
(B) Next, a metal film 24 is deposited on the surface of the n-type epitaxial growth layer 21 by vacuum evaporation or sputtering. As the metal film 24, for example, Mo can be used. Then, a resist is spin-coated on the metal film 24. Then, the resist is patterned by photolithography. Then, using the patterned resist as an etching mask, the metal film 24 is patterned to form an ion implantation mask 24 as shown in FIG. For the patterning of the metal film 24, RIE may be used. Then, as shown in FIG. 3A, the n-type epitaxial growth layer 21 is deeply inserted through the ion implantation mask 24 from the surface.¹¹B⁺Selective ion implantation is performed (deep ion implantation step). here,¹¹B⁺Is the substrate temperature T_SUB= Acceleration energy E around 700 ° C_ACC= 100 to 400 keV, total dose Φ = 6 × 10¹⁵cm^-2Multi-stage injection. As a result, an impurity concentration of 1 × 10 10 is obtained in a region having a depth of 0.25 to 0.8 μm from the surface.²⁰cm^-3An injection layer is formed.
[0047]
(C) Next, as shown in FIG. 3B, from the surface of the n-type epitaxial growth layer 21, the ion implantation mask 24 is used as a mask.¹¹B⁺In a position shallower than the projection range of²⁷Al⁺Selective ion implantation is performed (shallow ion implantation step).²⁷Al⁺Is the substrate temperature T_SUB= Acceleration energy E at around 700 ° C_ACC= 10 to 180 keV, total dose Φ = 2 × 10¹⁵cm^-2Multi-stage injection. As a result, an impurity concentration of 1 × 10 6 is obtained in a region having a depth of 0.25 μm from the surface.²⁰ cm^-3of²⁷Al⁺An injection layer is formed.
[0048]
(D) Thereafter, the mask 24 for ion implantation is removed, and the substrate temperature T_SUBAs shown in FIG. 3C, p-type deep expansion diffusion regions 25a and 25b are selectively formed by activation heat treatment at about = 1600 ° C. The p-type deep expansion type diffusion regions 25a and 25b are gate regions of the surface gate type SIT. At this time, the width of each of the deep expansion diffusion regions 25a and 25b is about 2 μm near the surface. In addition, the width of the channel sandwiched between the pair of mold deep expansion diffusion regions 25a and deep expansion diffusion regions 25b is set to about 1 μm near the surface.
[0049]
(E) Next, polycrystalline silicon is deposited on the surface of the n-type epitaxial growth layer 21 by the CVD method. Then, the polycrystalline silicon is thermally oxidized to form an oxide film 91 on the surface of the n-type epitaxial growth layer 21 as shown in FIG. When this polycrystalline silicon is thermally oxidized, a thin oxide film 30 is also formed on the back surface of the low-resistance SiC substrate 11. Further, the second metal film 32 is deposited on the surface of the oxide film 91 by vacuum vapor deposition or sputtering. For example, Mo can be used as the second metal film 32. Then, a resist 33 is spin-coated on the second metal film 32. Then, the resist 33 is patterned by photolithography as shown in FIG. Then, using the patterned resist 33 as an etching mask, the second metal film 32 is patterned to form a second mask 32M for ion implantation as shown in FIG. For the patterning of the second metal film 32, RIE may be used. Following the RIE of the second metal film 32, the underlying oxide film 91 is also selectively removed by RIE to expose part of the surface of the n-type epitaxial growth layer 21. Then, through the second mask 32M for ion implantation, as shown in FIG._SUB= Around 700 ℃³¹P⁺Accelerate energy E_ACC= 10 to 200 keV, total dose Φ = 5 × 10¹⁵cm^-2The multi-stage ion implantation is selectively performed under the following conditions. Then, after removing the second mask 32M for ion implantation and the oxide film 91, the substrate temperature T_SUBBy an activation heat treatment at about 1600 ° C., as shown in FIG. 5G, an impurity concentration of 1 × 10 is formed in a region having a depth of about 0.3 μm from the surface.²⁰cm^-3N-type source region 35 is formed.
[0050]
(F) Next, after the oxide film 31 is formed on the substrate surface by the CVD method or the like, the oxide film 31 is patterned using RIE or the like using the resist patterned in the same manner as described above as an etching mask. Thereafter, the resist is removed, and the opening of the patterned oxide film 31 is used as a source contact hole. Thereafter, the surface of the oxide film 31 having the source contact hole is covered with a resist, and the thin oxide film 30 on the back surface of the low-resistance SiC substrate 11 is etched with diluted hydrofluoric acid (HF) or buffered HF. On the back surface of the n-type low resistance SiC substrate 11, a Ni film is deposited as a third metal film 43 with a thickness of about 1 μm, and the substrate temperature T_SUB= Drain electrode 43 is formed by sintering at about 1000 ° C. to 1200 ° C.
[0051]
(G) Next, as shown in FIG. 5H, an Al film is deposited on the surface of the n-type source region 35 as a fourth metal film 36 to a thickness of about 1 μm. Then, a resist is spin-coated on the fourth metal film 36. Then, the resist is patterned by photolithography so that the resist remains above the source region 35. Then, using the patterned resist as an etching mask, the fourth metal film is etched to selectively leave the fourth metal film as shown in FIG. And substrate temperature T_SUBThe source electrode 41 is formed by a sintering process at about 1000 ° C. to 1100 ° C.
[0052]
(H) Next, a resist is spin-coated on the source electrode 41 and the oxide film 31 exposed from the source electrode 41. Then, the resist is patterned by photolithography so that an opening is formed above each of the deep expansion diffusion regions (gate regions) 25a and 25b. Then, using the patterned resist as an etching mask, the oxide film 31 is selectively etched to expose the surfaces of the gate regions 25a and 25b, and a gate contact hole as shown in FIG. 5I is opened. Thereafter, a Ti film is deposited on the entire surface sequentially with a thickness of about 200 nm and an Al film with a thickness of about 1 μm. A resist is spin-coated on the Al film, and patterning is performed by photolithography so that the resist remains on the upper portions of the deep expansion diffusion regions (gate regions) 25a and 25b. Then, using the patterned resist as an etching mask, the Al film and the Ti film are selectively etched sequentially by RIE as shown in FIG. 5I to form the patterns of the gate electrodes 45a and 45b. After that, the substrate temperature T_SUBSintering is performed at 800 to 1000 ° C., for example, 950 ° C. for about 5 minutes, so that the ohmic contact between the gate electrodes 45a and 45b is improved. In order to perform heat treatment for a short time of about 5 minutes, infrared (IR) lamp heating may be used. This completes the schematic process of the surface gate type SIT.
[0053]
Also here¹¹B⁺When²⁷Al⁺The ion implantation conditions as described above are used for the above, but in order to effectively perform pinch-off by the gate, the acceleration energy E_ACCIt is also possible to form the p-type deep expansion diffusion regions 26a and 26b in a substantially trapezoidal shape as shown in FIG. As described above, deep in the deep expansion diffusion region²⁷Al⁺The diffusion coefficient is several times larger than¹¹B⁺Therefore, after the activation heat treatment, the width of the deep expansion diffusion region can be effectively expanded toward the inside of the substrate as shown in FIG. More¹¹B⁺As another advantage of injecting deep into the²⁷Al⁺Compared to the above, the mass is light, so that the damage at the time of injection can be further reduced, and as a result, the leakage current at the time of pinch-off can be greatly suppressed.
[0054]
The results of evaluating the electrical characteristics of the surface gate type SIT manufactured as described above are as follows. With a surface gate type SIT with a withstand voltage of 1000 V, the leakage current when a gate voltage of −30 V and a drain voltage of 600 V is applied is 1 × 10^-6A / cm²The on-resistance is 16mΩcm²It became. On the other hand, in the conventional surface gate type SIT, the on-resistance is 26 mΩcm when compared with the same withstand voltage of 1000 V.²Before and after. Therefore, in the surface gate type SIT according to the second embodiment of the present invention, about 10 mΩcm.²The on-resistance can be reduced. Here, the on-resistance is about 10 mΩcm by the surface gate type SIT according to the second embodiment of the present invention.²The reason for the reduction is that the source area can be relatively expanded as compared with the same pinch-off characteristic. As a result, the parasitic resistance generated by the depletion layer extending from the pn junction between the deep expansion type diffusion regions 15a and 15b and the n-type epitaxial growth layer 12 to the n-type epitaxial growth layer 12 is about 10 mΩcm.²Has been reduced. Therefore, by adopting a configuration such as the surface gate type SIT according to the second embodiment, as described above, the width of the deep expansion diffusion region can be effectively expanded toward the inside of the substrate. Light weight¹¹B⁺Since this is implanted at a deeper position, the damage during implantation can be greatly reduced, and as a result, the forward resistance can be sufficiently reduced without impairing the gate breakdown voltage characteristics such as breakdown voltage and leakage current in the surface gate type SIT. It can be done. Since the voltage amplification factor μ of the surface gate type SIT depends on the interval between adjacent gate regions, the use of the deep expansion type diffusion regions 25a and 25b increases the voltage amplification factor μ and lowers the on-resistance. I can do it.
[0055]
(Third embodiment)
As shown in FIG. 8I, a cut gate type SIT according to the third embodiment of the present invention includes a first conductive type first main electrode region (drain region) 11, and the first main electrode region 11. A first conductivity type drift region 21 made of a wide forbidden band width material, and a plurality of trenches 48a, 48b dug from the surface of the drift region 21 toward the first main electrode region 11. A plurality of second conductivity type deep expansion diffusion regions (gate regions) 25a, 25b provided inside the drift region 21 at the bottoms of the plurality of trenches 48a, 48b,. ,..., A first conductive type second main electrode region (source region) provided in the drift region 21 between the plurality of deep expansion diffusion regions 25a, 25b,. 35a, 35b, 35c, ... It is composed of a .... Similarly to the second embodiment of the present invention, each of the deep expansion type diffusion regions 25a, 25b,... In the depth direction from the surface of the drift region 21 toward the first main electrode region 11, As the first main electrode region 11 is approached, the lateral diffusion width perpendicular to the depth direction increases. Each of the plurality of deep-expanded diffusion regions 25a, 25b,... Is located in an upper region made of the first impurity element and a lower forbidden band than the first impurity element. It consists of a lower region made of a second impurity element having a large diffusion coefficient in the width material. In the third embodiment, the case where n-type is used as the first conductivity type and p-type is used as the second conductivity type will be described.
[0056]
The first main electrode region (drain region) 11 has a drain electrode 43, and the second main electrode regions (source regions) 35a, 35b, 35c,... Have source electrodes 41a, 41b, 41c,. ... is in ohmic contact.
[0057]
The cut gate type SIT shown in FIG. 8 (i) can be manufactured by the following procedure:
(A) First, the impurity concentration is 1 × 10.¹⁹cm^-3On the n-type low resistance SiC substrate 11 having a thickness of 300 μm, as shown in FIG.¹⁵cm^-3The impurity concentration on the n-type epitaxial growth layer (first epitaxial growth layer) 21 having a thickness of 10 μm and the first epitaxial growth layer 21 is 6 × 10¹⁸cm^-3~ 1x10²⁰cm^-3Then, the second epitaxial growth layer 19 having a thickness of about 0.3 μm to 1 μm is formed. However, nitrogen is used as the n-type impurity here, but another impurity such as phosphorus may be used. A plurality of impurities such as nitrogen and phosphorus may be used at the same time. Instead of forming the second epitaxial growth layer 19, phosphorus is added to the surface of the n-type first epitaxial growth layer 21 at the substrate temperature T._SUB= Acceleration energy E around 700 ° C_ACC= 10 to 200 keV, total dose Φ = 5 × 10¹⁵cm^-2Then, the multi-stage ion implantation is selectively performed under the following conditions, and then an impurity concentration of 1 × 10 is applied to a region about 0.3 μm deep from the surface by activation heat treatment at about 1600 ° C.²⁰cm^-3The n-type low resistance region 19 may be formed.
[0058]
(B) Next, an oxide film 34 is formed on the surface of the second epitaxial growth layer 19. Thereafter, a resist 14 is spin-coated on the surface of the oxide film 34, and the resist 14 is patterned by photolithography as shown in FIG. 6B. Then, using the patterned resist as an etching mask, as shown in FIG. 6C, the oxide film 34 and the n-type low resistance region (second epitaxial growth layer) 19 are penetrated by anisotropic etching such as RIE. Trenches 48a, 48b,... Whose bottoms reach the n-type first epitaxial growth layer 21 are formed. By forming the trenches 48a, 48b,..., The n-type low resistance region (second epitaxial growth layer) 19 is divided into source regions 35a, 35b, 35c,.
[0059]
(C) After removing the resist 14, an oxide film 37 is formed inside the trenches 48a, 48b,... As shown in FIG. Then, the oxide film 37 at the bottom of the trenches 48a, 48b,... Is removed by directional etching such as RIE. Further, a first metal film is deposited on the surface of the oxide film 34 by vacuum vapor deposition or sputtering. For example, Mo can be used as the first metal film. Then, a resist is spin-coated on the first metal film, and the resist is patterned by a photolithography technique. Then, using the patterned resist as an etching mask, the first metal film may be patterned to form an ion implantation mask 13M as shown in FIG. RIE may be used for patterning the first metal film.
[0060]
(D) Then, through the ion implantation mask 13M, as shown in FIG. 7E, at a deep position of the n-type first epitaxial growth layer 21 exposed at the bottom.¹¹B⁺Selective ion implantation is performed (deep ion implantation step). here,¹¹B⁺Is the substrate temperature T_SUB= Room temperature to 700 ° C., where acceleration energy E is about 500 ° C._ACC= 100 to 400 keV, total dose Φ = 1.8 × 10¹³cm^-2Multi-stage injection. As a result, an impurity concentration of 3 × 10 6 is obtained in a region having a depth of 0.25 to 0.8 μm from the surface.¹⁷cm^-3An injection layer is formed.
[0061]
(E) Further, as shown in FIG. 7F, the ion implantation mask 13M is used as a mask for the n-type first epitaxial growth layer 21 exposed at the bottom.¹¹B⁺In a position shallower than the projection range of²⁷Al⁺Selective ion implantation is performed (shallow ion implantation step).²⁷Al⁺Is the substrate temperature T_SUB= Room temperature to 700 ° C, here about 500 ° C, acceleration energy E_ACC= 10 to 150 keV, total dose Φ = 2 × 10¹³cm^-2Multi-stage injection. As a result, an impurity concentration of 1 × 10 6 is obtained in a region having a depth of 0.25 μm from the surface.¹⁸cm^-3of²⁷Al⁺An injection layer is formed.
[0062]
(F) Thereafter, the oxide films 34 and 37 and the ion implantation mask 13M are removed, and the substrate temperature T_SUBAs shown in FIG. 8G, p-type deep expansion diffusion regions 25a, 25b,... Are selectively formed by activation heat treatment at about = 1600 ° C. The p-type deep expansion diffusion regions 25a, 25b,... are gate regions of a cut gate type SIT. Here, the ion implantation conditions as described above were used for boron and aluminum. However, in order to effectively perform pinch-off by the gate, the acceleration energy E_ACCFurther, the p-type deep expansion diffusion regions 25a, 25b,... Can be formed in a substantially trapezoidal shape by appropriately adjusting the dose amount Φ. As described above, boron having a diffusion coefficient several times larger than that of aluminum is intentionally implanted deep in the p-type deep expansion diffusion regions 25a, 25b,. As in the embodiment, after the activation heat treatment, the widths of the p-type deep expansion diffusion regions 25a, 25b,... Can be effectively expanded toward the inside of the substrate. Another advantage of implanting boron deeply is that the mass is lighter than aluminum, so that damage during implantation can be further reduced, and as a result, leakage current at pinch-off can be greatly suppressed.
[0063]
(G) Next, oxide films 74 and 77 are formed on the substrate surface and in the trenches 48a, 48b,. Then, as shown in FIG. 8G, the oxide film 77 at the bottom of the trenches 48a, 48b,... Is removed by directional etching such as RIE. After that, an Al film (second metal film) is deposited in the trenches 48a, 48b,... About 200 nm, and polycrystalline silicon is deposited on the Al film by the CVD method. Then, planarization is performed by CMP until the oxide film 74 is exposed, and the Al film / polycrystalline silicon is buried in the trenches 48a, 48b,... As shown in FIG. 45a, 45b,... Are formed.
[0064]
(H) Then, a resist is spin-coated on the oxide film 74, and the resist is patterned by a photolithography technique. Then, using the patterned resist as an etching mask, the oxide film 74 is selectively etched to open source contact holes and expose part of the source regions 35a, 35b, 35c,. For the patterning of the oxide film 74, RIE may be used. Thereafter, the surface of the oxide film 74 having the source contact hole opened is covered with a resist, and the thin oxide film 30 on the back surface of the low-resistance SiC substrate 11 is etched with diluted hydrofluoric acid (HF) or buffered HF. On the back surface of the n-type low resistance SiC substrate 11, a Ni film is deposited as a third metal film with a thickness of about 1 μm to form a drain electrode 43.
[0065]
(I) Next, an Al film is deposited on the surface of the n-type source regions 35a, 35b, 35c,... As a fourth metal film with a thickness of about 1 μm. As the fourth metal film, a metal such as Ti or Mo, or various metal silicides may be used. Then, a resist is spin-coated on the fourth metal film. Then, the resist is patterned by photolithography so that the resist remains above the source regions 35a, 35b, 35c,. Then, using the patterned resist as an etching mask, the fourth metal film is etched, and the fourth metal film as shown in FIG. 8I is formed on the source regions 35a, 35b, 35c,. The source electrodes 41a, 41b, 41c,... Are patterned while leaving selectively. And substrate temperature T_SUB= 800 to 1100 ° C., for example, 950 ° C., for about 5 minutes, to improve the ohmic contact between the source electrodes 41a, 41b, 41c,. This completes the outline process of the cut gate type SIT.
[0066]
The results of evaluating the electrical characteristics of the cut gate type SIT manufactured as described above are as follows. With a cut gate type SIT with a withstand voltage of 800 V, the leakage current when a gate voltage of −20 V and a drain voltage of 500 V is applied is 1 × 10^-6A / cm² The on-resistance is 13mΩcm²It became. On the other hand, in the SiC cut gate type SIT according to the prior art, when compared with the same withstand voltage of 800 V, the on-resistance is 26 mΩcm.²Before and after. Therefore, in the cut gate type SIT according to the third embodiment, about 13 mΩcm.² The on-resistance can be reduced. Here, the on-resistance is about 13 mΩcm according to the third embodiment.² The reason for the reduction is that the parasitic resistance caused by the depletion layer extending from the pn junction between the p-type deep expansion diffusion regions 25a, 25b,...² This is due to the reduction. Further, in the cut gate type SIT, the capacity of the gate regions 25a, 25b,... Is greatly reduced, so that the p-type deep expansion diffusion regions 25a, 25b,.・ By combining with, high-speed operation is greatly improved.
[0067]
Therefore, by adopting the configuration of the third embodiment, the width of the gate regions 25a, 25b,... Can be effectively expanded toward the inside of the substrate as described above. Since the lighter weight boron is implanted deeper, the damage during implantation can be greatly reduced. As a result, in the cut gate type SIT, the forward resistance without impairing the gate withstand voltage characteristics such as withstand voltage and leakage current. Can be lowered sufficiently.
[0068]
<Modification of Third Embodiment>
FIG. 11 (f) is a cross-sectional view of a trench sidewall gate type SIT according to a modification of the third embodiment of the present invention. The difference between the present invention and the third embodiment is that one-sided p-type deep expansion diffusion regions 39a, 39b, 39c, 39d,... Exist between the top and bottom of the trench. The method for manufacturing the trench sidewall gate type SIT shown in FIG. 11 (f) is the same until the p-type deep expansion diffusion regions 25a, 25b,... Are formed at the trench bottom shown in FIG. Since this is the same as the cut gate type SIT of the third embodiment, the description thereof is omitted.
[0069]
(A) After that, by anisotropic etching such as RIE, as shown in FIG. 9A, the bottom portion penetrates through the p-type deep expansion diffusion regions 25a, 25b,. Forming a second trench reaching. By the formation of the second trench, one-sided p-type deep expansion diffusion regions 39a, 39b, 39c, 39d,... Are formed in the side wall portion between the trench upper portion (first trench) and the bottom portion (second trench). Is done.
[0070]
(B) Thereafter, as shown in FIG. 10C, an insulating film 46 is deposited by the CVD method in the extension trench composed of the first trench and the second trench. For the insulating film 46, a material having a film quality that has a higher etching rate than that of the oxide film 74, such as an oxide film by low-temperature CVD or vacuum deposition, or a PSG film, is selected. Alternatively, a part or all of the surface of the oxide film 74 is made of a silicon nitride film (Si_ThreeN_FourFilm). Further, planarization is performed until the oxide film 74 is exposed by CMP, and the insulating film 46 is embedded in the extension trench. Further, back etching is performed using the film quality of the oxide film that is higher than that of the oxide film 74, and as shown in FIG. 10D, the buried insulating films 47a, 47b, ... is formed.
[0071]
(C) Next, an Al film (second metal film) is deposited to a thickness of about 200 nm inside the extension trench, and polycrystalline silicon is further deposited on the Al film by a CVD method. Then, planarization is performed by CMP until the oxide film 74 is exposed, and the Al film / polycrystalline silicon is buried in the extension trench as shown in FIG. 11E, and the buried gate electrodes 45a, 45b,... • Form.
[0072]
(D) Then, a resist is spin-coated on the oxide film 74, and the resist is patterned by a photolithography technique. Then, using the patterned resist as an etching mask, the oxide film 74 is patterned, a source contact hole is opened, and a part of the source regions 35a, 35b, 35c,. For the patterning of the oxide film 74, RIE may be used. Thereafter, the surface of the oxide film 74 having the source contact hole opened is covered with a resist, and the thin oxide film 30 on the back surface of the low-resistance SiC substrate 11 is etched with diluted hydrofluoric acid (HF) or buffered HF. On the back surface of the n-type low resistance SiC substrate 11, a Ni film is deposited as a third metal film 43 with a thickness of about 1 μm to form a drain electrode 43.
[0073]
(E) Next, an Al film is deposited on the surfaces of the n-type source regions 35a, 35b, 35c,... As a fourth metal film with a thickness of about 1 μm. As the fourth metal film, a metal such as Ti or Mo, or various metal silicides may be used. Then, a resist is spin-coated on the fourth metal film, and the resist is patterned by photolithography so that the resist remains above the source regions 35a, 35b, 35c,. Then, using the patterned resist as an etching mask, the fourth metal film is etched, and the fourth metal film as shown in FIG. 11F is formed on the source regions 35a, 35b, 35c,. Leave selectively. And substrate temperature T_SUB= Through a sintering process of about 1000 ° C. to 1100 ° C., the ohmic contact between the source electrodes 41a, 41b, 41c,..., The drain electrode 43, and the gate electrodes 45a, 45b is improved. This completes the outline process of the trench sidewall gate type SIT.
[0074]
The electrical characteristics of the trench sidewall gate type SIT according to the modification of the third embodiment are greatly improved in the same manner as the cut gate type SIT shown in FIG. In the trench sidewall gate type SIT according to the modification of the third embodiment, the capacity of the one side p-type deep expansion diffusion regions 39a, 39b, 39c, 39d,. To be improved. That is, by adopting the configuration shown in FIG. 11 (f), the width of one-sided p-type deep expansion diffusion regions 39a, 39b, 39c, 39d,... Can be effectively expanded toward the inside of the substrate. I can do it. In addition, since the lighter weight boron is implanted deeper, the damage during implantation can be greatly reduced. As a result, in the trench sidewall gate type SIT, the forward breakdown voltage without sacrificing the gate breakdown voltage characteristics such as breakdown voltage and leakage current. The resistance can be lowered sufficiently.
[0075]
(Fourth embodiment)
As shown in FIG. 15L, the vertical UMOSFET according to the fourth embodiment of the present invention includes a first conductive type first main electrode region (drain region) 11, and the first main electrode region 11. A first conductivity type drift region 21 made of a wide forbidden band width material provided at an upper portion, and a plurality of second conductivity type body regions 64a, 64b, 64c,. A plurality of first conductive type second main electrode regions (source regions) 63a, 63b, 63c, 63d,... Selectively disposed on the surfaces of the body regions 64a, 64b, 64c,. ..., a plurality of trenches dug in the direction of the drain region 11 from the surface of the source regions 63a, 63b, 63c, 63d, ..., gate oxide films formed on the inner walls of the plurality of trenches 65, multiple trenches Gate electrodes 45a, 45b,... Buried in the surface of the gate oxide film 65, and a plurality of second conductivity type deep expansion types provided in the drift region 21 at the bottom of the plurality of trenches. Diffusion regions (electric field relaxation regions) 66a, 66b,... As in the second and third embodiments of the present invention, each of the deep-expanded diffusion regions 66a, 66b,... In the depth direction from the surface of the drift region 21 toward the drain region 11, As the drain region 11 is approached, the lateral diffusion width perpendicular to the depth direction becomes wider. Each of the plurality of deep-expanded diffusion regions 66a, 66b,... Is located in the upper region made of the first impurity element and in the lower part of the upper region, and is wider than the first impurity element. It consists of a lower region made of a second impurity element having a large diffusion coefficient in the width material. In the fourth embodiment, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described.
[0076]
The drain electrode 43 is in the first main electrode region (drain region) 11, and the source electrode 41 is in ohmic contact with the second main electrode regions (source regions) 63a, 63b, 63c, 63d,. Has been. The source electrode 41 short-circuits the source regions 63a, 63b, 63c, 63d,... And the body regions 64a, 64b, 64c,.
[0077]
The vertical UMOSFET shown in FIG. 15 (l) can be manufactured by the following procedure:
(A) First, as shown in FIG.¹⁹cm^-3Impurity concentration of 3 × 10 5 by epitaxial growth on an n-type low resistance SiC substrate 11 having a thickness of 300 μm¹⁵cm^-3Impurity concentration of 1 × 10 10 on the n-type epitaxial growth layer (first epitaxial growth layer) 21 having a thickness of 10 μm and the first epitaxial growth layer 21¹⁶cm^-3Then, a p-type second epitaxial growth layer 55 having a thickness of 3 μm is formed. However, nitrogen is used as the n-type impurity here, but another impurity such as phosphorus may be used. A plurality of impurities such as nitrogen and phosphorus may be used at the same time. Further, boron is used as the p-type impurity, but another impurity such as aluminum may be used.
[0078]
(B) Next, an oxide film 76 is deposited on the surface of the second epitaxial growth layer 55. Next, a resist (not shown) is spin-coated on the oxide film 76, and the resist is patterned by a photolithography technique. Next, the oxide film 76 is patterned using the patterned resist as an etching mask. Thereafter, the resist is removed. Then, using the patterned oxide film 76 as an ion implantation mask, phosphorus is used as a substrate temperature T._SUB= Acceleration energy E around 700 ° C_ACC= 10 to 200 keV, total dose Φ = 5 × 10¹⁵cm^-2The multi-stage ion implantation is selectively performed under the following conditions.
[0079]
(C) Thereafter, the oxide film 76 is removed, and an impurity concentration of 1 × 10 is applied to a region having a depth of about 0.3 μm from the surface by activation heat treatment at about 1600 ° C.²⁰cm^-3N-type low resistance regions 57a, 57b,... Are formed. Thereafter, an oxide film 58 is deposited on the n-type low resistance regions 57a, 57b,... As shown in FIG.
[0080]
(D) Next, a resist 59 is spin-coated on the surface of the oxide film 58, and the resist 59 is patterned by photolithography as shown in FIG. Then, using the patterned resist 59 as an etching mask, the oxide film 58 is patterned. Then, using the patterned oxide film 58 as an etching mask, as shown in FIG. 13E, a trench reaching the n-type first epitaxial growth layer 21 through the p-type second epitaxial growth layer 55 by RIE or the like. 48a, 48b,... Are formed.
[0081]
The n-type low resistance regions 57a, 57b,... Are divided into source regions 63a, 63b, 63c, 63d,. The p-type second epitaxial growth layer 55 is divided into p-type body regions 64a, 64b, 64c,.
[0082]
(E) Then, as shown in FIG. 13F, an oxide film 65 having a thickness of about 10 nm is formed inside the trenches 48a, 48b,.
[0083]
(F) Then, using the oxide film 58 as a mask for ion implantation, as shown in FIG. 14G, the trenches 48a, 48b,...¹¹B⁺Selective ion implantation is performed (deep ion implantation step).¹¹B⁺This selective ion implantation is performed through the oxide film 65. At this time, a metal film may be deposited on the surface of the oxide film 58 by vacuum vapor deposition or sputtering, and the metal film may be patterned to serve as an ion implantation mask. here,¹¹B⁺Is the substrate temperature T_SUB= Room temperature to 700 ° C., where acceleration energy E is about 500 ° C._ACC= 100 to 400 keV, total dose Φ = 1.8 × 10¹³cm^-2Multi-stage injection. As a result, an impurity concentration of 3 × 10 6 is obtained in a region having a depth of 0.25 to 0.8 μm from the surface.¹⁷cm^-3An injection layer is formed.
[0084]
(G) Further, as shown in FIG. 14H, the oxide film 58 is used as an ion implantation mask for the n-type first epitaxial growth layer 21 located at the bottom of the trench.¹¹B⁺In a position shallower than the projection range of²⁷Al⁺Selective ion implantation is performed (shallow ion implantation step).²⁷Al⁺This selective ion implantation is performed through the oxide film 65.²⁷Al⁺Is the substrate temperature T_SUB= Room temperature to 700 ° C, here about 500 ° C, acceleration energy E_ACC= 10 to 150 keV, total dose Φ = 2 × 10¹³cm^-2Multi-stage injection. As a result, an impurity concentration of 1 × 10 6 is obtained in a region having a depth of 0.25 μm from the surface.¹⁸cm^-3of²⁷Al⁺An injection layer is formed.
[0085]
(H) Next, after removing the oxide films 58 and 65, the substrate temperature T_SUBAs shown in FIG. 14 (i), p-type deep expansion diffusion regions 66a, 66b,... Are selectively formed by activation heat treatment at about = 1600 ° C. The p-type deep expansion diffusion regions 66a, 66b,... are p-type field relaxation regions of the vertical UMOSFET. Since boron having a diffusion coefficient about several times larger than that of aluminum is intentionally implanted deeply in the p-type field relaxation regions 66a, 66b,..., as in the third embodiment. After the activation heat treatment, the widths of the p-type field relaxation regions 66a, 66b,... Can be effectively expanded toward the inside of the substrate. Furthermore, another advantage of implanting boron deeply is that the mass is lighter than aluminum, so that damage during implantation can be reduced, and as a result, electric field concentration during reverse voltage application can be greatly suppressed. can give.
[0086]
(I) Next, oxide films 58 and 65 are formed again on the substrate surface and in the trenches 48a, 48b,. Thereafter, polysilicon doped with phosphorus at a high concentration is deposited in the trenches 48a, 48b,... By CVD. Then, by using dry etching such as RIE, CDE, etc., polysilicon with a high concentration of phosphorus is left only in the trenches 48a, 48b,..., And other polysilicon (such as the substrate surface) is removed. As a result, buried gate electrodes 45a, 45b,... Are formed. Then, an interlayer insulating film 67 is deposited on the oxide film 58 by the CVD method as shown in FIG.
[0087]
(N) A resist is spin-coated on the interlayer insulating film 67, and the resist is patterned by a photolithography technique. Then, using the patterned resist as an etching mask, the interlayer insulating film 67 and the oxide film 58 are selectively etched, source contact holes are opened, source regions 63a, 63b, 63c, 63d,. P-type body regions 64a, 64b, 64c,... are partially exposed. The source contact holes are opened so that both the source regions 63a, 63b, 63c, 63d,... And the p-type body regions 64a, 64b, 64c,. Is done. The interlayer insulating film 67 and the oxide film 58 may be etched continuously using RIE. Thereafter, the surfaces of the interlayer insulating film 67 and the oxide film 58 in which the source contact holes are opened are covered with a resist, and the thin oxide film 30 on the back surface of the low-resistance SiC substrate 11 is diluted with hydrofluoric acid (HF) or buffered HF. Etching with etc. On the back surface of the n-type low resistance SiC substrate 11, a Ni film is deposited as a metal film 43 with a thickness of about 1 μm to form a drain electrode 43.
[0088]
(L) Next, as shown in FIG. 15 (l), an Al film is deposited on the surface of the n-type source regions 63a, 63b, 63c, 63d,. To do. As the metal film, a metal such as Ti or Mo, or various metal silicides may be used. Then, a resist is spin-coated on the metal film, and the resist is patterned by photolithography so that the resist remains above the source regions 63a, 63b, 63c, 63d,. Then, using the patterned resist as an etching mask, the metal film is etched, and the metal film as shown in FIG. 15 (l) is selectively formed on the source regions 63a, 63b, 63c, 63d,. Then, the source electrode 41 is patterned. In the case of a power device, the source electrode 41 may be formed on the entire surface and may not be patterned. And substrate temperature T_SUB= 800 to 1100 ° C., for example, 950 ° C., for about 5 minutes, and the ohmic contact between the source electrode 41, the drain electrode 43, and the gate electrodes 45a and 45b is improved. This completes the schematic process of the vertical UMOSFET.
[0089]
In the vertical UMOSFET manufactured as described above, the electric field strength of the insulating film at the bottom side ends of the p-type electric field relaxation regions 66a, 66b,. I can do it. This is because the voltage is equally shared by the p-type electric field relaxation regions 66a, 66b,... According to the fourth embodiment of the present invention. In the absence of the p-type electric field relaxation regions 66a, 66b,..., the breakdown voltage is about 700 to 900 V, whereas in the presence of the p-type electric field relaxation regions 66a, 66b,. .About.1200V, and the electric field concentration in the p-type electric field relaxation regions 66a, 66b,... Is remarkably improved, so that the reliability of the device is improved.
[0090]
<Modification of Fourth Embodiment>
FIG. 18L is a sectional view of a vertical UMOSFET according to a modification of the fourth embodiment of the present invention. 18 (l) differs from the structure shown in FIG. 15 (l) in that the structure shown in FIG. 18 (l) is different from the structure shown in FIG. 15 (l) in the second conductivity type (p-type) electric field relaxation region. 69a, 69b, 69c,... The electric field relaxation regions 69a, 69b, 69c,... Have a thickness of about 0.5 μm and a surface impurity concentration of 10¹⁷To 10¹⁸cm^-3P-type region (second conductivity type).
[0091]
The vertical UMOSFET shown in FIG. 18 (l) can be manufactured by the following procedure:
(A) First, the impurity concentration is 1 × 10.¹⁹cm^-3Impurity concentration of 3 × 10 5 by epitaxial growth on an n-type low resistance SiC substrate 11 having a thickness of 300 μm¹⁵cm^-3Then, an n-type epitaxial growth layer (first epitaxial growth layer) 21 having a thickness of 10 μm is grown. Thereafter, the SiC substrate 11 is taken out from the epitaxial growth furnace, and an oxide film (not shown) is formed on the first epitaxial growth layer 21. Next, a resist (not shown) is spin-coated on the oxide film, and the resist is patterned by a photolithography technique. Then, using the patterned resist as an etching mask, the oxide film 68 is patterned by RIE or the like. Next, after removing the resist, as shown in FIG.¹¹B⁺Selective ion implantation is performed (deep ion implantation step). here,¹¹B⁺Is the substrate temperature T_SUB= Room temperature to 700 ° C., where acceleration energy E is about 500 ° C._ACC= 50 to 200 keV, total dose Φ = 1.8 × 10¹³cm^-2Multi-stage injection. Furthermore, as shown in FIG. 16B, the oxide film 68 is used as an ion implantation mask for the n-type first epitaxial growth layer 21.¹¹B⁺In a position shallower than the projection range of²⁷Al⁺Selective ion implantation is performed (shallow ion implantation step).²⁷Al⁺Is the substrate temperature T_SUB= Room temperature to 700 ° C, here about 500 ° C, acceleration energy E_ACC= 5-70 keV, total dose Φ = 2 × 10¹³cm^-2Multi-stage injection.
[0092]
(B) Thereafter, the oxide film 68 on the surface is removed, and the substrate temperature T_SUBAs shown in FIG. 16C, p-type deep expansion diffusion regions 69a, 69b, 69c,... Are selectively formed by activation heat treatment at about = 1600 ° C. Thereafter, as shown in FIG. 16C, an impurity concentration of 1 × 10 6 is formed on the first epitaxial growth layer 21.¹⁶cm^-3Then, a p-type second epitaxial growth layer 55 having a thickness of 3 μm is formed.
[0093]
(C) The subsequent manufacturing steps are basically the same as the steps shown in FIGS. 12 (b) to 15 (l). For example, FIGS. 17 (g), (h), and (i) correspond to FIGS. 14 (g), (h), and (i), respectively. 18 (j), (k), and (l) correspond to FIGS. 15 (j), (k), and (l), respectively. Therefore, a duplicate description is omitted here.
[0094]
As described above, in the vertical UMOSFET according to the modification of the fourth embodiment, the voltage is equally shared by the deep expansion type p-type field relaxation regions 66a, 66b,... Further, the voltage is equally shared by the deep expansion type electric field relaxation regions 69a, 69b, 69c,..., So that the voltage sharing of the gate insulating film becomes very small and the electric field applied to the gate oxide film 65 is reduced. Concentration is further relaxed significantly. That is, a depletion layer extending from the junction between the deep expansion type electric field relaxation regions 69a, 69b, 69c,... And the first epitaxial growth layer 21, and a deep expansion type p-type electric field relaxation regions 66a, 66b, ... and the depletion layer extending from the junction of the first epitaxial growth layer 21 are combined, and as a result, the voltage applied between the drain and source electrodes is equally shared by the combined depletion layer. It is.
[0095]
Specifically, in the above configuration according to the modification of the fourth embodiment, the breakdown voltage is about 1000 to 1200 V in the absence of the p-type electric field relaxation regions 69a, 69b, 69c,. In the case where there are deep expansion type p-type electric field relaxation regions 66a, 66b,..., The breakdown voltage is significantly increased to about 1150 to 1350 V, and the electric field concentration on the gate oxide film 65 is further improved. Device reliability has also been significantly improved.
[0096]
(Fifth embodiment)
As shown in FIG. 20 (f), the surface gate type bipolar mode SIT (BSIT) according to the fifth embodiment of the present invention includes a first main electrode region (drain region) 11 of the first conductivity type, and its drain. A first conductivity type drift region (n-type epitaxial growth layer) 21 made of a wide forbidden band width material provided above the region 11, and a plurality of second conductivity type deep expansions provided inside the drift region 21 , Diffusion regions (gate regions) 25a, 25b,..., A second conductivity type base region 72 sandwiched between a plurality of deep expansion diffusion regions 25a, 25b,. And a second main electrode region (source region) 35 of the first conductivity type provided in the vicinity of the surface inside. The impurity concentration of the base region 72 is set sufficiently lower than the deep-expanded diffusion regions 25a, 25b,..., And the punching through is almost between the drain region 11 and the source region 35. Yes. However, in the state where no voltage is applied to the gate regions 25a, 25b,..., The height of the potential barrier against electrons is sufficiently high, so that the drain current does not flow, and the surface gate type BSIT exhibits normally-off characteristics. Show. When a voltage equal to or lower than the built-in voltage is applied to the gate regions 25a, 25b,..., The height of the potential barrier against electrons decreases due to the electrostatic induction effect, and the drain current of the surface gate type BSIT begins to flow.
[0097]
Like the surface gate type SIT according to the second embodiment, each of the surface gate type BSIT deep expansion regions 25a, 25b,... Approaches the drain region 11 from the surface of the drift region 21. Accordingly, it has a three-dimensional shape in which the horizontal cross-sectional area gradually increases. In the fifth embodiment, a case where n-type is used as the first conductivity type and p-type is used as the second conductivity type will be described. A drain electrode 43 is in ohmic contact with the first main electrode region (drain region) 11, and a source electrode 41 is in ohmic contact with the second main electrode region (source region) 35. Further, gate electrodes 45a and 45b are in ohmic contact with the deep expansion type diffusion regions (gate regions) 25a, 25b,.
[0098]
The surface gate type BSIT shown in FIG. 20 (f) can be manufactured by the following procedure:
(A) First, the impurity concentration is 1 × 10.¹⁹cm^-3Impurity concentration of 3 × 10 5 by epitaxial growth on an n-type low resistance SiC substrate 11 having a thickness of 300 μm¹⁵cm^-3Then, an n-type epitaxial growth layer 21 having a thickness of 10 μm is formed. However, nitrogen is used as the n-type impurity here, but another impurity such as phosphorus may be used. Next, a metal film is deposited on the surface of the n-type epitaxial growth layer 21 by vacuum evaporation or sputtering. For example, Mo can be used as the metal film. Then, a resist is spin-coated on the metal film, and the resist is patterned by a photolithography technique. Then, using the patterned resist as an etching mask, the metal film is patterned to form an ion implantation mask. Then, as in the second embodiment, the n-type epitaxial growth layer 21 is deeply inserted through the ion implantation mask from the surface of the n-type epitaxial growth layer 21.¹¹B⁺Selective ion implantation is performed (deep ion implantation step). here,¹¹B⁺Is the substrate temperature T_SUB= Room temperature to 700 ° C., where acceleration energy E is about 500 ° C._ACC= 100 to 400 keV, total dose Φ = 6 × 10¹⁴cm^-2Multi-stage injection. As a result, an impurity concentration of 1 × 10 10 is obtained in a region having a depth of 0.25 to 0.8 μm from the surface.¹⁹cm^-3An injection layer is formed. Further, from the surface of the n-type epitaxial growth layer 21, an ion implantation mask is used as a mask.¹¹B⁺In a position shallower than the projection range of²⁷Al⁺Selective ion implantation is performed (shallow ion implantation step).²⁷Al⁺Is the substrate temperature T_SUB= Room temperature to 700 ° C, here about 500 ° C, acceleration energy E_ACC= 10 to 150 keV, total dose Φ = 2 × 10¹⁶cm^-2Multi-stage injection. As a result, an impurity concentration of 1 × 10 6 is obtained in a region having a depth of 0.25 μm from the surface.²⁰cm^-3of²⁷Al⁺An injection layer is formed. Thereafter, the metal film of the ion implantation mask is removed, and the substrate temperature T_SUBAs shown in FIG. 19A, p-type deep expansion diffusion regions 25a, 25b,... Are selectively formed by activation heat treatment at about = 1600 ° C. The p-type deep expansion diffusion regions 25a, 25b,... are the gate regions of the surface gate type BSIT. At this time, the width of each of the deep expansion type diffusion regions 25a, 25b,... Is about 2 μm. In addition, the width of the channel sandwiched between the pair of mold deep expansion diffusion regions 25a and deep expansion diffusion regions 25b is set to about 1 μm near the surface. Here, the ion implantation conditions as described above were used for boron and aluminum. However, in order to effectively perform pinch-off by the gate, the acceleration energy E_ACCFurther, the p-type deep expansion diffusion regions 25a, 25b,... Can be formed in a substantially trapezoidal shape as shown in FIG. As described above, boron having a diffusion coefficient about several times larger than that of aluminum is intentionally implanted deep in the p-type low resistance region, so that after the activation heat treatment, as shown in FIG. The width of the gate regions 25a, 25b,... Can be effectively expanded toward the inside of the substrate. Another advantage of implanting boron deeply is that the mass is lighter than aluminum, so that damage during implantation can be further reduced, and as a result, leakage current at pinch-off can be greatly suppressed.
[0099]
(B) Next, as shown in FIG. 19A, boron is applied to the acceleration energy E on the entire surface of the n-type epitaxial growth layer 21._ACC= 10 to 200 keV, total dose Φ = 5 × 10¹²cm^-2Multistage ion implantation is performed under the following conditions. An ion implantation mask may be formed, and selective ion implantation may be performed in the gate regions 25a, 25b,.
[0100]
(C) After ion implantation of boron, an activation heat treatment at about 1600 ° C. is performed, and as shown in FIG. 19B, the impurity concentration extends from the surface of the n-type epitaxial growth layer 21 to a depth of about 0.5 μm. 1 × 10¹⁷cm^-3The p-type base region 72 is formed. Next, polycrystalline silicon is deposited on the surface of the n-type epitaxial growth layer 21 by the CVD method. Then, the polycrystalline silicon is thermally oxidized to form an oxide film 91 on the surface of the n-type epitaxial growth layer 21 as shown in FIG. When this polycrystalline silicon is thermally oxidized, a thin oxide film 30 is also formed on the back surface of the low-resistance SiC substrate 11. In addition to the above method, the oxide film may be deposited by a CVD method using SiH4, N2O, or the like.
[0101]
(D) Further, a second metal film 32 is deposited on the surface of the oxide film 91 by vacuum evaporation or sputtering. For example, Mo can be used as the second metal film 32. Then, a resist 33 is spin-coated on the second metal film 32. Then, the resist 33 is patterned by photolithography as shown in FIG. Then, using the patterned resist 33 as an etching mask, the second metal film 32 is etched by RIE to form a second mask 32M for ion implantation as shown in FIG. Following the RIE of the second metal film 32, the underlying oxide film 91 is also selectively removed by RIE to expose part of the surface of the n-type epitaxial growth layer 21. Then, through the second mask 32M for ion implantation, as shown in FIG._SUB= Around 700 ℃³¹P⁺Accelerate energy E_ACC= 10 to 200 keV, total dose Φ = 5 × 10¹⁵cm^-2The multi-stage ion implantation is selectively performed under the following conditions. Then, after removing the second mask 32M for ion implantation and the oxide film 91, the substrate temperature T_SUBAs a result of activation heat treatment at about 1600 ° C., as shown in FIG.²⁰cm^-3N-type source region 35 is formed.
[0102]
(E) Next, after the oxide film 31 is formed again on the substrate surface by the CVD method or the like, the oxide film 31 is patterned using RIE or the like using the resist patterned in the same manner as described above as an etching mask. Thereafter, the resist is removed, and the opening of the patterned oxide film 31 is used as a source contact hole. Thereafter, the surface of the oxide film 31 having the source contact hole is covered with a resist, and the thin oxide film 30 on the back surface of the low-resistance SiC substrate 11 is etched with diluted hydrofluoric acid (HF) or buffered HF. On the back surface of the n-type low resistance SiC substrate 11, a Ni film is deposited as a third metal film 43 with a thickness of about 1 μm to form a drain electrode 43. Next, an Al film is deposited on the surface of the n-type source region 35 as a fourth metal film with a thickness of about 1 μm. Then, a resist is spin-coated on the fourth metal film. Then, the resist is patterned by photolithography so that the resist remains above the source region 35. Then, using the patterned resist as an etching mask, the fourth metal film is etched, and the fourth metal film as shown in FIG. 20F is selectively left on the source region 35 to form the source electrode 41. To do. Next, a resist is spin-coated on the source electrode 41 and the oxide film 31 exposed from the source electrode 41. Then, by photolithography, the resist is patterned so as to have an opening on each of the deep expansion type diffusion regions (gate regions) 25a, 25b,. Then, using the patterned resist as an etching mask, the oxide film 31 is selectively etched to expose the surfaces of the gate regions 25a, 25b,..., And a gate contact as shown in FIG. Open a hole. Thereafter, a Ti film is deposited on the entire surface sequentially with a thickness of about 200 nm and an Al film with a thickness of about 1 μm. A resist is spin-coated on the Al film, and patterning is performed by a photolithography technique so that the resist is left on the deep expansion type diffusion regions (gate regions) 25a, 25b,. Then, using the patterned resist as an etching mask, as shown in FIG. 20F, the Al film and the Ti film are selectively etched sequentially by RIE to form patterns of the gate electrodes 45a and 45b. After that, the substrate temperature T_SUB= Sintering treatment at 800 to 1150 ° C., for example, 950 ° C. for about 5 minutes to improve the ohmic contact between the source electrode 41, the drain electrode 43 and the gate electrodes 45a and 45b. This completes the outline process of the surface gate type BSIT.
[0103]
The results of evaluating the electrical characteristics of the surface gate type BSIT manufactured as described above are as follows. With a surface gate type BSIT having a withstand voltage of 1000 V, the leakage current when applying a gate voltage of −10 V and a drain voltage of 600 V is 1 × 10^-6A / cm² The on-resistance is 18mΩcm² It became. On the other hand, the SiC surface gate type BSIT according to the prior art has an on-resistance of 26 mΩcm when compared with the same withstand voltage of 1000 V.² Before and after. Therefore, in the surface gate type BIT according to the fifth embodiment, about 8 mΩcm.² The on-resistance can be reduced.
[0104]
Here, the on-resistance is about 8 mΩcm according to the fifth embodiment.² The reason for the reduction is that the parasitic resistance caused by the depletion layer extending from the pn junction between the p-type deep expansion diffusion regions 25a, 25b,...² This is due to the reduction. 20 (f), the width of the gate regions 25a, 25b,... Can be effectively expanded toward the inside of the substrate. Also, since boron with a lighter mass is implanted deeper, damage during implantation can be greatly reduced. As a result, in the surface gate type BSIT, the forward withstanding voltage characteristics such as withstand voltage and leakage current are not impaired. Resistance can be lowered sufficiently. In the fifth embodiment, by providing the p-type base region 72, a normally-off type surface gate type BSIT is realized.
[0105]
Further, as shown in FIG. 21, an n-type region 73 having a low impurity concentration may be provided between the n-type source region 35 and the p-type base region 72.
[0106]
Furthermore, the invention according to the fifth embodiment can also be applied to the bipolar transistor (BJT) shown in FIG. A BJT according to a modification (second modification) of the fifth embodiment of the present invention is provided on a first main electrode region (collector region) 81 made of a SiC substrate and on the first main electrode region 81. A first conductivity type drift region (n-type epitaxial growth layer) 21 made of the wide forbidden band width material, and a plurality of second conductivity type deep expansion type diffusion regions 82 a and 82 b provided inside the drift region 21. ,..., A p-type base region 83 sandwiched between a plurality of deep expansion diffusion regions 82a, 82b,..., A first conductivity type provided inside the p-type base region 83. A second main electrode region (emitter region) 84 is formed.
[0107]
In the BSIT shown in FIG. 20F, the impurity concentration of the base region 72 is set sufficiently lower than the deep expansion type diffusion regions 25a, 25b,. The space is almost punching through. However, in the BJT shown in FIG. 22, the impurity concentration of the p-type base region 83 is set higher than that of the base region 72. For example, the impurity concentration of the p-type base region 83 is 1 × 10¹⁸cm^-3~ 1x10¹⁹cm^-3Is set to about. Therefore, a neutral p-type base region 83 remains between the collector region 81 and the emitter region 84, and the collector voltage applied to the collector region 81 is less likely to affect the emitter region 84 side. .
[0108]
Each of the deep-expanded diffusion regions 82a, 82b,... Has a three-dimensional shape in which the horizontal cross-sectional area gradually increases as it approaches the first main electrode region 81 from the surface of the drift region 21. In this case, the p-type deep expansion type diffusion regions 82a, 82b,... Function as an external base region (base electrode extraction region) of the BJT. A collector electrode 87 is in ohmic contact with the collector region 81, and an emitter electrode 86 is in ohmic contact with the emitter region 84. A base electrode 85 made of an Al / Ti composite film is in ohmic contact with the base electrode extraction regions 82a, 82b,. In the BJT shown in FIG. 22, the p-type deep expansion diffusion regions 82a, 82b,... Are effectively expanded toward the inside of the substrate, so that they are connected to the p-type base region 72 of the internal base with a low resistance. As a result, the base resistance can be greatly reduced. That is, it is possible to increase the frequency of BJT. In addition, since it is a bipolar device, it is possible to use conductive modulation and to further reduce the on-resistance.
[0109]
(Sixth embodiment)
The semiconductor device manufacturing methods described in the second to fifth embodiments of the present invention can also be applied to electrostatic induction thyristors (SI thyristors). In the case of an SI thyristor, the conductivity type of the n-type low resistance SiC substrate 11 in the surface gate type SIT structure shown in FIG. 5 (i) may be a p-type low resistance SiC substrate 51 as shown in FIG.
[0110]
That is, the SI thyristor according to the sixth embodiment of the present invention includes a first main electrode region 51 and a wide forbidden band width material provided on the first main electrode region 51 as shown in FIG. A first conductivity type drift region 21, a plurality of second conductivity type deep expansion diffusion regions 25 a, 25 b,... Provided in the drift region 21, and a plurality of deep expansion diffusions. The first conductive type second main electrode region 53 is provided between the regions 25a, 25b,... As in the first embodiment of the present invention, each of the deep-expanded diffusion regions 25a, 25b,... Extends in the horizontal direction as it approaches the first main electrode region 51 from the surface of the drift region 21. It has a three-dimensional shape that gradually increases in area. Each of the deep expansion diffusion regions 25a, 25b,... Is a control electrode region (gate regions 25a, 25b,. ). The first main electrode region 51 functions as an anode region of the SI thyristor. The second main electrode region 53 functions as a cathode region of the SI thyristor. Each of the plurality of deep-expanded diffusion regions 25a, 25b,... Is located in an upper region made of the first impurity element and a lower forbidden band than the first impurity element. It consists of a lower region made of a second impurity element having a large diffusion coefficient in the width material.
[0111]
An anode electrode 52 is in ohmic contact with the first main electrode region (anode region) 51, and a cathode electrode 54 is in ohmic contact with the second main electrode region (cathode region) 53. Further, gate electrodes 45a and 45b are in ohmic contact with the deep expansion type diffusion regions (gate regions) 25a, 25b,.
[0112]
In the SI thyristor, the height of a potential barrier (potential) that is a saddle point in a two-dimensional space of the potential between the cathode and the anode and the potential in the channel due to the gate voltage is controlled by the anode voltage and the gate voltage. The potential barrier (potential) is formed in front of the second main electrode region (cathode region) 35 under the influence of the potential of the deep expansion type diffusion regions (gate regions) 25a, 25b,. The anode current flows depending on the height of the potential barrier (potential). The turn-on of this SI thyristor is performed by capacitively coupling the height of the potential barrier formed in the drift region 21 by applying a positive potential to the deep expansion type diffusion regions (gate regions) 25a, 25b,. Realized by lowering by the electric induction effect). In other words, electrons are injected from the second main electrode region (cathode region) 35 into the drift region 21 by decreasing the height of the potential barrier. The injected electrons are accumulated on the front surface of the first main electrode region (anode region) 51 and promote the injection of holes from the first main electrode region (anode region) 51. That is, a large amount of electrons and holes start to flow instantaneously. The turn-off is performed by applying a negative potential or a zero potential to the deep expansion type diffusion regions (gate regions) 25a, 25b,..., And injecting into the drift region 21 from the second main electrode region (cathode region) 35. Start by blocking the electrons that are made.
[0113]
In the case of a normally-off type SI thyristor, a deep expansion type diffusion region (gate region) 25a, 25b,..., Zero potential is applied, and the drift region 21 is supplied from the second main electrode region (cathode region) 35. The electrons injected into the are blocked. In the case of a normally-on type SI thyristor, deep expansion type diffusion regions (gate regions) 25a, 25b,..., Negative potential is applied to increase the height of the potential barrier (potential), and the second Electrons injected into the drift region 21 from the main electrode region (cathode region) 35 are blocked. However, as long as electrons accumulated on the front surface of the first main electrode region (anode region) 51 do not disappear due to recombination or the like, there is injection of holes from the first main electrode region (anode region) 51. So there is a tail current.
[0114]
In the case of the SI thyristor as well, the cathode area can be relatively increased if compared with a constant pinch-off characteristic. Therefore, a lower on-resistance can be obtained with the same breakdown voltage.
[0115]
That is, similarly to SIT, in the case of an SI thyristor, forward loss can be sufficiently reduced without impairing gate breakdown voltage characteristics such as breakdown voltage and leakage current, and high-efficiency switching is possible.
[0116]
The manufacturing method of the SI thyristor according to the sixth embodiment of the present invention is the manufacturing method of the surface gate type SIT described with reference to FIGS. 3 to 5, and shows the conductivity type of the n-type low resistance SiC substrate 11. As shown in FIG. 23, if the p-type low-resistance SiC substrate 51 is changed, the rest is basically the same. Therefore, redundant description is omitted.
[0117]
FIG. 24 is a cross-sectional view of a semiconductor device according to a modification (first modification) of the sixth embodiment of the present invention. In the anode short-type SI thyristor shown in FIG. 24, the anode region is divided into a plurality of divided anode regions 62a, 62b, 62c,..., And n-type short regions 61a, 61b,. The SI anode short structure is formed. Further, the divided anode regions 62a, 62b, 62c,... Have the structure of a deep expansion diffusion region similar to the gate regions 25a, 25b,. In this case, electrons can be swept to the short regions 61a and 61b by the potentials of the divided anode regions 62a, 62b, 62c,... And the short regions 61a and 61b. Therefore, the tail current at the time of turn-off becomes small, and high-speed switching is possible. Note that the pitch of the divided anode regions 62a, 62b, 62c,... May be selected to be not more than twice the electron diffusion length.
By using a plurality of divided anode regions 62a, 62b, 62c,... Having the structure of the deep expansion type diffusion region shown in FIG. 24, the anode area can be effectively increased while increasing the effective area of the anode region. Electrons accumulated on the entire surface of the region can be extracted using the short regions 61a, 61b,. For this reason, the tail current can be suppressed without increasing the on-resistance. Therefore, an anode short-type SI thyristor that simultaneously exhibits a low on-voltage and a high-speed turn-off characteristic can be obtained.
[0118]
FIG. 25 is a cross-sectional view of a semiconductor device according to a modification (second modification) of the sixth embodiment of the present invention. The cut gate type SI thyristor shown in FIG. 25 corresponds to a structure in which the conductivity type of the resistive SiC substrate 11 of the cut gate type SIT according to the third embodiment shown in FIG.
[0119]
FIG. 26 is a cross-sectional view of a semiconductor device according to a modification (third modification) of the sixth embodiment of the present invention. The normally-off type SI thyristor shown in FIG. 26 corresponds to a structure in which the conductivity type of the resistive SiC substrate 11 of the BSIT according to the fifth embodiment shown in FIG.
(Seventh embodiment)
FIG. 27 is a cross-sectional view of a lateral UMOSFET (lateral UMOSFET) according to a seventh embodiment of the present invention. The difference between the horizontal UMOSFET according to the seventh embodiment and the vertical UMOSFET according to the fourth embodiment is that the drain electrode 90 is formed not on the back surface of the substrate but on the surface of the first epitaxial growth layer 21. It is.
[0120]
In the seventh embodiment, instead of the p-type second epitaxial growth layer 55 formed on the first epitaxial growth layer 21 by the epitaxial method in the fourth embodiment, a certain region is formed on the first epitaxial growth layer 21. For example, striped p-type body regions 64a, 64b, 64c,... Are formed by selective ion implantation using boron, aluminum, or both. Next, an n-type drain region 89 is formed on the first epitaxial growth layer 21 at a position away from the p-type body regions 64a, 64b, 64c,. Next, between the p-type body regions 64a, 64b, 64c,... And the n-type drain region 89, one or more p-type field relaxation regions 64d, 64e,. It is provided in parallel with the body regions 64a, 64b, 64c,. The p-type electric field relaxation regions 64d, 64e,... Relax the electric field concentration at the ends of the p-type body regions 64a, 64b, 64c,. Next, the drain electrode 90 is formed on the n-type drain region 89. Here, the drain electrode 90 is preferably formed in parallel with the gate electrodes 45a, 45b,... At a predetermined distance from the gate electrodes 45a, 45b,. The structure other than the above steps is basically the same as that of the vertical UMOSFET according to the fourth embodiment shown in FIG. The horizontal UMOSFET is thus completed.
[0121]
In the horizontal UMOSFET, since the source electrodes 41a, 41b, 41c,... And the drain electrode 90 are provided on the same surface, it is easy to integrate the monolithic IC on the same semiconductor chip. In addition, wiring work is simplified even when incorporated in a hybrid IC or the like. Further, since the drain electrode 90 is provided in each semiconductor device, the degree of freedom of surface wiring and connection is increased, and the design is facilitated.
[0122]
The configuration of the n-type drain region 8 and the drain electrode 90 shown in the seventh embodiment can be similarly applied to the configuration of the modification of the fourth embodiment shown in FIG.
[0123]
(Eighth embodiment)
FIG. 28 shows a semiconductor integrated circuit in which the JBS diode according to the first embodiment as the auxiliary element 2 and the anode short-type SI thyristor according to the sixth embodiment as the main element 1 are arranged on the same semiconductor chip. It is. The manufacturing process of the semiconductor integrated circuit according to the eighth embodiment is as described in detail in the first and sixth embodiments, and is omitted here.
[0124]
In the semiconductor integrated circuit according to the eighth embodiment, a unit cell is constituted by the JBS diode as the auxiliary element 2 and the anode short-type SI thyristor as the main element 1. The anode short-type SI thyristor is a reverse conducting SI thyristor, and the JBS diode functions as a free wheel diode connected in parallel to the reverse conducting SI thyristor. That is, a parallel connection structure of a reverse conducting SI thyristor and a free wheel diode is used as a unit cell, and these unit cells are periodically formed in a stripe shape in a multi-channel structure in the n-type drift region 21.
[0125]
Here, the p-type gate regions 25a, 25b,... Of each unit cell function as p-type gate regions 25a, 25b,... Forming an anode short-type SI thyristor region, and a JBS diode. It also functions as a guard ring. Therefore, the area of the entire device can be reduced and the device current density can be improved as compared with the case where the anode short-type SI thyristor and the JBS diode are independently formed.
[0126]
(Other embodiments)
As described above, the present invention has been described according to the first to eighth embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.
[0127]
In the first embodiment, if the deep expansion diffusion regions 18a and 18b are formed in a substantially trapezoidal shape as shown in FIG. 29, the leakage current in the reverse direction can be further reduced. In order to form a trapezoid, acceleration energy E_ACCAnd adjusting the dose Φ. In any case, since boron having a diffusion coefficient about several times larger than that of aluminum is intentionally implanted into deep deep diffusion regions 18a and 18b, after activation heat treatment after ion implantation, The width of the deep expansion type diffusion regions 18a and 18b can be effectively expanded toward the inside of the substrate. Another advantage of implanting boron deeply is that the mass is lighter than aluminum, so that damage during implantation can be further reduced, and as a result, leakage current at pinch-off can be greatly suppressed.
[0128]
In the description of the first to eighth embodiments already described, the case where the n-type is used as the first conductivity type and the p-type is used as the second conductivity type has been described. Of course, it is also good.
[0129]
In the first to eighth embodiments, SiC has been described by way of example. Forbidden band width Eg = ZnTe of about 2.2 eV, forbidden band width Eg = CdS of about 2.4 eV, forbidden band width Eg = ZnSe with about 2.7 eV, GaN with forbidden band width Eg = about 3.4 eV, ZnS with forbidden band width Eg = about 3.7 eV, and wide band gap semiconductors such as diamond with forbidden band width Eg = about 5.5 eV , As well as applicable.
[0130]
The present invention is not limited to the JBS diode, surface gate type SIT, cut gate type SIT, vertical UMOSFET, BSIT, SI thyristor, lateral UMOSFET, and integrated circuit described in the first to eighth embodiments. It can also be applied to various other semiconductor devices including MOS composite devices such as emitter-switched thyristors (EST). Further, in the vertical UMOS structure of FIGS. 15L and 18L described in the fourth embodiment, if the n-type low-resistance SiC substrate 11 is replaced with a p-type low-resistance SiC substrate, a trench type is obtained. It functions as an IGBT. In the lateral UMOS structure of FIG. 27 described in the seventh embodiment, if the n-type drain region 89 is replaced with a p-type collector region, it functions as a lateral IGBT. Furthermore, in the BSIT and BJT structures of FIG. 20 (f) and FIG. 22 described in the fifth embodiment, if the n-type low-resistance SiC substrate 11 is replaced with a p-type low-resistance SiC substrate, a normally-off type SI thyristor or Functions as a GTO thyristor. In addition, the present invention can be variously modified and applied to various other semiconductor devices without departing from the gist of the present invention.
[0131]
In the description of the first to eighth embodiments already described, the oxide film is used as the insulating film formed on the trench or the surface. However, tantalum oxide (Ta₂0_Five), Silicon nitride (Si_ThreeN_FourOther insulating films such as aluminum nitride (AlN) may be used.
[0132]
As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.
[0133]
【The invention's effect】
According to the first feature of the present invention, the forward resistance can be sufficiently lowered without impairing the reverse characteristics such as withstand voltage and leakage current.
[0134]
According to the second feature of the present invention, the forward resistance can be sufficiently reduced without impairing the breakdown voltage characteristics of the control electrode region of the semiconductor device.
[0135]
According to the third feature of the present invention, the deep expansion type diffusion region significantly relaxes the electric field strength of the gate insulating film in the vicinity of the bottom of the trench, and an insulated gate semiconductor device having a higher breakdown voltage can be realized. .
[0136]
According to the fourth feature of the present invention, similarly to the third feature, a lateral insulated gate semiconductor device having a higher breakdown voltage can be realized. Further, since the first and second main electrode regions are provided on the same side, integration is easy.
[0137]
According to the method for manufacturing a semiconductor device according to the fifth feature of the present invention, the semiconductor device according to the first to fourth features can be easily manufactured.
[Brief description of the drawings]
FIG. 1 is a process cross-sectional view for explaining a manufacturing process of a JBS diode according to a first embodiment of the present invention (No. 1).
FIG. 2 is a process cross-sectional view for explaining a manufacturing process of the JBS diode according to the first embodiment of the present invention (No. 2).
FIG. 3 is a process cross-sectional view for explaining a manufacturing process of a surface gate type SIT according to the second embodiment of the present invention (No. 1).
FIG. 4 is a process cross-sectional view for explaining a production process of a surface gate type SIT according to the second embodiment of the present invention (No. 2).
FIG. 5 is a process cross-sectional view for explaining a production process of a surface gate type SIT according to the second embodiment of the present invention (No. 3).
FIG. 6 is a process cross-sectional view for explaining a manufacturing process of a cut gate type SIT according to the third embodiment of the present invention (No. 1).
FIG. 7 is a process cross-sectional view for explaining a manufacturing process of a cut gate type SIT according to the third embodiment of the present invention (No. 2).
FIG. 8 is a process cross-sectional view for explaining a manufacturing process of a cut gate type SIT according to the third embodiment of the present invention (No. 3).
FIG. 9 is a process cross-sectional view for explaining a manufacturing process of a trench sidewall gate type SIT according to a modification of the third embodiment of the present invention (No. 1).
FIG. 10 is a process cross-sectional view for explaining a manufacturing process of a trench sidewall gate type SIT according to a modification of the third embodiment of the present invention (No. 2).
FIG. 11 is a process cross-sectional view for explaining a manufacturing process of a trench sidewall gate type SIT according to a modification of the third embodiment of the present invention (No. 3).
FIG. 12 is a process cross-sectional view for explaining a manufacturing process of a vertical UMOSFET according to the fourth embodiment of the present invention (No. 1).
FIG. 13 is a process cross-sectional view for explaining a manufacturing process of the vertical UMOSFET according to the fourth embodiment of the present invention (No. 2).
FIG. 14 is a process cross-sectional view for explaining a manufacturing process of the vertical UMOSFET according to the fourth embodiment of the present invention (No. 3).
FIG. 15 is a process cross-sectional view for explaining a manufacturing process of the vertical UMOSFET according to the fourth embodiment of the present invention (# 4).
FIG. 16 is a process cross-sectional view for explaining a manufacturing process of a vertical UMOSFET according to a modification of the fourth embodiment of the present invention (part 1);
FIG. 17 is a process cross-sectional view for explaining a manufacturing process of the vertical UMOSFET according to the modification of the fourth embodiment of the present invention (part 2);
FIG. 18 is a process cross-sectional view for explaining a manufacturing process of the vertical UMOSFET according to the modification of the fourth embodiment of the present invention (part 3);
FIG. 19 is a process cross-sectional view for explaining a manufacturing process of a BSIT according to the fourth embodiment of the present invention (part 1);
FIG. 20 is a process cross-sectional view for explaining the manufacturing process of the BSIT according to the fourth embodiment of the present invention (No. 2).
FIG. 21 is a cross-sectional view for explaining the structure of a BSIT according to a modification (first modification) of the fourth embodiment of the present invention.
FIG. 22 is a cross-sectional view for explaining the structure of a BSIT according to another modification (second modification) of the fourth embodiment of the present invention;
FIG. 23 is a schematic cross-sectional view for explaining the structure of an SI thyristor according to a sixth embodiment of the present invention.
FIG. 24 is a schematic cross-sectional view for explaining the structure of an SI thyristor according to a modification (first modification) of the sixth embodiment of the present invention.
FIG. 25 is a schematic cross-sectional view for explaining the structure of an SI thyristor according to another modification (second modification) of the sixth embodiment of the present invention.
FIG. 26 is a schematic cross-sectional view of an SI thyristor according to still another modified example (third modified example) of the sixth embodiment of the present invention.
FIG. 27 is a schematic cross-sectional view for explaining the structure of a lateral UMOS according to a seventh embodiment of the present invention.
FIG. 28 is a schematic cross-sectional view for explaining the structure of a semiconductor integrated circuit according to an eighth embodiment of the present invention.
FIG. 29 is a schematic cross-sectional view of a JBS diode according to another embodiment of the present invention.
FIG. 30 is a schematic cross-sectional view of a surface gate type SIT according to another embodiment of the present invention.
[Explanation of symbols]
1 Main element
2 Auxiliary elements
11 n-type low resistance SiC substrate (first main electrode region)
12, 21 n-type epitaxial growth layer (first epitaxial growth layer)
13 Metal film
13M ion implantation mask
14, 33, 56 resist
15a, 15b, 18a, 18b, 25a, 25b, 26a, 26b Deep expansion type diffusion region
16 Ohmic electrode (cathode electrode)
17 Schottky electrode (anode electrode)
19 n-type epitaxial growth layer (second epitaxial growth layer)
24 Ion implantation mask (metal film)
30, 31, 34, 37, 58, 74, 76, 77, 91 Oxide film
32 Second metal film
Second mask for 32M ion implantation
35, 35a, 35b, 35c, 63a, 63b, 63c, 63d Second main electrode region (source region)
36 4th metal film
39a, 39b, 39c, 39d One side p-type deep expansion type diffusion region (gate region)
41, 41a, 41b, 41c Source electrode
43 Third metal film (drain electrode)
45a, 45b, 45c Gate electrode
46, 71a, 71b Insulating film
47a, 47b buried insulating film
48a, 48b trench
51 First main electrode region (anode region)
52 Anode electrode 5
53 Second main electrode region (cathode region)
54 Cathode electrode
55 p-type epitaxial growth layer (second epitaxial growth layer)
57a, 57b n-type low resistance region
61a, 61b, 61c Short area
62a, 62b, 62c, 62d Split anode region
64a, 64b, 64c p-type body regions
64d, 64e p-type electric field relaxation region
65 Gate oxide film
67 Interlayer insulation film
68 Mask for ion implantation
69a, 69b, 69c Electric field relaxation region (deep expansion type diffusion region)
72,83 p-type base region
73 n-type region
81 First main electrode region (collector region)
82a, 82b Deep expansion type diffusion region (base electrode extraction region)
84 Second main electrode region (emitter region)
85 Base electrode
86 Emitter electrode
87 Collector electrode
89 Drain region (first main electrode region)
90 Drain electrode

Claims (9)

An ohmic contact region of a first conductivity type;
A drift region of a first conductivity type provided on the ohmic contact region and made of a wide forbidden band width material having a lower impurity concentration than the ohmic contact region and having a wider forbidden band than 2.2 eV;
A plurality of top surfaces exposed on the surface of the drift region, provided inside the drift region, and having a horizontal cross-sectional area gradually increasing from the surface of the drift region toward the ohmic contact region. A deep conductivity type diffusion region of a second conductivity type;
A Schottky electrode that forms a Schottky junction with the drift region provided in contact with the surface of the drift region, and each of the plurality of deep expansion diffusion regions includes an upper region containing a first impurity element; A semiconductor device comprising: a lower region located under the upper region and including a second impurity element having a larger diffusion coefficient in the wide forbidden band width material than the first impurity element . A first main electrode region of a first conductivity type or a second conductivity type;
A drift region of a first conductivity type that is provided above the first main electrode region and is made of a wide forbidden band width material having a lower impurity concentration than the first main electrode region and having a wider forbidden band than 2.2 eV;
A plurality of top surfaces exposed on the surface of the drift region, provided inside the drift region, and having a horizontal cross-sectional area gradually increasing from the surface of the drift region toward the ohmic contact region. A deep conductivity type diffusion region of a second conductivity type;
A second main electrode region of a first conductivity type that is provided inside the drift region with a top portion exposed at the surface of the drift region and sandwiched between the plurality of deep expansion diffusion regions; Each of the expansion type diffusion regions functions as a control electrode region for controlling a current flowing between the first and second main electrode regions.   The semiconductor device according to claim 2, further comprising a second conductivity type base region between the plurality of deep-expanded diffusion regions. A first main electrode region of a first conductivity type or a second conductivity type;
A drift region of a first conductivity type that is provided above the first main electrode region and is made of a wide forbidden band width material having a lower impurity concentration than the first main electrode region and having a wider forbidden band than 2.2 eV;
A plurality of body regions of the second conductivity type disposed on the surface of the drift region;
A second main electrode region of the first conductivity type disposed on the surface of the body region;
A plurality of trenches that are dug in the direction of the first main electrode region from the surface of the second main electrode region and reach the drift region through the body region; and a gate insulating film formed on the inner walls of the plurality of trenches When,
A gate electrode disposed on a surface of the gate insulating film inside the plurality of trenches;
Provided inside the drift region below the plurality of trenches, each having a horizontal cross-sectional area gradually increasing from the bottom of the trench toward the first main electrode region region, and functions as an electric field relaxation region A plurality of second conductivity type deep expansion diffusion regions. A first main electrode region of a first conductivity type or a second conductivity type;
  A drift region of a first conductivity type that is provided above the first main electrode region and is made of a wide forbidden band width material having a lower impurity concentration than the first main electrode region and having a wider forbidden band than 2.2 eV;
  A second main electrode region of the first conductivity type disposed on the surface of the drift region;
  A plurality of trenches penetrating the second main electrode region and reaching the drift region from the surface of the second main electrode region toward the first main electrode region;
  A gate insulating film formed on the inner walls of the plurality of trenches;
  A gate electrode disposed on a surface of the gate insulating film inside the plurality of trenches;
  Provided inside the drift region below the plurality of trenches and in contact with the gate electrode Subsequently, a plurality of second-conductivity-type deep expansion diffusions each having a horizontal cross-sectional area gradually increasing from the bottom of the trench toward the first main electrode region and functioning as an electric field relaxation region. region
  A semiconductor device comprising: A drift region of a first conductivity type composed of a wide forbidden band material having a wider forbidden band than 2.2 eV;
A plurality of body regions of the second conductivity type disposed on the surface of the drift region;
A first main electrode region of a first conductivity type or a second conductivity type spaced apart from the body region and disposed on the surface of the drift region at a higher impurity concentration than the drift region;
A second main electrode region of the first conductivity type disposed on the surface of the body region;
A plurality of trenches that penetrate the body region from the surface of the second main electrode region and reach the drift region; and a gate insulating film formed on an inner wall of the plurality of trenches;
A gate electrode disposed on a surface of the gate insulating film inside the plurality of trenches;
Provided inside the drift region of a lower portion of the plurality of trenches, the direction from the bottom of the trench in the direction away from the body region, is adapted to the respective horizontal cross-sectional area gradually wider, it serves as an electric field relaxation region A semiconductor device comprising: a plurality of second conductivity type deep expansion diffusion regions. Each of the plurality of deep expansion diffusion regions is
An upper region containing a first impurity element;
Located in the lower portion of the upper region, claim 2, characterized in that it consists of a lower region including a large second impurity element of the diffusion coefficient in the wide bandgap material than the first impurity element - the semiconductor device according to any one of 6. Forming a mask for ion implantation on the surface of the semiconductor region of the first conductivity type made of a wide forbidden band width material having a wider forbidden band than 2.2 eV;
A deep ion implantation step of implanting the first impurity ions exhibiting the second conductivity type into the semiconductor region a plurality of times while changing the acceleration energy using the ion implantation mask;
Using the ion implantation mask, the second impurity ions having a smaller diffusion coefficient in the semiconductor region than the first impurity ions are changed to a position shallower than the projection range of the first impurity ions, and the acceleration energy is changed. However, the shallow ion implantation process of implanting multiple times,
And a step of electrically activating the first and second impurity ions to form a deep expansion type diffusion region inside the semiconductor region by a heat treatment step. 9. The semiconductor device according to claim 8, wherein the wide forbidden band width material is silicon carbide (SiC), the first impurity ions are boron (B), and the second impurity ions are aluminum (Al). Manufacturing method.

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