JP5470254B2 - Junction type semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a junction type semiconductor device and a manufacturing method thereof, and more particularly to a junction type semiconductor device suitable for suppressing recombination of electrons and holes in the region of a base layer and increasing a current gain. About.

  Silicon carbide (Silicon Carbide, hereinafter referred to as “SiC”) has a characteristic that it has a larger band gap energy than silicon that is widely applied to semiconductor devices. Therefore, a semiconductor device using SiC is suitable for high voltage, high power, and high temperature operation conditions, and is expected to be applied to power devices and the like. The structures of SiC power devices currently being researched and developed are mainly classified into two types, “MOS type” and “junction type”.

  Here, it demonstrates from a viewpoint of the performance improvement of a junction type SiC power device. The junction type SiC power device includes a static induction transistor (hereinafter referred to as “SIT”), a junction field effect transistor (hereinafter referred to as “JFET”), or bipolar. A transistor (Bipolar Junction Transistor; hereinafter referred to as “BJT”). In the following, SIT, JFET, and BJT are collectively referred to as “junction transistors”.

As an example of a conventional SIT, for example, one having a structure disclosed in Patent Document 1 is known. The SIT disclosed in Patent Document 1 is an n ⁺ type first high resistance layer, a p type channel doped layer, an n ⁻ type on the n ⁺ type 4H—SiC (0001) plane substrate serving as a drain region from below. The second high resistance layer and the n ⁺ type source region are stacked in this order. In the SIT, the source region thereof, n ⁺ -type source region from the top surface in the laminated structure, and the n ^- by being etched in a predetermined planar pattern shape to the middle of the mold the second high-resistance layer is separated form Is done. The SIT has a plurality of source regions separated on the upper surface based on a predetermined pattern shape. In the region between the plurality of separated source regions, an Al ion implantation process is subsequently performed to form a p-type gate region. Accordingly, each of the plurality of separated source regions is surrounded by a p-type gate region when viewed in a planar shape of the SIT. The SIT disclosed in Patent Document 1 has a structure in which the SiC surface in the SIT is covered with a surface recombination suppressing semiconductor layer between the source region and the gate region. This surface recombination suppressing semiconductor layer has a function of suppressing recombination between electrons flowing out from the source region (n ⁺ type source region and n ⁻ type second high resistance layer) and holes flowing out from the gate region. Yes. As a result, recombination of electrons from the source region and holes from the gate region is suppressed, and an improvement in the current amplification factor of the junction type semiconductor layer device is achieved.

Further, as an example of a conventional BJT, there is one having a structure described in Non-Patent Document 1 or Patent Document 2, for example. The BJT is laminated on the low resistance n ⁺ type 4H-SiC (0001) plane 8 degree off substrate in the order of the n ⁻ type high resistance region, the p type base region, and the n ⁺ type emitter region from below. It is formed. The emitter region is composed of a number of elongated regions. Electrodes for establishing electrical connection to the outside are formed in the emitter region, base region, and collector region.

  FIG. 10 shows a cross-sectional structure diagram of the BJT disclosed in Non-Patent Document 1. As shown in FIG. 10, the BJT 500 surrounds the collector region 501, which is an n-type low resistance layer, the n-type high resistance region 502, the base region 503 of the p-type region, the emitter region 504 of n-type low resistance, and the emitter region. The base contact region 505 of the p-type low resistance region is formed. A collector electrode 506, a base electrode 507, and an emitter electrode 508 for electrical connection are joined to the outside of the collector region 501, the base region 503, and the emitter region. Further, the entire exposed surface other than the electrodes of the BJT 500 is covered with a surface protective film 509.

JP 2006-269681 A JP 2006-351621 A

J. Zhang et al., “High Power (500V-70A) and High Gain (44-47) 4H-SiC Bipolar Junction Transistors” Materials Science Forum Vols. 457-460 (2004) pp. 1149-1152.

  In a junction transistor such as SIT or BJT, a control electrode portion called a gate or base (base contact region) is formed by a pn junction. In order to pass a current between main electrodes such as between a source and a drain or between a collector and an emitter, it is necessary to pass a current through the control electrode. When the current flowing between the main electrodes is “main current Id” and the current flowing through the control electrode is “control current Ig”, the ratio of both currents (Id / Ig) is called “current amplification factor”. In the development of junction transistors, increasing the value of the current amplification factor is an important issue.

  As a factor for reducing the current amplification factor, recombination of holes flowing from the control electrode (carrier of the control current Ig) and electrons flowing between the main electrodes (carrier of the main current Id) can be mentioned. The value of the recombination current depends on the electron density, hole density, and recombination level density, and the higher the density, the larger the recombination current.

  The SiC surface is known as a site where recombination is likely to occur. In order to reduce the density of recombination levels on the SiC surface, various proposals have been made in the process of forming a protective film by oxidizing the SiC surface. This point is also described in Patent Document 1. Further, in Patent Document 1, in order to reduce the recombination probability, a surface recombination suppressing semiconductor layer composed of a p-type region having a low concentration is provided on the SiC surface. When such a surface recombination-inhibiting semiconductor layer is formed, a potential barrier against electrons is formed on the SiC surface, so that the electron density on the SiC surface can be lowered. Furthermore, the hole density can be kept low by forming a high resistance layer on the SiC surface in a p-type region having a low concentration. By forming such a surface recombination suppressing semiconductor layer, even if a recombination level exists on the SiC surface of the junction transistor, the recombination probability can be reduced and the current amplification factor of the junction transistor is increased. be able to.

  As described above, in the junction transistor, many attempts have been made to increase the current amplification factor by suppressing recombination on the SiC surface. However, it is known that the recombination probability of electrons and holes is high even in the channel doped layer near the p-type gate region of SIT. However, in the development of a conventional junction transistor, there is no attempt to suppress recombination in the vicinity of the channel dope layer.

  The above-mentioned problem relating to SIT is also a problem that occurs in a BJT having a base region corresponding to the channel dope layer.

  The object of the present invention is to reduce the recombination probability of electrons and holes in the vicinity of the channel doped layer and the base region around the p-type gate region of the SIT and the p-type base contact region of the BJT. An object of the present invention is to provide a junction type semiconductor device capable of suppressing recombination of a main current flowing through a control electrode and a control current flowing through a control electrode and improving a current gain, and a method for manufacturing the same.

  A junction type semiconductor device according to one aspect of the present invention includes a first main electrode region (a first region corresponding to one main electrode), which is a substrate made of a silicon carbide semiconductor crystal, and one surface of the substrate. A second main electrode region (second region corresponding to the other main electrode) formed on the side, a high resistance layer formed between the first and second main electrode regions, and a second Cover the control electrode region formed around the main electrode region, the intermediate layer formed in the high resistance layer and in contact with the control electrode region, and the portion in contact with the control electrode region in the intermediate layer And a recombination suppression region formed on the substrate.

  In the junction type semiconductor device according to the one aspect, the first main electrode region is a drain region or a collector region, the second main electrode region is a source region or an emitter region, and the control electrode according to SIT or BJT. The use region is a gate region or a base contact region. The intermediate layer means a layer or region existing between the first and second main electrode regions. The intermediate layer is a base region in the case of BJT, and a channel dope layer in the case of SIT. Since the recombination suppression region is provided so as to cover the portion in contact with the adjacent region for the control electrode in the intermediate layer or the adjacent portion, in the conventional structure, in the region where the density of holes and electrons is high and recombination occurs frequently. By providing a potential barrier against electrons or the like, electrons or the like flowing from the source region or the like to the intermediate layer can be kept away by the recombination suppression region that is a potential barrier. Thereby, the density of electrons in this region can be reduced, and the current amplification factor can be increased.

  A junction type semiconductor device according to another aspect of the present invention includes a first main electrode region which is a substrate made of a silicon carbide semiconductor crystal, and a second main electrode formed on one surface side of the substrate. Formed in the high resistance layer, a high resistance layer formed between the first and second main electrode regions, a control electrode region formed around the second main electrode region, A first intermediate layer that is in contact with the control electrode region and has a low resistance, and is formed in the high resistance layer, is connected to the first intermediate layer, and is between the first and second main electrode regions. And a second intermediate layer disposed on the substrate.

  In the junction type semiconductor device according to another aspect, the first main electrode region is a drain region or a collector region, and the second main electrode region is a source region or an emitter region according to SIT or BJT. The electrode region is a gate region or a base contact region. As described above, the intermediate layer is a base region in the case of BJT and a channel dope layer in the case of SIT. By reducing the resistance of the first intermediate layer that is in contact with or adjacent to the control electrode region, the hole current flowing from the control electrode is likely to flow through the first intermediate layer and is difficult to flow in the vicinity of the SiC surface. It is possible to suppress recombination on the SiC surface where a large amount of is present, and to increase the current amplification factor.

  According to one aspect of the present invention, there is provided a method for manufacturing a junction type semiconductor device, comprising: a first step of forming a high resistance layer on a substrate made of a silicon carbide semiconductor crystal and serving as a first main electrode region; A second step of forming an intermediate layer in the layer, a third step of forming a low-resistance layer serving as a second main electrode region on the high-resistance layer, and control on the surface side of the high-resistance layer A fourth step of forming a recombination suppression region by ion implantation so as to be in contact with the upper and lower surfaces of the intermediate layer in the vicinity of the predetermined region where the electrode region is to be formed; and a predetermined region on the surface side of the high resistance layer. And a fifth step of forming the control electrode region in contact with the intermediate layer by ion implantation.

  According to another aspect of the present invention, there is provided a method of manufacturing a junction type semiconductor device including a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystal and serving as a first main electrode region; A second step of forming an intermediate layer therein, a third step of forming a low-resistance layer serving as a second main electrode region on the high-resistance layer, and a control electrode on the surface side of the high-resistance layer A fourth step of reducing the resistance of a part of the intermediate layer by ion implantation in the vicinity of a predetermined region where the formation of the control region is planned, and a control electrode region by ion implantation in the predetermined region on the surface side of the high resistance layer And a fifth step of forming so as to contact the low resistance portion of the intermediate layer.

The junction type semiconductor device according to the present invention has the following effects.
First, in a junction semiconductor device such as BJT or SIT, a recombination suppression region is provided in the intermediate layer that contacts the control electrode region so as to cover a portion that contacts the control electrode region. Electrons can be prevented from flowing into the intermediate layer, and recombination in the intermediate layer can be suppressed, whereby the current gain can be increased.

  Second, in the junction type semiconductor device, the first and second intermediate layers disposed between the first and second main electrode regions, and in particular, the first and second layers which are in contact with or adjacent to the control electrode region. Since the resistance of the intermediate layer is further lowered, the hole current flowing from the control electrode hardly flows in the vicinity of the SiC surface, and the current amplification factor can be increased.

  According to the method for manufacturing a junction type semiconductor device according to the present invention, the junction type semiconductor device according to the present invention can be manufactured by a simple manufacturing procedure.

1 is a partial longitudinal sectional view of a junction type semiconductor device (BJT) according to a first embodiment of the present invention. 1 is a plan view of a part of a junction type semiconductor device (BJT) according to a first embodiment. It is a fragmentary longitudinal cross-section explaining the problem of operation | movement of the conventional junction type semiconductor device (BJT). It is a fragmentary longitudinal cross-section explaining operation | movement of the junction type semiconductor device by 1st Example. 3 is a flowchart showing a method for manufacturing a junction type semiconductor device according to the first embodiment. It is a fragmentary longitudinal cross-section which shows the device structure corresponding to each process of the manufacturing method of the junction type semiconductor device which concerns on 1st Embodiment. It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 2nd Example of this invention. It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 3rd Example of this invention. It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 4th Example of this invention. It is a fragmentary longitudinal cross-section explaining the structure of the conventional junction type semiconductor device (BJT).

  Several preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

<First embodiment>
A first embodiment of a junction type semiconductor device according to the present invention will be described with reference to FIGS. FIG. 1 shows a unit structure of a junction type semiconductor device according to the first embodiment, and FIG. 2 is a plan view of the junction type semiconductor device. FIG. 1 is a vertical cross-sectional view of a portion including at least one emitter electrode in a cross section taken along line AA in FIG. This junction type semiconductor device shows an example of BJT (bipolar transistor). Note that the SIT (electrostatic induction transistor) is different in that the channel doped layer of the SIT corresponds to the base region of the BJT and the depth of the gate region of the SIT is deeper than the depth of the base contact region of the BJT. However, the other basic structural parts have substantially the same structure. 1 and 2 are a longitudinal sectional view and a plan view of an element portion as a unit of BJT.

  As shown in FIG. 2, the BJT 10 includes, for example, five emitter electrodes 19 arranged in parallel in a specific unit region on the upper surface of the device. These emitter electrodes 19 are surrounded by a base electrode 20.

In the longitudinal cross-sectional structure shown in FIG. 1, the BJT 10 has a collector region 11 formed of an n-type low-resistance layer (n ⁺ layer) formed on a lower surface portion having a SiC (silicon carbide) crystal, and the SiC crystal. An emitter region 12 made of an n-type low resistance layer (n ⁺ layer) formed on the upper side surface portion is provided. A layer forming the collector region 11 is a substrate.

As shown in FIG. 2, a base electrode 20 is formed around each of the plurality of emitter electrodes 19 so as to surround the emitter electrode 19 in the positional relationship of the plan view. This means that the periphery of the emitter region 12 located below the emitter electrode 19 is surrounded by the p-type base contact region 13 located below the base electrode 20. The base contact region 13 is formed up to a predetermined depth position. Further, in the BJT 10, a first n-type high resistance layer (n ⁻ layer) 14 A, a p-type base region 15, and a second n-type high resistance layer are disposed between the upper emitter region 12 and the lower collector region 11. (N ^- layer) 14B is laminated. The base region 15 of the BJT 10 corresponds to the channel doped layer of SIT. The base region 15 is formed so as to be in contact with and electrically connected to the base contact region 13.

  In this embodiment, the “n-type” is a “first conductivity type”, and the “p-type” is a “second conductivity type”.

In the BJT 10 according to the present embodiment, the p ⁺ type base contact region 13 and the layered p type base region 15 that is in contact with or adjacent to the base contact region 13 are covered above and below the portion. A recombination suppression region 16 is provided. The recombination suppression region 16 covers the upper and lower surfaces of a predetermined portion of the base region 15 in layers. The recombination suppression region 16 is a p ^- semiconductor having the same conductivity type as the base region 15 and having a higher resistivity than the base region 15, or the same conductivity type as the first and second n-type high resistance layers 14A and 14B. The n ⁻ semiconductor has a higher rate than the first and second n-type high resistance layers 14A and 14B. The base contact region 13 is formed so as to be in contact with the upper surface of the base region 15 and further enter the base region 15 from the upper surface.

  In the structure of the BJT 10 described above, as shown in FIG. 1, the collector electrode 18 is bonded to the lower surface of the collector region 11, the emitter electrode 19 is bonded to the upper surface of the emitter region 12, and the base contact region 13 A base electrode 20 is joined to the upper surface. On the upper surface of the BJT 10, the exposed surface between the emitter electrode 19 and the base electrode 20 is covered with a surface protective film 17 and is protected thereby.

  As shown in FIG. 2, an upper layer electrode 21 is provided above each of the emitter electrode 19 and the base electrode 20. In FIG. 1, the upper layer electrode 21 is not shown.

  In the BJT 10, the main current is an electron flow that flows from the emitter region 12 (or the emitter electrode 19) to the collector region 11 (or the collector electrode 18). The emitter region 12 and the collector region 11 are main electrode regions for flowing a main current. Energization (ON) and non-energization (OFF) of the main current are based on a base voltage applied to the base electrode 20, that is, a control signal applied between the base contact region 13 and the base region 15 and the emitter region 12. Be controlled. The base contact region 13 and the base region 15 are control electrode regions. When the applied voltage between the base and the emitter is 0 V or less, the BJT 10 does not flow main current and is turned off. When a voltage of a certain level or higher is applied between the base and the emitter, the BJT 10 is turned on due to the main current flowing. In the ON state, the pn junction formed between the gate region 13 and the source region 12 is forward-biased, and a hole current that is a control current flows from the gate region 13 to the source region 12.

  The characteristic structure of the BJT 10 will be described with reference to FIGS. 3 and 4 while comparing the conventional BJT structure with the BJT structure according to the present embodiment.

  FIG. 3 shows a BJT 10A having a conventional structure. In FIG. 3, the same elements as those described in FIG. When the BJT 10A is on, a hole current that is a control current flows into the emitter region 12 via the base electrode 20, the base contact region 13, and the base region 15. On the other hand, an electron current 12 which is a main current flows from the emitter region 12 to the collector region. Since holes exist at a high density in the base region 15, the holes 32 flow from the emitter region 12 and the electrons 33 existing in the vicinity of the base region 15 are actively recombined. In particular, the base region immediately below the base contact region 13 and the base region between the base contact region 13 and the emitter region 12 are regions in which recombination of electrons and holes is active even though the main current does not flow. This greatly affects the decrease in amplification factor.

In contrast to the BJT 10A having the conventional structure, in the BJT 10 according to the present embodiment, as shown in FIG. It is formed. The recombination suppression region 16 is formed by, for example, ion implantation in a region portion located between two adjacent emitter regions 12. The recombination suppressing region 16 is a p ^- semiconductor having the same conductivity type as the base region 15 and having a higher resistivity than the base region 15 or the same conductivity type as that of the first and second n-type high resistance layers 14A and 14B. The n ^- semiconductor is higher than the first and second n-type high resistance layers 14A and 14B.

When the recombination suppression region 16 is made of a p ⁻ semiconductor, it is formed of a “p ⁻ ” region, and the hole density in the recombination suppression region 16 is suppressed to be lower than that of the base region 15. In addition, since a potential barrier against electrons due to a pn junction is formed between the recombination suppression region 16 and the n ⁻ high resistance layers 14A and 14B, the entry of electrons into the base region 15 is suppressed. This is a high electron barrier against the electrons 33. Therefore, the presence of the recombination suppression region 16 causes the holes 32 flowing from the base contact region 13 to the base region 15 to move to the right in FIG. 4, and a part of the main current I2 flowing from the emitter region 12 is The base region 15 is not attracted to the vicinity of the base contact region. As shown in FIG. 4, the recombination of electrons and holes in the vicinity of the base region 15 is suppressed, and the current amplification factor of the BJT 10 can be improved.

When the recombination suppression region 16 is composed of an n ⁻ semiconductor, the electron density in the recombination suppression region 16 is suppressed to be lower than that of the n − high resistance layers 14A and 14B, and the base region Since a potential barrier against holes due to a pn junction is formed between 15 and the recombination suppression region 16, penetration of holes from the base region 15 into the recombination suppression region 16 is suppressed. As a result, the current amplification factor of the BJT 10 can be improved.

  When the recombination suppression region 16 is formed, an ion implantation method of Al or the like is used as in the case where the base contact region 13 is formed. In this case, since the implantation depth is shallow and the implantation concentration is low, no new recombination level is generated when the recombination suppression region 16 is formed.

  Next, a method for manufacturing the BJT 10 will be described with reference to FIGS. FIG. 5 is a flowchart showing each step of the manufacturing method. 6A to 6D are longitudinal sectional views showing a structure manufactured in each step.

  The manufacturing method of the BJT 10 includes the following processes (1) to (11) (steps S11 to S21). As shown in FIG. 5, the process is executed in the order from step S11 to step S21.

(1) High resistance layer forming process (step S11)
(2) Base region formation process (step S12)
(3) High resistance layer formation process (step S13)
(4) Low resistance layer formation process (step S14)
(5) Emitter etching process (step S15)
(6) Recombination suppression region formation process (step S16)
(7) Base contact region formation process (step S17)
(8) Ion implantation layer activation process (step S18)
(9) Surface protective film formation process (step S19)
(10) Electrode formation process (step S20)
(11) Upper layer electrode formation process (step S21)

  The structure shown in FIG. 6A is formed by performing the above steps S11 to S14.

In the high resistance layer formation process (step S11), a high resistance in which nitrogen having a thickness of 10 μm and a concentration of 1 × 10 ¹⁶ cm ⁻³ is doped as an impurity on an n-type substrate 40 formed of SiC by an epitaxial growth method. Layer 41 is grown. As the substrate 40, “4H—SiC (0001) 8 ° off” is used. The substrate 40 becomes the collector region 11 of the n-type low resistance layer described above.

In the base region formation process (step S12), 0.1 to a concentration of 4 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ⁻³ with aluminum (Al) as an impurity is formed on the n-type high resistance layer 41 by an epitaxial growth method. A 0.5 μm p-type base region 42 is grown.

In the high resistance layer forming process (step S13), nitrogen having a thickness of 0.1 to 0.4 μm and a concentration of 5 × 10 ^{15 to} 5 × 10 ¹⁷ cm ⁻³ is then formed on the base region 42 by an epitaxial growth method. An n-type high resistance layer 43 doped as an impurity is grown.

In the low resistance layer forming process (step S14), nitrogen of 0.5 to 2.0 μm in thickness and 1 to 5 × 10 ¹⁹ cm ⁻³ is doped on the n-type high resistance layer 43 by an epitaxial growth method. An n-type low resistance layer 44 doped as follows is grown. The low resistance layer 44 is a portion for forming the emitter region 12 described above.

In the next emitter etching process (step S15), a silicon oxide film 51 is deposited on the upper surface of the structure shown in FIG. 6A by CVD, photolithography is performed, and then silicon oxide is oxidized by RIE. The film 51 is etched. Thus, a mask is formed. Then, using this silicon oxide film 51, SiC etching is performed on the low resistance layer 44 by RIE, and the emitter region 12 is formed using the low resistance layer 44. Etching is performed in a gas atmosphere such as RIE in SF ₆ for SiC etching. The resulting structure is shown in FIG. The etching depth is, for example, about 0.5 to 2.3 μm.

  In the process (S16) for forming the recombination suppression region, as shown in FIG. 6C, a mask 52 for forming the recombination suppression region 16 is formed. In this mask formation, a silicon oxide film is deposited by the CVD method, photolithography is performed, and then the silicon oxide film in a portion where the recombination suppression region 16 is to be formed is etched by RIE. Thereafter, ion implantation of aluminum (Al) as an impurity (ion species) is performed. The region to be implanted is a range between two adjacent emitter regions 12.

The amount of impurities to be implanted is preferably the same as or around the n-type impurity concentration of the n ⁻ high resistance layers 14A and 14B from the viewpoint of making the recombination suppressing region 16 an n ⁻ or p ⁻ type semiconductor. . For example, when the n-type impurity concentration of the n ⁻ high resistance layers 14A and 14B is 1 × 10 ¹⁶ cm ⁻³ , the ion implantation amount is in the range of 5 × 10 ^{15 to} 5 × 10 ¹⁶ cm ^−3. Is desirable. On the other hand, the implantation energy is set to an appropriate value according to the thickness from the SiC surface to the base region 15. For example, the desired recombination suppression region 16 can be formed by using an implantation energy in the range of 100 to 500 keV. Since the injection amount is small and the injection energy is kept low, no new recombination level is generated in this process.

In the base contact region forming process (step S17), as shown in FIG. 6D, the mask 53 is formed so that the surface portion for forming the base contact region 13 is further exposed. The mask 53 is formed by further depositing a silicon oxide film by a CVD method, performing photolithography, and then etching the silicon oxide film by RIE. Thereafter, the base contact region 13 is formed by ion implantation. The ion to be implanted is aluminum (Al), and the depth of implantation is, for example, 0.1 to 0.3 μm. The ion implantation amount is 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ .

  In the process of activating the ion implantation layer (step S18), after the ion implantation, the implanted ions are electrically activated in the semiconductor, and a heat treatment is performed to eliminate crystal defects generated by the ion implantation. In this activation heat treatment, both the implanted ions in the base contact region 13 and the implanted ions in the recombination suppression region 16 are activated at the same time. Heat treatment is performed for about 10 minutes at a high temperature of about 1700 to 1800 ° C. using a high-frequency heat treatment furnace or the like. For example, argon gas (Ar) is used as the atmospheric gas.

  Thereafter, a process for forming a surface protective film (step S19) is performed. In this process, first, sacrificial oxidation is performed to remove the oxide film after thermal oxidation in order to remove the surface layer generated in the ion implantation process and the activation process. Thereafter, heat treatment (POA: Post Oxidation Anneal) is performed to reduce the impurity level at the interface of the SiC oxide film.

  Next, a process for forming electrodes (step S20) is performed. In this process, an emitter electrode 19, a base electrode 20, and a collector electrode 18 are formed on the surfaces of the emitter region 12 (low resistance layer 44), the base contact region 13, and the collector region 11 (substrate 40). The emitter electrode 19 and the collector electrode 18 are made of nickel or titanium, and the base electrode 20 is made of a titanium / aluminum laminated film. Each electrode 18, 19, 20 is formed by vapor deposition or sputtering. For the formation of the electrode pattern, dry etching, wet etching, lift-off method or the like is used. In addition, after the electrodes 18 to 20 are formed, heat treatment is performed to reduce the contact resistance between the metal portion and the semiconductor portion. The heat treatment conditions are a temperature condition of 800 to 1000 ° C. and a time condition of about 10 to 30 minutes.

  Finally, a process (step S21) for forming the upper layer electrode is performed. In this process, an upper layer wiring for taking out a plurality of separated emitter electrodes 12 to one electrode is formed.

  As described above, the BJT 10 shown in FIGS. 1 and 2 is manufactured.

  In the first embodiment described above, the example in which the recombination suppression region 16 shown in FIG. 1 is a p-type region (second conductivity type) has been described, but this is referred to as an n-type region (first conductivity type). You can also

  In the first embodiment, the combination of the first and second conductivity types such as the collector region, the emitter region, the high resistance layer, the base region, the base contact region, and the recombination suppression region may be reversed. it can. The combination will be specifically described as follows. This also applies to the following embodiments.

  When the two regions through which the main current flows are used as the first and second main electrode regions, in the case of BJT, the following occurs.

  In the first combination, the first main electrode region is a collector region made of a low resistance layer of the first conductivity type, the second main electrode region is an emitter region made of a low resistance layer of the first conductivity type, The control electrode region is a second contact type base contact region (base region), and the recombination suppression region is a combination having the same second conductivity type as the base contact region or the same first conductivity type as the emitter region. .

  In the second combination, the first main electrode region is a collector region made of the second conductive type low resistance layer, the second main electrode region is made of the second conductive type low resistance layer, The control electrode region is a base contact region (base region) of the first conductivity type, and the recombination suppression region is a combination having the same first conductivity type as the base contact region or the same second conductivity type as the emitter region. .

  In the case of SIT, when the two regions through which the main current flows are the first and second main electrode regions, the following is performed.

  In the first combination, the first main electrode region is a drain region made of a low resistance layer of the first conductivity type, the second main electrode region is a source region made of a low resistance layer of the first conductivity type, The control electrode region has a second conductivity type gate region, and the recombination suppression region has the same second conductivity type as the gate region or the same first conductivity type as the source region.

  In the second combination, the first main electrode region is a drain region made of the second conductivity type low resistance layer, the second main electrode region is made of the second conductivity type low resistance layer, The control electrode region is a combination of the first conductivity type gate region and the recombination suppression region having the same first conductivity type as the gate region or the same second conductivity type as the source region.

  In the case of SIT, the channel dope layer corresponds to the base region of the BJT, and the gate region corresponds to the base contact region of the BJT.

<Second embodiment>
A second embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG. FIG. 7 is a view similar to FIG. The junction type semiconductor device according to the second embodiment is also a BJT. In FIG. 7, elements that are substantially the same as those described in FIG. 1 are given the same reference numerals. The BJT 100 according to the second embodiment is characterized in that the portion 15A of the base region 15 in the vicinity of the base contact region that is in contact with the base contact region 13 is formed by a p ⁺ region having a lower resistivity than the other base regions. There is. Further, in this embodiment, the base contact region 13 is formed such that the bottom portion thereof is in contact with the low resistance portion 15 </ b> A of the base region 15. It is also desirable to make the thickness of the low resistance portion 15A larger than that of the other portions of the base region 15. Other configurations are the same as those described in the first embodiment.

  When the BJT 100 is in the ON state, a hole current that is a control current flows from the base electrode 20 to the emitter region 12 via the base contact region 13, the low resistance portion 15 </ b> A, and the base region 15. In this embodiment, since a part of the base region 15 has a low resistance, the control current is concentrated in the low resistance portion 15A as compared with the conventional structure, and the base contact region 13 and the emitter region where many recombination levels exist. It becomes difficult to flow on the SiC surface of the high resistance layer 14B between the twelve. Therefore, recombination on the SiC surface that occurs actively in the conventional structure is suppressed, and as a result, the current amplification factor is improved.

The manufacturing method of the BJT 100 according to the second embodiment is the same as the manufacturing method of the BJT 10 according to the first embodiment, except that the predetermined portion 15A of the base region 15 formed in the base region forming process (step S12) is a low resistance portion. It is comprised by providing the process for forming this after that. In the recombination suppression region forming process (step S16) in the first embodiment, the injection amount and the injection energy may be designed in accordance with the formation of 15A. The implantation energy is substantially the same as that of the first embodiment, and the implantation amount is set so that the impurity concentration of the low resistance portion 15A is higher than that of the base region 15. For example, the impurity concentration is about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ .

  When the configuration of the second embodiment is applied to SIT, the channel dope layer is divided into a channel dope layer portion (first channel dope layer) corresponding to the low resistance portion 15A, and other normal ones. It is comprised from a channel dope layer part (2nd channel dope layer). The first channel dope layer and the second channel dope layer are connected.

<Third embodiment>
A third embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG. The junction type semiconductor device of the third embodiment is BJT. In FIG. 8, elements that are substantially the same as those described in FIG. The BJT 200 of the third embodiment has a configuration in which the characteristic configuration of the first embodiment and the characteristic configuration of the second embodiment are combined. That is, the low resistance portion 15A is formed in a predetermined region of the base region 15, and the upper and lower surfaces of the low resistance portion 15A are covered with the recombination suppression region 16 described above. Other configurations are the same as those described in the first or second embodiment. In the BJT 200 of the third embodiment, since recombination in the base region can be suppressed by the recombination suppression region 16 and recombination on the SiC surface can also be suppressed, an extremely high current amplification factor can be realized. Also, the manufacturing method is not complicated, and when performing ion implantation in the recombination suppression region forming process of the first embodiment, a necessary implantation amount is set according to the depth and multistage implantation is performed. Good.

<Fourth embodiment>
A fourth embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG. The junction type semiconductor device of the fourth embodiment shows an example of BJT. A BJT 300 shown in FIG. 9 is a modification of the BJT 10 of the first embodiment described above. In the BJT 300 of the present embodiment, the recombination suppression region 16 is formed from the surface of the base contact region to the lower surface side of the base region 15. Other configurations are the same as those described in the first embodiment. In BJT300 the fourth embodiment, p of higher resistance than the base region 15 ^- semiconductor or n ^- high resistance layer 14A, the high resistance of the n than 14B ^- by the SiC surface covering base region 15 in the semiconductor base Recombination in both the vicinity of the region 15 and the SiC surface can be suppressed.

  The configurations, shapes, sizes, and arrangement relationships described in the embodiments are merely shown to the extent that the present invention can be understood and implemented, and numerical values and compositions (materials) of the respective configurations Is merely an example. Therefore, the present invention is not limited to the described embodiments, and can be variously modified without departing from the scope of the technical idea shown in the claims.

  The present invention can be used for manufacturing a high-performance junction type semiconductor device.

10 Junction semiconductor devices (BJT)
DESCRIPTION OF SYMBOLS 11 Collector area | region 12 Emitter area | region 13 Base contact area | region 14 High resistance layer 15 Base area | region 15A Low resistance part 16 Recombination suppression area | region 17 Surface protective film 18 Collector electrode 19 Emitter electrode 20 Base electrode 21 Upper layer electrode 40 Substrate 41, 43 High resistance layer 42 Base region 44 Low resistance layer 100 Junction semiconductor device (BJT)
200 Junction semiconductor devices (BJT)
300 Junction semiconductor device (BJT)

Claims (4)

A junction type semiconductor device that suppresses recombination of a main current flowing between two main electrodes and a control current flowing through a control electrode,
A substrate made of a silicon carbide semiconductor crystal and having a first main electrode region of a first conductivity type ;
The one main electrode provided on the lower surface of the first main electrode region and constituting the two main electrodes;
And the other main electrode which constitute the two main electrodes a main electrode of the other provided on a side of the upper surface of said first main electrode region,
A second main electrode region of the first conductivity type formed under the other main electrode;
A first high-resistance layer of the first conductivity type formed on the first main electrode region;
A second high-resistance layer of the first conductivity type formed under the second main electrode region;
The control electrode formed so as to completely surround the periphery of the other main electrode in plan view, the control electrode region being a second conductivity type formed under the control electrode;
An intermediate layer of the second conductivity type formed on the first high-resistance layer, formed below the second high-resistance layer, and in contact with the control electrode region;
A first region formed under the intermediate layer in the first high-resistance layer so as to be formed below a portion in contact with the control electrode region in the intermediate layer; and A second region formed on the intermediate layer in the second high resistance layer so as to be formed above, the first conductivity type or the second conductivity type. A binding inhibition region;
I have a,
Each of the resistivity of the first high-resistance layer and the resistivity of the second high-resistance layer is higher than the resistivity of the second main electrode region . A junction type semiconductor device that suppresses recombination of a main current flowing between two main electrodes and a control current flowing through a control electrode,
A substrate made of a silicon carbide semiconductor crystal and having a first main electrode region of a first conductivity type ;
The one main electrode provided on the lower surface of the first main electrode region and constituting the two main electrodes;
And the other main electrode which constitute the two main electrodes a main electrode of the other provided on a side of the upper surface of said first main electrode region,
A second main electrode region of the first conductivity type formed under the other main electrode;
A first high-resistance layer of the first conductivity type formed on the first main electrode region;
A second high-resistance layer of the first conductivity type formed under the second main electrode region;
The control electrode formed so as to completely surround the periphery of the other main electrode in plan view, the control electrode region being a second conductivity type formed under the control electrode;
The second high-resistance layer is formed on the first high-resistance layer, is formed below the second high-resistance layer, and is in contact with the control electrode region and includes a low-resistance portion formed in the vicinity thereof. The intermediate layer having the conductivity type, wherein the low resistance portion that is a part of the intermediate layer has a resistivity lower than that of the rest of the intermediate layer by ion implantation ; and
A first region formed below a portion of the intermediate layer in the first high resistance layer, and a second region formed on a portion of the intermediate layer in the second high resistance layer. And a recombination suppression region that is the first conductivity type or the second conductivity type, and
I have a,
Each of the resistivity of the first high-resistance layer and the resistivity of the second high-resistance layer is higher than the resistivity of the second main electrode region . A method for manufacturing a junction semiconductor device that suppresses recombination of a main current flowing between two main electrodes and a control current flowing through a control electrode,
A first main electrode region, which is a substrate made of a silicon carbide semiconductor crystal, on the first main electrode region, which is the first conductivity type. A first step of forming one high resistance layer;
A second step of forming an intermediate layer of a second conductivity type on the first high-resistance layer;
A third step of forming a second main electrode region of the first conductivity type on the second high resistance layer of the first conductivity type formed on the intermediate layer ;
By ion implantation in contact with the upper and lower surfaces of the intermediate layer in the vicinity of a predetermined region scheduled to form the control electrode region of the second conductivity type on the surface side of the second high resistance layer , A fourth step of forming a recombination suppression region of the first conductivity type or the second conductivity type in the first high resistance layer and the second high resistance layer ;
A fifth step of forming the control electrode region in contact with the intermediate layer by ion implantation in the predetermined region on the surface side of the second high resistance layer;
The one main electrode that forms the two main electrodes is formed below the first main electrode region, and the other main electrode is formed on the second main electrode region. A sixth step of forming the other main electrode constituting the two main electrodes and forming the control electrode on the control electrode region;
Only including,
Each of the resistivity of the first high resistance layer and the resistivity of the second high resistance layer is higher than the resistivity of the second main electrode region. Method. A method for manufacturing a junction semiconductor device that suppresses recombination of a main current flowing between two main electrodes and a control current flowing through a control electrode,
A first main electrode region, which is a substrate made of a silicon carbide semiconductor crystal, on the first main electrode region, which is the first conductivity type. A first step of forming one high resistance layer;
A second step of forming an intermediate layer of a second conductivity type on the first high-resistance layer;
A third step of forming a second main electrode region of the first conductivity type on the second high resistance layer of the first conductivity type formed on the intermediate layer ;
In the vicinity of a predetermined region where the control electrode region of the second conductivity type is to be formed on the surface side of the second high resistance layer, a part of the intermediate layer is made to have a low resistance by ion implantation. And the process of
In the vicinity of the predetermined region on the surface side of the second high resistance layer, the first high resistance layer and the second high resistance are formed by ion implantation so as to be in contact with the upper and lower surfaces of a part of the intermediate layer. A recombination suppression region having the first conductivity type or the second conductivity type is formed in a layer, and the control electrode region is formed by ion implantation in the predetermined region on the surface side of the second high resistance layer. A fifth step of forming a contact with the part of the intermediate layer;
The one main electrode that forms the two main electrodes is formed below the first main electrode region, and the other main electrode is formed on the second main electrode region. A sixth step of forming the other main electrode constituting the two main electrodes and forming the control electrode on the control electrode region;
Only including,
Each of the resistivity of the first high resistance layer and the resistivity of the second high resistance layer is higher than the resistivity of the second main electrode region,
The method for manufacturing a junction type semiconductor device, wherein the part of the intermediate layer is a low resistance part having a resistivity lower than that of the remaining part of the intermediate layer .

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