JP3681992B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a method for manufacturing a semiconductor integrated circuit in which semiconductor elements are three-dimensionally integrated.
[0002]
[Prior art]
Three-dimensional integration of semiconductor elements is important for increasing the degree of integration of semiconductor integrated circuits, and is an extremely important basic technology for the construction of optical switch arrays. Development of optical switch arrays is highly desired as a key device for optical signal processing and optical information processing. Conventionally, as this type of device, as seen in, for example, the document “IEEE PHOTONICS TECHNOLOGY LETTERS Vol. 7, p. 360 (1995)”, a multiple quantum well type pin diode is mounted on a silicon integrated circuit substrate by solder bumps, An element called “hybrid seed (H-SHEED)” has been proposed in which a quantum well pin diode is used as a light receiving element or an optical modulator to input and output light and to perform a logic function in a silicon integrated circuit. In this element, an input optical signal incident on an input multiple quantum well pin diode is converted into an electric signal, transmitted to a silicon integrated circuit substrate and electrically processed, and then applied to an output multiple quantum well pin diode. Control the voltage. At this time, the output multiple quantum well pin diode can control the reflection intensity of light biased at a constant intensity by the quantum confined Stark effect according to the voltage change. The configuration is shown in FIG. 12, and the characteristics are shown in FIG.
[0003]
As shown in FIG. 12A, the epitaxial substrate 10 includes a p-AlGaAs layer 12, an i-MQW layer 13, and (n^--GaAs layer and n⁺-GaAs layer) 14 are sequentially laminated to form a light modulation section in which a Be ion implantation layer 15 and a Ti / Au film 16 as a reflection layer are formed. The p-side and n-side electrodes are on the same plane, and solder 17 is formed on the Be ion-implanted layer 15 and the Ti / Au film 16. On the other hand, an Al: Ti / Pt / Au film 21 for improving wettability is formed on the surface of the silicon integrated circuit substrate 20 on which the CMOS is formed, and a solder 17 is provided thereon. The two substrates are joined by solder bumps as shown in FIG. 12B, and the optical modulator is mounted on the silicon integrated circuit substrate. After bonding, the periphery of the bonded portion is filled with epoxy resin 18, and then the GaAs substrate is removed. The epoxy resin can then be removed. Finally, as shown in FIG. 12C, an anti-reflection coating 19 is applied to obtain an optical modulator integrated with silicon CMOS. This conventional example has a 2-input 2-output switch function.
[0004]
FIG. 13 shows the relationship between the gate-source voltage and the reflectivity in the hybrid seed device thus prepared. Switching operation is possible by controlling the gate-source voltage of the CMOS.
[0005]
[Problems to be solved by the invention]
However, the optical switch array described above has the following problems.
[0006]
First, since a multiple quantum well pin diode is used as the light modulator, the extinction ratio is low and the loss is large.
[0007]
Second, since it is necessary to make bias light incident on the light modulator, the optical system becomes complicated.
[0008]
Third, since the operating voltage of the light modulator is as large as about 10 V, the response speed is slow.
[0009]
Fourthly, the operating wavelength of the modulator using the quantum confined Stark effect is limited to a few nm, and the operating wavelength of the modulator fluctuates due to heat generated from the silicon integrated circuit, so that the wavelength of the bias light to the light source is limited. However, it is necessary to control the element at a constant temperature.
[0010]
On the other hand, the method for constructing a three-dimensional structure of an electronic device and an optical device using solder bumps as in the conventional device described above has the following problems.
[0011]
That is, for example, when optical elements having different layer structures, such as a light receiver and a surface emitting laser, are simultaneously arranged on a silicon integrated circuit, each optical element has a different structure, so that they are formed on the same substrate. Therefore, it is necessary to place each element separately on the silicon integrated circuit by solder bumps. Such individual mounting involves the following difficulties.
[0012]
First, since the solder bumps must be performed a plurality of times, the process becomes complicated.
[0013]
Secondly, in the optical switch array, the relative position of each optical element must match the predetermined positional relationship of the incoming and outgoing light. However, the individual optical elements can be obtained by performing solder bumps for each individual optical element. It is difficult to accurately determine the relative position between them. Therefore, it is difficult to make the positional relationship of each optical element coincide with the positional relationship of the incoming and outgoing light.
[0014]
An object of the present invention is to realize a method of manufacturing a semiconductor integrated circuit that solves the above-described problems associated with conventional optical switch arrays. It is another object of the present invention to provide a method for manufacturing an optical switch array having a large extinction ratio, a simple optical system, a high response speed, and a large operation margin.
[0015]
[Means for Solving the Problems]
  According to the method of manufacturing a semiconductor integrated circuit of the present invention, a selective etching layer, a contact layer, a first DBR layer, an active layer, a second DBR layer, and a light absorption layer are epitaxially grown in this order on one main surface of a compound semiconductor substrate. An optical input / output substrate having a laminate formed thereon and a silicon integrated circuit substrate on which a semiconductor element is integrated on one main surface and a metal layer for electrical connection and a metal layer for heat dissipation are formed. The surface of the output substrate on which the laminated body is formed and the surface of the silicon integrated circuit substrate on which the semiconductor elements are integrated are opposed to each other via an insulating adhesive layer made of an organic material, A first step of removing the compound semiconductor substrate and the selective etching layer by polishing and chemical etching;Following the first step,A second step of processing the laminated body to form a light emitting element and a light receiving element, and forming respective electrodes of the light emitting element and the light receiving element, a semiconductor element on the silicon integrated circuit substrate, the light emitting element, and Forming a through hole for connecting each electrode of the light receiving element, filling the through hole with a metal and electrically connecting the third step, and the second step includes the contact layer and Processing the first DBR layer, the active layer, and the second DBR layer to form a light emitting element portion; and forming electrodes on the contact layer and the second DBR layer of the formed light emitting element portion Forming a light emitting element, and forming a light receiving element by forming an electrode on the light absorption layer exposed by the step of forming the light emitting element portion.
[0016]
    Further, a light input / output in which a stacked body is formed on one main surface of the compound semiconductor substrate by epitaxial growth in the order of a selective etching layer, a light absorption layer, a first DBR layer, an active layer, a second DBR layer, and a contact layer. A first step of bonding the surface of the substrate on which the laminate is formed and a quartz substrate using wax, and removing the compound semiconductor substrate and the selective etching layer of the optical input / output substrate by polishing and chemical etching; A semiconductor element is integrated on one main surface of the surface of the optical input / output substrate from which the compound semiconductor substrate and the selective etching layer are removed, and a metal layer for electrical connection and a metal layer for heat dissipation are patterned. The silicon integrated circuit substrate is bonded to the surface on which the semiconductor elements are integrated with an insulating adhesive layer made of an organic material, and the wafer is heated by heating. A second step of removing the quartz substrate by dissolving scan,Following the second step,A third step of processing the laminate to form a light emitting element and a light receiving element, and forming respective electrodes of the light emitting element and the light receiving element; a semiconductor element on the silicon integrated circuit substrate; the light emitting element; Forming a through hole for connecting each electrode of the light receiving element, filling the through hole with a metal and electrically connecting the fourth step, and the third step includes the contact layer and Processing the second DBR layer, the active layer, and the first DBR layer to form a light emitting element portion, and forming electrodes on the contact layer and the first DBR layer of the formed light emitting element portion Forming a light emitting element, and forming a light receiving element by forming an electrode on the light absorption layer exposed by the step of forming the light emitting element portion.
[0017]
  In addition, compound semiconductor substrateA stacked body is formed on one main surface by epitaxial growth in the order of a selective etching layer, a light absorbing layer, a first DBR layer, an active layer, a second DBR layer, and a contact layer, and the stacked body is processed.A plurality of light emitting elements, a plurality of light receiving elements and respective electrodes are formed.A first step of forming an optical input / output substrate;SaidOptical input / outputThe surface of the substrate on which the plurality of light emitting elements and the plurality of light receiving elements and each electrode are formed and the quartz substrate are bonded together using wax,Of the optical input / output substrateCompound semiconductor substrateAnd the selective etching layerRemoved by polishing and chemical etchingAnd removing the compound semiconductor substrate and the selective etching layer of the optical input / output substrate.The surface on which the semiconductor element is integrated on one main surface and the surface on which the semiconductor element of the silicon integrated circuit substrate on which the metal layer for electrical connection and the metal layer for heat dissipation are patterned are integrated, Positioning using infrared light, bonding through an insulating adhesive layer made of an organic material, melting the wax by heating, and removing the quartz substrateThe third stepForming a through hole for connecting the semiconductor element on the silicon integrated circuit substrate to each of the electrodes of the plurality of light emitting elements and the plurality of light receiving elements, and filling the through hole with a metal for electrical connection.A fourth step, wherein the first step forms the light emitting element portion by processing the contact layer, the second DBR layer, the active layer, and the first DBR layer; Forming electrodes on the contact layer and the first DBR layer of the formed light emitting element portion to form a light emitting element, and forming electrodes on the light absorbing layer exposed by the step of forming the light emitting element portion And forming a light receiving element.It is characterized by that.
[0018]
  Further, on one main surface of the compound semiconductor substrate, a first selective etching layer, a contact layer, a first DBR layer, an active layer, a second DBR layer, a second selective etching layer, an FET element constituent layer, An optical input / output substrate in which a laminated body is formed by epitaxial growth in the order of a light absorption layer, and a silicon integrated circuit substrate in which semiconductor elements are integrated on one main surface and a metal layer for electrical connection and a metal layer for heat dissipation are patterned And the surface of the optical input / output substrate on which the stacked body is formed and the surface of the silicon integrated circuit substrate on which the semiconductor elements are integrated are opposed to each other via an insulating adhesive layer made of an organic material, A first step of removing the compound semiconductor substrate and the first selective etching layer of the optical input / output substrate by polishing and chemical etching;Following the first step,A second step of forming the light emitting element, the FET element, and the light receiving element by processing the laminate, and forming electrodes of the light emitting element, the FET element, and the light receiving element; and a semiconductor on the silicon integrated circuit substrate. Forming a through hole for connecting an element to each electrode of the light emitting element, the FET element, and the light receiving element, and filling the through hole with metal to electrically connect the third step, The second step is a step of processing the contact layer, the first DBR layer, the active layer, and the second DBR layer to form a light emitting element portion and exposing the second selective etching layer; Etching the exposed second selective etching layer to expose the FET element constituent layer, and processing the exposed FET element constituent layer to form an FET element part Forming a light emitting element by forming an electrode on the contact layer and the second DBR layer of the formed light emitting element part, and forming an FET element by forming an electrode on the formed FET element part And a step of forming a light receiving element by forming an electrode on the light absorption layer exposed by the step of forming the FET element portion.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an embodiment of a device according to the present invention. An optical input / output substrate 100 is integrated with an insulating layer 300 on an integrated circuit substrate 200 in which semiconductor elements such as MOSFETs, transistors, and diodes are integrated on one main surface. The light input / output substrate 100 is provided with a plurality of light receiving elements 100A and a vertical cavity surface emitting laser (hereinafter referred to as a surface emitting laser) 100B. The insulating layer 300 is provided with a window, and the light receiving element 100 </ b> A and the surface light emitting element 100 </ b> B are connected to the metal wiring 200 </ b> A of the integrated circuit substrate 200 through the window through the wiring 400. Reference numerals 100C and 100D denote wirings of the light receiving element 100A and the surface light emitting element 100B, respectively. This element converts the light input by the light receiving element 100A into an electrical signal, performs processing such as amplification and switching with a semiconductor element integrated on the integrated circuit board 200, and uses the processing result as a current output. The light can be transmitted to the light emitting laser 100B and its operation can be controlled.
[0020]
FIG. 2 shows the operating characteristics of this element. In the example of FIG. 2, the result of synchronizing, amplifying, and shaping the input signal is shown. In the case of the element of the present invention, various processing is possible by the processing function of the integrated circuit board. Besides this example, 2 × 2 switching, various arithmetic processing, image processing, and the like can be given.
[0021]
In the optical switch array according to the present invention, since the vertical cavity surface emitting laser is used as the optical modulator, no bias light is required and high contrast is obtained, so that the optical system is simplified. Further, since an operating voltage of about 3V is sufficient, a high speed operation can be realized. In addition, when the element of the present invention is configured in multiple stages and processing such as optical interconnection is performed by performing optical connection such that the output light from the previous stage is input light, the surface emitting laser has an oscillation wavelength of film thickness Although it is very sensitive to fluctuations in the light and difficult to control, if a pin diode, MSM photodiode, or the like is used as the light receiving portion, almost uniform light sensitivity can be obtained over a wide wavelength range of 100 nm or more. There is also a feature that there is no limitation on the oscillation wavelength of the light emitting laser, which is advantageous for multistage.
[0022]
If an optical switch array as described above is to be manufactured, the layer structure of the vertical cavity surface emitting laser and the light receiver are different, and thus cannot be formed simultaneously on a single substrate. The technology cannot be used. In order to solve this problem, according to the present invention, a semiconductor element such as a vertical resonator is disposed on a semiconductor substrate in which a semiconductor element is integrated on one main surface via an insulating layer. Wiring is provided between a semiconductor element integrated on the semiconductor substrate and a vertical resonator disposed on the insulating layer through a window formed in the layer.
[0023]
As an insulating layer, polyimide or SiO₂However, all have the ability to bond semiconductors by an appropriate process. Therefore, the three-dimensional arrangement of the semiconductor element is facilitated by using these insulating layers as the adhesive layer. Further, since it is insulative, wiring can be easily performed on the adhesive layer, and therefore, necessary wiring can be applied to the elements arranged on the integrated circuit. For example, when a layer structure for a laser and a layer structure for a light receiver are stacked on a single substrate and bonded to a semiconductor integrated circuit with an insulating adhesive layer, each layer is etched by etching as shown in FIG. Necessary wiring can be easily performed after exposing the structure as necessary.
[0024]
【Example】
Example 1  When the growth surface of the optical input / output substrate is bonded to the integrated circuit substrate side
A first specific example in which the present invention is applied to an optical switch array is shown in FIGS.
[0025]
FIG. 3 is a sectional view of an optical input / output substrate when a GaAs / AlGaAs multiple quantum well is used for the active layer. On the semi-insulating GaAs substrate 101, an AlAs layer 102 for selective etching, n⁺A −GaAs contact layer 103, an n-DBR (Distributed Bragg Reflector) layer 104, an active layer 105, a p-DBR layer 106, and an i-GaAs light absorption layer 107 were sequentially formed by molecular beam epitaxial growth. Be and Si were used for the p-type and n-type dopants, respectively. Here, the n-DBR layer is n-AlAs (71.5 nm) / n-Al_0.15Ga_0.85It has a structure in which As (62.9 nm) is alternately stacked for 25 periods, and the p-DBR layer is p-AlAs (71.5 nm) / p-Al_0.15Ga_0.85It has a structure in which As (62.9 nm) is alternately stacked for 30 periods.
[0026]
FIG. 4 shows a method for manufacturing an optical switch. First, as shown in FIG. 4A, the growth layer 100E of the optical input / output substrate 100 is bonded with an adhesive 300 toward the main surface of the silicon integrated circuit substrate 200 on which the semiconductor elements are integrated. In this case, polyimide is applied as an adhesive to the bonding surfaces of both substrates by spin coating to prevent bubbles from entering. Then, both substrates are bonded together and cured by heat treatment at a high temperature while applying a load. In the bonding procedure, first, temporary bonding is performed at a temperature of about 150 ° C., and the GaAs substrate 101 is divided into sizes of about one chip. Thereafter, it is finally cured at 350 ° C. This is to prevent the substrate from warping due to the difference in thermal expansion coefficient between silicon and GaAs when the substrate becomes larger than 2 inches. At this time, when a thick metal film 200A for electrical connection and cooling is formed on the integrated circuit board 200, the metal film 200A is subjected to a load when the polyimide 300 interposed between the optical input / output board 100 is bonded. As a result, as shown in FIG. 4B, the optical input / output substrate 100 comes into direct contact.
[0027]
Thereafter, the GaAs substrate 101 is polished to a thickness of about 50 μm, and the PA30 solution (H₂O₂  : NH_ThreeOnly GaAs substrate 101 is selectively etched by OH = 30: 1), and etching is stopped by AlAs layer 102. Next, only the AlAs layer 102 is selectively etched with hydrochloric acid, and n as shown in FIG.⁺The GaAs contact layer 103 is exposed on the surface. FIG. 4C 'is an enlarged view showing the growth layer in this state.
[0028]
Next, as shown in FIG. 4D, the optical input / output substrate is processed to form the surface emitting laser 100B and the SMS photodetector 100A. FIG. 4D 'is an enlarged view of the surface emitting laser section. AuZnNi was used as the p-type electrode 110 of the surface emitting laser, AuGeNi was used as the n-type electrode 111, and Ti / Pt / Au was used as the Schottky electrode 112 of the photodetector.
Thereafter, as shown in FIG. 4E, through-holes are opened by etching until the metal film 200A is exposed at the portion of the optical input / output substrate 100 where electrical wiring between the two substrates is performed. The SMS photodetector portion is also defined.
[0029]
Then, the inter-element wiring metal 400 is formed by plating, and the wiring 113 is applied to obtain the structure shown in FIG.
[0030]
When solder bumps are used as in the conventional example, the electrodes must be formed on the surface of the substrate on which the laser and the light receiver are laminated, so that it is difficult to form the electrodes on either one of the elements. For example, when the stacked structure as shown in FIG. 3 is used, it is difficult to form an electrode in a laser structure including the p-DBR layer 106, the active layer 105, and the n-DBR layer 104. However, such a problem does not occur in the structure of the present invention. The thick metal film 200A on the integrated circuit substrate 200 has an effect of reducing a step difference in electrical connection between the two substrates, an effect of preventing light from entering the integrated circuit substrate from the light receiving element and the light emitting element, and the light input / output substrate. This has the effect of removing the generated heat through the metal film.
[0031]
Actually, a two-dimensional array of 8 × 8 = 64 pixels having MSM-PD, three MESFETs, and a surface emitting laser in one pixel is fabricated, and 0.1 mW, 200 MHz input light is supplied to the MSD-PD in the 850 nm wavelength band. It was confirmed that the operation of inputting 1 mW output light from the surface emitting laser in parallel to all the pixels is performed in parallel.
[0032]
Further, the number of surface emitting lasers and light receiving elements is not limited to one for each processing unit (cell) in the integrated circuit, and there may be a plurality of input / output elements.
[0033]
In this embodiment, the plating is used to form the inter-element wiring metal. However, the present invention is not limited to this, and the step may be filled by selective growth using, for example, tungsten. In addition, polyimide is used for bonding both substrates, but the present invention is not limited to this, and various adhesives such as an epoxy type may be used.₂It is also possible to bond dielectrics such as.
[0034]
An optical input / output substrate is formed on a semi-insulating GaAs substrate 101, an AlAs layer for selective etching, p.⁺-A GaAs contact layer, a p-DBR layer, an i-GaAs / AlGaAs active layer, an n-DBR layer, and an i-GaAs light absorption layer are stacked in this order, and the polarities of p and n of the DBR layer of the surface emitting laser are interchanged. Good. In this case, the p-DBR layer has a 25-layer structure, and the n-DBR layer has a 30-layer structure. This is because the output light can be obtained on the output side with high efficiency by setting the reflectivity of the DBR mirror on the integrated circuit board side higher than the reflectivity of the DBR mirror on the output side. The same applies to the following embodiments.
[0035]
Example 2  When the growth surface of the optical I / O substrate is bonded opposite to the integrated circuit substrate side
(Part 1)When processing optical input / output substrates after bonding substrates
5 to 7 show a second specific example in which the present invention is applied to an optical switch array.
[0036]
FIG. 5 is a sectional view of an optical input / output substrate when a GaAs / AlGaAs multiple quantum well is used for the active layer. On the semi-insulating GaAs substrate 101, an AlAs layer for selective etching 102, an i-GaAs light absorption layer 107, a p-DBR layer 106, an i-GaAs / AlGaAs active layer 105, an n-DBR layer 104, and n⁺The -GaAs contact layer 103 was sequentially formed by molecular beam epitaxial growth. The stacking order of the light receiving element constituent layer and the light emitting element constituent layer is reversed from that of the first embodiment. Here, similarly to Example 1, the n-DBR layer has a structure in which 30 cycles are stacked, and the p-DBR layer has a structure in which 25 cycles are stacked.
[0037]
FIG. 6 shows a method for creating an optical switch. First, as shown in FIG. 6A, the optical input / output substrate 100 is attached to a flat quartz plate 400 with a wax 500 with the growth layer 100E facing up.
[0038]
Next, as shown in FIG. 6B, after the GaAs substrate 101 is polished to a thickness of about 50 μm, only the GaAs substrate is etched with a citric acid solution, and the etching is stopped with the AlAs layer 102. Next, only the AlAs layer 102 is selectively etched with hydrochloric acid.
[0039]
Next, as shown in FIG. 6C, bonding to the integrated circuit substrate 200 is performed using polyimide 300. First, the polyimide is cured by baking at about 100 ° C.
[0040]
At this time, since the wax existing between the quartz plate 400 and the optical input / output substrate 100 is melted by heat, the integrated circuit substrate 200 and the growth layer 100E of the optical input / output substrate are joined together as shown in FIG. Remove from. Thereafter, the polyimide is finally cured at a high temperature of about 300 ° C. This state is the same as that in FIG. 4C of the first embodiment, and thereafter, the device can be manufactured in the same manner as in the first embodiment.
[0041]
In this case, it is not necessary to expose the i-GaAs light absorption layer by selective etching, and the semi-insulating GaAs substrate 101 may remain attached to the integrated circuit substrate 200. An example of this is shown in FIG.
[0042]
(Part 2)When bonding optical input / output boards after processing
FIG. 8 shows a third specific example of the optical switch array to which the present invention is applied. The optical input / output substrate is the same as that of the second specific example shown in FIG.
[0043]
FIG. 8 shows a method for manufacturing an optical switch. First, after the surface emitting laser 100B and the MSM photodiode 100A are processed without processing the semi-insulating GaAs substrate 101, the flat quartz plate 400 and the processed surface face each other as shown in FIG. Bonding with wax 500. FIG. 8A is an enlarged view of the optical input / output substrate.
[0044]
Next, as shown in FIG. 8B, the GaAs substrate is polished to a thickness of about 50 μm, then only the GaAs substrate is etched with the PA30 solution, the etching is stopped with the AlAs layer, and only the AlAs layer is removed with hydrochloric acid. Selectively etch.
[0045]
Next, as shown in FIG. 8C, after polyimide 300 is applied to both substrates, the circuit patterns of the integrated circuit substrate 200 and the optical input / output substrate 100 are monitored using an infrared camera (CCD camera). Then, the two substrates are aligned using the fine moving table 600 and bonded together.
[0046]
Next, as in the case of (Part 1), the polyimide is cured at about 100 ° C., and at the same time, after removing both substrates from the quartz plate, the polyimide 300 is finally cured by raising the temperature to 300 ° C., The structure shown in FIG. 8D is obtained. This state is the same as that shown in FIG. 4D, and the same process as in the previous specific example is performed thereafter.
[0047]
In this case, as in the second specific example, it is not necessary to expose the i-GaAs light absorption layer by selective etching, and the semi-insulating GaAs substrate 101 may be stuck to the integrated circuit substrate 200 while remaining.
[0048]
Example 3  When an electric circuit is also formed on the optical input / output board
In the above embodiments, the light input / output substrate 100 includes a surface emitting laser and a photodetector. However, the light input / output substrate 100 may include an electric circuit such as an FET. Here, an example in which an optical switch is configured by the same method as in the first specific example will be described. The FET can be configured by epitaxial growth as described below, or by ion implantation.
[0049]
FIG. 9 is a sectional view of an optical input / output substrate when a GaAs / AlGaAs multiple quantum well is used for the active layer.
[0050]
On the semi-insulating GaAs substrate 101, an AlAs layer 102 for selective etching, p⁺-GaAs contact layer 120, p-DBR layer 106, i-GaAs / AlGaAs active layer 105, n-DBR layer 104, n-InGaP layer 121 (10 nm) as a selective etching layer, n as an FET contact layer⁺-GaAs layer 122 (0.4 μm), n as FET channel layer^-A −GaAs channel layer 123 (0.2 μm) and an i-GaAs light absorption layer 107 (2 μm) were sequentially formed by molecular beam epitaxy. Be and Si were used for the p-type and n-type dopants, respectively. Here, the p-DBR layer is p-AlAs (71.5 nm) / p-Al._0.15Ga_0.85It has a structure in which As (62.9 nm) is alternately stacked for 25 periods, and the n-DBR layer is n-AlAs (71.5 nm) / n-Al_0.15Ga_0.85It has a structure in which As (62.9 nm) is alternately stacked for 30 periods.
[0051]
This is processed as shown in FIG. 10 to produce an optical switch.
[0052]
First, as shown in FIG. 10A, in the same manner as in the first embodiment, the optical input / output substrate 100 is bonded onto the integrated circuit substrate 200 using the polyimide 300, and then the epitaxial growth layer is formed by polishing and etching. Leave only 100E. FIG. 10A is an enlarged sectional view of the growth layer.
[0053]
Next, as shown in FIG. 10B, mesa etching of the surface emitting laser unit 100B is performed. FIG. 10B 'is an enlarged cross-sectional view of the surface emitting laser section. At this time, the mesa depth reaches the InGaP layer 121 by selective etching.
[0054]
In the FET process, as shown in FIG. 10C, after the InGaP layer 121 is etched, mesa etching of the FET 100F is performed up to the i-GaAs light absorption layer 107. Then n⁺-Source and drain electrodes 124 are formed on the GaAs contact layer 122. Recess etching is n^-The process is performed up to the GaAs channel layer 123, and then the gate electrode 125 is formed. At this time, the electrodes of the MSM photodetector 100A are also formed.
[0055]
Finally, as shown in FIG. 10D, electrical wiring 400 with the integrated circuit board 200 is provided.
[0056]
In this way, when an electric circuit is also configured on the optical input / output substrate, an FET having a larger gain than Si can be created, and the surface emitting laser can be driven with only a small voltage amplitude in the integrated circuit, The burden on the integrated circuit board can be reduced, and a faster response is possible.
[0057]
In the above-described specific examples, the example in which the MSM photodiode is used as the light receiving element has been described. However, the semi-invention element can be configured by using a pin photodiode, a photoconductor, or the like as the light receiving part.
[0058]
Example 4
An example created using a pin photodiode is shown in FIG. As shown in the figure, the pin photodiode 100G includes an n-GaAs layer 131, an i-GaAs light absorption layer 107, and a p-GaAs layer 130. The pin photodiode 100G is bonded to the integrated circuit substrate 200 with polyimide 300 through an insulating film 132. And are electrically connected by the wiring 400. The configuration of the surface emitting laser 100B is as described above. In this case, unlike the case of the MSM photodiode, since the conductive layer is also included in the light receiving portion, it is necessary to separate each light receiving portion, and when the integrated circuit substrate 200 and the optical input / output substrate 100 are bonded together, The insulating film 132 is vapor-deposited on the surface to be bonded to the input / output substrate 100, which is different from the specific examples so far.
[0059]
In the specific examples described so far, the optical switch is composed of GaAs / AlGaAs, but the present invention is not limited to this, and other material systems such as InGaAs / InP, InAlAs / InGaAs, and GaAs / InGaAs can also be used. It goes without saying that GaAs, InP, etc. can be used as the integrated circuit substrate in addition to silicon.
[0060]
In the above embodiment, only the optical switch array has been described. However, it is apparent that the present invention is effective for the configuration of other three-dimensional integrated circuits other than the optical switch array. In the present invention, each element can be separated even when elements integrated on an insulating film such as polyimide do not have different layer structures, so that electrical isolation (isolation) between the elements is easy. There is an advantage of becoming.
[0061]
【The invention's effect】
As described above, the semiconductor integrated circuit manufacturing method according to the present invention can manufacture a semiconductor integrated circuit that combines the high speed and high functionality of an integrated circuit substrate with the high parallel and high speed of an optical input / output substrate. It has the feature. By connecting these elements in multiple stages with light, it becomes very promising as a future optical information processing element and an optical interconnection element for LSI.
[0062]
In addition, according to the present invention, it is possible to form a three-dimensional semiconductor integrated circuit composed of semiconductor elements having different layer structures. Furthermore, it is possible to provide a three-dimensional semiconductor integrated circuit excellent in isolation between elements.
[Brief description of the drawings]
FIG. 1 shows a cross-sectional structure of an element according to the present invention.
FIG. 2 is a graph showing characteristics of the element of the present invention.
FIG. 3 is a cross-sectional view of an example of an optical input / output substrate.
FIG. 4 is a diagram showing a method for manufacturing the optical switch of the first embodiment.
FIG. 5 is a cross-sectional view of another example of an optical input / output substrate.
FIG. 6 is a diagram showing a method for manufacturing the optical switch of the second embodiment.
FIG. 7 is a cross-sectional view of an embodiment in the case where selective etching is not used.
FIG. 8 is a diagram showing a method for manufacturing another specific example of the element of the present invention.
FIG. 9 is a cross-sectional view of an optical input / output substrate forming an electric circuit.
FIG. 10 is a diagram showing a manufacturing method of an embodiment in which an electric circuit is also formed on an optical input / output substrate.
FIG. 11 is a cross-sectional view of a specific example using a pin photodiode as a light receiving element.
FIG. 12 is a cross-sectional view of a conventional example.
FIG. 13 is a characteristic diagram of a conventional example.
[Explanation of symbols]
101 Semi-insulating GaAs substrate
102 AlAs layer for selective etching
103 n⁺-GaAs contact layer
104 n-DBR layer
105 Active layer
106 p-DBR layer
107 i-GaAs light absorption layer
110 p-type electrode
111 n-type electrode
112 Schottky electrode
113 Metal for wiring
120 p⁺-GaAs contact layer
121 Selective etching InGaP layer
122 n⁺-GaAs contact layer
123 n^--GaAs channel layer
130 p-GaAs layer
131 n-GaAs layer
132 Insulating film

Claims (4)

A light input / output substrate in which a stacked body is formed on one main surface of the compound semiconductor substrate by epitaxial growth in the order of a selective etching layer, a contact layer, a first DBR layer, an active layer, a second DBR layer, and a light absorption layer; ,
A silicon integrated circuit substrate in which a semiconductor element is integrated on one main surface, and a metal layer for electrical connection and a metal layer for heat dissipation are patterned;
The surface of the optical input / output substrate on which the laminated body is formed and the surface of the silicon integrated circuit substrate on which the semiconductor elements are integrated are opposed to each other via an insulating adhesive layer made of an organic material, A first step of removing the compound semiconductor substrate and the selective etching layer of the output substrate by polishing and chemical etching;
Subsequent to the first step, the laminate is processed to form a light emitting element and a light receiving element, and a second step of forming each electrode of the light emitting element and the light receiving element;
A third step of forming a through hole for connecting the semiconductor element on the silicon integrated circuit substrate and each electrode of the light emitting element and the light receiving element, filling the through hole with metal and electrically connecting the through hole; With
The second step includes a step of processing the contact layer, the first DBR layer, the active layer, and the second DBR layer to form a light emitting element portion, and the contact of the formed light emitting element portion. Forming a light emitting element by forming an electrode on the layer and the second DBR layer, and forming a light receiving element by forming an electrode on the light absorption layer exposed by the step of forming the light emitting element portion A method for manufacturing a semiconductor integrated circuit, comprising: An optical input / output substrate in which a stacked body is formed on one main surface of a compound semiconductor substrate by epitaxial growth in the order of a selective etching layer, a light absorption layer, a first DBR layer, an active layer, a second DBR layer, and a contact layer. A first step of bonding the surface on which the laminate is formed and a quartz substrate together using wax, and removing the compound semiconductor substrate and the selective etching layer of the optical input / output substrate by polishing and chemical etching;
The surface of the optical input / output substrate from which the compound semiconductor substrate and the selective etching layer have been removed, and silicon on which the semiconductor elements are integrated on one main surface, and the metal layer for electrical connection and the metal layer for heat dissipation are patterned. A second step of attaching the semiconductor element of the integrated circuit substrate facing each other through an insulating adhesive layer made of an organic material, and dissolving the wax by heating to remove the quartz substrate;
Subsequent to the second step, the laminated body is processed to form a light emitting element and a light receiving element, and a third step of forming each electrode of the light emitting element and the light receiving element;
Forming a through hole for connecting the semiconductor element on the silicon integrated circuit substrate and each electrode of the light emitting element and the light receiving element;
A fourth step of filling the through hole with metal and electrically connecting it,
The third step includes a step of processing the contact layer, the second DBR layer, the active layer, and the first DBR layer to form a light emitting element portion, and the contact of the formed light emitting element portion. Forming a light emitting element by forming an electrode on the layer and the first DBR layer, and forming a light receiving element by forming an electrode on the light absorbing layer exposed by the step of forming the light emitting element portion A method for manufacturing a semiconductor integrated circuit, comprising: On one main surface of the compound semiconductor substrate, a stacked body is formed by epitaxial growth in the order of a selective etching layer, a light absorbing layer, a first DBR layer, an active layer, a second DBR layer, and a contact layer. A first step of processing to form a light input / output substrate by forming a plurality of light emitting elements and a plurality of light receiving elements and respective electrodes;
The plurality of light emitting elements and the plurality of light receiving elements of the light input / output substrate and the surfaces on which the respective electrodes are formed and a quartz substrate are bonded together using wax, and the compound semiconductor substrate and the selective etching of the light input / output substrate are bonded together. A second step of removing the layer by polishing and chemical etching;
The surface of the optical input / output substrate from which the compound semiconductor substrate and the selective etching layer have been removed, and silicon on which the semiconductor elements are integrated on one main surface, and the metal layer for electrical connection and the metal layer for heat dissipation are patterned. The surface of the integrated circuit substrate facing the surface on which the semiconductor elements are integrated is positioned using infrared light, bonded through an insulating adhesive layer made of an organic material, and the wax is melted by heating, A third step of removing the quartz substrate;
Forming a through hole for connecting the semiconductor element on the silicon integrated circuit substrate to each of the electrodes of the plurality of light emitting elements and the plurality of light receiving elements, and filling the through hole with a metal for electrical connection; With four steps,
The first step includes a step of processing the contact layer, the second DBR layer, the active layer, and the first DBR layer to form a light emitting element portion, and the contact of the formed light emitting element portion Forming a light emitting element by forming an electrode on the layer and the first DBR layer, and forming a light receiving element by forming an electrode on the light absorbing layer exposed by the step of forming the light emitting element portion A method for manufacturing a semiconductor integrated circuit, comprising: On one main surface of the compound semiconductor substrate, a first selective etching layer, a contact layer, a first DBR layer, an active layer, a second DBR layer, a second selective etching layer, an FET element constituent layer, light absorption An optical input / output substrate in which a laminate is formed by epitaxial growth in the order of the layers;
A silicon integrated circuit substrate in which a semiconductor element is integrated on one main surface, and a metal layer for electrical connection and a metal layer for heat dissipation are patterned;
The surface of the optical input / output substrate on which the laminated body is formed and the surface of the silicon integrated circuit substrate on which the semiconductor elements are integrated are opposed to each other via an insulating adhesive layer made of an organic material, A first step of removing the compound semiconductor substrate of the output substrate and the first selective etching layer by polishing and chemical etching;
Subsequent to the first step, the stacked body is processed to form a light emitting element, an FET element, and a light receiving element, and a second step of forming each electrode of the light emitting element, the FET element, and the light receiving element;
Forming a through hole for connecting the semiconductor element on the silicon integrated circuit substrate to the respective electrodes of the light emitting element, the FET element, and the light receiving element, and filling the through hole with a metal to electrically connect them; With the process of
In the second step, the contact layer, the first DBR layer, the active layer, and the second DBR layer are processed to form a light emitting element portion and to expose the second selective etching layer. Etching the exposed second selective etching layer to expose the FET element constituent layer, processing the exposed FET element constituent layer to form an FET element part, and forming the light emitting element part Forming a light emitting element by forming electrodes on the contact layer and the second DBR layer; forming an FET element by forming electrodes on the formed FET element part; and forming the FET element part Forming a light receiving element by forming an electrode on the light absorption layer exposed by the step of performing a manufacturing method of a semiconductor integrated circuit.

Images