JP3673230B2 - Flip-flop circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a flip-flop circuit to which a latch circuit having a small occupation area is applied.
[0002]
[Prior art]
Memory circuits occupy a large portion of current digital integrated circuits. This is because, along with the miniaturization of devices, various functions can be incorporated on the same chip, so that intermediate results need to be stored on the same chip in a form that can be accessed at high speed.
[0003]
Conventionally, a memory circuit has been realized by a latch circuit or a flip-flop circuit. The latch circuit is a circuit that captures new data while the level of the clock signal is high or low. Although the circuit scale is small, it is necessary to design with careful attention to the timing of fetching data. On the other hand, the flip-flop circuit is a circuit that captures new data at the rising edge or falling edge of the clock signal. Although the circuit scale is larger than that of the latch circuit, there is an advantage that the timing design is easy.
[0004]
In recent years, a circuit format that combines the small area of a latch circuit with the ease of timing design of a flip-flop circuit has been proposed. FIG. 6 shows a flip-flop circuit using a transmission gate type latch circuit, and FIG. 7 shows a timing chart of the flip-flop circuit of FIG. This flip-flop circuit includes inverter circuits G11, G12, G13, G15, G16, G17, and G18, a two-input NAND circuit G14, and a pMOS transistor M11 and an nMOS transistor M12 that constitute a transmission gate.
[0005]
In the flip-flop circuit of FIG. 6, using the inverter circuits G11, G12, G13, G15 and the two-input NAND circuit G14, a minute time width pulse signal CK * synchronized with the rising edge of the clock signal CK as shown in FIG. And its inverted signal bar CK *. A CMOS transmission gate type latch circuit is driven by these minute time width pulse signals CK * and CK * to operate as an edge trigger flip-flop circuit. However, in the flip-flop circuit shown in FIG. 6, since the latch circuit is a transmission gate system, the circuit is not sufficiently miniaturized, and an inverter circuit is used to generate minute time width pulse signals CK * and CK *. It was necessary to add G11, G12, G13, G15 and a two-input NAND circuit G14.
[0006]
A latch circuit having a RAM type structure is known as a latch circuit that can be downsized. The RAM-type latch circuit is a single memory circuit that is cut out from a memory element circuit used in an SRAM (Static Random Access Memory). It is characterized by its small size due to its circuit configuration that is conscious of high-density layout. FIG. 8 shows a RAM type latch circuit, and FIG. 9 shows a timing chart of the RAM type latch circuit of FIG. The RAM type latch circuit includes inverter circuits G21, G22, G23 and nMOS transistors M21, M22, M23, M24.
[0007]
Inverter circuits G21 and G22 constitute a memory circuit and hold data at data holding terminals QP and QN. Transistors M21, M22, M23, and M24 are devices for accessing the data holding terminals QP and QN. When the clock signal CK is at a high level, the data signal D is transferred to the data holding terminal QP and the inverted signal is transferred to the data holding terminal QN. When the clock signal CK is at a low level, the data holding terminal The holding mode for holding the data signal D transferred to QP and QN and its inverted signal is set.
[0008]
Although the RAM type latch circuit of FIG. 8 can be miniaturized, there is a problem that timing design is difficult. That is, since the data signal D is transferred as it is to the data holding terminal QP as shown in FIG. 9 during the period when the clock signal CK is at the high level, the update of the stored data is limited to a certain time point, not within a certain period. There is a problem that it is not suitable for an edge trigger flip-flop circuit that needs to be performed.
[0009]
FIG. 10 shows a circuit example in which the RAM type latch circuit shown in FIG. 8 is configured as a master-slave type flip-flop circuit, and FIG. 11 shows a timing chart thereof. This flip-flop circuit includes inverter circuits G31, G32, G33, G34, G35 and nMOS transistors M31, M32, M33, M34, M35, M36, M37, M38.
[0010]
In the flip-flop circuit shown in FIG. 10, since the data signal D can be taken in at the rising edge of the clock signal CKP as shown in FIG. 11, the timing design is easier than in the latch circuit shown in FIG. . However, since the flip-flop circuit shown in FIG. 10 requires two RAM-type latch circuits, even if each latch circuit is small, it is disadvantageous because the area is large as a whole.
[0011]
[Problems to be solved by the invention]
As described above, the conventional flip-flop circuit is insufficiently miniaturized, and there is a problem that the area of the digital circuit that frequently uses the flip-flop circuit is increased.
The present invention has been made to solve the above problems, and an object thereof is to provide a small-sized flip-flop circuit.
[0012]
[Means for Solving the Problems]
The flip-flop circuit of the present invention has a first level at which the clock signal indicates the passing mode. Just before A RAM type latch circuit that captures the data signal input to the data input terminal and retains the captured data signal when the clock signal is at the second level indicating the retention mode; and the clock signal is at the first level. When the data signal and the data input terminal are electrically separated, and the clock signal is at the second level The data signal is input to the data input terminal A switching circuit, and the clock signal is changed from the second level to the first level. Was input to the data input terminal just before A data signal is stored in the RAM type latch circuit. In the present invention, the basic latch circuit has a RAM type configuration, and a switch circuit is connected to the data input terminal of the latch circuit so that the data signal and the latch circuit can be electrically separated. With this configuration, when the latch circuit is in the passing mode, the data signal is disconnected from the latch circuit, and the data input terminal of the latch circuit is in a floating state. Therefore, even if the data signal is updated while the latch circuit is in the passing mode, it is not reflected in the data held by the latch circuit. Since the data held in the latch circuit is captured only when the clock signal changes from the second level to the first level (falling edge or rising edge), it can be operated as an edge trigger type flip-flop circuit. it can. On the other hand, the data signal is dynamically held in the RAM type latch circuit while the latch circuit is in the passing mode. At this time, since the data holding unit of the RAM type latch circuit maintains the cross-coupled structure of the inverter, the data of the previous cycle is held even if the charge of the data input terminal disappears and the driving MOSFET is turned off. In addition, erroneous data updates can be prevented. According to the present invention, an edge trigger type D flip-flop circuit can be realized by one RAM type latch circuit and a switch circuit capable of a small layout.
[0013]
In the configuration example of the flip-flop circuit of the present invention, the switch circuit has an inverted signal of the data signal input to the source terminal, a drain terminal connected to the first switch output terminal, and an input to the gate terminal. In addition, when the clock signal is at the second level, a first transistor (M1 in FIGS. 1 and 3) that outputs the input inverted signal to the first switch output terminal, and the data signal at the source terminal Is input, the drain terminal is connected to the second switch output terminal, and the input data signal is output to the second switch output terminal when the clock signal input to the gate terminal is at the second level. And the second transistor (M2).
In one configuration example of the flip-flop circuit of the present invention, the switch circuit includes: An inverter for inverting the clock signal; The inverted signal of the data signal is input to the source terminal, the drain terminal is connected to the first switch output terminal, and the input inverted signal is input when the clock signal input to the gate terminal is at the second level. The first conductivity type first transistor (M1 in FIGS. 4 and 5) to be output to the first switch output terminal, the data signal is input to the source terminal, and the drain terminal is to the second switch output terminal. A second transistor (M2) of a first conductivity type that is connected and outputs the input data signal to the second switch output terminal when the clock signal input to the gate terminal is at the second level; The inverted signal of the data signal is input to the source terminal, the drain terminal is connected to the first switch output terminal, and is input to the gate terminal. The output signal of the inverter is the first A third transistor (M7) of the second conductivity type that outputs the inputted inverted signal to the first switch output terminal when the level is, the data signal is inputted to the source terminal, and the drain terminal is the first transistor 2 connected to the switch output terminal and input to the gate terminal The output signal of the inverter is the first And a fourth transistor (M8) of the second conductivity type that outputs the inputted data signal to the second switch output terminal when the level is.
[0014]
Further, in one configuration example of the flip-flop circuit of the present invention, the RAM type latch circuit has a first input terminal connected to the first data holding terminal and an output terminal connected to the second data holding terminal. An inverter (G1 in FIGS. 1 and 4), a second inverter (G2) having an input terminal connected to the second data holding terminal and an output terminal connected to the first data holding terminal, and a gate A fifth transistor (M3) having a terminal connected to the first switch output terminal of the switch circuit, a source terminal connected to the first data holding terminal, and a drain terminal being the drain terminal of the fifth transistor A sixth transistor that connects between the drain terminal and the source terminal when the source terminal is grounded and the clock signal input to the gate terminal is at the first level M4), a seventh transistor (M6) having a gate terminal connected to the second switch output terminal of the switch circuit, a source terminal connected to the second data holding terminal, and a drain terminal being the seventh transistor. And an eighth transistor (M5) connecting the drain terminal and the source terminal when the clock signal input to the gate terminal is at the first level. It will be.
Further, in one configuration example of the flip-flop circuit of the present invention, the RAM type latch circuit has a first input terminal connected to the first data holding terminal and an output terminal connected to the second data holding terminal. An inverter (G1 in FIGS. 3 and 5), one input terminal is connected to the second data holding terminal, a clear signal is input to the other input terminal, and an output terminal is connected to the first data holding terminal A connected two-input NAND circuit (G5), and a fifth transistor (a gate terminal connected to the first switch output terminal of the switch circuit and a source terminal connected to the first data holding terminal) M3), the drain terminal is connected to the drain terminal of the fifth transistor, the source terminal is grounded, and the drain signal is input when the clock signal input to the gate terminal is at the first level. A sixth transistor (M4) for connecting the terminal and the source terminal; a seventh terminal having a gate terminal connected to the second switch output terminal of the switch circuit; and a source terminal connected to the second data holding terminal. Transistor (M6), the drain terminal is connected to the drain terminal of the seventh transistor, the source terminal is grounded, and when the clock signal input to the gate terminal is at the first level, the drain terminal and the source terminal And an eighth transistor (M5) that connects the first data holding terminal and the second data holding terminal to the desired logic value by inputting the clear signal. It is to be fixed.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram of a flip-flop circuit using a RAM type latch circuit according to the first embodiment of the present invention. The flip-flop circuit of this embodiment includes a RAM type latch circuit, a switch circuit, and an inverter circuit G4. The RAM type latch circuit has nMOS transistors M3, M4, M5, and M6 and inverter circuits G1, G2, and G3. The switch circuit has nMOS transistors M1 and M2.
[0016]
Inverter circuits G1 and G2 constitute a data holding unit. The connection point between the input terminal of the inverter circuit G1 and the output terminal of the inverter circuit G2 is the first data holding terminal QN, and the connection point between the output terminal of the inverter circuit G1 and the input terminal of the inverter circuit G2 is the second data holding terminal. Terminal QP. The data holding terminal QP and its inverting terminal QN are output terminals of the flip-flop circuit of the present embodiment.
[0017]
The inverter circuit G3 receives the data signal D and outputs its inverted signal. The inverter circuit G4 receives the clock signal CK and outputs its inverted signal. The nMOS transistors M1, M2, M3, M4, M5, and M6 constitute a data input control unit. Each of the transistors M1, M2, M3, M4, M5, and M6 is controlled by the clock signal CK, the data signal D, or an inverted signal thereof, and connects or disconnects the data holding unit to the ground electrode.
[0018]
The transistors M2 and M1 are controlled to be turned on and off by a clock signal CK input to the gate terminal, and play a role of transferring the data signal D and its inverted signal to the data holding unit and disconnecting from the data holding unit. The transistor M1 outputs an inverted signal of the data signal D input to the source terminal from the inverter circuit G3, and the drain terminal (first switch output terminal) to the gate terminal of the transistor M3 (first data input terminal of the RAM type latch circuit). ). The transistor M2 outputs the data signal D input to the source terminal from the drain terminal (second switch output terminal) to the gate terminal of the transistor M6 (second data input terminal of the RAM type latch circuit).
[0019]
That is, during a period when the clock signal CK is at a high level (second level), the transistors M1 and M2 are turned on to transfer an inverted signal of the data signal D to the gate terminal of the transistor M3 and to transfer the data signal D to the gate of the transistor M6. Transfer to the terminal. On the other hand, during the period when the clock signal CK is at the low level (first level), the transistors M1 and M2 are turned off, and the gate terminals of the transistors M3 and M6 are disconnected from the data input to be in a floating state.
[0020]
The source terminals of the transistors M4 and M5 are connected to the ground electrode, and the drain terminals are connected to the drain terminals of the transistors M3 and M6, respectively. The source terminals of the transistors M3 and M6 are connected to the data holding terminals QN and QP, respectively. The transistors M4 and M5 are controlled to be turned on / off by an inverted signal of the clock signal CK input to the gate terminal from the inverter circuit G4, and the data holding terminals QN and QP of the data holding unit are forcibly grounded through the transistors M3 and M6. It plays a role of connecting with an electrode or disconnecting from a ground electrode.
[0021]
The transistors M4 and M5 are turned on while the clock signal CK is at a low level. As a result, the data holding terminal of either QN or QP is connected to the ground electrode depending on the value of the data signal D immediately before the clock signal CK goes low. At this time, the data signal D is stored in the data holding unit. Details of this operation will be described later. Further, during the period when the clock signal CK is at the high level, the transistors M4 and M5 are turned off, and the data holding units of the inverter circuits G1 and G2 are set in the holding mode.
[0022]
A timing chart of the operation of this embodiment is shown in FIG. FIG. 2 shows signal waveforms of the data signal D, the clock signal CK, and the data holding terminal QP. It can be seen that the data signal D is captured and held at the falling edge of the clock signal CK, and operates as an edge trigger type flip-flop circuit.
[0023]
8 differs from the RAM type latch circuit of FIG. 8 in that the transistors M1 and M2 are provided, so that the data signal D is the gate of the transistors M3 and M6 while the latch circuit is in the passing mode, that is, the period when the clock signal CK is at the low level. It is electrically disconnected from the terminal. For this reason, even if the data signal D is updated during the pass mode, it is not reflected in the data held in the data holding unit. The data signal D is taken into the data holding unit only at the edge where the clock signal CK switches from the high level to the low level.
[0024]
For example, when the clock signal CK is at a high level and the data signal D is at a high level, a low level is applied to the gate terminal of the transistor M3 and a high level is applied to the gate terminal of the transistor M6. Here, when the clock signal CK is switched to the low level, the gate terminals of the transistors M3 and M6 are in a floating state, and the charge due to the data signal D immediately before the clock signal CK becomes the low level is held in the gate terminals of the transistors M3 and M6. The state where the transistor M3 is off and the transistor M6 is on is maintained. As the clock signal CK goes low, the transistors M4 and M5 are turned on, so that the data holding terminal QP is connected to the ground electrode via the transistors M5 and M6, and the data signal D is stored in the data holding unit.
[0025]
On the other hand, when the clock signal CK is at a high level and the data signal D is at a low level, a high level is applied to the gate terminal of the transistor M3 and a low level is applied to the gate terminal of the transistor M6. Here, when the clock signal CK is switched to the low level, the charge immediately before the clock signal CK goes to the low level is held in the gate terminals of the transistors M3 and M6, and the transistor M3 is on and the transistor M6 is off. Maintained. When the transistors M4 and M5 are turned on, the data holding terminal QN is connected to the ground electrode via the transistors M3 and M4, and the data signal D is stored in the data holding unit.
[0026]
During the period when the clock signal CK is at the low level, the charge due to the data signal D immediately before the clock signal CK becomes the low level is held at the gate terminals of the transistors M3 and M6. The transistor M3 or M6 in the on state may be turned off and the data in the data holding unit may be updated.
[0027]
However, since the data holding unit is composed of two pairs of inverter circuits G1 and G2, it is necessary to inject a large current into the data holding terminal QP or QN in order to invert the data in the data holding unit. However, the transistor M3 or M6 which is going to be turned off if the charge is not lost does not have such a current supply capability. Therefore, the possibility that the data in the data holding unit is erroneously updated is very small, and the function as an edge trigger type flip-flop circuit can be maintained.
[0028]
As described above, in the present embodiment, the size of the latch circuit itself can be reduced by adopting the RAM type latch circuit, and a new additional circuit can be operated as a flip-flop circuit with only one latch circuit. A flip-flop circuit can be realized. In addition, in order to perform data fetching and holding timing with good controllability, a reverse-phase clock signal is generated inside the flip-flop circuit by the inverter circuit G4.
[0029]
[Second Embodiment]
FIG. 3 is a circuit diagram of a flip-flop circuit using a RAM type latch circuit according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. The flip-flop circuit of this embodiment uses a 2-input NAND circuit (2-input NAND circuit) G5 in place of the inverter circuit G2 in the flip-flop circuit of the first embodiment, and a new clear input signal. By adding CLR, the data held in the data holding unit can be forcibly set to QP = 0 and QN = 1.
[0030]
The inverter circuit G1 and the 2-input NAND circuit G5 constitute a data holding unit. The connection point between the input terminal of the inverter circuit G1 and the output terminal of the 2-input NAND circuit G5 becomes the data holding terminal QN, and the connection point between the output terminal of the inverter circuit G1 and one input terminal of the 2-input NAND circuit G5 holds the data. Terminal QP. The clear input signal CLR is input to the other input terminal of the 2-input NAND circuit G5.
[0031]
When the clear input signal CLR is set to a high level, that is, a logical value 1, the 2-input NAND circuit G5 operates in the same manner as the inverter circuit G2. Therefore, the operation at this time is as described in the first embodiment. On the other hand, when the clear input signal CLR is set to the low level, that is, the logical value 0, the output terminal of the 2-input NAND circuit G5 becomes the high level, the data holding terminal QN is fixed to the logical value 1, and as a result, the data holding terminal QP is Fixed to a logical value of zero. In this way, the data held in the data holding unit can be set to QP = 0 and QN = 1.
[0032]
[Third Embodiment]
FIG. 4 is a circuit diagram of a flip-flop circuit using a RAM type latch circuit according to a third embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the flip-flop circuit of this embodiment, pMOS transistors M7 and M8 are added to the flip-flop circuit of the first embodiment, so that the nMOS pass transistors M1 and M2 that connect the data input and the RAM type latch circuit are CMOS. It was replaced with a transmission gate.
[0033]
The nMOS transistor M1 and the pMOS transistor M7 constitute a first CMOS transmission gate, and the nMOS transistor M2 and the pMOS transistor M8 constitute a second CMOS transmission gate. The source terminal of the transistor M7 is connected to the output terminal of the inverter circuit G3, and the drain terminal is connected to the gate terminal of the transistor M3. The data signal D is input to the source terminal of the transistor M8, and the drain terminal is connected to the gate terminal of the transistor M6.
[0034]
The gate terminals of the transistors M7 and M8 are connected to the output terminal of the inverter circuit G4. Accordingly, the transistors M1, M2, M7, and M8 are turned on while the clock signal CK is at a high level, and the transistors M1, M2, M7, and M8 are turned off while the clock signal CK is at a low level. The operation is the same as in the first embodiment. In this embodiment, by using the CMOS transmission gate, the voltage amplitude at the nodes N1 and N2 (the gate terminals of the transistors M3 and M6) can be set to the power supply potential, so that the noise margin can be increased.
[0035]
[Fourth Embodiment]
FIG. 5 is a circuit diagram of a flip-flop circuit using a RAM type latch circuit according to a fourth embodiment of the present invention. The same components as those in FIGS. 1 and 3 are denoted by the same reference numerals. The flip-flop circuit according to the present embodiment uses the 2-input NAND circuit G5 instead of the inverter circuit G2 in the flip-flop circuit according to the third embodiment, and newly adds a clear input signal CLR to hold data. The data held in the copy can be forcibly set to QP = 0 and QN = 1.
[0036]
The inverter circuit G1 and the 2-input NAND circuit G5 constitute a data holding unit. The connection point between the input terminal of the inverter circuit G1 and the output terminal of the 2-input NAND circuit G5 becomes the data holding terminal QN, and the connection point between the output terminal of the inverter circuit G1 and one input terminal of the 2-input NAND circuit G5 holds the data. Terminal QP. The clear input signal CLR is input to the other input terminal of the 2-input NAND circuit G5.
[0037]
When the clear input signal CLR is set to a logical value 1, the 2-input NAND circuit G5 performs the same operation as the inverter circuit G2. Therefore, the operation at this time is as described in the third embodiment. On the other hand, when the clear input signal CLR is set to the logical value 0, the data holding terminal QN is fixed to the logical value 1, and the data holding terminal QP is fixed to the logical value 0. In this way, the data held in the data holding unit can be set to QP = 0 and QN = 1.
[0038]
【The invention's effect】
According to the present invention, when the clock signal is at the first level indicating the passing mode, the data signal input to the data input terminal is captured, and when the clock signal is at the second level indicating the holding mode, the captured data signal is retained. A RAM latch circuit that electrically isolates the data signal and the data input terminal when the clock signal is at the first level, and connects the data signal and the data input terminal when the clock signal is at the second level By providing a circuit, an edge-triggered D flip-flop circuit can be realized with one RAM-type latch circuit capable of a small layout and a switch circuit. For this reason, it is possible to downsize the memory circuit that conventionally required two latch circuits and to greatly reduce the area occupied by the edge trigger flip-flop circuit, and to reduce the area occupied by the entire digital circuit that frequently uses the flip-flop circuit. Thus, the degree of integration of the digital circuit can be increased. As a result, more functions can be incorporated on a semiconductor chip of the same area, or the same function can be realized with a smaller area, the semiconductor utilization efficiency can be increased, and the speed of the circuit and the reduction of power consumption can be achieved.
[0039]
The first conductivity type first transistor and the second conductivity type third transistor constitute one transmission gate, and the first conductivity type second transistor and the second conductivity type fourth transistor. By constructing another transmission gate, the voltage amplitude at the first switch output terminal and the second switch output terminal can be set to the power supply potential, so that the noise margin can be increased.
[0040]
Further, instead of the second inverter, one input terminal is connected to the second data holding terminal, a clear signal is input to the other input terminal, and an output terminal is connected to the first data holding terminal. By using an input NAND circuit, it can be operated as a flip-flop circuit by setting a clear signal, or the logical value of data held in the first data holding terminal and the second data holding terminal is fixed to a desired value. You can do it.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a flip-flop circuit using a RAM type latch circuit according to a first embodiment of the present invention.
FIG. 2 is a timing chart showing the operation of the flip-flop circuit of FIG. 1;
FIG. 3 is a circuit diagram of a flip-flop circuit using a RAM type latch circuit according to a second embodiment of the present invention.
FIG. 4 is a circuit diagram of a flip-flop circuit using a RAM type latch circuit according to a third embodiment of the present invention.
FIG. 5 is a circuit diagram of a flip-flop circuit using a RAM type latch circuit according to a fourth embodiment of the present invention.
FIG. 6 is a circuit diagram of a conventional flip-flop circuit using a transmission gate type latch circuit.
7 is a timing chart showing the operation of the flip-flop circuit of FIG. 6. FIG.
FIG. 8 is a circuit diagram of a conventional RAM type latch circuit.
9 is a timing chart showing the operation of the RAM type latch circuit of FIG. 8. FIG.
FIG. 10 is a circuit diagram of a conventional master-slave type flip-flop circuit using a RAM type latch circuit.
11 is a timing chart illustrating the operation of the flip-flop circuit of FIG. 10;
[Explanation of symbols]
G1 to G4... Inverter circuit, G5... 2 input NAND circuit, M1 to M6... NMOS transistor, M7 and M8.

Claims (5)

A RAM that captures the data signal input to the data input terminal immediately before the clock signal becomes the first level indicating the passing mode, and holds the captured data signal when the clock signal is the second level indicating the holding mode. Type latch circuit;
Switch the clock signal is electrically separating the data input terminal and said data signal when said first level, said clock signal to input the data signal when the second level to the data input terminal Circuit and
A flip-flop circuit, wherein a data signal input to the data input terminal immediately before the clock signal changes from the second level to the first level is stored in the RAM type latch circuit. The flip-flop circuit according to claim 1,
The switch circuit is
The inverted signal of the data signal is input to the source terminal, the drain terminal is connected to the first switch output terminal, and the input inverted signal is input when the clock signal input to the gate terminal is at the second level. A first transistor that outputs to the first switch output terminal;
When the data signal is input to the source terminal, the drain terminal is connected to the second switch output terminal, and the clock signal input to the gate terminal is at the second level, the input data signal is the second signal. And a second transistor that outputs to the switch output terminal of the flip-flop circuit. The flip-flop circuit according to claim 1,
The switch circuit is
An inverter for inverting the clock signal;
The inverted signal of the data signal is input to the source terminal, the drain terminal is connected to the first switch output terminal, and the input inverted signal is input when the clock signal input to the gate terminal is at the second level. A first conductivity type first transistor that outputs to the first switch output terminal;
When the data signal is input to the source terminal, the drain terminal is connected to the second switch output terminal, and the clock signal input to the gate terminal is at the second level, the input data signal is the second signal. A second transistor of the first conductivity type that outputs to the switch output terminal;
The inverted signal of the data signal is input to the source terminal, the drain terminal is connected to the first switch output terminal, and the input signal is input when the output signal of the inverter input to the gate terminal is at the first level. A second transistor of a second conductivity type that outputs an inverted signal to the first switch output terminal;
The input data signal is input when the data signal is input to the source terminal, the drain terminal is connected to the second switch output terminal, and the output signal of the inverter input to the gate terminal is at the first level. A flip-flop circuit comprising: a fourth transistor of a second conductivity type that outputs to the second switch output terminal. The flip-flop circuit according to claim 2 or 3,
The RAM type latch circuit includes:
A first inverter having an input terminal connected to the first data holding terminal and an output terminal connected to the second data holding terminal;
A second inverter having an input terminal connected to the second data holding terminal and an output terminal connected to the first data holding terminal;
A fifth transistor having a gate terminal connected to the first switch output terminal of the switch circuit and a source terminal connected to the first data holding terminal;
A drain terminal is connected to the drain terminal of the fifth transistor, a source terminal is grounded, and when the clock signal input to the gate terminal is at the first level, a sixth terminal is connected between the drain terminal and the source terminal. A transistor,
A seventh transistor having a gate terminal connected to the second switch output terminal of the switch circuit and a source terminal connected to the second data holding terminal;
The drain terminal is connected to the drain terminal of the seventh transistor, the source terminal is grounded, and when the clock signal input to the gate terminal is at the first level, the eighth terminal connects between the drain terminal and the source terminal. A flip-flop circuit comprising a transistor. The flip-flop circuit according to claim 2 or 3,
The RAM type latch circuit includes:
A first inverter having an input terminal connected to the first data holding terminal and an output terminal connected to the second data holding terminal;
A two-input NAND circuit in which one input terminal is connected to the second data holding terminal, a clear signal is input to the other input terminal, and an output terminal is connected to the first data holding terminal;
A fifth transistor having a gate terminal connected to the first switch output terminal of the switch circuit and a source terminal connected to the first data holding terminal;
A drain terminal is connected to the drain terminal of the fifth transistor, a source terminal is grounded, and when the clock signal input to the gate terminal is at the first level, a sixth terminal is connected between the drain terminal and the source terminal. A transistor,
A seventh transistor having a gate terminal connected to the second switch output terminal of the switch circuit and a source terminal connected to the second data holding terminal;
The drain terminal is connected to the drain terminal of the seventh transistor, the source terminal is grounded, and when the clock signal input to the gate terminal is at the first level, the eighth terminal connects between the drain terminal and the source terminal. Consisting of transistors,
A flip-flop circuit that fixes a logical value of data held in the first data holding terminal and the second data holding terminal to a desired value by inputting the clear signal.

Images