JP3668150B2 - Bias circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bias circuit used in a transistor circuit such as a high frequency amplifier circuit.
[0002]
[Prior art]
FIG. 1 shows an example of a conventional high-frequency amplifier circuit, particularly a push-pull amplifier circuit. In the circuit shown in this figure, a pair of FETs Q1 and Q2 are used as amplifying elements. The sources of the FETs Q1 and Q2 are grounded, the gates are respectively combined with a balun ( abbreviation of balance unbalance transfermer ) B1 via a DC cut capacitor C11 or C12, and the drains are respectively combined via a DC cut capacitor C21 or C22. Is connected to the side balun B2.
[0003]
The balun B1 is an unbalance / balance conversion element for connecting the unbalanced transmission line on the input terminal IN side and the balanced transmission lines on the FETs Q1 and Q2 side. The balun B1 distributes a radio frequency (RF) signal applied to the input terminal IN to the FETs Q1 and Q2 via the DC cut capacitor C11 or C12. At this time, the balun B1 gives a 180 ° phase difference between the signal distributed to the FET Q1 and the signal distributed to the FET Q2, and causes the FETs Q1 and Q2 to perform a push-pull operation. The balun B2 is a balanced / unbalanced conversion element for connecting the balanced transmission paths on the FETs Q1 and Q2 side and the unbalanced transmission path on the output terminal OUT side. The balun B2 receives the high frequency signals amplified from the FETs Q1 and Q2 via the DC cut capacitor C21 or C22, synthesizes them, and outputs them from the output terminal OUT to a circuit (not shown).
[0004]
The DC cut capacitors C11, C12, C21 and C22 prevent the DC bias supplied from the bias circuit to the gates and drains of the FETs Q1 and Q2 from being applied to the baluns B1 and B2. The bias circuit in this prior art is composed of a gate bias circuit for applying a gate bias voltage VG to the gates of the FETs Q1 and Q2, and a drain bias circuit for applying a drain bias voltage VD to the drains of the FETs Q1 and Q2. ing. Each of the gate bias circuit and the drain bias circuit has an LPF type LC circuit corresponding to each of the FETs Q1 and Q2 in order to block a high-frequency signal. In the figure, an inverted L-type LC circuit constituted by an inductor L11 or L12 and a capacitor C31 or C32 is a high-frequency signal cutoff circuit in a gate bias circuit, and an LPF constituted by an inductor L21 or L22 and a capacitor C41 or C42. This type of LC circuit is a high-frequency signal cutoff circuit in the drain bias circuit. Further, the resistor R11 or R12 is a gate resistor.
[0005]
[Problems to be solved by the invention]
First, in a communication system using a plurality of carriers having different frequencies, an amplifier circuit that simultaneously amplifies the plurality of carriers is used as a high-frequency amplifier circuit. Usually, the difference frequency (channel separation or frequency pitch) between these carriers is significantly lower than the frequency of each carrier. On the other hand, not only the FET but also the amplifying element generally has non-linearity, and a distortion component is generated by the non-linearity during signal amplification.
[0006]
For example, when a high frequency signal including a frequency f1 component and a frequency f2 (> f1) component is amplified by an amplifying element, not only the frequency f1 component and the frequency f2 component are amplified, but generally the frequency Δf = f2 A difference frequency component having −f1 appears at each terminal of the amplifying element. Provided for DC bias cut in applications where Δf << f1, Δf << f2, such as an amplifier circuit for a communication system using multiple carriers, that is, where the difference frequency Δf is separated from the frequencies f1 and f2. The impedance of the DC cut capacitor is very high at the difference frequency Δf. Therefore, the current having the difference frequency component is blocked by the DC cut capacitor, and a voltage having the difference frequency Δf is generated by the circuit elements constituting the bias circuit. That is, the DC bias is modulated by the voltage having the difference frequency Δf. When the DC bias is modulated by the voltage of the difference frequency Δf, an intermodulation component of the frequencies f1, f2 and the difference frequency Δf appears at the output side terminal of the amplifying element. The intermodulation components, as shown in FIG. 2 is a component having a frequency f1, a frequency close to f2 f1-Δf, f2 + Δf , signal quality quality on the amplified output is a component of interest.
[0007]
Of course, by selecting the element values of the circuit elements constituting the bias circuit (C31, C32, C41, C42, etc. in the example of FIG. 1), the impedance at the difference frequency Δf is lowered and the DC bias is modulated by the difference frequency component. It is not impossible to suppress. However, since the impedance does not become zero, there is a limit to the degree of intermodulation component suppression that can be realized by it, and the selection of element values is a burden on the designer. Further, when a resistance element exists in the bias circuit, resistance is generated regardless of the frequency in the resistance element (the gate resistances R11 and R12 in the example of FIG. 1). The generation of the difference frequency voltage is inevitable. In addition, this phenomenon appears more significantly during class AB operation than during class A operation.
[0008]
Further, in a high frequency amplifier circuit having a configuration in which a high frequency amplification transistor is arranged on a circuit board and a high frequency signal line is formed by a high frequency transmission line such as a microstrip line, a sufficient amount is provided between the high frequency signal line and the power supply line. Without isolation, the desired characteristics cannot be obtained. However, in the conventional technology described above, wirings through which high-frequency signals flow, that is, high-frequency signal lines, and wirings through which DC bias flows, that is, power supply lines intersect at the locations indicated by A and B in the circuit diagram. Yes. Therefore, the three-dimensional intersection to ensure the isolation between the high-frequency signal line and the power line, such as forming the high-frequency signal line with a microstrip line, etc. Measures such as were necessary. This measure imposes restrictions on pattern design on the circuit board, that is, component placement / transmission path formation, and not only lowers the degree of freedom of design but also hinders downsizing.
[0009]
The present invention has been made in order to solve such problems, and by devising the circuit constituting the bias circuit, the modulation of the DC bias due to the difference frequency component flowing in the bias circuit is prevented, and the transistor output is reduced. The first object is to suppress the generation of intermodulation components. The present invention further provides a signal line for transmitting a signal input to the transistor or a signal output from the transistor by using a circuit for preventing modulation of the DC bias due to the difference frequency component, and a DC bias to the transistor. It is a second object of the present invention to be able to suitably isolate the power supply line for applying the voltage on the same circuit board plane.
[0010]
[Means for Solving the Problems]
In order to achieve these objects, the present invention provides (1) a plurality of transistors connected in parallel to each other and arranged on a circuit board, and a signal including a component of frequency f1 and a component of frequency f2 = f1 + Δf. A distribution side circuit unit for supplying to the input side terminal of the transistor; and a DC cut capacitor connected between the input side terminal of each transistor and the distribution side circuit unit so as not to apply a DC bias to the distribution side circuit unit. (2) In a bias circuit that applies the voltage or current as the DC bias to the input side terminal of each transistor, (3) is connected between the input side terminals of adjacent transistors, and the DC bias is A notch filter that passes and blocks the signal of frequency Δf, and (4) is arranged at one end on the circuit board. Possess a side feed circuit to the input side terminal of the are transistors for applying the DC bias, and the notch filter is obtained by combining the two LC series resonant circuits of the one end ground to resonate at the frequency Δf wherein the T-type LC resonance filter der Rukoto.
[0011]
Alternatively, (1) a signal including a plurality of transistors connected in parallel to each other and arranged on the circuit board and a component of frequency f1 and a component of frequency f2 = f1 + Δf is supplied to the input side terminals of the transistors. The distribution side circuit unit, the synthesis side circuit unit that synthesizes and outputs the signals output from the output side terminals of each transistor, and the output side terminal of each transistor so that no DC bias is applied to the synthesis side circuit unit. (2) In a bias circuit for applying the voltage or current as the DC bias to the output side terminal of each transistor (3), a DC cut capacitor connected to the side circuit unit. ) It is connected between the output side terminals of adjacent transistors, passes the DC bias, and has a signal of frequency Δf. A notch filter for blocking the item, (4) possess a side feed circuit to the output side terminal of the transistor disposed at one end on the circuit board by applying the DC bias, and the notch filter, wherein the T-type LC resonance filter der Rukoto obtained by combining two of the LC series resonant circuit at one end ground to resonate at the frequency Delta] f.
[0012]
As described above, in the present invention, a DC bias supply application to a transistor (bipolar transistor, FET, etc.) is performed by a single-side power supply circuit for a transistor provided at one end on a circuit board and a notch connecting adjacent transistors. This is done by filtering and feeding with a filter. Since the notch filter blocks the difference frequency component, that is, the component of the frequency Δf, the DC bias is not modulated by the difference frequency component. As a result, the generation of intermodulation components in the transistor output, that is, the components of the frequencies f1−Δf and f2 + Δf is prevented. Moreover, since adjacent transistors are connected using a notch filter for preventing intermodulation, measures such as a three-dimensional intersection between a signal line and a power supply line are not necessary. Thus, according to the present invention, not only can the generation of intermodulation components be prevented and the signal quality related to the transistor output can be improved, but also the degree of freedom in circuit board design can be expanded, thereby reducing the design time and eliminating the wiring outside the pattern. This makes it possible to achieve downsizing and lower prices. Since there is no need for wiring outside the pattern on the circuit board, all the components can be mounted on the circuit board automatically by a chip mounter or the like. The notch filter can be easily realized by synthesizing a T-type LC resonance filter from two LC series resonance circuits grounded at one end and resonating at a frequency Δf.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. For the sake of simplification of explanation, the following description will be given by taking as an example the case where the push-pull amplifier circuit shown in FIG. 1 is improved according to the present invention, and parts overlapping with the circuit shown in FIG. The description will be omitted.
[0014]
FIG. 3 shows a gate bias circuit in the present embodiment. As shown in FIG. 3A, the gate bias circuit in the present embodiment includes an LPF type LC circuit composed of an inductor L2 and a capacitor C3, a one-side power feeding circuit composed of a gate resistor R1, and FETs Q1 and Q2. It has a notch filter composed of two inductors (L in the figure) connected between the gates and a capacitor (2C in the figure) grounded at one end connected to the connection point of these inductors. The notch filter is a T-type LC filter obtained by combining two series resonant circuits that resonate in series at the difference frequency Δf as shown in FIG. 3B. That is,
[Expression 1]
Δf = 1 / {2π (LC) ^1/2 }
Thus, the inductance L of the inductor in the series arm connecting the balanced lines and the capacitance 2C of the one-end grounded capacitor in the parallel arm are respectively selected and set.
[0015]
The notch filter shown in FIG. 3 is constituted by the inductor and the capacitor set to such an inductance and capacitance, and the notch filter shown in FIG. 3 is connected between the input side terminals or gates of the adjacent FETs Q1 and Q2, thereby providing a gate bias circuit. The component of the difference frequency Δf that has flowed into is removed. For this reason, the difference frequency voltage is not generated in the elements in the gate bias circuit, and hence the DC bias is not modulated. Accordingly, the intermodulation component of the frequency f1 and frequency f2 components in the input signal via the distribution side circuit unit balun B1 and the difference frequency component appears in the amplified output from the output side terminals or drains of the FETs Q1 and Q2. As a result, it can be prevented from appearing in the output from the balun B2 which is the synthesis side circuit unit (at least it can be suppressed to a level that can be substantially ignored). Further, the loss due to the provision of the notch filter remains negligible in the vicinity of the frequencies f1 and f2 that are significantly higher than the difference frequency Δf. In addition, measures such as the three-dimensional intersection required at the location A in FIG. 1 are no longer necessary, and the abolition (or reduction) of the wiring outside the pattern and the improvement of the degree of freedom in designing the circuit board can be achieved. it can proceed and thus reduce the manufacturing cost, shorter design time required, automated due chip mounter mounting of.
[0016]
The same circuit modification can be applied to the drain bias circuits of the FETs Q1 and Q2. That is, a circuit configuration as shown in FIG. However, since there is no resistance corresponding to the gate resistance R1 on the drain side, as shown in FIG. 4A, a simple circuit in which the drains of adjacent FETs Q1 and Q2 are connected by an inductor L ′ may be used. .
[0017]
The present invention is not only a push-pull amplifier circuit but also a parallel operation in which a signal is distributed in-phase to two or more transistors by a distribution side circuit unit and the outputs of those transistors are combined in phase by a combination side circuit unit. Variations can be applied to the bias of a type amplifier circuit or the like. The present invention can be applied to a bias of an amplifier circuit using a bipolar transistor as well as an FET. Those skilled in the technical field to which the present invention pertains will find it easy to replace the above description when applying these modifications. Although focused-simplified frequency components f1, f2 for simplifying the description, can be applied to a circuit for simultaneously amplifying a number of frequency components higher than (carrier) having a frequency interval Delta] f, the same effect is obtained It is done .
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an example configuration of a high-frequency push-pull amplifier circuit.
FIG. 2 is a frequency distribution diagram showing a problem of intermodulation distortion in the prior art.
FIGS. 3A and 3B are circuit diagrams showing a configuration of a gate bias circuit according to an embodiment of the present invention, in particular, FIG. 3A is a diagram showing a circuit configuration, and FIG. 3B is a diagram showing a synthesis principle of a notch filter.
4A and 4B are diagrams illustrating a configuration of a drain bias circuit according to an embodiment of the present invention, in particular, FIG. 4A is a simplified circuit, and FIG. 4B is a diagram illustrating a circuit having a notch filter.
[Explanation of symbols]
B1, B2 balun, C, C11, C12, C21, C22, C3, C4 capacitor, L, L ′, L1, L2 inductor, Q1, Q2 transistor, R1 gate resistance, Δf difference frequency.

Claims (2)

A plurality of transistors connected in parallel to each other and arranged on the circuit board; a distribution side circuit unit that supplies a signal including a component of frequency f1 and a component of frequency f2 = f1 + Δf to an input side terminal of each transistor; Used in a circuit comprising a DC cut capacitor connected between the input side terminal of each transistor and a distribution side circuit unit so that a DC bias is not applied to the circuit unit;
In the bias circuit for applying the voltage or current as the DC bias to the input side terminal of each transistor,
A notch filter connected between the input side terminals of adjacent transistors and passing the DC bias and blocking a signal of frequency Δf;
A one-sided power feeding circuit for applying the DC bias to the input side terminal of a transistor disposed at one end on the circuit board;
Have a,
The notch filter, a bias circuit, wherein the T-type LC resonance filter der Rukoto obtained by combining two of the LC series resonant circuit at one end ground to resonate at the frequency Delta] f. A plurality of transistors connected in parallel with each other and arranged on the circuit board; a distribution-side circuit unit that supplies a signal including a component of frequency f1 and a component of frequency f2 = f1 + Δf to the input-side terminal of each transistor; Are connected between the output terminal of each transistor and the combining circuit unit so that no DC bias is applied to the combining circuit unit. Used in a circuit comprising a DC cut capacitor,
In the bias circuit that applies the voltage or current as the DC bias to the output terminal of each transistor,
A notch filter connected between the output side terminals of adjacent transistors, passing the DC bias and blocking a signal of frequency Δf;
A single-side power feeding circuit that applies the DC bias to the output-side terminal of the transistor disposed at one end on the circuit board;
Have a,
The notch filter, a bias circuit, wherein the T-type LC resonance filter der Rukoto obtained by combining two of the LC series resonant circuit at one end ground to resonate at the frequency Delta] f.

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