JP3622102B2 - CR oscillation circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a CR oscillation circuit.
[0002]
[Prior art]
The conventional CR oscillation circuit has a configuration as shown in FIG. Reference numeral 51 is a reference power supply, and resistors r1, r2, and r3 are connected in series between the power supply terminals VDD and VSS, and the first reference potential V1 is connected from the connection point of the resistors r1, r2 from the connection point of the resistors r2, r3. A second reference potential V2 (here, V2>V1> 0) is obtained. A CR time constant circuit 52 includes a resistor r4 and a capacitor c1 connected in series between the output of the buffer circuit 53 and the power supply terminal VSS. The capacitor c1 is charged / discharged according to the output level of the buffer circuit 53. To do. A connection point between the capacitor c1 and the resistor r4 is used as an output terminal Out1. Reference numerals 54 and 55 denote first and second OP (Operational) amplifier circuits. The first OP amplifier circuit 54 receives the reference potential V1 at the − input terminal, and the + input terminal is connected to the output terminal Out1 of the CR time constant circuit. Receive potential. The second OP amplifier circuit 55 receives the reference potential V2 at the + input terminal and the potential of the output terminal Out1 at the − input terminal. F1 and f2 are cascade-connected flip-flop circuits. The output of the second OP amplifier circuit 55 and the first OP amplifier circuit 54 are respectively connected to the set input terminal S bar and the reset terminal R bar of the flip-flop circuit f1. The output terminal Q ′ bar of the flip-flop circuit f 2 is connected to the inverter 56. The output of the inverter 56 becomes the input of the buffer circuit 53, and the buffer circuit 53 thereby generates an oscillation output. At present, in the CR oscillation circuit as described above, it is common to integrate other than the resistor r4 and the capacitor c1 and externally attach the resistor r4 and the capacitor c1.
[0003]
The oscillation operation of this CR oscillation circuit is as follows. For example, if the CR time constant circuit 52 is in the discharging operation at the timing t1 in FIG. 6A, the outputs of the first OP amplifier circuit 54 and the second OP amplifier circuit 55 are both “H”. As a result, the flip-flop circuits f1 and f2 maintain their output states. When discharge progresses and the potential of the output terminal Out1 becomes lower than the reference potential V1 at timing t2, the first OP amplifier circuit 54 inverts the output to “L”. As a result, the output terminals Q and Q bar of the flip-flop circuit f1 become “L” and “H”, respectively, and the output terminals Q′Q ′ bar of the flip-flop circuit f2 become “H” and “L”, respectively. Become. As a result, the inverter 56 sets the output to “H”, the output of the buffer circuit 53 to “H”, and the CR time constant circuit 52 stops the discharging operation and starts the charging operation. Thereafter, the potential of the output terminal Out1 becomes higher than the reference potential V1 due to charging, and the output of the first OP amplifier circuit 54 returns to “H”, but the flip-flop circuits f1 and f2 maintain their output states and are charged. Operation continues. Further, when the potential of the output terminal Out1 becomes higher than the reference potential V2 at the timing of charging t3, the second OP amplifier circuit 55 inverts the output to “L”. As a result, the output terminals Q and Q bar of the flip-flop circuit f1 become “H” and “L”, respectively, and the output terminals Q′Q ′ bar of the flip-flop circuit f2 become “L” and “H”, respectively. Become. As a result, the CR time constant circuit 52 stops the charging operation and starts the discharging operation. Immediately after this, the potential of the output terminal Out1 becomes lower than the reference potential V2 by charging, and the output of the second OP amplifier circuit 55 returns to “H”, but the flip-flop circuits f1 and f2 hold their output states and discharge Operation continues. By repeating such a series of operations, an oscillation output as indicated by Out 2 in FIG. 6A is obtained from the output terminal Out 2 of the buffer circuit 53.
[0004]
[Problems to be solved by the invention]
Although the operation of the CR oscillation circuit shown in FIG. 5 is ideally as described above, in reality, the first OP amplifier circuit 54 and the second OP amplifier circuit 55 have input offset characteristics, and each of them is simply shown in FIG. As shown in (a), the potential of the output terminal Out1 is not compared with the reference potentials V1 and V2. That is, due to the offset characteristics of the OP amplifier circuit, the input potential on the −input terminal side is lowered by, for example, the offset voltage Vo with respect to the + input terminal (here, it is assumed to be lowered, but may be raised conversely). Therefore, when the potential of the output terminal Out1 is input to the input terminal having the opposite polarity, the + input terminal, and the −input terminal in the first OP amplifier circuit 54 and the second OP amplifier circuit 55, respectively, FIG. As shown, the potential of the output terminal Out1 is compared with the potential V1 ′ that is lower than the reference potential V1 by the offset voltage Vo in the first OP amplifier circuit 54, and conversely from the reference potential V2 in the second OP amplifier circuit 55. This is compared with the potential V2 ′ that is higher by the offset voltage Vo. For this reason, even if the first reference potential V1 which is a predetermined discharge potential and the second reference potential V2 which is a predetermined charge potential are further discharged or charged, a determination output is not generated, and the discharge is completed and charged. Both completion outputs will be delayed. For this reason, Out2 showing the oscillation output waveform in FIG. 6B has a longer cycle (lower frequency) than the ideal waveform like Out2 in FIG. 6A. Thus, the offset voltage that affects the oscillation frequency of the CR oscillation circuit is difficult to control during integration, and is one of the factors that make it difficult to set the frequency of the CR oscillation circuit.
[0005]
[Means for Solving the Problems]
Therefore, in the present invention, a reference potential circuit for selectively outputting the first and second reference potentials used for comparison according to the potential level of the control signal for controlling the charging / discharging operation with the CR time constant is provided. One comparator circuit is used to determine the level of the potential corresponding to the charge of the circuit, and the potential corresponding to the charge of the CR time constant circuit is input to one input and selectively output to the other input. A control circuit is provided for inputting the first and second reference potentials, comparing them, and generating the control signal having two states having different potential levels based on the determination output. Thus, the vectors of the potentials that are actually used as the reference in the comparison operation shifted from the first and second reference potentials by the offset voltage are made the same, and the potentials at the completion of predetermined charging and discharging are the same vector. A CR oscillation circuit is provided which can be determined with a deviation of the input frequency to reduce the influence of the input offset voltage on the oscillation frequency to facilitate the setting of the frequency of the CR oscillation circuit.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
A reference potential circuit for selectively outputting first and second reference potentials having different potential levels according to the state of the potential level of the control signal; a resistance element; and a capacitive element. A CR time constant circuit that charges and discharges the capacitive element via the resistor and outputs a signal having a potential level corresponding to the charged charge according to a state;
A comparison circuit that generates a determination output by comparing the potential levels of the output from the CR time constant circuit and the output from the reference potential circuit, and two states having different potential levels based on the determination output of the comparison circuit. It is preferable to constitute a CR oscillation circuit including a control circuit that generates the control signal.
[0007]
The control circuit inverts and holds the state of the control signal every time the determination output of the comparison circuit is inverted, and switches the first and second reference potentials by the reference potential circuit. It is also preferable to have a prohibition circuit for prohibiting the state inversion operation of the control signal for a specified time from the start.
[0008]
The control circuit includes a flip-flop circuit that inverts and holds the control signal, a delay circuit that delays an output from the flip-flop circuit by the specific time, an output of the delay circuit, and a determination output from the comparison circuit It is also preferable to have the prohibition circuit comprising a logic circuit that prohibits the inversion holding operation of the flip-flop circuit based on the above.
[0009]
【Example】
Next, a CR oscillation circuit according to an embodiment of the present invention will be described. First, the configuration of this example will be described with reference to FIG. In the figure, the same reference numerals as those in FIG. 5 are the same as those in FIG.
[0010]
In the figure, reference numeral 1 denotes a reference potential circuit, resistors r1, r2 and r3 connected in series between power supply terminals VSS and VDD, one terminal being a connection point between resistors r1 and r2, resistors r2 and r3, respectively. The first and second transmission gates tr1 and tr2 are connected to a connection point between the first and second transmission gates, and the other end is connected to a common output terminal Out0. The first and second transmission gates tr1 and tr2 pass the first reference potentials V1 and V2, respectively, and the first reference potentials V1 and V2 are output from the output terminal Out0 according to a control signal described later. Output selectively.
[0011]
Reference numeral 2 denotes a CR time constant circuit, which includes a resistor r4 and a capacitor c1. The time constant circuit 2 is controlled in charge / discharge operation by a control signal to be described later, and a potential corresponding to the charge is output from the output terminal Out1.
[0012]
Reference numeral 3 denotes an OP amplifier circuit. The potential of the output terminal Out1 of the CR time constant circuit 2 is applied to the + input, and the first or second reference potential from the output terminal Out0 is applied to the − input. Specifically, every time the potential of the output terminal Out1 exceeds the potential of the output terminal Out0, the output is set to “H”, that is, a determination output is generated. However, generally, the OP amplifier circuit 3 has an offset voltage. Here, the OP amplifier circuit 3 has an input characteristic that lowers the input potential on the −input terminal side by, for example, the offset voltage Vo with reference to the + input terminal. In fact, it is assumed that the judgment output “H” is generated every time the potential of the output terminal Out1 exceeds the potential lower than the potential of the output terminal Out0 by the offset voltage Vo.
[0013]
A control circuit 4 includes inverter circuits i1 to i4, a flip-flop circuit f1, a delay circuit d1, a NAND gate na1, and a NOR gate no1. The flip-flop circuit f1 generates a control signal from the output terminal Q bar and inverts and holds it. This control signal is output from the terminal N1 bar and applied to the gates of the N-channel MOS transistor and the P-channel MOS transistor at transmission gates tr1 and tr2, respectively. The control signal is inverted by the inverter i1, is output from the output terminal N1, and is applied to the gates of the P-channel MOS transistor and the N-channel MOS transistor at the transmission gates tr1 and tr2, respectively. That is, the transmission gates tr1 and tr2 are alternately opened and closed by the control signal, and the first and second reference potentials V1 and V2 are switched. The delay circuit d1 receives the control signal via the inverters i1 and i2, and delays the control signal by a specific time T0. The determination output from the OP amplifier circuit 3 is input to one input terminal of the NAND gate na1 and the NOR gate no1 via the inverter circuit i3, and the delay output from the delay circuit d1 is input to the other terminal. The NAND gate na1 and the NOR gate no1 are for setting and resetting the flip-flop circuit f1, respectively. The signal is input to the reset terminal R bar of the flip-flop circuit f1 through the inverter i4. The delay circuit d1, the NAND gate na1, the NOR gate no1, and the inverters i3 and i4 prohibit the state inversion operation of the control signal from being switched for a specific time from the switching of the first and second reference potentials V1 and V2. A circuit 40 is configured.
[0014]
A buffer circuit 5 receives the control signal via the inverters i1, i2, and i5 and outputs “H” and “L”. A resistor r4 and a capacitor c1 constituting the CR time constant circuit 2 are connected in series between the output terminal of the buffer circuit 5 and the power supply terminal VSS, and the capacitor c1 is charged and discharged according to the output level of the buffer circuit 5. .
[0015]
In this example, the above-described components other than the CR time constant circuit 2 are integrated on one chip, and a resistor r4 and a capacitor c1 are externally attached to this chip to constitute the CR time constant circuit 2.
[0016]
Next, the operation of this example will be described with reference to the waveform diagrams showing the waveforms of the respective terminals in FIG. 1 shown in FIGS.
[0017]
In FIG. 2, the waveform of the output terminal Out1 of the CR oscillation circuit 2 and the control signal through the inverter i1 that is the oscillation output, that is, the oscillation output N1 are shown for one period. FIG. 3 is a diagram for explaining in detail the waveform of each terminal at the timings T1 to T2 and T3 to T4 in FIG. 2, and the time axis is particularly enlarged compared to FIG.
[0018]
First, the operation at the timings T1 to T2 in FIG. 2, that is, the charging of the capacitor c1 proceeds in the CR time constant circuit 2, and the output terminal Out1 exceeds the potential V2 ′ that is lower than the second reference potential V2 by the offset potential Vo. The operation before and after will be described. At this time, the output of the output terminal Q bar of the flip-flop circuit f1, that is, the control signal is held at “L”, and the output of the buffer circuit 5 is set to “H” to charge the capacitor c1.
[0019]
At timing T1, the output terminal N2 of the OP amplifier circuit 3 is “L”, the output terminal N3 of the inverter i3 is “H”, and the output terminal N4 of the delay circuit d1 is “L”. The NAND gate na1 and the NOR gate no1 both receive the output of the output terminal N3 as one input and the output of the output terminal N4 as the other input, and here output “H” and “L”, respectively. Yes. Further, the output “L” of the NOR gate no1 is inverted to “H” via the inverter i4. Thus, both the set terminal S bar and the reset terminal R bar of the flip-flop circuit f1 are “H”, and the flip-flop circuit f1 holds the control signal of the output terminal Q bar at “L”. .
[0020]
When the charging of the capacitor c1 proceeds at timing T11 and the output terminal Out1 exceeds the potential V2 ′, the output of the output terminal N2 of the OP amplifier circuit 3 is “H” and the output of the output terminal N3 of the inverter i3 is “L”. Become. The NAND gate na1 makes the other input invalid by the output “L” of the output terminal N4 of the delay circuit d1 inputted to one side, and the output “H” even if the output from the output terminal N3 becomes “L”. As a result, the set terminal S bar is held at “H”. The NOR gate no1 sets the output to “H” when the output from the output terminal N3 becomes “L”. As a result, the reset terminal R bar 1 becomes “L”, the flip-flop circuit f1 inverts the output, and the output terminal Q bar becomes “H”. As a result, the output from the output terminal N1 of the inverter i1 becomes “L”, the second transmission gate tr2 is turned off, the first transmission gate tr1 is turned on, and the output from the output terminal Out0 becomes the second reference potential V2. To the first reference potential V1. At the time of this switching, switching noise is added to the output of the output terminal Out0. In FIG. 3, for the sake of convenience, such noise is shown as n1 at timing T12 delayed from timing T11. Further, the control signal “H” from the output terminal Q bar sets the output of the buffer circuit 5 to “L” via the inverters i1, i2, and i5, thereby starting the discharge of the capacitor c1.
[0021]
At timing T12, due to the influence of the noise n1, the output N2 of the OP amplifier circuit 3 and the output N3 of the inverter i3 rapidly repeat “H” and “L”. However, in the NAND gate na1 that sets the flip-flop circuit f1, the output N4 of the delay circuit d1, which is the other input, has a delay of a specific time T0 with respect to the control signal Q bar. The control signal Q bar is held at “L” for a specific time T0 after “H”, that is, the output N4 is held at “L”. During this time, the input of the output N3 from the inverter i3 is held. It is invalidated. Further, the output of the NOR gate or1 repeats “H” and “L”, but since the flip-flop circuit f1 is designated to be reset and retained, the output from the output terminal Q bar is “H”. Retained. In this manner, the control signal is prohibited from being inverted with respect to the inversion of the output N2 of the OP amplifier circuit 3 due to noise at the time of switching the reference potential, and parasitic oscillation due to noise is prevented.
[0022]
Further, at timing T13, the specific time T0 has elapsed since the switching of the reference potential, and the output N4 of the delay circuit d1 also becomes “H”. Thereby, in the NAND gate na1, the input of the output N3 of the inverter i3 becomes valid. This timing is a timing set so that the occurrence of noise due to the switching of the reference potential is already eliminated, and the output terminal Out0 stably outputs the first reference potential V1, and the OP amplifier circuit The output N2 of No. 3 is stably “H”. Therefore, even if the input of the output N3 of the inverter i3 is enabled in the NAND gate na1, there is no risk of being affected by noise. On the other hand, in the NOR gate no1, the input of the output N3 of the inverter i3 becomes invalid, and the output is held at “L”, thereby resetting the flip-flop circuit f1 regardless of the output N2 of the OP amplifier circuit 3. The terminal R bar is held at “H”.
[0023]
Next, the operation at the timings T3 to T4 in FIG. 2, that is, the operation before and after the timing when the discharge of c1 progresses and the output terminal Out1 exceeds the potential V1 ′ that is lower than the first reference potential V1 by the offset potential Vo will be described.
[0024]
The discharge of the capacitor c1 proceeds from the state of the timing T3 in the discharge operation state similar to the timing T13, and at the timing T31, the potential of the output terminal Out1 exceeds the potential V1 ′ that is lower than the first reference potential V1 by the offset potential Vo. When low, the output N2 of the OP amplifier circuit 3 becomes "L". As a result, the potential of the output of the NAND gate na1 becomes “L”, that is, the potential of the set terminal S bar of the flip-flop circuit f1 becomes “L”, the flip-flop circuit f1 is set, and the output terminal Q bar becomes “L”. It becomes. As a result, the first transmission gate tr1 is turned off, the second transmission gate tr2 is turned on, and the reference potential is switched from the first reference potential V1 to the second reference potential V2. Even at the time of this switching, switching noise is applied to the output terminal Out0. Here, this is indicated by n2 at timing T32. Further, charging of the capacitor c1 is started by the control signal “L” from the output terminal Q bar.
[0025]
Due to the influence of the noise n2 at the timing T32, the output N2 of the OP amplifier circuit 3 and the output N3 of the inverter i3 abruptly repeat “H” and “L”. However, the NOR gate no1 that resets the flip-flop circuit f1 disables the input of the output N3 of the inverter i3 by the output “H” of the output terminal N4 of the delay circuit d1 until a specific time elapses after the reference potential is switched. Has been. Thereby, inversion of the control signal is prohibited. Thereafter, at the timing T33 when the specific time T0 expires from the switching of the reference potential, the output from the output terminal N4 becomes “L”, and the NOR gate no1 that resets the flip-flop circuit f1 receives the input of the output N3 of the inverter i3. Valid. At subsequent timing T4, the charging operation state is the same as that at timing T1.
[0026]
By repeating the above operation, a waveform as indicated by Out1 in FIG. 2 is obtained from the output terminal Out1, and a waveform as indicated by N1 in the same figure is obtained from the output terminal N1. In this example, a potential corresponding to the charged charge from the output terminal Out1 of the CR time constant circuit 2 is input to one input terminal of one OP amplifier circuit 3, and the other terminal is used for comparison with this. The first reference potential V1 and the second reference potential V2 are selectively input. As a result, the potentials V1 ′ and V2 ′ that are actually compared with the output terminal Out1 are both shifted to the lower potential side by the offset voltage Vo from the first and second reference potentials V1 and V2. As a result, the potential at the completion of predetermined charging and discharging can be determined with the same vector deviation, and the influence of the input offset voltage on the oscillation frequency can be reduced. Thus, it is possible to provide a CR oscillation circuit that facilitates the frequency setting of the CR oscillation circuit, and in turn enables highly accurate frequency setting. Further, only one OP amplifier circuit is required, and the scale can be reduced and simplified.
[0027]
Further, since the control signal is prohibited from being inverted in accordance with the determination output of the OP amplifier circuit 3 until the specific time has elapsed from the switching of the reference potential, stable oscillation without being affected by the noise due to the switching of the reference potential. Operation is possible.
[0028]
In order to suppress the influence of such noise, it is possible to configure as shown in FIG. 4 without using the control circuit 4. In the figure, the output of the output terminal N3 of the inverter i3 is replaced with the output of the terminal N1 in FIG. 1, the output of the output terminal N2 of the OP amplifier circuit 3 is replaced with the output of the terminal N1 bar, and the inverter i3 is used. Is output to the inverter i5 via the inverter i6. The CR time constant circuit 6 is connected to the output terminal Out0 to absorb noise. However, in this case, in order to effectively absorb noise, it is necessary to appropriately set the sizes of the resistor r5 and the capacitor c2 of the CR time constant circuit.
[0029]
【The invention's effect】
According to the present invention, since one reference circuit is used by switching its reference potential, the influence of the input offset voltage of the comparison circuit on the oscillation frequency can be reduced, and the frequency setting of the CR oscillation circuit is easy. And As a result, it is possible to provide a CR oscillation circuit capable of setting a frequency with high accuracy.
[0030]
Further, by providing the prohibition circuit, it is possible to prevent parasitic oscillation accompanying switching of the reference potential. For this reason, a CR oscillation circuit capable of stable oscillation operation can be provided.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram for explaining a configuration of a CR oscillation circuit according to an embodiment of the present invention.
FIG. 2 is a waveform diagram for explaining the operation of FIG. 1;
FIG. 3 is a waveform diagram for explaining the operation of FIG. 1;
FIG. 4 is an explanatory diagram for explaining another example of the present invention.
FIG. 5 is an explanatory diagram showing a configuration of a conventional CR oscillation circuit.
6 is a waveform diagram for explaining the operation of FIG. 5;
[Explanation of symbols]
1 Reference potential circuit 2 CR time constant circuit 3 OP amplifier circuit (comparison circuit)
4 Control circuit 40 Forbidden circuit

Claims (3)

A reference potential circuit that selectively outputs first and second reference potentials having different potential levels according to the state of the potential level of the control signal;
A resistive element and a capacitive element connected to one end of the resistive element, and charging and discharging the capacitive element via the resistive element according to the state of the potential level of the control signal, and depending on the charged charge A CR time constant circuit for outputting a potential level signal;
A comparison circuit for comparing the potential levels of the output from the CR time constant circuit and the output from the reference potential circuit to generate a determination output;
And a control circuit for generating the control signal having two states having different potential levels based on the determination output of the comparison circuit and supplying the control signal to the reference potential circuit. A CR oscillation circuit output to the other end of the resistance element via a circuit. Each time the determination output of the comparison circuit is inverted, the control circuit inverts and holds the state of the control signal and switches the first and second reference potentials by the reference potential circuit. 2. The CR oscillation circuit according to claim 1, further comprising a prohibition circuit for prohibiting the state inversion operation of the control signal for a period of time. The control circuit includes a flip-flop circuit that inverts and holds the control signal, a delay circuit that delays an output from the flip-flop circuit by the specific time, an output of the delay circuit, and a determination output from the comparison circuit. 3. The CR oscillation circuit according to claim 2, further comprising: a prohibiting circuit including a logic circuit that prohibits the inversion holding operation of the flip-flop circuit.

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