KR100348301B1 - Power-on reset circuit - Google Patents

Abstract

The present invention relates to a power-on reset circuit suitable for generating a long time reset pulse, comprising: a delay charge-up circuit unit which charges up and outputs Vdd at power-on; a Vdd value output from the delay charge-up circuit; The input inverters PMOS 5 and NMOS 1 are configured between the node 4 (n4) and the ground terminal, and the third and fourth PMOS transistors (PMOS 3) are connected in series between the node 4 (n4) and the power supply voltage terminal. 6th PMOS transistor (PMOS 6) configured between (PMOS 4) and node 4 (n4) and the power supply voltage terminal, and a reset signal is inputted to the gate, so that node 4 (n4) rises according to the input Vdd value. A high threshold inversion circuit unit configured to lengthen an inversion time of the inverter; a second NMOS transistor NMOS 2 to which an output signal of the delay charge up circuit is input to a gate, and an inverter output terminal node 5 (n5) of the high threshold inversion circuit unit ) Signal of gay And a voltage level shifter unit configured to include a third NMOS transistor (NMOS 3) inputted to and shift the voltage level so that the reset signal is switched to the Vdd level by turning off the third NMOS transistor (NMOS 3). do.

Description

Power-on reset circuit

TECHNICAL FIELD The present invention relates to a power on reset circuit, and more particularly, to a power on reset circuit adapted to generate a long time reset pulse.

The system must be reset to the initial state when the power supply voltage is applied and the power supply voltage drops below the half supply voltage (Vd / 2) at the supply voltage (Vdd) level to ensure the stability of the system. Can be.

When the power supply voltage is applied, the initial state should always be set constant, because if the power supply voltage drops suddenly and falls below the Vc / 2 level, it is very likely that all the register values of the internal circuits of the system will be erased. .

For this reason, in order to prevent abnormal operation of the system, a power-on reset circuit is essentially adopted in the integrated circuit, which automatically resets the system to its initial state.

Hereinafter, a power on reset circuit of the related art will be described with reference to the accompanying drawings.

1 is a configuration diagram of a power-on reset circuit of the prior art, and FIG. 2 is an operation timing diagram of the power-on reset circuit of the prior art.

PMOS transistor 1 that is turned on at power-on and pulls up Vdd to output V1, and is configured between the drain (V1 output terminal) and ground terminal of the PMOS transistor 1 to be charged up to Vdd and reset at power-on. A capacitor 2 for determining time, a first inverter 3 for inverting the V1 value, and a second inverter 4 for inverting the output signal of the first inverter 3 again and outputting a reset pulse. .

Here, the first and second inverters 3 and 4 are adopted for shaping pulses.

Although the gate of the PMOS transistor 1 is connected to the ground terminal and is always in the on state, only when the power is turned on, as shown in FIG. 2A, a pull-up operation is performed to output V1 having a predetermined level as shown in FIG.

Since the power-on reset circuit of the related art has a delay time Δ as shown in FIG. 2C and a reset time is determined according to the RC time constant of the pull-up resistor of the PMOS transistor 1 and the capacitance value of the capacitor 2, the reset time is determined. To get a long time reset pulse, both values must be made large.

Such a power-on reset circuit of the prior art requires a large pull-up resistor (R) and capacitance (C) to obtain a long time reset pulse, so that the area is inevitably enlarged.

This causes difficulty in making the circuit on chip.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem of the conventional power-on reset circuit, and an object thereof is to provide a power-on reset circuit suitable for generating a long time reset pulse.

1 is a block diagram of a power-on reset circuit of the prior art

2 is an operation timing diagram of a conventional power-on reset circuit.

3 is a configuration diagram of a power-on reset circuit according to the present invention;

4 is a graph showing the reset pulse characteristics of the power-on reset circuit according to the present invention

Explanation of symbols for the main parts of the drawings

31. Delay charge-up circuit 32. High threshold switching circuit

33. Voltage level shifter

According to an embodiment of the present invention, a power-on reset circuit includes a delay charge-up circuit unit which charges up and outputs Vdd at power-on; an inverter (PMOS 5, NMOS) to which the Vdd value output from the delay charge-up circuit is input. 1) is configured between node 4 (n4) and the ground terminal, and the third and fourth PMOS transistors (PMOS 3) (PMOS 4) and node 4 (which are configured in series connection between the node 4 (n4) and the power supply voltage terminal. a sixth PMOS transistor (PMOS 6) configured between n4) and a power supply voltage terminal and having a reset signal input to the gate, and configured to cause node 4 (n4) to rise according to the input Vdd value to increase the inversion time of the inverter. A high threshold inverting circuit unit configured to lengthen; a second NMOS transistor (NMOS 2) in which the output signal of the delay charge-up circuit is input to the gate, and a signal in which the signal of the inverter output terminal node 5 (n5) of the high threshold inverting circuit unit is input to the gate 3 NMOS tracks Register is included and configured (NMOS 3) is characterized in that comprises a voltage level shifter for the first 3 NMOS transistor (NMOS 3) a reset signal by a is off to shift the voltage level to be converted to the Vdd level.

Hereinafter, a power-on reset circuit according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a configuration diagram of a power-on reset circuit according to the present invention, Figure 4 is a graph showing the reset pulse characteristics of the power-on reset circuit according to the present invention.

The power-on reset circuit according to the present invention does not determine the reset time by the RC time constant, but adopts a high threshold inversion circuit to allow a long reset time. First, a source is connected to a power supply voltage terminal and a gate A first PMOS transistor (PMOS 1) having a common drain connected to node 1 (n1), a second PMOS transistor having a source connected to node 1 (n1), and a gate and a drain connected to node 2 (n2); (PMOS 2) and a capacitor (C1) configured between the node 2 (n2) and the ground terminal to charge up to the Vdd value at power-on to determine the reset time to charge up and output Vdd at power-on The delay charge up circuit 31 is configured.

An inverter (PMOS 5, NMOS 1) to which the Vdd value outputted through the node 2 (n2) of the delay charge-up circuit 31 is input is configured between the node 4 (n4) and the ground terminal, and the node 4 ( a third and fourth PMOS transistor (PMOS 3) (PMOS 4) configured in series connection between n4) and the power supply voltage terminal and a sixth PMOS configured between the node 4 (n4) and the power supply voltage terminal and a reset signal is input to the gate The transistor PMOS 6 is configured so that the node 4 (n4) rises in accordance with the input Vdd value, thereby forming a high threshold inversion circuit section 32 which lengthens the inversion time of the inverter.

The second NMOS transistor NMOS 2, to which the output signal of the delay charge-up circuit 31 is input to the gate, and the inverter output terminal of the high threshold inversion circuit unit 32, that is, the signal of node 5 (n5), are connected to the gate. A latch unit (seventh PMOS, eighth PMOS transistor) for shifting the voltage level so that the reset signal is switched to the Vdd level by turning off the input third NMOS transistor NMOS 3 and the third NMOS transistor NMOS 3. A voltage level shifter section 33 composed of

The reset pulse generation operation of the power-on reset circuit according to the present invention having such a configuration is as follows.

Each node voltage at the initial power-off, i.e., V (n2), V (n5), V (reset) is 0V.

First, as shown in FIG. 4, as power-on and Vdd increases, the voltages of the nodes n4, n5, and n6, that is, the voltages of V (n4), V (n5), and V (n6) increase.

At this time, the sixth PMOS transistor PMOS 6 of the high threshold inversion circuit unit 32 plays a role of allowing V (n4) to immediately rise along the Vdd value.

As such, V (n4) immediately rises along the Vdd value, thereby increasing the logic threshold voltage of the inverter composed of the fifth PMOS transistor PMOS 5 and the first NMOS transistor NMOS 1.

As such, when the logic threshold voltage of the high threshold inversion circuit unit 32 becomes high, the inversion time of V (n5) by V (n2) becomes long.

When Vdd increases above 2Vth (Vth = turn-on voltage of PMOS Tr), the first and second PMOS transistors PMOS 1 and PMOS 2 of the delay charge-up circuit 31 are turned on so that the voltage of the node 2 (n2) is turned on. The level is taken up.

In this way, the voltage level of the node 2 (n2) is not charged up until Vdd becomes 2Vth, so the reset time can be longer.

When V (n2) is charged up to the same level as the logic threshold voltage level of the high threshold inversion circuit unit 32, the voltage level of the node 5 (n5) drops to 0V without rising along Vdd.

At this time, the second NMOS transistor NMOS 2 of the voltage level shifter 33 is turned on and the third NMOS transistor NMOS 3 is turned off.

As such, when the second NMOS transistor NMOS 2 of the voltage level shifter 33 is turned on, the voltage level of the node 6 (n6) is turned down, and the eighth PMOS transistor PMOS 8 is turned on.

On the contrary, when node 5 (n5) goes down to 0V, the third NMOS transistor NMOS 3 is turned off and the voltage level of V (reset) is switched to the Vdd level. The sixth and seventh PMOS transistors PMOS 6 and PMOS 7 are turned off.

Here, the node 4 (n4) is dropped by the paths of the third and fourth PMOS transistors (PMOS 3) (PMOS 4), not the sixth PMOS transistor (PMOS 6).

Such a power-on reset circuit according to the present invention adopts a high threshold inversion circuit portion having a high threshold voltage level without a reset time determined by the RC time constant, and thus has a long inversion time, thereby minimizing a circuit construction area. Can be.

This reduces the cost of system fabrication by enabling on-chip external reset circuits in systems that require long time reset times.

Claims (4)

A delay charge up circuit unit which charges up and outputs Vdd at power on; An inverter (PMOS 5, NMOS 1) to which the Vdd value output from the delay charge-up circuit is input is configured between node 4 (n4) and a ground terminal, and is configured in series between the node 4 (n4) and a power supply voltage terminal. And a sixth PMOS transistor PMOS 6 configured between the third and fourth PMOS transistors PMOS 3 (PMOS 4) and the node 4 (n4) and the power supply voltage terminal, and a reset signal is input to the gate. a high threshold inversion circuit unit for increasing the inversion time of the inverter by allowing n4) to rise according to the input Vdd value; The second NMOS transistor NMOS 2 having the output signal of the delay charge-up circuit input to the gate and the third NMOS transistor NMOS 3 having the signal of the inverter output terminal node 5 (n5) of the high threshold inverting circuit part input to the gate. And a voltage level shifter portion configured to shift the voltage level so that the reset signal is switched to the Vdd level by the third NMOS transistor (NMOS 3) being turned off. The delay charge-up circuit of claim 1, further comprising: a first PMOS transistor (PMOS 1) having a source connected to a power supply voltage terminal, a gate and a drain connected to a node 1 (n1) in common; A second PMOS transistor (PMOS 2) having a source connected to the node 1 (n1) and a gate and a drain connected to the node 2 (n2); And a capacitor (C1) configured between the node 2 (n2) and the ground terminal to charge up to a Vdd value at power-on to determine a reset time. 3. The logic threshold voltage of an inverter comprising the fifth PMOS transistor (PMOS 5) and the first NMOS transistor (NMOS 1) is increased by increasing V (n4) along the Vdd value. A power on reset circuit characterized by a long inversion time of V (n5) by V (n2). The voltage level of node 5 (n5) does not rise along Vdd but drops to 0V when V (n2) is charged up to the same level as the logic threshold voltage level of the high threshold inversion circuit portion. And a power-on reset circuit.