JP3602313B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having an element isolation region.
[0002]
[Prior art]
As one of element isolation methods in a semiconductor device, there is a technique called LOCOS (Local Oxidation of Silicon). In this technique, a predetermined portion of the surface of a silicon substrate is selectively thermally oxidized using a silicon nitride layer as an oxidation prevention mask, and an oxide layer formed thereby is used as an element isolation region. The oxide layer formed in the element isolation region is generally called a field oxide layer.
[0003]
However, element isolation by the LOCOS method has the following two problems.
One of them is called bird's beak. This is because when the silicon substrate is thermally oxidized by the LOCOS method, oxygen enters from the edge of the antioxidant mask and the oxidized layer on the surface of the silicon substrate bites under the antioxidant mask. Is called a bird's beak because it is shaped like a bird's beak.
[0004]
Since this bird's beak enlarges the field oxide layer, there is a problem in that the size of the element isolation region is increased.
The other is a phenomenon called a thinning effect, in which the field oxide layer becomes thinner as the width of the element isolation region becomes smaller. This is caused by reducing the amount of oxygen supplied through the opening when the size of the opening of the oxidation prevention mask for supplying oxygen to the element isolation region of the silicon substrate is reduced.
[0005]
These problems have been conventionally known, but when the size of the element is large, both bird's beak and thinning have not so much adverse effect.
However, when not only elements but also element isolation regions are miniaturized with miniaturization of semiconductor devices, these problems become apparent.
Since it is difficult to reduce the size of the bird's beak in accordance with the miniaturization of the element, the rate at which the bird's beak erodes the element formation region to reduce the size of the element formation region increases. Further, when the width of the element isolation region is 1 μm or less, a thinning effect is remarkably exhibited, and the thickness of the field oxide layer may be half or less than that of the element isolation region having a large width.
[0006]
When the field oxide layer becomes thinner as described above, the effect of introducing impurities introduced immediately below the field oxide layer in order to prevent the formation of the channel of the parasitic MOS transistor may be lost.
As an element isolation structure that does not cause such a problem, there is known an element isolation structure in which a trench is formed in a silicon substrate and an insulator or polycrystalline silicon is embedded therein. This method has been conventionally applied to a bipolar transistor LSI requiring deep element isolation, but since neither bird's beak nor thinning occurs, application to a MOS transistor LSI is also progressing.
[0007]
The MOS transistor LSI does not require the element isolation as deep as the bipolar transistor LSI. Therefore, a structure called STI (Shallow Trench Isolation) that performs element isolation with a relatively shallow groove having a depth of about 1 μm is used.
Next, an element isolation method using STI will be described.
First, as shown in FIG. 11A, after a first thermal oxide layer 102 is formed to a thickness of 10 nm on a silicon substrate 101, a silicon nitride layer 103 is formed thereon to a thickness of 150 nm by CVD. I do. Subsequently, the element isolation region S is determined by the window 105 of the resist mask 104.
[0008]
Thereafter, as shown in FIG. 11B, the silicon nitride layer 103 and the first thermal oxide layer 102 under the window 105 are etched to form an opening 103a, and the silicon substrate 101 under the window 105 A groove 106 having a depth of about 0.5 μm is formed by RIE (Reactive Ion Etching).
Next, as shown in FIG. 11C, after removing the resist mask 104, the inner wall of the groove 106 is thermally oxidized to form a second thermal oxide layer 107 having a thickness of 50 nm along the inner wall. . Then, a silicon oxide layer 108 is formed to a thickness of 1 μm by CVD, and the inside of the groove 106 is filled with the silicon oxide layer 108.
[0009]
After performing an appropriate heat treatment, as shown in FIG. 11D, the silicon oxide layer 108 on the silicon nitride layer 103 is removed by CMP (Chemical Mechanical Polishing) or RIE, and the silicon oxide layer 108 is grooved. 106 and only above it. In this case, the silicon nitride layer 103 functions as a CMP stopper layer.
[0010]
Thereafter, as shown in FIG. 12A, the silicon nitride layer 103 is removed using phosphoric acid. Next, the first thermal oxide layer 102 on the silicon substrate 101 is removed with hydrofluoric acid.
Next, after the surface of the silicon substrate 101 is thermally oxidized to form a third thermal oxide layer (not shown) on the entire surface, impurities are ion-implanted into a part of the silicon substrate 101, and the impurities are activated by heating. After the formation of a well (not shown) in the silicon substrate 101, the third thermal oxide layer is removed with hydrofluoric acid.
[0011]
Thereafter, as shown in FIG. 12B, the surface of the element forming region of the silicon substrate 101 is thermally oxidized to form a gate oxide layer 109, and then a gate electrode 110 is formed on the gate oxide layer 109. Then, an impurity diffusion layer 111 serving as a source and a drain is formed on the silicon substrate 101 on both sides of the gate electrode 110 (in a direction perpendicular to the paper surface).
[0012]
[Problems to be solved by the invention]
By the way, after the trench 106 is filled with the silicon oxide layer 108 and the silicon nitride layer 103 is removed, the hydrofluoric acid treatment as described above is performed a plurality of times, so that the silicon substrate of the silicon oxide layer 108 embedded in the trench 106 is removed. The portion protruding from 101 is isotropically etched by hydrofluoric acid. When isotropic etching occurs in the silicon oxide layer 108 as described above, a concave portion 121 as shown in FIG. 13A is formed in the silicon oxide layer 108 embedded in the groove 106.
[0013]
Since such a recess 121 is formed between the element forming region and the element isolation region S, the upper edge (shoulder) of the groove 106 is exposed from the recess 121. Therefore, when a voltage is applied to the gate electrode 110 formed across the element isolation region S, the electric field E concentrates on the shoulder at the edge of the groove 106 as shown in FIG.
This makes it easier for a leak current to flow through the silicon substrate 101 near the shoulder of the groove 106 even when the gate voltage is low. In other words, the state is the same as when a parasitic transistor having a low threshold is formed, and the MOS transistor has characteristics as shown in FIG.
[0014]
The measurement results of the transistor characteristics show that the n-type MOS transistor has transistor characteristics as shown in FIG. 15A and the p-type MOS transistor has transistor characteristics as shown in FIG. 16A. I have. When the changes in the characteristic curves of FIGS. 15 (a) and 16 (a) are obtained, the changes shown in FIGS. 15 (b) and 16 (b) appear, and the small peaks appearing there are the parasitic peaks shown in FIG. A change at a boundary between a transistor characteristic curve and a normal transistor characteristic curve is shown. The size of the gate electrode in FIGS. 15A and 16A is 1/10 gate length / gate width.
[0015]
The phenomenon that the threshold voltage is reduced by such a parasitic MOS transistor is called a hump.
In order to reduce the leakage current of the parasitic transistor, ion implantation is performed on the shoulder of the groove 106. Davari et al. , IEDM 1988 pp. 92-95. However, according to this method, the impurity spreads not only to the shoulder of the trench 106 but also to the periphery thereof, so that the element formation region is narrowed.
[0016]
As another method, it has been proposed that the shoulder portion of the groove 106 is thermally oxidized and rounded to reduce the electric field concentration at that portion. However, in order to round the shoulder of the groove 106, high-temperature oxidation near 1200 ° C. is required, and at such a temperature, a large-diameter semiconductor wafer is easily warped.
As another method, a method of using a polycrystalline silicon layer instead of the silicon nitride layer 103 as a stopper layer for CMP and RIE and using the polycrystalline silicon layer as it is as a gate electrode was announced in '96 International Electron Device Meeting. ing. However, in this method, since it is necessary to implant impurity ions for forming a well through the gate electrode and the gate oxide layer, the gate oxide layer is damaged. In addition, since the gate electrode is formed by patterning the oxidation prevention mask, the height of the gate electrode becomes non-uniform according to the uniformity of the CMP and RIE processes. As a result, there is a concern that variations in transistor characteristics will increase.
[0017]
A method of forming an insulating sidewall on the side surface of the silicon oxide film 108 projecting from the silicon substrate 101 of the silicon oxide layer 108 shown in FIG. 12A and embedding the recess 121 with the insulating sidewall is described in Pierre C. . Fazan et al. , IEDM 1993, PP. 57-60. However, in this method, when forming the sidewall, it is necessary to suppress the variation in the growth of the insulating layer and the variation in the etch back of the insulating layer, and it is difficult to form the sidewall with good controllability. Furthermore, since the etch back for forming the sidewall is performed before the gate oxide layer is formed, the surface of the silicon substrate is roughened by ion irradiation at the time of the etch back, so that the gate oxide layer may be adversely affected.
[0018]
An object of the present invention is to provide a method of manufacturing a semiconductor device which can obtain good transistor characteristics and can prevent defects in a semiconductor wafer.
[0019]
[Means for Solving the Problems]
The above-mentioned problem involves a step of forming a stopper layer 3 on a semiconductor substrate 1 as illustrated in FIGS.Forming a mask layer 4 on the stopper layer 3, forming a first opening 6b in the mask layer 4, and etching the stopper layer 3 through the first opening 6b. A second opening 6a is formed, and the second opening 6aDetermining an element isolation region A;The second openingEtching the semiconductor substrate 1 through 6aGroove 7Forming a groove, andForming a substrate protection layer 8 covering the wall surface, and protecting the substrate 1 with the substrate protection layer 8By partially etching the stopper layer 3The second opening of the stopper layer 3Expanding the width of 6a;Etching the mask layer 4 and removing the substrate protective layer 7;The stopper layer 3 and theSecond opening6a, forming an oxide film 9 in the inside of the groove 7; removing the oxide film 9 above the stopper layer 3; removing the stopper layer 3; Reducing the side portion of the oxide film 9 protruding from the semiconductor device.
[0020]
In the method for manufacturing a semiconductor device described above,The oxide film 9 formed inside the groove 7 is a silicon oxide film, and a side portion of the oxide film 9 protruding from the groove 7 is reduced by hydrofluoric acid.It is characterized by the following.In the method of manufacturing a semiconductor device described above, the second opening of the stopper layer 3 may be used.6a in the step of spreadingSecond openingThe expansion width of 6a is wider than the width of the oxide film 9 reduced by the hydrofluoric acid.
[0021]
Furthermore,In the method of manufacturing a semiconductor device described above, the removal of the oxide film 9 on the stopper layer 3 is performed by polishing or anisotropic etching.Furthermore,SaidSecond opening6a is CF_Four, CHF_Three, HBr, and Ar gas, or dry etching using a phosphoric acid solution.
[0022]
Furthermore,In the method of manufacturing a semiconductor device described above,The method further comprises a step of removing the mask layer 9 after the expansion of the second opening 6a.
Furthermore, after the expansion of the second opening 6a, the first opening 6b of the mask layer 4 is expanded to be equal to or larger than the second opening 6a.
[0023]
Furthermore,In the method of manufacturing a semiconductor device described above,The stopper layer 3 is formed by growing silicon nitride, the mask layer 4 is formed by growing silicon oxide or applying a resist, and the expansion of the second opening 6a of the stopper layer 3 is performed by using silicon oxide or resist. And the oxide film 9 is formed by growing silicon oxide.
[0024]
In the above-described method for manufacturing a semiconductor device, the thickness of the stopper layer is 1.2 times or less the thickness of an electrode formed across the oxide film protruding from the groove.
Next, the operation of the present invention will be described.
According to the present invention, when an oxide film is filled in a trench for element isolation formed in a semiconductor substrate, an oxide film protruding upward from the trench is left wider than the trench.
[0025]
Therefore, even if an etching process is performed to reduce the oxide film on the substrate surface thereafter, the supply of the etchant into the groove is obstructed by the protrusion of the oxide film, and as a result, the inside of the groove is prevented. The formation of the concave portion in the oxide film is prevented, and the electric field from the electrode straddling the element isolation groove is not concentrated on the shoulder of the groove.
To expand the opening of the stopper layer, a mask layer such as silicon dioxide is formed thereon, the stopper layer is sandwiched between the mask layer and the substrate, and the stopper layer is selectively laterally isotropic. The opening uniformly expands by the etching. The selective etching may be wet or dry. When a stopper layer made of silicon nitride is used, the mask layer is formed of silicon oxide, and the stopper layer is wet-etched with phosphoric acid. Or CF₄, CHF₃, HBr, and Ar gases are isotropically and selectively etched by dry etching in any combination.
[0026]
In order to protect the semiconductor substrate exposed from the groove from etching or contamination, it is preferable to cover the inner surface of the groove with a protective layer such as silicon oxide.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Therefore, embodiments of the present invention will be described below with reference to the drawings.
1 to 3 are cross-sectional views showing one embodiment of a process for manufacturing a semiconductor device of the present invention.
First, a description will be given of a state until the state shown in FIG.
[0028]
First, a main surface of a silicon substrate (semiconductor substrate) 1 is thermally oxidized to form a first silicon oxide layer 2 having a thickness of 10 nm on the main surface. Subsequently, a silicon nitride layer (stopper layer) 3 is formed on the first silicon oxide layer (substrate protection layer) 2 by CVD, and a second silicon layer 100 nm thick is formed on the silicon nitride layer 3. An oxide layer (mask layer) 4 is grown by CVD. The thickness of the silicon nitride layer 3 is preferably 40 nm or more and 1.2 times or less the thickness of a gate electrode material described later. Details of the thickness will be described later.
[0029]
After that, a resist (mask layer) 5 is applied on the second silicon oxide layer 4, and is exposed and developed to form a window 5a in the element isolation region A. The width of the window 5a in the element isolation region A is, for example, 1 μm or less, and decreases to 0.2 μm or less as the miniaturization of the semiconductor element progresses.
Next, as shown in FIG. 1B, the second silicon oxide layer 4 and the silicon nitride layer 3 are etched through the window 5a to form openings 6a and 6b below the window 5a. Subsequently, the silicon substrate 1 is etched through the window 5a and the openings 6a and 6b to form a groove 7 having a depth of 0.5 μm. In these cases, CF is used as an etching gas for the first and second silicon oxide layers 2 and 4 and the silicon nitride layer 3.₄  And CHF₃And a mixed gas of Ar and Ar. HBr and O are used as etching gases for the silicon substrate 1.₂Mixed gas or Cl₂And O₂, The side surface of the groove 7 is inclined, and the inclination alleviates the electric field concentration on the shoulder (upper edge) of the groove 7. The second silicon oxide layer 4 is formed, for example, at a temperature of 750 to 800 ° C.
[0030]
Next, after removing the resist 5 with a solvent, as shown in FIG. 1C, the inner wall surface of the groove 7 of the silicon substrate 1 is thermally oxidized to form a third silicon oxide layer (substrate protective layer) having a thickness of 5 nm. 8), thereby covering the inner surface of the groove 7 with the third silicon oxide layer 8. Subsequently, as shown in FIG. 2A, the silicon nitride layer 3 sandwiched between the first silicon oxide layer 2 and the second silicon oxide layer 4 is heated at about 140 ° C. through the openings 6a and 6b. Side opening to widen the opening 6a of the silicon nitride layer 3 by about 50 nm. In this case, since the first and second silicon oxide layers 2 and 4 are hardly etched by hot phosphoric acid, the second silicon oxide layer 4 overhangs from the silicon nitride layer 3 in the opening 6b, Moreover, the surface of the silicon substrate 1 exposed from the groove 7 is protected from hot phosphoric acid by the third silicon oxide layer 8.
[0031]
The etching of the silicon nitride layer 3 is performed by CF in addition to wet etching with hot phosphoric acid.₄, CHF₃, HBr and Ar gas may be arbitrarily selected for dry etching.
Thereafter, as shown in FIG. 2B, the first, second and third silicon oxide layers 2, 4, and 8 are etched with a diluted hydrofluoric acid solution, and the first, second and third silicon oxide layers 2, 4 and 8 are exposed from the openings 6a and 6b. And the second silicon oxide layers 2 and 4 are removed, and an overhang portion of the third silicon oxide layer 8 with respect to the silicon nitride layer 3 is removed. The lateral etching amount of the third silicon oxide layer 8 is set to 50 nm or more. In this case, in the second silicon oxide layer 4, the opening 6b is wider than the opening 6a of the silicon nitride layer 3 by the isotropic etching, and the edge of the second silicon oxide layer 4 is smoothed. Become.
[0032]
Next, as shown in FIG. 2C, a fourth silicon oxide layer 9 is grown to a thickness of about 0.6 to 1 μm by CVD, and the fourth silicon oxide layer 9 The third silicon oxide layer 4 is covered and the inside of the groove 7 is buried. During the CVD, SiH₄A mixed gas of oxygen and oxygen or a mixed gas of TEOS and ozone is used. After the growth of the fourth silicon oxide layer 9, the inside of the fourth silicon oxide layer 9 is densified by annealing at about 1000 ° C.
[0033]
Subsequently, the fourth and third silicon oxide layers 9 and 4 are polished by CMP to remove the third and fourth silicon oxide layers 4 and 9 on the silicon nitride layer 3.
The polishing is performed with the silicon substrate 1 interposed between the rotating upper and lower platens (not shown). The rotation speed of the upper and lower platens is 20 rpm, the pressure between the upper and lower platens is 5 PSI, the back pressure is 5 PSI, and a slurry containing colloidal silica as a main component or a cerium oxide slurry is used as an abrasive. Under such conditions, the etching rate of the silicon nitride layer 3 is low and this is the end point of the polishing. When the polishing is completed, the fourth silicon oxide layer 9 is placed in the opening 6a and the groove 7 of the silicon nitride layer 3. Will only remain.
[0034]
Next, when the silicon nitride layer 3 is removed with a hot phosphoric acid solution, a part of the fourth silicon oxide layer 9 burying the groove 7 becomes a projection 9a on the silicon substrate 1, as shown in FIG. The projection 7a protrudes from the element isolation region A to the element formation region B.
Thereafter, the first silicon oxide layer 2 remaining on the silicon substrate 1 is removed with diluted hydrofluoric acid, and the surface of the silicon substrate 1 is thermally oxidized to grow a sacrificial oxide layer (not shown). After forming a well 10 of one conductivity type by ion implantation in 1, the sacrificial oxide layer is removed with diluted hydrofluoric acid.
[0035]
By such two hydrofluoric acid treatments, the protrusion 9a of the fourth silicon oxide layer 9 is reduced as shown in FIG. 3 (b) to reduce the amount of protrusion α to the element formation region B, or The protruding portion disappears and the shoulder of the projection 9a becomes round.
As a result, no etchant is supplied to the silicon oxide layer 9 in the groove 7, so that the conventional concave portion is not formed in the silicon oxide layer 9 in and on the groove 7.
[0036]
The protrusion amount α of the protrusion 9a into the element formation region B is determined in advance by examining the side etching amount of the silicon nitride layer 3 shown in FIG. 2A and the reduction amount of the protrusion 9a due to hydrofluoric acid. After the removal of the sacrificial oxide layer, the protrusion 9a is adjusted so that the outer edge thereof coincides with the upper edge of the groove 7 or slightly protrudes into the element formation region B to several nm or less. The adjustment can be performed with good controllability.
[0037]
Thus, the element isolation structure is completed by the fourth silicon oxide layer 9 buried in the trench 7.
Next, as shown in FIG. 3C, the surface of the silicon substrate 1 is thermally oxidized to form a gate oxide layer (gate insulating film) 11 having a thickness of 5 nm. After the gate electrode 12 is formed over A, impurities of the opposite conductivity type to the impurities in the silicon substrate 1 are ion-implanted on both sides of the gate electrode 12 to form impurity diffusion layers 13 and 14 serving as a source and a drain. Thus, the step of forming the MOS transistor shown in FIG. 4 is completed.
[0038]
The impurities to be ion-implanted into the silicon substrate 1 to form the impurity diffusion layers 13 and 14 are p-type impurities (boron or the like) when the well 10 is n-type, or when the well 10 is p-type. Is an n-type impurity (phosphorus, arsenic, etc.).
When the transistor characteristics of the n-type MOS transistor formed by the above steps were measured, the result as shown in FIG. 5A was obtained, and the existence of the parasitic MOS transistor was not confirmed. That is, as shown in FIG. 5B, there was no peak showing a remarkable change in the transistor characteristic curve, and almost no decrease in the threshold voltage was observed. Similarly, when the transistor characteristics of the p-type MOS transistor were examined, the result as shown in FIG. 6A was obtained. The change in the transistor characteristic curve was as shown in FIG. 6B, and the existence of the parasitic capacitance was confirmed. Was not done. The size of the gate electrode 12 in FIGS. 5A and 6A is 1/10 gate length / gate width.
[0039]
When the inverse narrow channel effect was examined, the result as shown in FIG. 7 was obtained. That is, the change in the threshold voltage (Vth) was examined by changing the width of the gate electrode (that is, the length of the gate electrode in a direction perpendicular to the channel length direction) in the MOS transistor formed by the manufacturing process of the above-described embodiment. As shown in the triangular plot of FIG. 7, there was almost no change in the threshold voltage with respect to the change in the gate width. In this case, the hydrofluoric acid treatment time of the projection 9a was set to 11 minutes so that the side portion of the projection 9a almost coincided with the upper edge of the groove 7.
[0040]
On the other hand, when the change of the threshold voltage (Vth) with respect to the change of the gate width of the MOS transistor having the structure as shown in FIG. 13B according to the conventional method was examined, as shown in the black circle plot of FIG. It has been found that the threshold voltage decreases as the width decreases. This is because the influence of the parasitic capacitance on the transistor characteristics increases.
[0041]
By the way, as the width of a region (also referred to as an active region) in which a transistor is formed becomes narrower, an allowable amount L of side etching when the silicon nitride layer 3 is side-etched as shown in FIG. , Which is determined as follows.
Before the formation of the gate oxide layer 11, a hydrofluoric acid treatment is performed to etch the thermal oxide film by 20 nm. The film quality of the fourth silicon oxide layer 9 in the annealed groove 7 is substantially the same as that of the thermal oxide film.
[0042]
Therefore, it is necessary to prevent the width of the projection 9a from becoming narrower than the groove 7 due to such hydrofluoric acid treatment. In order to prevent such minimization, the width of both sides of the opening 6a of the silicon nitride layer 3 needs to be wider than the groove 6a by 20 nm or more, so that the width of the projection 9a must be secured in advance. On the other hand, if the width of the active region in which the MOS transistor is formed is made too narrow and the width of the opening 6a is made too wide, the width of the silicon nitride layer 3 becomes too narrow as shown in FIG. It is necessary to prevent this since the layer 4 may lift off. At present, when the lateral etching amount is 45% of the width of the minimum active region, the second silicon oxide layer 4 does not lift off. For example, the minimum active region width W₁Is 200 nm, the side etching amount L of the silicon nitride layer 3 through the opening 6a is₁Is 90 nm.
[0043]
As the side etching amount, the minimum active region width W₁Is 200 nm, the side etching amount of the silicon nitride layer 3 is 20 to 90 nm, and when the minimum active region width is 180 nm, it is 20 to 81 nm.
Next, the thickness of the silicon nitride layer 3 that determines the height of the protrusion 9a will be described.
As shown in FIG. 3A, if the height h of the projection 9a defined by the thickness of the silicon nitride layer 3 is too low, as shown in FIG. Parasitic MOS transistor T formed in_r1Turns on easily. The parasitic MOS transistor T_r1Causes humps. Note that in FIG._r0Indicates an original MOS transistor.
[0044]
When the power supply voltage is 1.8 V, the parasitic MOS transistor T_r1The limit of the method in which the height h of the projection 9a is low so that the LED does not turn on is about 40 nm. Its threshold V_thIs determined by the following equation.
V_th= V_fb+ 2φF + √ (2ε_si・ Q ・ NA ・ 2φF) × 1 / C_0x        (1)
Where V_fbIs the flat band voltage, φF is the Fermi potential, ε_siIs the dielectric constant of silicon, q is the elementary charge (unit is C), and NA is the substrate impurity concentration. Also, C_0xIs C_0x= Ε_ox/ D. Where ε_oxIs the dielectric constant of silicon oxide, d is the thickness of the gate oxide layer, and the unit is cm. Further, there is the following relationship.
[0045]
ε_si= 11.7ε₀
ε_ox= 3.9ε₀
φF = k · T · In (NA / ni)
Where ε₀(Vacuum permittivity) = 8.854 × 10^-14(F / cm), k = 8.62 × 10^-5, Ni = 1.45 × 10¹⁰, K = 8.62 × 10^-5, Q = 1.6 × 10^-19C. Also, T (absolute temperature) = 300K, V_fb= 1.054V, d = 40 × 10^-7cm, V in equation (1)_thIs as follows.
[0046]
V_th= 1.756kg^-1・ M^-2・ Sec²・ Coul ・ volt
Threshold V_thIs C_0xAre constants determined on the substrate side, and considering the influence thereof, when the protrusion amount of the projection 9a from the substrate is small, the parasitic capacitance MOS transistor T having a deep (small) threshold voltage_r1Can be done. Under the above conditions, when the protrusion amount is 40 nm and the parasitic MOS transistor T_r1Is 1.8 V, it can be said that the thickness of the silicon nitride layer 3 is preferably 40 nm or more. On the other hand, to what extent the upper limit of the protruding amount is allowed is determined by the parasitic MOS transistor T._r1Of the gate electrode or the thickness of the gate electrode.
[0047]
For example, if the protrusion amount of the protrusion 9a is too large, a concave portion is formed in the active region of the silicon substrate 1 when the gate electrode 12 is formed. That is, in order to form the gate electrode 12, as shown in FIG. 10A, a polycrystalline silicon layer 12a doped with impurities is formed so as to cover the protrusion 9a, and then the polycrystalline silicon layer 12a is formed. 12a will be patterned. However, in the polycrystalline silicon layer 12a which does not form the pattern of the gate electrode 12, in order to completely remove the portion remaining on the side surface of the projection 9a as shown in FIG. An over-etching time is required to remove the remaining amount after subtracting the thickness of the crystalline silicon film 12a. According to this over-etching, the gate oxide layer 11 on the side of the gate electrode 12 is simultaneously etched, so that it is necessary to prevent the silicon substrate 1 from being etched later. For this purpose, the height h of the protrusion 9a which is about 1.2 times the height of the polycrystalline silicon film 12a serving as the gate electrode 12 is appropriate. For example, when the thickness of the gate electrode 12 is 200 nm, the upper limit of the height h of the projection 9a is 2400 nm, and when the thickness of the gate electrode is 180 nm, the upper limit of the height h of the projection 9a is 216 nm. Reasonable.
[0048]
When removing the fourth silicon oxide layer 9 constituting the above-described element isolation structure from above the silicon nitride layer 3, CMP was used.₄And CHF₃RIE using a mixed gas of
Further, the third silicon oxide layer 4 on the silicon nitride layer 3 is used as a mask when the silicon substrate 1 is etched to form the grooves 7, but a resist layer may be used instead. In this case, the growth of the third silicon oxide layer 4 on the silicon nitride layer 3 may be omitted.
[0049]
Further, before forming the fourth silicon oxide layer 9, a fifth silicon oxide layer (substrate protection layer) 20 is formed along the inner peripheral surface of the groove as shown in FIG. Is also good.
[0050]
【The invention's effect】
As described above, according to the present invention, when an oxide film is filled in a trench for element isolation formed in a semiconductor substrate, the range of the oxide film protruding and protruding from the semiconductor substrate is increased by expanding the opening of the stop layer. Even if the etching process to reduce the oxide film on the substrate surface is performed later, the supply of the etchant into the groove is suppressed, and as a result, It is possible to prevent a concave portion from being formed in an oxide film present thereon, and to prevent an electric field from an electrode formed in an element isolation region from being concentrated on a shoulder of a groove.
[Brief description of the drawings]
FIGS. 1A to 1C are cross-sectional views (part 1) illustrating an embodiment of a semiconductor device manufacturing process of the present invention.
FIGS. 2A to 2C are cross-sectional views (part 2) illustrating one embodiment of a process for manufacturing a semiconductor device of the present invention.
3A to 3C are cross-sectional views (part 3) illustrating one embodiment of a semiconductor device manufacturing process of the present invention.
FIG. 4 is a cross-sectional view showing a MOS transistor formed through one embodiment of a semiconductor device manufacturing process of the present invention.
FIG. 5A is a transistor characteristic diagram showing a relationship between a gate voltage and a drain current of an n-type MOS transistor formed according to an embodiment of the present invention, and FIG. FIG. 7 is a diagram showing a change in log ID with respect to a gate voltage of FIG.
FIG. 6 (a) is a transistor characteristic diagram showing a relationship between a gate voltage and a drain current of a p-type MOS transistor formed according to an embodiment of the present invention, and FIG. 6 (b) is a transistor characteristic diagram. FIG. 7 is a diagram showing a change in log ID with respect to a gate voltage of FIG.
FIG. 7 is a characteristic diagram showing the inverse narrow channel effect of each of a MOS transistor formed according to an embodiment of the present invention and a MOS transistor formed according to a conventional process.
FIG. 8 is a cross-sectional view for explaining optimization of side etching of a silicon nitride layer used as a mask in one embodiment of the present invention.
FIG. 9 is a cross-sectional view of a MOS transistor formed in an element region and a parasitic transistor formed on an upper edge of a groove in an element isolation region according to an embodiment of the present invention, and an equivalent circuit of a transistor corresponding thereto; FIG.
FIGS. 10A and 10B show a relationship between the height of a protrusion of a silicon oxide film formed in and on a groove of an element isolation region and the thickness of a polycrystalline silicon film forming a gate electrode. FIG.
FIGS. 11A to 11D are cross-sectional views (part 1) illustrating an example of a manufacturing process of a conventional semiconductor device.
FIGS. 12A and 12B are cross-sectional views (part 2) illustrating an example of a manufacturing process of a conventional semiconductor device.
FIGS. 13A and 13B are cross-sectional views showing defects formed in an oxide film for element isolation in a conventional semiconductor device manufacturing process.
FIG. 14 is a transistor characteristic diagram of the MOS transistor shown in FIG. 13 (b).
FIG. 15 (a) is a transistor characteristic diagram showing a relationship between a gate voltage and a drain current of an n-type MOS transistor formed by a conventional process, and FIG. 15 (b) is a transistor characteristic diagram of FIG. 15 (a). FIG. 9 is a diagram showing a change in log ID with respect to.
FIG. 16 (a) is a transistor characteristic diagram showing a relationship between a gate voltage and a drain current of a p-type MOS transistor formed by a conventional process, and FIG. 16 (b) is a graph showing the gate voltage of FIG. 16 (a). FIG. 9 is a diagram showing a change in log ID with respect to.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate (semiconductor substrate), 2 ... first silicon oxide layer, 3 ... silicon nitride layer (stop layer), 4 ... second silicon oxide layer, 5 ... resist, 6a, 6b ... opening, 7 ... Groove, 8: third silicon oxide layer, 9: fourth silicon oxide layer, 9a: protrusion, 10: well, 11: gate oxide film, 12: gate electrode, 13, 14: impurity diffusion layer.

Claims (9)

Forming a stopper layer on the semiconductor substrate;
Forming a mask layer on the stopper layer;
Forming a first opening in the mask layer;
Etching the stopper layer through the first opening to form a second opening, and defining an element isolation region by the second opening ;
Etching the semiconductor substrate through the second opening to form a groove ;
Forming a substrate protection layer covering the wall surface of the groove,
A step of partially etching the stopper layer while protecting the substrate with the substrate protection layer, and increasing the width of the second opening of the stopper layer ;
While etching the mask layer, removing the substrate protective layer,
Forming an oxide film on the stopper layer, in the second opening , and inside the groove;
Removing the oxide film above the stopper layer;
Removing the stopper layer;
Reducing the side portion of the oxide film protruding from the groove. 2. The method according to claim 1 , wherein the oxide film formed inside the trench is a silicon oxide film, and a side portion of the oxide film protruding from the trench is reduced with hydrofluoric acid . The width of the second opening in the step of expanding the second opening of the stopper layer is wider than the width of the oxide film reduced by the hydrofluoric acid. Manufacturing method of a semiconductor device. 2. The method according to claim 1, wherein the removal of the oxide film on the stopper layer is performed by polishing or anisotropic etching. 2. The method according to claim 1 , further comprising a step of removing the mask layer after the expansion of the second opening . After expansion of the second opening, the manufacture of a semiconductor device according to claim 1, wherein said first opening of said mask layer, wherein the extended to the second opening greater than or equal to Method. The stopper layer is formed by growing silicon nitride;
The mask layer is formed by growing silicon oxide or applying a resist,
The expansion of the second opening of the stopper layer is performed by selective etching of the stopper layer with respect to silicon oxide or resist ,
2. The method according to claim 1, wherein the oxide film is formed by growing silicon oxide. 2. The method according to claim 1, wherein the substrate protective layer is formed of silicon oxide. 2. The method according to claim 1, wherein a thickness of the stopper layer is 1.2 times or less a thickness of an electrode formed across the oxide film protruding from the groove.

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