JP2003332413A - Semiconductor element isolation layer and method for forming insulated gate transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively restrain the reverse narrow channel effect without increasing the number of masks. <P>SOLUTION: This method is provided with a process wherein a part of the surface of a semiconductor substrate 1 (or semiconductor retained by the substrate) is dug by dry etching, and a trench 1a is formed, a process for forming a sacrificial oxide film 5 on an inner wall of the trench 1a (figure 2 (A)), a process for eliminating the formed sacrificial oxide film 5 (figure 2 (B)), a process for forming a nitride film 6 on the inner wall of the trench 1a (figure 2 (C)), and a process wherein the inside of the trench 1a on which the nitride film 6 is formed is filled with an insulating material. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor element isolation layer in which a trench is formed in a semiconductor substrate or a semiconductor supported by the substrate by dry etching and the trench is filled with an insulator. , And a method for forming an insulated gate transistor including the step of forming a semiconductor element isolation layer.

[0002]

2. Description of the Related Art A conventional LO is used as a semiconductor element isolation method.
Since it is difficult to miniaturize by the COS method, STI (Shallow
Trench element isolation methods such as w Trench Isolation) have become mainstream. In the trench element isolation method, with the element formation portion protected by a mask layer such as silicon nitride, the semiconductor substrate surface around the mask layer is dug down by dry etching to form a trench, and the inner surface of the trench is thinly oxidized, followed by silicon oxide. An insulator such as is buried in the trench and planarized. Remove the mask layer,
A desired semiconductor element is formed on the substrate surface (element active region) around the trench.

FIG. 5 shows a general pattern of a MOS transistor. In FIG. 5, reference numeral 100b denotes a surface region (active region) of the semiconductor substrate left by the trench element isolation layer 105 formed around. When the gate finger portion of the gate electrode 107 overlaps the active region 100b as shown, the width of the overlapping portion of the gate finger portion and the active region 100b is the gate length L.
g, the length of the overlapping portion becomes the gate width Wg.

FIGS. 6A to 8C show a method of forming this MOS transistor. These figures are shown in FIG.
It is a sectional view taken along the line A. First, a pad film 101 such as silicon dioxide and a mask layer 102 such as silicon nitride are formed on a silicon substrate 100, and a resist 103 having a pattern covering an active region of a transistor is formed thereon (FIG. 6A). ). The mask layer 102 and the pad film 101 are etched using the resist 103 as a mask (see FIG.
(B), the exposed silicon surface is dug down by dry etching to form a trench 100a (FIG. 6).
(C)).

Next, the exposed surface in the trench 100a is thermally oxidized to form a silicon dioxide film 104 (see FIG. 7).
(A)), a buried oxide film 105a made of thick silicon dioxide is deposited so as to completely fill the trench 100a and the mask layer 102 (FIG. 7B). In this state, the buried oxide film is polished by a flattening method such as CMP,
When the mask layer 102 is exposed, the end point is detected and polishing is stopped (FIG. 7C).

The exposed mask layer 102 is selectively removed using an etchant containing phosphoric acid (FIG. 8A), and the pad film 101 is selectively removed using an etchant containing hydrofluoric acid (FIG. FIG. 8B). At this time, the pad film 101 is etched together with the surface of the buried oxide film 105 and the end portion of the silicon dioxide film 104 thereunder, so that the active region 100b is exposed on the surface. The exposed active region 100b is washed by hydrofluoric acid treatment or the like to remove a natural oxide film and the like, and then thermally oxidized to form a gate oxide film 106. Subsequently, doped polysilicon containing impurities is deposited. The doped polysilicon is etched into a gate pattern by dry etching using a resist or the like as a mask. As a result, the gate electrode 107 is formed (FIG. 8C). After that, ion implantation is performed twice before and after the formation of the sidewall to form a source / drain impurity region (not shown) having an LDD structure and a conductivity type opposite to that of the active region 100b, thereby forming a MOS transistor. Finalize.

The trench isolation layer thus formed is indispensable for forming a fine MOS LSI.
There is a problem of the reverse narrow channel effect which causes variations in the threshold value of the transistor and causes an increase in standby current. The reverse narrow channel effect means the gate electrode width Wg of the MOS transistor.
Is a phenomenon in which the threshold voltage is lowered and the off-current is increased as is decreased.

FIG. 9A is a graph showing changes in the threshold voltage Vth of the transistor when the gate width Wg is reduced. Further, FIG. 9B is a graph showing a change in Vg-Ig characteristics of the transistor when the threshold voltage is lowered. When the transistor size is relatively large, a narrow channel effect occurs in which the gate width Wg of the transistor is reduced and the threshold voltage Vth rises. However, when the transistor size becomes extremely small, the threshold value is reversed, as shown in FIG. 9A. The inverse narrow channel effect in which the voltage Vth decreases becomes dominant. Threshold voltage V due to inverse narrow channel effect
When th decreases, as shown in FIG. 9B, the drain current Id (off current Ioff) when the gate voltage Vg is not applied increases, and as a result, the switching speed decreases and power consumption decreases. It causes various harmful effects such as increase or malfunction of the circuit.

The cause of the reverse narrow channel effect is the removal of the pad oxide film 101 and the hydrofluoric acid treatment just before the formation of the gate oxide film 106 causes the silicon oxide film buried in the trenches to be thinned, resulting in a corner portion at the upper part of the trench. There is a parasitic transistor. FIG. 10A is a schematic sectional view immediately after depositing polysilicon to be a gate electrode. Further, FIG. 10B is a diagram showing a parasitic transistor formation portion. Since the buried oxide film 105 and the pad film 102 are made of silicon dioxide, the active region 10
When the hydrofluoric acid treatment is performed as a pretreatment for forming the gate oxide film to remove the natural oxide film of 0b, the buried oxide film 105
Is reduced. Further, etching of silicon dioxide proceeds at the corners of the trench 100 where stress is particularly concentrated. As a result, a depression (divot) occurs in this portion. After that, when the gate oxide film 106 is formed and the doped polysilicon 107 is deposited, a parasitic transistor is generated at the corner portion of this trench. The parasitic transistor has a lower threshold voltage than the original MOS transistor, which causes an inverse narrow channel effect. The formation of the divot is promoted also when the gate oxide film is formed. In other words, since oxygen, which is an oxidizer for silicon, has a higher diffusion rate in silicon oxide than in single crystal silicon, it is considered that silicon in the trench corner portion is oxidized through the inside of the trench when the gate oxide film is formed. The amount of divot increases.

The first cause of the decrease in the threshold voltage Vth in the parasitic transistor section is that the electric field is concentrated in the trench corner section. Secondly, the channel concentration decreases at the trench corners. In order to alleviate the electric field concentration at the trench corner portion, which is the first cause, a method of controlling the oxide film thickness of the thermal oxide silicon film after the trench formation to optimize the rounding amount of the corner portion is proposed. , To some extent effective. But,
That is not enough, and it is necessary to take measures against the above-mentioned second cause.

In order to compensate for the decrease in channel concentration at the trench corner portion, which is the second cause, for example, "1997 Symposium on VLSI T" is used.
technology Digest of Techn
As described in "Technical Paper pp125-126", after forming the trench, the photoresist is formed so as to cover only the P-type MOS region, and the boron is obliquely ion-implanted while rotating the substrate. A method has been proposed in which the inner wall of the trench is thermally oxidized in order to round the trench corner portion after peeling (hereinafter referred to as the first prior art).

Also, Ono et al., “1997 Inter
national Electron Device
Meeting Technical Digest ”
Report that it is possible to suppress the reverse narrow channel effect by implanting nitrogen into the sidewall of the trench, and the mechanism is described as (1) and (2) below. (1) Normally, transition enhanced diffusion (TED) near the LDD edge
As a result, impurities (Boron) are piled up, the impurity concentration is increased, and the threshold voltage Vth is increased.
However, in the vicinity of the trench side, interstitial silicon that causes TED is absorbed by the interface between the oxide film on the side wall of the trench and the silicon, so that the impurity concentration decreases, and as a result, the threshold voltage Vth becomes shallow. This effect becomes more remarkable as the transistor width Wg becomes smaller, which is a phenomenon called an inverse narrow channel effect. (2) When nitrogen ion implantation is performed on the sidewalls of the trench, nitrogen piles up at the interface between the oxide film and silicon in the subsequent heat treatment process. The nitrogen functions to prevent the interstitial silicon that causes TED from being absorbed in the interface between the oxide film and the silicon on the trench sidewall, and as a result, the impurities pile up near the LDD even near the trench sidewall. . As a result, the inverse narrow channel effect is suppressed.
For the purpose of suppressing such an inverse narrow channel effect or the like, for example, Japanese Patent No. 3064994, or Japanese Patent Laid-Open No. 20-195940.
No. 00-133700, the trench sidewall is directly
A technique of thermally nitriding (or thermally oxynitriding) or implanting nitrogen ions has been proposed (hereinafter referred to as Prior Art 2).

[0013]

However, in the method of ion-implanting nitrogen in the prior art 2 described above, it is necessary to ion-implant a large amount of nitrogen in order to obtain a sufficient absorption effect of interstitial silicon. As a result, crystal defects such as dislocation loops are formed in the subsequent heat treatment process, which causes problems such as junction leakage. Further, even when the inner wall of the trench is directly thermally nitrided or thermally oxynitrided to form the silicon nitride layer (silicon oxynitride layer), damage during the trench formation remains and the leak current increases and the breakdown voltage decreases sufficiently. I can't avoid it. This is the same in the method of selectively implanting boron into the trench wall surface as in the prior art 1 described above. In particular, the prior art 1 is disadvantageous in terms of cost as the number of masks increases. is there.

An object of the present invention is to provide a method for forming a semiconductor element isolation layer that can effectively suppress the reverse narrow channel effect without increasing the number of masks, and a method for forming an insulated gate transistor using the method. It is in.

[0015]

A method for forming a semiconductor element isolation layer according to a first aspect of the present invention is for achieving the above-mentioned object, and is a semiconductor substrate or a surface of a semiconductor supported by the substrate. A step of forming a trench by digging a part of it by dry etching, a step of forming a sacrificial oxide film on the inner wall of the trench, a step of removing the formed sacrificial oxide film, and a step of forming a nitride film on the inner wall of the trench, Filling the inside of the trench where the nitride film is formed with an insulating material. Suitably, the step of forming the trench, on the surface of the semiconductor substrate or semiconductor, a step of forming a mask layer of a pattern covering the active region of the semiconductor element, and the trench around the semiconductor around the mask layer is dug by dry etching. The method includes a step of forming and a step of burying an insulator in the trench and planarizing the trench to remove the insulator on the mask layer. It is more desirable to remove the sacrificial oxide film by wet etching. It is more desirable to form the nitride film by a chemical vapor deposition method and then perform annealing.

A method for forming an insulated gate transistor according to a second aspect of the present invention is for achieving the above-mentioned object, and includes a step of forming a trench on the surface of a semiconductor substrate or a semiconductor supported by the substrate. A step of forming a sacrificial oxide film on the inner wall of the trench, a step of removing the formed sacrificial oxide film, a step of forming a nitride film on the inner wall of the trench,
A step of filling the inside of the trench in which the nitride film is formed with an insulating material; a step of forming a gate electrode with a gate insulating film interposed on an element active region which is a semiconductor portion around the trench; and a step between the gate electrode and the trench. A step of introducing into the element active region an impurity of a conductivity type opposite to that of the element active region to form source / drain regions.

In these methods for forming the semiconductor element isolation layer and the insulated gate transistor, a mask layer is formed on the surface of the semiconductor substrate or the semiconductor layer, and the semiconductor exposed around the mask layer is dug down by dry etching. A sacrificial oxide film is formed to remove the etching damage layer at this time, and then the sacrificial oxide film is removed by wet etching or the like to expose the inner surface of the trench again. A nitride film is formed on the exposed inner surface of the trench by a low-damage film forming method such as a chemical vapor deposition method, annealing is performed as necessary, and then the trench is filled with an insulator. The insulator is planarized to remove the insulator above the mask layer, and the mask layer is removed.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a method for forming a semiconductor element isolation layer and an insulated gate transistor according to the present invention will be described below with reference to an N-type channel MOS having a pattern shown in FIG.
A transistor will be described as an example. 1 (A) to 4
(C) is a diagram showing a method for forming this MOS transistor, and is a cross-sectional view taken along the line AA of FIG. 5. First, a P-type SOI wafer supported by a P-type silicon wafer or substrate
A layer or the like (hereinafter simply referred to as the substrate 1) is prepared. Figure 1
As shown in (A), a film 2 a of silicon dioxide or the like to be the pad film 2 for relaxing the adhesiveness of the mask layer 3 and stress on the substrate and a film 3 a of silicon nitride or the like to be the mask layer 3 are formed on the substrate 1. Form on top. Although the film thickness and the forming method thereof are not limited, since the mask layer 3 is used later as a stopper for polishing to detect the end point, the mask layer 3 is hard to be ground by polishing as compared with the buried insulating film in the trench and is dense and chemically. A material with a low etching rate is selected. For example,
The silicon dioxide film 2a to be a pad film is thermally oxidized to 1
About 0 nm, the silicon nitride film 3a to be a mask layer is CV
It is formed to a thickness of about 110 nm by the D method. A resist 4 having a pattern covering the active region of the transistor is formed thereon by photolithography.

As shown in FIG. 1B, this resist 4
The peripheral silicon nitride film 3a and the silicon dioxide film 2a are removed by dry etching using as a mask to form a laminated body of the mask layer 3 and the pad film 2. Figure 1 (C)
Then, the silicon surface exposed around this laminated body is dug down by dry etching to form the trench 1a.
The depth of the trench 1a is deep enough to allow element isolation and is arbitrary as far as it is, but here it is about 300 nm.

In this embodiment, as shown in FIG. 2A, the sacrificial oxide film 5 is formed by thermally oxidizing the trench surface around the mask layer. As the oxidation condition, for example, 100
If a thermal oxide film of about 10 nm can be formed by dry oxidation at 0 ° C., the silicon damage layer at the time of trench formation by normal dry etching is consumed during this oxidation. The sacrificial oxide film thickness is 10 n if the damaged layer can be removed.
It may be thinner than m, and conversely, may be thicker in relation to the rounding amount of the trench corner portion described later. here,
The sacrificial oxide film 5 is set to have a film thickness that satisfies both conditions.

In the step shown in FIG. 2B, this sacrificial oxide film 5 is completely removed by hydrofluoric acid treatment. This allows
The etching damage layer on the surface of the trench 1a is removed together with the sacrificial oxide film 5. Then, a nitride film 6 made of, for example, silicon nitride is deposited on the entire surface by the CVD method. The nitride film 6 is a film for preventing defects such as interstitial silicon and impurities such as boron that cause the reverse narrow channel effect from diffusing from the silicon active region into the trench. Generally, a film thickness of about 10 nm is sufficient. If this diffusion preventing effect is sufficient, a thinner film may be used, and conversely, a thicker film may be used. C
As the VD condition, for example, the source gas is DCS (dichlorosilane): ammonia NH ₃ = 30 sccm: 150.
It is preferable that the sccm, the pressure is 20 Pa, and the substrate temperature is 650 ° C. The nitride film 6 formed by this CVD is used as the mask layer 3
Is similarly deposited on the surface of the.

As shown in FIG. 3A, a thick buried oxide film 7a made of, for example, silicon dioxide is deposited to fill the inside of the trench 1a and the mask layer 3 completely. The buried oxide film 7a is desirable because it can be deposited in a short time when deposited by high density plasma CVD. In this state, the buried oxide film 7a is polished from the surface by a planarizing method such as chemical mechanical polishing (CMP), and when the mask layer 3 is exposed, the end point is detected and the polishing is stopped. As a result, as shown in FIG. 3B, the buried oxide film 7 separated on the mask layer 3 and buried in the trench 1a.
Is formed.

As shown in FIG. 4A, the exposed mask layer 3 is selectively removed using an etchant containing phosphoric acid. Subsequently, as shown in FIG. 4B, the pad film 2
Are selectively removed using an etchant containing hydrofluoric acid. At this time, when the buried oxide film 7 is silicon dioxide, the surface thereof is etched, but the film 6 thereunder is not etched because it is silicon nitride. Ion implantation of impurities for forming wells or ion implantation for adjusting the threshold voltage of the channel is performed on the active region 1b exposed by this etching or before removing the pad film 2. The exposed active region 1b is washed with hydrofluoric acid treatment or the like to remove a natural oxide film and the like, and then dry-oxidized to form a gate oxide film 8 of several nm to several tens of nm. Doped polysilicon containing impurities (of the same conductivity type) is deposited, and the doped polysilicon is etched into a gate pattern by dry etching using a resist or the like as a mask. As a result, FIG.
As shown in (C), the gate electrode 9 is formed. After that, ion implantation is performed twice before and after the formation of the sidewalls to form a source / drain impurity region (not shown) having an LDD structure and a conductivity type opposite to that of the active region 1b, and forming a source / drain electrode. Form. Furthermore, if necessary,
The MOS transistor is completed through various steps such as forming an interlayer insulating film, an upper wiring layer, forming an overcoat film, and opening a pad.

In this embodiment, since the sacrificial oxide film 5 is formed and the step of etching off the sacrificial oxide film 5 is included, the etching damage layer introduced at the time of forming the trench can be removed. Further, since the nitride film 6 is formed by the CVD method, there is an advantage that the silicon at the trench interface is less likely to be damaged as compared with the method of implanting nitrogen ions.
Further, since the sacrificial oxide film 5 has a thickness sufficient to replace the conventional thermal oxide film on the inner wall of the trench, the roundness of the trench corner portion can be adjusted. The increase in the number of steps is only the step of removing the sacrificial oxide film 5 and the CVD step of the nitride film 6, and since there is no increase in the number of masks, the increase in cost is negligible in the whole process.

In this embodiment, various process changes can be made. For example, the nitride film 6 of the trench is not limited to silicon nitride, but silicon oxynitride or a laminated film thereof can be used instead. As the CVD conditions for silicon oxynitride, for example, the source gas is DCS (dichlorosilane): ammonia NH ₃ : nitrogen dioxide N ₂ O = 94.5.
sccm: 63 sccm: 315 sccm, pressure is 40
Pa and the substrate temperature are preferably 775 ° C. The oxygen concentration of silicon oxynitride is preferably 60% or less. Further, an atomic layer deposition (ALD) method can be adopted as CVD of these silicon nitride and silicon oxynitride. In the ALD method, a nitrogen (or oxygen) -rich layer and a silicon-rich layer are atomically exposed by exposing a substrate to a nitrogen (or nitrogen and oxygen) -containing gas and a silicon-containing gas alternately at a predetermined temperature. It is a type of CVD method of alternately depositing. AL
The method D has advantages such as excellent film thickness controllability because the incubation time can be suppressed. Specifically, ALD
-As the CVD conditions, for example, the pressure is 170 Torr.
r, a silicon wafer having a substrate temperature of 375 ° C. is exposed to a SiCl ₄ gas atmosphere having a flow rate of 100 sccm for about 1 minute,
Subsequently, the pressure is 300 Torr and the flow rate is 500 sccm.
It is preferable that the exposure of the silicon wafer having the substrate temperature of 550 ° C. for about 2 minutes to the ammonia NH ₃ gas atmosphere described above is repeated a necessary number of times according to the desired film thickness. Either of these cases may be used, but particularly when the nitride film is silicon nitride or in the case of the ALD method, an annealing step may be added thereafter. This is because the slight damage of CVD can be recovered and the leak current can be further reduced. Annealing conditions include annealing for 30 seconds in an ammonia NH ₃ gas atmosphere at 1000 ° C. under normal pressure, and for 30 seconds in a nitrogen dioxide N ₂ O gas atmosphere at 900 ° C. under normal pressure.
Annealing for a second or a combination thereof can be preferably adopted. In addition, various modifications such as a gate oxide film material and a gate electrode material can be made without departing from the spirit of the present invention.

[0026]

According to the method for forming a semiconductor element isolation layer and the method for forming an insulated gate transistor according to the present invention,
Since it has a sacrificial oxide film formation process and its removal process,
The dry etching damage layer at the time of forming the trench can be completely removed. Further, since the subsequent formation of the nitride film is performed by the chemical vapor deposition method, the introduction of damage thereafter can be suppressed to the minimum. Annealing can recover even the slight damage introduced during the chemical vapor deposition. Furthermore, with this method, the number of masks does not increase, and the increase in cost can be suppressed to the necessary minimum. From the above, it becomes possible to completely suppress the inverse narrow channel effect with the minimum necessary increase in cost.

[Brief description of drawings]

1A to 1C are views showing an M according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view taken along the line AA of FIG. 5 showing up to formation of a trench in manufacturing an OS transistor.

2A to 2C are cross-sectional views taken along the line AA of FIG. 5, showing up to the formation of a nitride film in the step following FIG. 1C.

3A and 3B are cross-sectional views taken along the line AA in FIG. 5, showing up to planarization in the step following FIG. 2C.

4A to 4C are cross-sectional views taken along the line AA of FIG. 5, showing up to the formation of the gate electrode in the step following FIG. 3B.

FIG. 5 is a plan view of a MOS transistor according to an embodiment of the present invention.

6 (A) to (C) show the process up to trench formation in the manufacture of a conventional MOS transistor, FIG.
It is a sectional view taken along the line A.

7A to 7C are cross-sectional views taken along the line AA in FIG. 5, showing up to planarization in the step following FIG. 6C.

8A to 8C are cross-sectional views taken along the line AA of FIG. 5, showing up to the formation of the gate electrode in the step following FIG. 7C.

FIG. 9A is a graph showing changes in the threshold voltage of a transistor when the gate width is reduced.
(B) is a graph showing a change in Vg-Ig characteristics of a transistor when a threshold voltage drop occurs.

FIG. 10A is a schematic sectional view immediately after depositing polysilicon to be a gate electrode. (B) is a diagram showing a parasitic transistor formation portion.

[Explanation of symbols]

1a ... Trench, 1b ... Active region, 1 ... Substrate, 2 ... Pad film, 2a ... Silicon dioxide film serving as pad film, 3 ... Mask layer, 3a ... Silicon nitride film serving as mask layer, 4 ... Resist, 5 ... Sacrifice Oxide film, 6 ... Nitride film, 7, 7a ... Buried oxide film, 8 ... Gate oxide film, 9 ... Gate electrode, Lg
... gate length, Wg ... gate width

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F032 AA35 AA44 AA46 AA48 CA03                       CA17 DA04 DA23 DA24 DA33                       DA43                 5F140 AA01 AA02 AA16 AA24 AA26                       AC36 BA01 BC06 BE03 BE07                       BF01 BF04 BG08 BG27 BG38                       BH15 BK13 CB04 CB10

Claims (11)

[Claims] 1. A step of forming a trench by digging a part of a surface of a semiconductor substrate or a semiconductor supported by the substrate by dry etching, a step of forming a sacrificial oxide film on an inner wall of the trench, and a step of forming the sacrificial oxide film. Removal step,
A method of forming a semiconductor element isolation layer, comprising: a step of forming a nitride film on an inner wall of a trench; and a step of filling the inside of the trench having the nitride film with an insulating material. 2. A step of forming a mask layer having a pattern covering an active region of a semiconductor element on the surface of the semiconductor substrate or the semiconductor in the step of forming the trench, and the semiconductor around the mask layer is dug down by dry etching. 2. The method for forming a semiconductor element isolation layer according to claim 1, comprising a step of forming a trench and a step of burying an insulator in the trench and removing the insulator on the mask layer by planarization. 3. The method for forming a semiconductor element isolation layer according to claim 1, wherein the semiconductor in which the trench is formed is silicon, and the sacrificial oxide film is silicon oxide formed by thermally oxidizing the inner surface of the trench. 4. The method for forming a semiconductor element separation layer according to claim 1, wherein the sacrificial oxide film is removed by wet etching using a chemical solution. 5. The method for forming a semiconductor element isolation layer according to claim 1, wherein the nitride film is silicon nitride formed on the inner surface of the trench after the oxide film is removed by a chemical vapor deposition method. 6. The semiconductor element isolation layer according to claim 1, wherein the nitride film is silicon oxynitride having an oxygen concentration of 60% or less formed by chemical vapor deposition on the inner surface of the trench after removing silicon oxide. Forming method. 7. The film thickness of the sacrificial oxide film is the first film thickness required to absorb the damage layer at the time of forming the trench and the second film thickness required to round a corner portion of the upper portion of the trench by a predetermined amount. The film thickness is set to be equal to or larger than the larger one of the film thicknesses.
A method for forming a semiconductor element isolation layer as described above. 8. The method for forming a semiconductor element isolation layer according to claim 5, wherein as the chemical vapor deposition method, an atomic layer deposition method is used in which the inner wall of the trench is exposed while the nitrogen-containing gas and the silicon-containing gas are alternately switched. 9. An atomic layer deposition method in which the inner wall of the trench is exposed while the nitrogen- and oxygen-containing gas and the silicon-containing gas are alternately switched as the chemical vapor deposition method.
A method for forming a semiconductor element isolation layer as described above. 10. The method for forming a semiconductor element isolation layer according to claim 1, further comprising an annealing step after forming the nitride film. 11. A step of forming a trench on a surface of a semiconductor substrate or a semiconductor supported by the substrate, a step of forming a sacrificial oxide film on the inner wall of the trench, a step of removing the formed sacrificial oxide film, and a step of forming an inner wall of the trench. A step of forming a nitride film, a step of filling the inside of the trench in which the nitride film is formed with an insulating material, and a step of forming a gate electrode on the device active region which is a semiconductor portion around the trench with a gate insulating film interposed. And a step of introducing into the element active region between the gate electrode and the trench an impurity of a conductivity type opposite to that of the element active region to form source / drain regions.