JP3599957B2 - Method for manufacturing multilayer wiring board - Google Patents

Description

【００２６】
表１から、実施例はビア１２，１８が不導通の配線基板２８の比率が低く、且つ上層・最上層配線パターン１４，２０のピール強度も全ての配線基板２８が一応強固な密着強度とされる１ｋｇ／ｃｍ^２以上であった。この結果から、実施例では樹脂残りや形状不良の少ないビア１２等が得られ、上層配線パターン１４等の密着強度も強固に維持されたことが理解される。
一方、比較例は同様にビア１２等による導通不良の基板の発生率が低くなった反面、上層配線パターン１４等の密着強度が従来例よりも低いレベルなった。これは比較例では２つの表面粗化工程間における研磨工程を省いたため、樹脂絶縁層６，１６の上面が過度にエッチングされ、大きく脆い凹凸面６ａが形成されたことによると思われる。
更に、従来例は上層配線パターン１４等の密着強度が高い反面、ビア１２等による不良の発生率が５０％以上と高く、生産性が低くなることも確認された。
【００２７】
係る結果から、本発明による実施例では樹脂絶縁層６，１６の表面のうち、ビアホール７，１７の表面に２回の粗化を行ってビア１２，１８の底部に樹脂残りや形状不良が生じるのを防ぎ、且つ樹脂絶縁層６等の上面は中間に研磨を施して実質１回の表面粗化のみとして上層配線パターン１４等の密着強度の低下を防いだことが容易に理解される。
尚、本発明は、表面粗化、上面研磨、及び表面粗化の工程順だけでなく、表面粗化の工程を３回以上としその間において上面研磨を行う形態や、同じく表面粗化の工程を３回以上として最後の表面粗化の直前のみに上面研磨を行う形態も含まれる。要するに、ビアホール７内等の表面には複数回の表面粗化を行う一方、樹脂絶縁層６等の上面には実質的に１回のみ表面粗化を行う方法であれば良い。
【００２８】
図４は本発明による異なる形態のビアに関する。
同図（Ａ）は上下２層の樹脂絶縁層を貫通するビアを示す。先ず、前記同様のコア基板３０の上面に下層配線パターン３２が形成され、その上方に感光性エポキシからなる樹脂絶縁層３４，３６が形成される。この樹脂絶縁層３４の上面の図示しない位置には上層配線パターンが形成されている。次に、下層配線パターン３２の上面における樹脂絶縁層３４，３６には、露光と現像により緩い円錐状のビアホール３５が形成される。更に、樹脂絶縁層３６（３４）の表面、即ちその上面とビアホール３５の表面には複数回の前記表面粗化が行われ、且つその間において樹脂絶縁層３６の上面に前記研磨が行われる。そして、樹脂絶縁層３６上に無電解銅メッキ等を行い、且つ図示しない感光性樹脂層を形成した後、露光、現像、及びエッチングを行って最上層配線パターン３９が形成される。同時に、ビアホール３５内に下・最上層配線パターン３２，３９間を導通する略円錐形状のビア３８を得ることができる。
【００２９】
また、図４（Ｂ）ではコア基板４０の上面に下層配線パターン４２が形成され、その上方に上記と同様の樹脂絶縁層４４，４６が形成されている。この樹脂絶縁層４４の上面の図示しない位置には上層配線パターンが形成されている。次に、上方からレーザを樹脂絶縁層４４，４６に対し下向きに照射し、下層配線パターン４２の上面が露出する円柱状のビアホール４５を形成する。更に、樹脂絶縁層４６の上面とビアホール４５の表面に複数回の前記表面粗化を行い、且つその間で樹脂絶縁層４６の上面を研磨する。そして、無電解メッキ等を行って最上層配線パターン４９と円柱状のビア４８が形成される。
【００３０】
更に、図４（Ｃ）は異なる方法により形成されるビアに関する。先ず、コア基板５０の上面に下層配線パターン５２が形成され、その上方に樹脂絶縁層５４が形成される。この樹脂絶縁層５４に露光と現像を行い、下層配線パターン５２の上に緩い円錐形状のビアホール５５を形成する。次に、樹脂絶縁層５４の上面とビアホール５５の表面に複数回の表面粗化を行い、その間に樹脂絶縁層５４の上面を研磨して図示しない位置に上層配線パターンを形成する。この際、ビアホール５５内にはメッキレジストが形成されているので、ビアは形成されない。
次いで、樹脂絶縁層５４の上面に樹脂絶縁層５６が形成され、露光と現像により上記ビアホール５５があった位置とも重なるビアホール５７が形成される。該ビアホール５７は、現像処理を強めとすることで底部側が略垂直に形成される。
【００３１】
このビアホール５７の表面と樹脂絶縁層５６の上面に複数回の表面粗化を行い、且つその間で樹脂絶縁層５６の上面を研磨する。そして、無電解メッキ等を行って最上層配線パターン５９を形成すると共に、断面形状が２段階のテーパを有するビア５８が形成される。
これらのビア３８，４８，５８は各ビアホール３５，４５，５７に倣った断面形状になると共に、それらの底部において前記樹脂残りや狭隘な形状不良を形成することが少ない。従って、上下に離隔した下層配線パターン３２等と最上層配線パターン３９等の間を直かに導通させることが可能となる。
【００３２】
本発明は、以上において説明した各形態に限定されるものではない。
例えば、図５（Ａ）及び（Ｂ）に示すように、図１と同じくコア基板１の両面に下層配線パターン４を形成し、その上方に樹脂絶縁層６を形成し且つビアホール７を形成した後、前記複数回の表面粗化とその間に研磨を施したものを用意する。
次に、図５（Ｃ）に示すように、この樹脂絶縁層６の表面全体に無電解銅メッキ等を施して数１０μｍの厚さの銅膜（導体層）６０を形成し、更に、図５（Ｄ）に示すように、上記銅膜６０の上面に感光性の樹脂からなる絶縁層６２を形成する。
次いで、係る樹脂絶縁層６２に露光と現像を行い、図５（Ｅ）に示すように、所定の樹脂パターン６３とする。そして、係る樹脂パターン６３と上記銅膜６０とをエッチング液に浸漬することにより、図５（Ｆ）に示すように、上記樹脂パターン６３によって保護された位置に上層配線パターン６４及びビア６６が形成される。同様の方法により、図示しない樹脂絶縁層や最上層配線パターン等を形成して、前記配線基板２８と同様な多層配線基板６８を形成することができる。
【００３３】
また、前記多層配線基板２８のコア基板１には、ＢＴ樹脂とガラス繊維布との複合材（ガラス−ＢＴレジン材）の他、ガラス−エポキシ材、ガラス−ＰＰＥ材や、紙−エポキシ材等の複合材、或いはエポキシ、ＢＴレジン、ポリイミド、ＰＰＥ等の樹脂を用いても良い。
更に、コア基板１を上記樹脂に限らず、セラミック製としても良い。係る剛性の高いセラミックのコア基板１を用いる場合、その両面に同数の樹脂絶縁層６，１６と下層・上層・最上層配線パターン４，１４，２０を形成せず、互いに異なる層数としたり、或いはコア基板１の片面にのみ樹脂絶縁層６等や下層・上層配線パターン４，１４等を形成しても良い。後者の場合、前記貫通孔２等を省略することができる。
更にまた、上記コア基板１は必須の要素ではなく、例えば既設の樹脂絶縁層の上面に下層配線パターン４を形成して順次前記の各工程を行って、樹脂製多層配線基板を製造しても良い。或いは、既設のセラミック層又はセラミック多層配線基板の上面に下層配線パターン４を形成して順次前記の各工程を行い、セラミックと樹脂の複合多層配線基板を製造することも可能である。
【００３４】
また、前記表面粗化に用いるエッチング液には、過マンガン酸、濃硫酸、又はクロム酸を含むものを用いることもでき、樹脂絶縁層の表面等に形成すべき凹凸面に応じて適宜調整して使用される。
更に、前記多層配線基板２８の外部との導通用端子にパッド２６を用いたが、これに替えて半田バンプ、リード、又はピン等を使用することもできる。
尚、配線パターン４等を銅で形成したが、Ｎｉ及びその合金（Ｎｉ−Ｐ，Ｎｉ−Ｂ，Ｎｉ−Ｃｕ−Ｐ）、Ｃｏ及びその合金（Ｃｏ−Ｐ，Ｃｏ−Ｂ，Ｃｏ−Ｎｉ−Ｐ）、Ｓｎとその合金（Ｓｎ−Ｐｂ，Ｓｎ−Ｐｂ−Ｐｄ）、Ａｕ，Ａｇ，Ｐｄ，Ｐｔ，Ｒｈ，又はＲｕ等とそれらの合金の何れかを用いることもできる。
【００３５】
【発明の効果】
以上において説明した本発明の製造方法によれば、下層配線パターンの上方に形成された樹脂絶縁層のビアホール内を含む表面に複数回の表面粗化と、その間において樹脂絶縁層の上面を研磨する工程を行うため、追って形成されるビア底部の樹脂残りやビアの形状不良を確実に低減でき、ビアにおける導通不良を減らすことができる。同時に、樹脂絶縁層の上面に追って形成される上層配線パターンの密着強度を強固な状態で維持できる。
また、請求項４の発明によれば、樹脂絶縁層の上面に形成される上層配線パターンが強固に密着されるので、前記下層配線パターン及びビアと共に所定の立体回路を確実に形成することが可能となる。
【図面の簡単な説明】
【図１】（Ａ）乃至（Ｈ）は本発明の多層配線基板の製造工程の概略を示す部分断面図。
【図２】（Ａ）乃至（Ｄ）は本発明方法の各工程を示す部分端面図。
【図３】（Ａ）及び（Ｂ）は本発明により得られる各ビアを示す部分断面図。
【図４】（Ａ）乃至（Ｃ）は本発明により得られる異なるビアを示す部分断面図。
【図５】（Ａ）乃至（Ｆ）は本発明の異なる製造工程の概略を示す部分断面図。
【図６】（Ａ）及び（Ｂ）は従来の配線基板の製造工程を示す部分断面図、（Ｃ）及び（Ｄ）はこれにより形成されたビアを示す部分断面図。
【符号の説明】
４，３２，４２，５２……………………………下層配線パターン
６，１６，３４，３６，４４，４６，５４，５６…樹脂絶縁層
７，１７，３５，４５，５５，５７………………ビアホール
８………………………………………………導体薄膜
１０，６３………………………………………樹脂パターン
１２，１２′，１８，３８，４８，５８，６６……ビア
１４，６４………………………………………上層配線パターン
２０，３９，４９，５９…………………最上層配線パターン（上層配線パターン）
２８，６８……………………………………多層配線基板
６０……………………………………………導体層[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a multilayer wiring board having a wiring pattern formed via a resin insulating layer and a via penetrating through the resin insulating layer and conducting between the wiring patterns.
[0002]
[Prior art]
Generally, as shown in FIG. 6A, a multilayer wiring board 70 having a resin insulating layer interposed between wiring patterns has a photosensitive thickness of a predetermined thickness above a lower wiring pattern 72 formed on the upper surface of a core substrate 71. A resin paste is applied and dried to form a resin insulating layer 74.
As shown in FIG. 6B, a via hole 76 for exposing the upper surface of the lower wiring pattern 72 is formed by exposing and developing or laser processing the resin insulating layer 74, and then the upper surface of the resin insulating layer 74 is formed. An upper wiring pattern 82 is formed by electroless copper plating, electrolytic copper plating, exposure and development. At the same time, a via 78 that conducts between the upper and lower wiring patterns 82 and 72 is formed in the via hole 76.
[0003]
By the way, as shown in FIG. 6C, due to the variation in the processing when the via hole 76 is formed, a resin chip is formed between the bottom surface of the via 78 and the upper surface of the lower wiring pattern 72 due to insufficient opening of the via hole 76. 75 may remain.
Further, as shown in FIG. 6 (D), when a via hole 76 having a substantially cylindrical shape and a lower portion spreading obliquely is formed due to excessive development, the above-described poor surrounding with copper plating occurs, and a narrow portion is formed at the bottom of the via 78. The part 80 may be formed.
If the resin pieces 75 remain or the narrow portion 80 exists, conduction between the upper and lower wiring patterns 82 and 72 due to the via 78 becomes unstable, and a case where a three-dimensional circuit is not formed may occur.
[0004]
In order to prevent such a conduction failure, the upper surface of the resin insulating layer 74 in which the via hole 76 is formed is polished and removed to a thickness of about 5 μm to flatten the surface. , The surface of the resin insulating layer 74 was roughened. Thereafter, Sn / Pd colloid-type plating catalyst nuclei (not shown) were adsorbed on the surface of the resin insulating layer 74 whose surface was roughened, and the upper wiring pattern 82 was formed by the electroless copper plating or the like.
According to this method, the defect of the via 78 due to variation in processing when forming the via hole 76 can be slightly reduced, but it is still insufficient and lacks stability.
[0005]
When the surface of the resin insulating layer 74 is strongly roughened by the etching solution, the upper surface of the resin insulating layer 74 is excessively roughened, and the adhesion between the upper wiring pattern 82 formed thereon and the resin insulating layer 74 is increased. There was also a problem that the strength was reduced.
Further, a method of irradiating the laser strongly so as not to leave the resin piece 75 in the via hole 76 is conceivable. However, if the laser irradiation becomes excessive, the narrow portion 80 shown in FIG. 78 was formed.
[0006]
[Problems to be solved by the invention]
The present invention solves the above-mentioned problems in the prior art, eliminates resin residue and shape defects at the bottom portion of the via, corrects the shape of the via to ensure conduction between the upper and lower wiring patterns, and reduces the resin insulation. It is an object of the present invention to provide a method for manufacturing a multilayer wiring board in which the adhesion strength between a layer and an upper wiring pattern is maintained.
[0007]
[Means for Solving the Problems]
The present invention solves the above problem by performing surface roughening on a resin insulating layer a plurality of times and polishing the upper surface of the resin insulating layer during the roughening process, thereby obtaining the roughness between the surface in the via hole and the upper surface of the resin insulating layer. Are made with a focus on making the differences.
That is, the method for manufacturing a multilayer wiring board according to the present invention includes a method for forming a surface of a resin insulating layer formed above a lower wiring pattern and having at least one via hole formed on an upper surface of the lower wiring pattern. Polishing step, a polishing step of polishing and removing the upper surface of the surface-roughened resin insulating layer by a predetermined thickness, and thereafter, a surface roughening step of roughening the polished surface of the resin insulating layer, It is characterized by including.
[0008]
According to this method, the surface in the via hole is appropriately roughened, the resin residue on the lower wiring pattern is eliminated, the resin residue is reduced even in the case of a defective via hole, and the shape defect of the via hole is reduced. Can be. Therefore, it is possible to ensure conduction between the via formed later and the lower wiring pattern, and to maintain the adhesion strength between the resin insulating layer and the upper wiring pattern formed following the upper surface thereof.
The surface of the resin insulating layer includes both the upper surface and the surface in the via hole.
Further, the present invention also includes a method for manufacturing a multilayer wiring board in which the surface roughening step is performed a plurality of times, and the polishing step is performed at least once during the step.
In this case, the surface roughening step and the polishing step may be alternately repeated. However, if the polishing step is performed once immediately before the final surface roughening step, the roughness between the surface in the via hole and the upper surface of the resin insulating layer is reduced. Can be easily adjusted to a level suitable for each.
[0009]
Furthermore, the surface roughening step includes a method of manufacturing a multilayer wiring board in which the surface of the resin insulating layer is etched with permanganic acid, concentrated sulfuric acid, or chromic acid.
The above specifically includes potassium permanganate, potassium chromate and the like.
According to this, by using any one of the above-mentioned etching solutions according to the material of the resin insulating layer and adjusting the concentration and the etching time, the residual resin in the via hole is reduced, and the roughness of the upper surface of the resin insulating layer is reduced. Can be moderated.
[0010]
Further, before and after the polishing step, each surface roughening step can be performed using an etching solution having a different concentration or type. That is, since the main purpose of the surface roughening step performed before the polishing step is to completely remove the resin pieces remaining at the bottom of the via hole, the concentration of the etchant may be increased or the etching time may be increased. Alternatively, a different type of etchant from the one used in the surface roughening step after the polishing step may be used.
In this case, even if the upper surface of the resin insulating layer is excessively roughened, a roughened portion in the surface layer of the resin insulating layer is removed by a subsequent polishing step. Therefore, in the surface roughening step after the polishing step, it is preferable to use an etching solution that optimizes the adhesion strength between the upper wiring pattern and the resin insulating layer.
[0011]
Further, according to the present invention, after the subsequent or final surface roughening step, an upper wiring pattern is formed on the upper surface of the resin insulating layer, and a via that connects between the upper and lower wiring patterns is formed in the via hole. A method for manufacturing a multilayer wiring board including a step is also proposed.
According to this method, there is no resin residue or shape defect, or a small via can be formed, so that conduction between the upper and lower wiring patterns can be ensured. Further, the adhesion strength between the upper surface of the resin insulating layer and the upper wiring pattern can be maintained without lowering.
[0012]
Further, the step of forming the upper wiring pattern includes forming a conductive thin film on the upper surface of the resin insulating layer, forming a resin pattern of a dry film on the upper surface of the thin film, and forming an upper wiring pattern between the resin patterns. Thereafter, the resin pattern and the conductive thin film located on the bottom surface of the resin pattern may be removed.
Further, the step of forming the upper wiring pattern includes forming a conductive layer on the upper surface of the resin insulating layer, forming a resin pattern on the upper surface of the conductive layer, and etching the conductive layer to form the resin pattern. An upper layer wiring pattern that follows the pattern can also be used.
According to these, the upper wiring pattern can be firmly formed on the upper surface of the resin insulating layer according to its characteristics and the like, and the wiring pattern of a plurality of layers can be reliably formed.
[0013]
Embodiment
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view of each step schematically showing the method for manufacturing the multilayer wiring board.
As shown in FIG. 1A, first, a lower wiring pattern 4 is formed on both surfaces of a core substrate 1. The lower wiring pattern 4 is formed in a predetermined pattern by exposing and developing a photosensitive resin (not shown) formed on the upper surface thereof in advance and then etching. The wiring pattern 4 is made of copper having a thickness of 18 μm. In this case, in order to electrically connect the wiring patterns 4 on both surfaces, a cylindrical conductive portion 3 is formed simultaneously with the wiring pattern 4 in the through hole 2 opened in the core substrate 1. The inside of the conductive portion 3 is filled with a thermosetting resin (not shown) by mask printing. The core substrate 1 is made of a composite material of 0.8 mm thick BT (bismaleimide / trizian) resin and glass fiber cloth.
[0014]
Next, as shown in FIG. 1B, a photosensitive epoxy resin insulating layer 6 having a thickness of 55 μm is formed on the entire surface above the lower wiring pattern 4. Exposure and development are performed on a predetermined position of the resin insulating layer 6 to form a substantially conical via hole 7. At the bottom of the via hole 7, the upper surface of the lower wiring pattern 4 is exposed.
Depending on the above-described developing method for forming the via hole 7, the above-described resin residue may occur, or the via hole 7 itself may have a defective shape. Therefore, the surface of the resin insulating layer 6 including the via holes 7 is subjected to a plurality of times of surface roughening and upper surface polishing during the roughening. This will be described later in detail with reference to FIG.
[0015]
Next, as shown in FIG. 1C, the entire surface of the resin insulating layer 6 including the via hole 7 is covered with electroless copper plating to form a copper thin film 8 having a thickness of 1 μm. The copper thin film 8 forms a base 9 of a conical via in the via hole 7.
Further, when a photosensitive resin of a water-soluble dry film is adhered to the entire upper surface of the copper thin film 8 and exposed and developed, a plating resist (resin pattern) having a predetermined pattern is obtained as shown in FIG. ) 10 is formed.
Next, when the copper thin film 8 on which the plating resist 10 is formed is subjected to copper sulfate plating, the thickness of the copper thin film 8 not covered with the plating resist 10 is increased as shown in FIG. An upper wiring pattern 14 of 15 μm is formed. At the same time, a via 12 of the same thickness is formed on the base 9 of the copper thin film in the via hole 7.
[0016]
Thereafter, the plating resist 10 is peeled off by contact with an aqueous solution of NaOH, and in order to remove the exposed copper thin film 8, the upper surfaces thereof, including the upper wiring pattern 14 and the via 12, are etched to a thickness of about 2 μm. To remove. The state after the removal is shown in FIG. Thus, a three-dimensional circuit in which the upper and lower wiring patterns 14 and 4 are conducted by the via 12 is formed.
Further, as shown in FIG. 1 (G), a resin insulating layer 16 having a thickness of 55 μm is formed on the entire upper surface of the resin insulating layer 6, and a predetermined position of the insulating layer 16 is exposed and developed to substantially A conical via hole 17 is formed. The resin insulating layer 16 including the via hole 17 is also subjected to a plurality of times of surface roughening and upper surface polishing during the surface roughening.
[0017]
When a copper thin film and a plating resist (not shown) are formed on the upper surface of the resin insulating layer 16 and copper sulfate plating is applied thereto, the uppermost wiring pattern having a thickness of 15 μm is formed on the upper surface of the copper thin film without the plating resist. 20 are formed, and at the same time, a via 18 similar to the above is formed in the via hole 17. Thus, as shown in FIG. 1 (G), a three-dimensional circuit including the lower, upper, and uppermost wiring patterns 4, 14, and 20, and the vias 12 and 18 connecting these wiring patterns is formed.
Then, as shown in FIG. 1H, a solder resist 22 made of a photosensitive epoxy-modified resin is formed on the entire upper surfaces of the resin insulating layer 16 and the uppermost wiring pattern 20, and is exposed and developed to form the uppermost layer. An opening 24 is formed on the upper surface of the wiring pattern 20. A pad 26 composed of a Ni (Ni-P) plating layer and an Au plating layer was formed on the upper surface of the uppermost wiring pattern 20 exposed in the opening 24 by electroless plating to obtain a multilayer wiring board 28.
[0018]
In the multilayer wiring board 28, the surface of the resin insulating layers 6 and 16 and the surfaces of the via holes 7 and 17 are roughened twice or more in a process immediately before forming the upper / uppermost wiring patterns 14 and 20 and the vias 12 and 18. Is performed, resin residue and shape defects are less at the bottoms of the via holes 7 and 17. In addition, since the upper surfaces of the resin insulating layers 6 and 16 are polished in the meantime, the upper surfaces of the resin insulating layers 6 and 16 are not excessively roughened.
Therefore, the adhesion strength between the resin insulating layers 6 and 16 and the upper / uppermost wiring patterns 14 and 20 is also firmly maintained, so that the vias 12 and 18 surely connect the three wiring patterns 4, 14 and 20 to each other. A stable three-dimensional circuit can be provided.
The uppermost wiring pattern 20 is a relative name in the vertical direction. If the upper wiring pattern 14 is a lower wiring pattern, the upper wiring pattern 20 becomes the upper wiring pattern.
[0019]
Next, a characteristic manufacturing process of the present invention will be described with reference to FIG.
FIG. 2A is a schematic enlarged end view of the vicinity of the via hole 7 in FIG. 1B, in which the resin insulating layer 6 and the via hole 7 are formed above the lower wiring pattern 4.
First, a step of bringing the surface of the resin insulating layer 6 including the via hole 7 into contact with an etching solution to roughen the surface is performed. As the etching solution, an alkali / permanganate type etching solution (potassium permanganate: 45 g / liter, manufactured by Okuno Pharmaceutical Co., Ltd., trade name: OPC-1200 epoch 200 ml / liter) was used.
When the temperature of the etching solution is set to 80 ° C. and the surface of the resin insulating layer 6 is immersed for 4 minutes, the upper surface of the resin insulating layer 6 becomes a random uneven surface 6a as shown in FIG. Also has an uneven surface 7a.
[0020]
Next, the surface of the resin insulating layer 6 is neutralized. The surface of the resin insulating layer 6 (uneven surface 6a, 7a) is immersed at a liquid temperature of 45 ° C. for 4 minutes using OPC-1300 Nutriser (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.) for 4 hours. Neutralized.
Next, a step of polishing the upper surface of the resin insulating layer 6 is performed. In this polishing, the upper surface of the resin insulating layer 6 was removed by about 5 μm using a roll-shaped abrasive (# 320, trade name: IH Buff, manufactured by Nippon Tokushu Kenkyu).
As a result, as shown in FIG. 2C, the surface layer including the uneven surface 6a is removed from the upper surface of the resin insulating layer 6, and a flat surface 6b is formed. The thickness of the resin insulating layer 6 when the flat surface 6b was formed was approximately 50 μm.
[0021]
Further, a step of roughening the surface (6b, 7a) of the resin insulating layer 6 again is performed. This roughens the surface of the resin insulating layer 6 using the same etching solution as described above under the same conditions.
As a result, as shown in FIG. 2D, the surface of the via hole 7 becomes a roughened uneven surface 7b, and the upper surface of the resin insulating layer 6 becomes the same uneven surface 6a as described above.
The surface (6a, 7b) of the resin insulating layer 6 is also neutralized using the same neutralizing solution as described above. Thereafter, the respective steps shown in FIG. 1C and thereafter are performed.
Then, at the bottom of the via hole 7 which has been subjected to the surface roughening twice, all the resin pieces on the lower wiring pattern 4 are removed. In addition, the surface of the via hole 7 becomes a rough uneven surface 7b, and the corners become loose. Therefore, when electroless copper plating or the like is performed later, the turn of the copper plating forming the via 12 is ensured.
[0022]
Therefore, when the via hole 7 is formed in a substantially conical shape by appropriate development, the via 12 formed therein is formed in a substantially conical shape without the resin residue as shown in FIG. -Conductivity between the upper wiring patterns 4 and 14 is ensured.
Also, even if the via hole 7 is formed to have a substantially cylindrical shape and the lower portion is spread obliquely due to excessive development, the inclined corner portion of the lower portion of the via hole 7 is curved by surface roughening, and copper plating is applied. The performance is improved. Therefore, as shown in FIG. 3B, a via 12 'having no narrow portion at the bottom can be formed, and conduction between the lower and upper wiring patterns 4 and 14 can be secured.
On the other hand, on the upper surface of the resin insulating layer 6 which has been formed into the uneven surface 6a only by the subsequent surface roughening step, copper plating for forming the upper wiring pattern 14 is firmly adhered to the uneven surface 6a. Therefore, the adhesion strength between the wiring pattern 14 and the resin insulating layer 6 can be maintained as in the related art.
[0023]
Here, the effect of the embodiment of the present invention in which the steps of the surface roughening, the upper surface polishing, and the surface roughening are performed in the order of the steps will be specifically described together with a conventional example according to the related art and a comparative example.
Twenty multilayer wiring boards 28 of the example which were subjected to the steps of surface roughening, neutralization, upper surface polishing, surface roughening, and neutralization in this order were prepared. In each wiring board 28, 1000 vias 12 and 18 having a diameter of 100 μm are formed.
A probe (not shown) is brought into contact with the pads 26 of the wiring board 28, and a current is supplied from an external power supply to a three-dimensional circuit including 1000 vias 12 and 18 in each substrate 28, and the resistance value of the three-dimensional circuit is determined. Was measured to determine whether or not conduction was observed.
In addition, the adhesion strength of the upper and upper wiring patterns 14, 20 to the resin insulating layers 6, 16 was determined by measuring the peel strength based on the copper foil peeling strength (JIS: C6481).
[0024]
On the other hand, the same multilayer wiring board 28 as that of the embodiment in which the surface roughening, neutralization, surface roughening, and neutralization were performed, except that only the upper surface polishing step was removed from the steps performed in the above embodiment, was set as a comparative example. I prepared them. In each wiring board 28 of this comparative example, 1000 vias 12 and 18 having a diameter of 100 μm are formed. Further, as an example of the conventional technique, 20 wiring boards 28 having the same structure in which the resin insulating layers 6 and 16 were subjected to only surface roughening with the etching solution and neutralization with the neutralizing solution were prepared.
In these comparative examples and the conventional example, the presence / absence of conduction of the three-dimensional circuit including the vias 12 and 18 and the adhesion strength of the upper and uppermost wiring patterns 14 and 20 were measured in the same manner as described above.
From the measurement of the resistance value by the probe, it is determined that the wiring board 28 having the three-dimensional circuit having a non-conducting portion in at least one of the 1000 vias 12 and 18 is defective, and that the wiring of the conduction failure in the entire 20 wiring boards in each example is defective. The incidence of the substrate 28 was calculated. Further, the levels of the peel strengths of the upper and upper wiring patterns 14 and 20 were also determined for each example. Table 1 shows the measurement results of these examples, comparative examples, and conventional examples.
[0025]
[Table 1]

[0026]
According to Table 1, in the embodiment, the ratio of the wiring boards 28 in which the vias 12 and 18 are non-conductive is low, and the peel strength of the upper and uppermost wiring patterns 14 and 20 is all set to a firm adhesion strength. 1kg / cm ² That was all. From this result, it is understood that in the example, the vias 12 and the like with little resin residue and shape defects were obtained, and the adhesion strength of the upper wiring pattern 14 and the like was firmly maintained.
On the other hand, in the comparative example, the occurrence rate of the substrate having the conduction failure due to the vias 12 and the like was similarly low, but the adhesion strength of the upper wiring pattern 14 and the like was lower than the conventional example. This is presumably because in the comparative example, the polishing step between the two surface roughening steps was omitted, so that the upper surfaces of the resin insulating layers 6 and 16 were excessively etched, and the large brittle uneven surface 6a was formed.
Further, it has been confirmed that, in the conventional example, the adhesion strength of the upper wiring pattern 14 and the like is high, but the occurrence rate of defects due to the vias 12 and the like is as high as 50% or more, and the productivity is lowered.
[0027]
From these results, in the embodiment according to the present invention, of the surfaces of the resin insulating layers 6 and 16, the surfaces of the via holes 7 and 17 are roughened twice to cause resin residue and shape defects at the bottoms of the vias 12 and 18. It can be easily understood that the upper surface of the resin insulating layer 6 and the like are polished in the middle, and the surface of the upper layer wiring pattern 14 and the like are prevented from deteriorating by only one roughening.
In addition, the present invention is not limited to the order of the steps of surface roughening, upper surface polishing, and surface roughening, as well as a form in which the surface roughening step is performed three times or more and the upper surface is polished in the meantime, An embodiment in which the upper surface is polished only immediately before the final surface roughening as three or more times is also included. In short, any method may be used in which the surface of the via hole 7 or the like is roughened a plurality of times, while the upper surface of the resin insulating layer 6 or the like is roughened only substantially once.
[0028]
FIG. 4 relates to different forms of vias according to the invention.
FIG. 2A shows a via penetrating the upper and lower resin insulating layers. First, a lower wiring pattern 32 is formed on the upper surface of the same core substrate 30, and resin insulating layers 34 and 36 made of photosensitive epoxy are formed thereon. An upper wiring pattern is formed at a position (not shown) on the upper surface of the resin insulating layer 34. Next, in the resin insulating layers 34 and 36 on the upper surface of the lower wiring pattern 32, a loose conical via hole 35 is formed by exposure and development. Further, the surface of the resin insulating layer 36 (34), that is, the upper surface thereof and the surface of the via hole 35 are subjected to the surface roughening a plurality of times, and the polishing is performed on the upper surface of the resin insulating layer 36 therebetween. Then, after performing electroless copper plating or the like on the resin insulating layer 36 and forming a photosensitive resin layer (not shown), exposure, development, and etching are performed to form the uppermost wiring pattern 39. At the same time, a substantially conical via 38 that conducts between the lower and uppermost wiring patterns 32 and 39 can be obtained in the via hole 35.
[0029]
In FIG. 4B, a lower wiring pattern 42 is formed on the upper surface of the core substrate 40, and resin insulating layers 44 and 46 similar to the above are formed above the lower wiring pattern 42. An upper wiring pattern is formed at a position (not shown) on the upper surface of the resin insulating layer 44. Next, a laser is irradiated downward from above to the resin insulating layers 44 and 46 to form a cylindrical via hole 45 exposing the upper surface of the lower wiring pattern 42. Further, the surface roughening is performed a plurality of times on the upper surface of the resin insulating layer 46 and the surface of the via hole 45, and the upper surface of the resin insulating layer 46 is polished between them. Then, the uppermost wiring pattern 49 and the columnar via 48 are formed by performing electroless plating or the like.
[0030]
Further, FIG. 4C relates to vias formed by different methods. First, a lower wiring pattern 52 is formed on the upper surface of the core substrate 50, and a resin insulating layer 54 is formed above the lower wiring pattern 52. Exposure and development are performed on the resin insulating layer 54 to form a loose conical via hole 55 on the lower wiring pattern 52. Next, the upper surface of the resin insulating layer 54 and the surface of the via hole 55 are subjected to surface roughening a plurality of times, during which the upper surface of the resin insulating layer 54 is polished to form an upper wiring pattern at a position (not shown). At this time, no via is formed because the plating resist is formed in the via hole 55.
Next, a resin insulating layer 56 is formed on the upper surface of the resin insulating layer 54, and a via hole 57 that overlaps the position where the via hole 55 was located is formed by exposure and development. The via hole 57 is formed substantially vertically on the bottom side by strengthening the developing process.
[0031]
The surface of the via hole 57 and the upper surface of the resin insulating layer 56 are roughened a plurality of times, and the upper surface of the resin insulating layer 56 is polished between them. Then, the uppermost wiring pattern 59 is formed by performing electroless plating or the like, and a via 58 having a two-stage taper in cross section is formed.
These vias 38, 48, 58 have a cross-sectional shape following the via holes 35, 45, 57, and at the bottom thereof, the resin residue and narrow shape defects are rarely formed. Accordingly, it is possible to directly conduct between the upper and lower wiring patterns 39 and the like which are vertically separated from each other.
[0032]
The present invention is not limited to the embodiments described above.
For example, as shown in FIGS. 5A and 5B, a lower wiring pattern 4 is formed on both surfaces of a core substrate 1 as in FIG. 1, a resin insulating layer 6 is formed thereon, and a via hole 7 is formed. After that, a material that has been subjected to the surface roughening a plurality of times and polished in the meantime is prepared.
Next, as shown in FIG. 5C, the entire surface of the resin insulating layer 6 is subjected to electroless copper plating or the like to form a copper film (conductor layer) 60 having a thickness of several tens of μm. As shown in FIG. 5D, an insulating layer 62 made of a photosensitive resin is formed on the upper surface of the copper film 60.
Next, the resin insulating layer 62 is exposed and developed to form a predetermined resin pattern 63 as shown in FIG. Then, by immersing the resin pattern 63 and the copper film 60 in an etching solution, the upper wiring pattern 64 and the via 66 are formed at positions protected by the resin pattern 63 as shown in FIG. Is done. By a similar method, a multi-layer wiring board 68 similar to the wiring board 28 can be formed by forming a resin insulating layer, an uppermost wiring pattern, and the like (not shown).
[0033]
The core substrate 1 of the multilayer wiring board 28 includes a composite material (glass-BT resin material) of BT resin and glass fiber cloth, a glass-epoxy material, a glass-PPE material, a paper-epoxy material, and the like. Or a resin such as epoxy, BT resin, polyimide, or PPE.
Further, the core substrate 1 is not limited to the above resin, but may be made of ceramic. When such a rigid ceramic core substrate 1 is used, the same number of resin insulating layers 6, 16 and the lower, upper, and uppermost wiring patterns 4, 14, 20 are not formed on both surfaces thereof, and the number of layers is different from each other. Alternatively, the resin insulating layer 6 and the like and the lower and upper wiring patterns 4 and 14 may be formed only on one surface of the core substrate 1. In the latter case, the through holes 2 and the like can be omitted.
Furthermore, the core substrate 1 is not an essential element. For example, a resin multilayer wiring board may be manufactured by forming a lower wiring pattern 4 on the upper surface of an existing resin insulating layer and sequentially performing the above-described steps. good. Alternatively, it is also possible to form a lower multilayer wiring pattern 4 on the upper surface of an existing ceramic layer or ceramic multilayer wiring substrate and sequentially perform the above-described steps to manufacture a composite multilayer wiring substrate of ceramic and resin.
[0034]
Further, the etching solution used for the surface roughening may be a solution containing permanganic acid, concentrated sulfuric acid, or chromic acid, and may be appropriately adjusted according to the uneven surface to be formed on the surface of the resin insulating layer. Used.
Further, although the pad 26 is used as a terminal for conduction with the outside of the multilayer wiring board 28, a solder bump, a lead, a pin, or the like may be used instead.
Although the wiring pattern 4 and the like were formed of copper, Ni and its alloys (Ni-P, Ni-B, Ni-Cu-P), Co and its alloys (Co-P, Co-B, Co-Ni- P), Sn and its alloys (Sn-Pb, Sn-Pb-Pd), Au, Ag, Pd, Pt, Rh, Ru, or the like and any of these alloys can also be used.
[0035]
【The invention's effect】
According to the manufacturing method of the present invention described above, the surface of the resin insulating layer formed above the lower wiring pattern is roughened a plurality of times including the inside of the via hole, and the upper surface of the resin insulating layer is polished between them. Since the process is performed, resin residue at the bottom of the via formed later and defective shape of the via can be reliably reduced, and defective conduction in the via can be reduced. At the same time, the adhesion strength of the upper wiring pattern formed following the upper surface of the resin insulating layer can be maintained in a strong state.
According to the fourth aspect of the present invention, since the upper wiring pattern formed on the upper surface of the resin insulating layer is firmly adhered, a predetermined three-dimensional circuit can be reliably formed together with the lower wiring pattern and the via. It becomes.
[Brief description of the drawings]
FIGS. 1A to 1H are partial cross-sectional views schematically showing a manufacturing process of a multilayer wiring board according to the present invention.
FIGS. 2A to 2D are partial end views showing each step of the method of the present invention.
FIGS. 3A and 3B are partial cross-sectional views showing vias obtained by the present invention.
4A to 4C are partial sectional views showing different vias obtained by the present invention.
5 (A) to 5 (F) are partial cross-sectional views schematically showing different manufacturing steps of the present invention.
FIGS. 6A and 6B are partial cross-sectional views showing a conventional manufacturing process of a wiring board, and FIGS. 6C and 6D are partial cross-sectional views showing vias formed by the steps.
[Explanation of symbols]
4, 32, 42, 52 ... lower-layer wiring pattern
6, 16, 34, 36, 44, 46, 54, 56 ... resin insulating layer
7, 17, 35, 45, 55, 57 via holes
8 ………………………… Conductor thin film
10, 63 ............................................ Resin pattern
12, 12 ', 18, 38, 48, 58, 66 ... Via
14, 64 ……………………………… Upper layer wiring pattern
20, 39, 49, 59 ... Top layer wiring pattern (upper layer wiring pattern)
28, 68 ............ Multi-layer wiring board
60 …………………………… Conductor layer

Claims (4)

A surface roughening step of roughening the surface of a resin insulating layer formed above the lower wiring pattern and having at least one via hole formed on the upper surface of the lower wiring pattern;
A polishing step of polishing and removing the upper surface of the surface-roughened resin insulating layer by a predetermined thickness,
And thereafter, a surface roughening step of roughening the polished surface of the resin insulating layer. The method according to claim 1, wherein the surface roughening step is performed a plurality of times, and the polishing step is performed at least once during the plurality of times. 3. The method according to claim 1, wherein the surface roughening step etches a surface of the resin insulating layer with permanganic acid, concentrated sulfuric acid, or chromic acid. 4. Forming the upper wiring pattern on the upper surface of the resin insulating layer after the subsequent or final surface roughening step, and forming a via in the via hole to conduct between the upper and lower wiring patterns. The method for manufacturing a multilayer wiring board according to claim 1, wherein:

Images