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JP2008135570A - Method of manufacturing wiring board - Google Patents

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JP2008135570A
JP2008135570A JP2006320674A JP2006320674A JP2008135570A JP 2008135570 A JP2008135570 A JP 2008135570A JP 2006320674 A JP2006320674 A JP 2006320674A JP 2006320674 A JP2006320674 A JP 2006320674A JP 2008135570 A JP2008135570 A JP 2008135570A
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wiring
layer
resist film
thickness
wiring board
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JP2008135570A5 (en
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Shigeji Muramatsu
茂次 村松
Mikiyuki Komatsu
幹幸 小松
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of efficiently manufacturing a wiring board having wiring layers different in wiring thickness control levels on two faces. <P>SOLUTION: Plating feeding layers are formed on insulating layers 3 on both faces of an insulating substrate 1 and resist films 5 are laminated on them at uniform thickness. The respective resist films 5 are patterned and the plating feeding layers are exposed to openings. The wiring layers 6a exceeding thickness of the resist films 5 are formed on one exposed feeding layer and the wiring layers 6b smaller than thickness of the resist film 5 are formed on the other feeding layer by deposition of a wiring material by electrolytic plating. Part of the wiring layers 6a on one feeding layer is removed to thickness similar to the resist film 5. The wiring layers 6a are made into the same thickness as the resist films 5 and the resist films 5 on both faces and the feeding layers below them are removed. Thus, the wiring layers 6a and 6b are formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、配線基板の製造方法、特にフィルムレジストを使用する配線形成工程を含む配線基板の製造方法に関する。   The present invention relates to a method for manufacturing a wiring board, and more particularly to a method for manufacturing a wiring board including a wiring forming process using a film resist.

配線基板に要求される電気的特性は年々厳しくなっており、特に電気的特性に影響の大きい配線厚を設計値どおりに作製し、製品間のバラツキも小さくすることは、必須となってきている。一方で、配線基板の設計においては、所定の電気特性を得るために、1つの製品内においても幅の異なる配線が必要になってきている。また配線基板の製造方法においては、生産性を向上するため、最終段階までは複数の個別製品を配置した大型のワークで処理が行われている。これらの設計、処理は、1つの基板内の個々の製品に関する均一性を低下させるため、配線を形成するめっき厚さのバツラキを増加する原因となる。   The electrical characteristics required for wiring boards are becoming stricter year by year, and it is indispensable to produce wiring thicknesses that have a great influence on the electrical characteristics as designed and to reduce variations between products. . On the other hand, in designing a wiring board, wirings having different widths are required in one product in order to obtain predetermined electrical characteristics. In the method of manufacturing a wiring board, in order to improve productivity, processing is performed with a large work in which a plurality of individual products are arranged until the final stage. Since these designs and processes reduce the uniformity of individual products in one substrate, it causes an increase in the variation in plating thickness for forming the wiring.

配線基板の配線の形成においては、通常、配線パターンを形成するためのドライフィルムレジスト(DFR)膜に対し、配線めっきはその厚さよりも低く形成される。この場合、製品ごとの配線厚さのバラツキが生じやすい。その一方、管理された均一な厚さで供給を受けることができるDFRの表面より飛出した凸部を持つめっきを形成し、研磨あるいはエッチングなどで凸部を除去することで、配線厚さを均一にする技術が提案されている。   In the formation of the wiring on the wiring substrate, the wiring plating is usually formed lower than the thickness of the dry film resist (DFR) film for forming the wiring pattern. In this case, variations in wiring thickness for each product are likely to occur. On the other hand, by forming plating with protrusions protruding from the surface of the DFR that can be supplied with a controlled uniform thickness, and removing the protrusions by polishing or etching, the wiring thickness can be reduced. A technique for making it uniform has been proposed.

このような、研磨やエッチングにより配線厚さを設計厚さに調整する従来技術について、図4を参照して説明する。   A conventional technique for adjusting the wiring thickness to the designed thickness by polishing or etching will be described with reference to FIG.

図4において、配線基板の基材41上にDFR42を被覆し、DFR42をフォトリソグラフィーで露光・現像して溝パターン43を形成し、電解銅めっきによりパターン溝43内に配線材料である銅44を析出させて、銅44を最終の配線厚さよりも厚く且つDFR42の表面より例えば厚さtだけ飛び出すように形成する。その後、DFR42の表面より飛び出した銅めっきの凸部を研磨、あるいはエッチングにより加工して設計厚さまで配線厚さを薄くする。研磨には、バフ、ベルトサンダー等を使用する。   In FIG. 4, a DFR 42 is coated on a substrate 41 of a wiring board, the DFR 42 is exposed and developed by photolithography to form a groove pattern 43, and copper 44 as a wiring material is formed in the pattern groove 43 by electrolytic copper plating. The copper 44 is formed so as to be thicker than the final wiring thickness and to protrude from the surface of the DFR 42 by a thickness t, for example. Thereafter, the copper plating protrusions protruding from the surface of the DFR 42 are polished or processed by etching to reduce the wiring thickness to the design thickness. For polishing, a buff, a belt sander or the like is used.

例えば、特許文献1(特開平06−053660号公報)には、レジストのパターニング後セミアディディブ法により行うめっきをレジストの厚さより厚く析出後、研磨によりめっきの突出部を除去し平坦化することが記載されている。   For example, in Patent Document 1 (Japanese Patent Application Laid-Open No. 06-053660), after plating a resist, the plating performed by the semi-additive method is deposited to be thicker than the thickness of the resist, and then the plating protrusions are removed and planarized by polishing. Is described.

特許文献2(特開2002−076620号公報)には、レジストのパターニング後セミアディディブ法により行うめっきをレジストの厚さより厚く析出後、レジスト上に配置したストッパーメタルを利用する研磨によりめっきの厚さを揃えることが記載されている。   In Patent Document 2 (Japanese Patent Laid-Open No. 2002-0776620), after the resist patterning, plating performed by the semi-additive method is deposited to be thicker than the resist thickness, and then the thickness of the plating is polished by using a stopper metal disposed on the resist. It is described that the same.

特許文献3(特開2003−258410号公報)には、レジストのパターニング後セミアディディブ法によりめっきをレジストの厚さより厚く析出後、機械研磨によりめっきの突出部を除去し、レジストの厚さを基準として配線の高さを揃えることが記載されている。   In Patent Document 3 (Japanese Patent Application Laid-Open No. 2003-258410), after patterning a resist, the plating is deposited to be thicker than the resist thickness by a semi-additive method, and then the plating protrusions are removed by mechanical polishing, and the resist thickness is adjusted. As a reference, it is described that the height of the wiring is made uniform.

特許文献4(特開2005−277258号公報)には、めっきレジストのパターニング後、レジストを含む全面にめっきシード層を形成し、レジストより高くめっきを析出した後、物理的又は化学的研磨によりめっきを研磨しレジストを露出させて、その後レジストを剥離することが記載されている。   In Patent Document 4 (Japanese Patent Application Laid-Open No. 2005-277258), after patterning a plating resist, a plating seed layer is formed on the entire surface including the resist, plating is deposited higher than the resist, and then plated by physical or chemical polishing. Is exposed to expose the resist, and then the resist is peeled off.

特開平06−053660号公報Japanese Patent Laid-Open No. 06-053660 特開2002−076620号公報Japanese Patent Laid-Open No. 2002-076620 特開2003−258410号公報JP 2003-258410 A 特開2005−277258号公報JP 2005-277258 A

銅(Cu)などの配線と比較して非常に加工されやすいDFRを加工することなく、配線材料のみをDFR膜と同じ厚さまで加工することは非常に難しい。例えば、機械的研磨の場合、めっき金属よりもDFRの方がはるかに加工速度が高いため、DFR膜を加工停止層として、その表面に沿って加工を完了させることは非常に難しい。   It is very difficult to process only the wiring material to the same thickness as the DFR film without processing a DFR that is very easy to process compared to a wiring such as copper (Cu). For example, in the case of mechanical polishing, since the processing speed of DFR is much higher than that of plated metal, it is very difficult to complete the processing along the surface using the DFR film as a processing stop layer.

そこで、本願の発明者らは、めっきによる配線をDFRよりも高く形成した後、樹脂製のパッドと酸系スラリーを使用する研磨により、DFRの厚さを基準として配線厚さを均一にする手法を提案した(特願2006−036530)。   Therefore, the inventors of the present application have made a method of making the wiring thickness uniform based on the thickness of the DFR by forming a wiring by plating higher than the DFR and then polishing using a resin pad and acid-based slurry. Was proposed (Japanese Patent Application No. 2006-036530).

配線基板の各面は、通常、別個の電気・電子部品に接続される(例えば、片側は半導体チップなどに、反対側は別の実装基板に接続される)。そのため、両面で同じ配線厚さ制御レベルが要求される場合はむしろ稀である。ところが、樹脂製の配線基板は、通常、中心のコア基板の両面に1層ずつ同時プロセスを適用して作製される。従って、片面の配線層だけ配線厚さの高度の制御が必要な場合であっても、通常は両面で同じ厚さのDFRを使用し、同じめっき厚で配線を形成している。そのため、先に説明した従来技術による場合も、発明者らが提案した新しい技術による場合も、それほど高度の配線厚さの制御は不要な配線層に対し、研磨などの追加工程が発生するため、生産性低下、製造コスト上昇の原因となっている。   Each surface of the wiring board is usually connected to a separate electric / electronic component (for example, one side is connected to a semiconductor chip and the other side is connected to another mounting board). Therefore, it is rare that the same wiring thickness control level is required on both sides. However, a resin wiring board is usually manufactured by applying a simultaneous process one layer on each side of a central core board. Therefore, even when a high degree of control of the wiring thickness is necessary only for the wiring layer on one side, the wiring is usually formed with the same plating thickness using the DFR having the same thickness on both sides. Therefore, both in the case of the prior art described above and in the case of the new technique proposed by the inventors, an additional process such as polishing occurs for the wiring layer that does not require a very high wiring thickness control. This is a cause of reduced productivity and increased manufacturing costs.

本発明の目的は、このような問題を解決して、二つの面に配線厚さ制御レベルを異にする配線層を有する配線基板を効率よく製造するのを可能にする方法を提供することである。   An object of the present invention is to solve such a problem and to provide a method that enables efficient production of a wiring board having wiring layers having different wiring thickness control levels on two surfaces. is there.

本発明が提供する配線基板製造方法は、絶縁基板(コア基板)の両面に所定数の配線層を、絶縁層を間に挟み、積層して配線基板を製造する方法であって、配線層の形成を、
両面の絶縁層上にめっき用給電層を形成し、その上にレジスト膜を均一厚で積層する工程、
各レジスト膜をパターニングし、それにより形成した開口部にめっき用給電層を露出させる工程、
電解めっきにより配線材料を析出させて、露出した一方の給電層上にはレジスト膜の厚さを超える配線層を、他方の給電層上にはレジスト膜の厚さより低い配線層を形成する工程、
一方の給電層上の配線層の一部をレジスト膜と同じ厚さまで除去し、配線層をレジスト膜と同じ厚さにする工程、
両面のレジスト膜及びその下のめっき給電層を除去する工程、
により行うことを特徴とする。
A wiring board manufacturing method provided by the present invention is a method for manufacturing a wiring board by laminating a predetermined number of wiring layers on both sides of an insulating substrate (core substrate) with an insulating layer interposed therebetween, Formation,
Forming a plating power supply layer on the insulating layers on both sides, and laminating a resist film thereon with a uniform thickness;
Patterning each resist film and exposing the power feeding layer for plating in the opening formed thereby,
A step of depositing a wiring material by electrolytic plating and forming a wiring layer exceeding the thickness of the resist film on the exposed one power supply layer and forming a wiring layer lower than the thickness of the resist film on the other power supply layer;
Removing a part of the wiring layer on one power feeding layer to the same thickness as the resist film, and making the wiring layer the same thickness as the resist film;
Removing the resist film on both sides and the plating power feeding layer underneath,
It is characterized by performing by.

本発明の配線基板製造方法の一つの態様では、レジスト膜を積層する工程において、一方の給電層の上には薄いレジスト膜を、他方の給電層の上には厚いレジスト膜を積層しておくことにより、一方の給電層上にレジスト膜の厚さを超える配線層、他方の給電層上にレジスト膜の厚さより低い配線層を形成することができる。この場合、二つの面の給電層上に析出させる配線材料の高さは、同一であっても異なっていてもよい。   In one aspect of the wiring board manufacturing method of the present invention, in the step of laminating a resist film, a thin resist film is laminated on one power feeding layer, and a thick resist film is laminated on the other power feeding layer. Thus, a wiring layer exceeding the thickness of the resist film can be formed on one power supply layer, and a wiring layer lower than the thickness of the resist film can be formed on the other power supply layer. In this case, the height of the wiring material deposited on the power feeding layers on the two surfaces may be the same or different.

本発明の配線基板製造方法のもう一つの態様では、電解めっきによる配線材料の析出により配線層を形成する工程において、配線材料を一方の給電層の上には厚く析出させ、他方の給電層の上には薄く析出させることにより、一方の給電層上にレジスト膜の厚さを超える配線層、他方の給電層上にレジスト膜の厚さより低い配線層を形成することができる。二つの面に厚さの異なる配線材料を析出させるのは、各面に対し異なる条件で電解めっき処理を施すことにより行うことができる。この場合、二つの面のレジスト膜の厚さは、同一であっても異なっていてもよい。   In another aspect of the wiring board manufacturing method of the present invention, in the step of forming the wiring layer by depositing the wiring material by electrolytic plating, the wiring material is deposited thickly on one power feeding layer, and the other power feeding layer By depositing a thin film on the top, a wiring layer exceeding the thickness of the resist film can be formed on one power supply layer, and a wiring layer lower than the thickness of the resist film can be formed on the other power supply layer. The wiring materials having different thicknesses can be deposited on the two surfaces by subjecting each surface to electrolytic plating treatment under different conditions. In this case, the thicknesses of the resist films on the two surfaces may be the same or different.

本発明によれば、二つの面に配線厚さ制御レベルを異にする配線層を有する配線基板を効率よく製造することができる。   According to the present invention, it is possible to efficiently manufacture a wiring board having wiring layers having different wiring thickness control levels on the two surfaces.

図1(a)〜1(c)を参照して、本発明の基本概念を説明する。
本発明の配線基板製造方法の重要な特徴は、レジスト膜をマスクとする電解めっきで配線層を形成する工程において、片側にはレジスト膜の厚さを超える配線層、反対側にはレジスト膜の厚さより低い配線層を形成することである。図1(a)は、片側にレジスト膜5の厚さを超える配線層6a、反対側にレジスト膜5の厚さより低い配線層6bを形成した、製造中の配線基板の例を示している。この図において、配線層6a、6bは、セミアディティブ法を利用して、コア基板1の各面の絶縁層3上のめっき給電層として働くシード層(図示せず)の上に、レジスト膜5をマスクとする電解めっきにより形成されている。電解めっきによる配線材料の析出で形成したままの配線の上部は、いくらか丸みを帯びており、図1(a)(及び以下で参照する図)では、これを示すため、電解めっきで形成したままの配線の上部に誇張した丸みをつけている。
The basic concept of the present invention will be described with reference to FIGS. 1 (a) to 1 (c).
An important feature of the method for manufacturing a wiring board of the present invention is that, in the step of forming a wiring layer by electrolytic plating using a resist film as a mask, the wiring layer exceeds the thickness of the resist film on one side, and the resist film on the other side. It is to form a wiring layer lower than the thickness. FIG. 1A shows an example of a wiring substrate being manufactured in which a wiring layer 6a exceeding the thickness of the resist film 5 is formed on one side and a wiring layer 6b lower than the thickness of the resist film 5 is formed on the opposite side. In this figure, wiring layers 6a and 6b are formed on a resist film 5 on a seed layer (not shown) serving as a plating power supply layer on the insulating layer 3 on each surface of the core substrate 1 by using a semi-additive method. It is formed by the electroplating which uses as a mask. The upper part of the wiring as formed by the deposition of the wiring material by electrolytic plating is somewhat rounded. In FIG. 1 (a) (and the figure referred to below), this is shown by being formed by electrolytic plating. An exaggerated round is added to the top of the wiring.

高度の厚さ制御を求められる配線基板上面の配線層6aは、電解めっき後の配線材料の析出高さにバラツキがあっても、絶縁膜3の厚さを超えて飛出した部分を、例えば研磨により除去して、図1(b)に示したようにその厚さを絶縁膜3の管理された厚さに揃えられる。それほどの厚さ制御を必要としない配線基板下面の配線層6bは、研磨等の処理を施すことなく、そのまま使用される。   The wiring layer 6a on the upper surface of the wiring board that requires a high degree of thickness control has a portion protruding beyond the thickness of the insulating film 3, for example, even if the deposition height of the wiring material after electrolytic plating varies. By removing by polishing, the thickness is adjusted to the controlled thickness of the insulating film 3 as shown in FIG. The wiring layer 6b on the lower surface of the wiring board that does not require much thickness control is used as it is without being subjected to a treatment such as polishing.

その後、図1(c)に示したように、両面の絶縁膜3とその下のシード層(図示せず)を除去して、配線層6a、6bの形成を完了する。   Thereafter, as shown in FIG. 1C, the insulating films 3 on both sides and the seed layer (not shown) thereunder are removed to complete the formation of the wiring layers 6a and 6b.

基板の一方にレジスト膜の厚さを超える配線層、他方にレジスト膜の厚さより低い配線層を形成するのには、一方のレジスト膜を薄く、他方のレジスト膜を厚く形成しておくのが有効である。また、配線材料を基板の一方に薄く、他方に厚く析出させることも有効である。   In order to form a wiring layer exceeding the thickness of the resist film on one side of the substrate and a wiring layer lower than the thickness of the resist film on the other side, it is necessary to form one resist film thin and the other resist film thick. It is valid. It is also effective to deposit the wiring material thinly on one side of the substrate and thickly on the other side.

本発明の方法では、レジスト膜として、管理された均一な厚さで供給されるドライフィルムレジスト(DFR)を用いるのが好適である。とは言え、場合によっては、DFR以外の材料のレジスト膜を用いることも可能である。   In the method of the present invention, it is preferable to use a dry film resist (DFR) supplied with a controlled uniform thickness as the resist film. However, in some cases, a resist film made of a material other than DFR may be used.

配線材料としては、通常の配線基板で用いられる材料を使用することができる。代表的な配線材料として、銅を挙げることができる。   As a wiring material, the material used with a normal wiring board can be used. A typical wiring material is copper.

一方の配線層の厚さをレジスト膜の厚さに揃えるため、その一部を除去するには、研磨、エッチングなどの一般的な手法を利用することができる。本発明にとって好ましいのは、レジスト膜に損傷を与えずに、レジスト膜の厚さを超えて突出した部分の配線材料を優先的に除去して、レジスト膜の厚さを基準として均一な配線厚さにまで研磨することができる方法である。そのような方法の一例として、樹脂製の研磨パッドを用いる化学機械研磨(CMP)を挙げることができる。   Since the thickness of one wiring layer is made equal to the thickness of the resist film, general methods such as polishing and etching can be used to remove a part of the wiring layer. Preferably, the present invention preferentially removes the wiring material protruding beyond the thickness of the resist film without damaging the resist film, and uniform wiring thickness based on the resist film thickness. It is a method that can be further polished. An example of such a method is chemical mechanical polishing (CMP) using a resin polishing pad.

そのような化学機械研磨では、ポリウレタンを含浸させたポリエステル不織布繊維、又はポリウレタン樹脂発泡体を、研磨パッドとして用いるのが好ましい。このようにポリウレタンを含むパッド材料には、内部に空気層があり、そのため研磨スラリーの保持性が向上し、有利である。   In such chemical mechanical polishing, it is preferable to use a polyester nonwoven fabric fiber impregnated with polyurethane or a polyurethane resin foam as a polishing pad. Thus, the pad material containing polyurethane has an air layer inside, which is advantageous in that the retention of the polishing slurry is improved.

研磨スラリーとしては、酢酸、クエン酸、リンゴ酸、酒石酸、又はそれらの混合物などの有機酸を主成分とするものが好適である。砥粒としては、SiO2粉末、アルミナ粉末、又はそれらの混合物を好適に使用することができる。 As the polishing slurry, those having an organic acid such as acetic acid, citric acid, malic acid, tartaric acid, or a mixture thereof as a main component are suitable. As the abrasive grains, SiO 2 powder, alumina powder, or a mixture thereof can be suitably used.

本発明により配線を形成した基板は、最上層の配線層を覆う保護絶縁層とその表面に露出したパッドなどを形成して完成される。完成した配線基板は、半導体チップなどの他の電子・電気部品や、別の実装基板などへ接続することができる。   A substrate on which wiring is formed according to the present invention is completed by forming a protective insulating layer covering the uppermost wiring layer and a pad exposed on the surface thereof. The completed wiring board can be connected to another electronic / electrical component such as a semiconductor chip or another mounting board.

実施例により、本発明をより詳しく説明するが、以下の例は本発明を限定するものではない。
本発明の製造方法の各工程で利用する手法自体はいずれも既知のものであり、それらについて必要以上には説明しない。本発明で使用する材料も、特に制限されず、以下の例で挙げるもの以外に、通常の配線基板で用いられるものを使用することができる。
The present invention will be described in more detail by way of examples, but the following examples are not intended to limit the present invention.
All the techniques themselves used in each step of the production method of the present invention are known and will not be described more than necessary. The material used in the present invention is not particularly limited, and materials used in ordinary wiring boards can be used in addition to those described in the following examples.

〔実施例1〕
図2(a)に示したように、製造過程にある配線基板20の両側の絶縁層21(上下の配線層の接続用の孔22が形成してある)の全面に、無電解めっきにより銅(Cu)のシード層(図示せず)を薄く形成後、配線層形成用にパターン化したレジスト膜23a、23bを形成する。レジスト膜23a、23bは、各面のシード層上に所定厚のドライフィルムレジスト(DFR)を貼り付け、フォトリソグラフィーの手法でパターン化して形成することができる。上面のレジスト膜23aが下面のレジスト膜23bより厚くなるように、上面用と下面用のDFRは厚さが異なる。
[Example 1]
As shown in FIG. 2 (a), copper is electrolessly plated on the entire surface of the insulating layer 21 (both holes 22 for connecting the upper and lower wiring layers) on both sides of the wiring substrate 20 in the manufacturing process. After a thin (Cu) seed layer (not shown) is formed, resist films 23a and 23b patterned for forming a wiring layer are formed. The resist films 23a and 23b can be formed by attaching a dry film resist (DFR) having a predetermined thickness on the seed layer on each surface and patterning it by a photolithography technique. The upper and lower DFRs have different thicknesses so that the upper resist film 23a is thicker than the lower resist film 23b.

レジスト膜23a、23bの開口部24a、24bに露出したシード層(図示せず)を給電層として使用する電解めっきにより、上面では薄いレジスト膜23aの厚さを超えて、下面では厚いレジスト膜23bよりも低く、シード層(図示せず)上に銅(Cu)の配線材料25a、25bを析出させる(図2(b))。両面の配線材料25a、25bの高さは同じでよい。   By electrolytic plating using a seed layer (not shown) exposed in the openings 24a and 24b of the resist films 23a and 23b as a power feeding layer, the resist film 23b exceeds the thickness of the thin resist film 23a on the upper surface and is thick on the lower surface. The copper (Cu) wiring materials 25a and 25b are deposited on the seed layer (not shown) (FIG. 2B). The heights of the wiring materials 25a and 25b on both sides may be the same.

上面のレジスト膜23aより上に突出した部分の配線材料を研磨により除去して、図2(c)に示したように厚さをレジスト膜23aの厚さに揃え、上面の配線層26aを形成する。例えば、ポリウレタン含浸のポリエステル不織布繊維の研磨パッドと、有機酸(例えば酢酸)及びアルミナ砥粒の研磨スラリーとを使用する化学機械研磨により、レジスト膜23aから突出した配線材料を、レジスト膜23aに損傷を与えることなく、除去することができる。   The portion of the wiring material protruding above the resist film 23a on the upper surface is removed by polishing, and the thickness is made equal to the thickness of the resist film 23a as shown in FIG. 2C to form the upper wiring layer 26a. To do. For example, the wiring material protruding from the resist film 23a is damaged to the resist film 23a by chemical mechanical polishing using a polishing pad of polyester nonwoven fabric fiber impregnated with polyurethane and a polishing slurry of organic acid (for example, acetic acid) and alumina abrasive grains. Can be removed without giving.

両面のレジスト膜23a、23bを剥離除去し、続いてシード層(図示せず)をエッチングにより除去して、上面の配線層26aと下面の配線層26bの形成を完了する(図2(d))。上面の配線層26aの厚さは、シード層除去のエッチングの際に減少するが、その分はレジスト膜23aの下にあったシード層の厚さに相当することから、最終的に形成された配線層26aの厚さはレジスト膜23aの厚さと同じになる。下面の配線層26bは、シード層除去のエッチングの際にやはり減少するが、電解めっきで析出した配線材料25bの形状を引き継いでいる。   The resist films 23a and 23b on both sides are peeled and removed, and then the seed layer (not shown) is removed by etching to complete the formation of the upper wiring layer 26a and the lower wiring layer 26b (FIG. 2D). ). The thickness of the wiring layer 26a on the upper surface is reduced during the etching for removing the seed layer, but the thickness corresponds to the thickness of the seed layer under the resist film 23a. The thickness of the wiring layer 26a is the same as the thickness of the resist film 23a. The wiring layer 26b on the lower surface also decreases during the etching for removing the seed layer, but inherits the shape of the wiring material 25b deposited by electrolytic plating.

〔実施例2〕
図3(a)に示したように、製造過程の配線基板30の両側の絶縁層31(上下の配線層接続用の孔32が形成してある)の全面に、無電解めっきにより銅(Cu)のシード層(図示せず)を薄く形成後、実施例1と同様にDFRを利用して、配線層形成用にパターン化したレジスト膜33a、33bを形成する。上面と下面のレジスト膜33a、33bは同じ厚さでよい。
[Example 2]
As shown in FIG. 3A, copper (Cu) is formed by electroless plating on the entire surface of the insulating layer 31 (both upper and lower wiring layer connection holes 32 are formed) on both sides of the wiring substrate 30 in the manufacturing process. After forming a thin seed layer (not shown), resist films 33a and 33b patterned for forming a wiring layer are formed using DFR as in the first embodiment. The upper and lower resist films 33a and 33b may have the same thickness.

レジスト膜33a、33bの開口部34a、34bに露出したシード層(図示せず)を給電層として使用する電解めっきにより、シード層(図示せず)上に銅(Cu)の配線材料35a、35bを析出させる(図3(b))。上面の配線材料35aと下面の配線材料35bの析出する高さは、めっき条件を変えて(例えば電流密度を変えて)、上面の配線材料35aはレジスト膜33aの厚さを超えて突出し、下面の配線材料35bはレジスト膜33bの開口部34b内にとどまるようにする。   Copper (Cu) wiring materials 35a and 35b are formed on the seed layer (not shown) by electrolytic plating using a seed layer (not shown) exposed in the openings 34a and 34b of the resist films 33a and 33b as a power feeding layer. Is deposited (FIG. 3B). The height at which the wiring material 35a on the upper surface and the wiring material 35b on the lower surface are deposited changes the plating conditions (for example, by changing the current density), and the upper wiring material 35a protrudes beyond the thickness of the resist film 33a. The wiring material 35b remains in the opening 34b of the resist film 33b.

実施例1と同様の研磨により、上面のレジスト膜33aより上に突出した部分の配線材料を除去して、図3(c)に示したように厚さをレジスト膜33aの厚さに揃えた上面の配線層36aを形成する。   By polishing in the same manner as in Example 1, the wiring material in the portion protruding above the resist film 33a on the upper surface was removed, and the thickness was made equal to the thickness of the resist film 33a as shown in FIG. A wiring layer 36a on the upper surface is formed.

両面のレジスト膜33a、33bを剥離除去し、続いてシード層(図示せず)をエッチングにより除去して、上面の配線層36aと下面の配線層36bの形成を完了する(図2(d))。この例の場合も、上面の配線層36aの厚さは、シード層除去のエッチングの際に減少するが、その分はレジスト膜33aの下にあったシード層の厚さに相当するので、最終的に形成された配線層36aの厚さはレジスト膜33aの厚さと同じになる。下面の配線層36bは、シード層除去のエッチングの際にやはり減少するが、電解めっきで析出した配線材料35bの形状を引き継いでいる。   The resist films 33a and 33b on both sides are peeled and removed, and then the seed layer (not shown) is removed by etching to complete the formation of the upper wiring layer 36a and the lower wiring layer 36b (FIG. 2D). ). Also in this example, the thickness of the wiring layer 36a on the upper surface decreases during the etching for removing the seed layer, but this amount corresponds to the thickness of the seed layer under the resist film 33a. The thickness of the wiring layer 36a thus formed is the same as the thickness of the resist film 33a. The wiring layer 36b on the lower surface also decreases during the etching for removing the seed layer, but takes over the shape of the wiring material 35b deposited by electrolytic plating.

本発明の基本概念を説明する図である。It is a figure explaining the basic concept of this invention. 実施例1の工程を説明する図である。FIG. 5 is a diagram illustrating a process of Example 1. 実施例2の工程を説明する図である。6 is a diagram illustrating a process of Example 2. FIG. 配線厚さを調整する従来技術を説明する図である。It is a figure explaining the prior art which adjusts wiring thickness.

符号の説明Explanation of symbols

1 コア基板
3 絶縁層
5 レジスト膜
6a、6b 配線層
20、30 配線基板
21、31 絶縁層
23a、23b、33a、33b レジスト膜
25a、25b、35a、35b 配線材料
26a、26b、36a、36b 配線層
1 Core substrate 3 Insulating layer 5 Resist film 6a, 6b Wiring layer 20, 30 Wiring substrate 21, 31 Insulating layer 23a, 23b, 33a, 33b Resist film 25a, 25b, 35a, 35b Wiring material 26a, 26b, 36a, 36b Wiring layer

Claims (8)

絶縁基板の両面に所定数の配線層を、絶縁層を間に挟み、積層して配線基板を製造する方法であって、配線層の形成を、
両面の絶縁層上にめっき用給電層を形成し、その上にレジスト膜を均一厚で積層する工程、
各レジスト膜をパターニングし、それにより形成した開口部にめっき用給電層を露出させる工程、
電解めっきにより配線材料を析出させて、露出した一方の給電層上にはレジスト膜の厚さを超える配線層を、他方の給電層上にはレジスト膜の厚さより低い配線層を形成する工程、
一方の給電層上の配線層の一部をレジスト膜と同じ厚さまで除去し、配線層をレジスト膜と同じ厚さにする工程、
両面のレジスト膜及びその下のめっき給電層を除去する工程、
により行うことを特徴とする配線基板製造方法。
A method of manufacturing a wiring board by sandwiching a predetermined number of wiring layers on both sides of an insulating substrate and sandwiching the insulating layers therebetween, and forming the wiring layer,
Forming a plating power supply layer on the insulating layers on both sides, and laminating a resist film thereon with a uniform thickness;
Patterning each resist film and exposing the power feeding layer for plating in the opening formed thereby,
A step of depositing a wiring material by electrolytic plating and forming a wiring layer exceeding the thickness of the resist film on the exposed one power supply layer and forming a wiring layer lower than the thickness of the resist film on the other power supply layer;
Removing a part of the wiring layer on one power feeding layer to the same thickness as the resist film, and making the wiring layer the same thickness as the resist film;
Removing the resist film on both sides and the plating power feeding layer underneath,
The wiring board manufacturing method characterized by performing by this.
レジスト膜の積層工程において、一方の給電層の上には薄いレジスト膜を、他方の給電層の上には厚いレジスト膜を積層する、請求項1記載の配線基板製造方法。   The wiring board manufacturing method according to claim 1, wherein in the step of laminating the resist film, a thin resist film is laminated on one power supply layer and a thick resist film is laminated on the other power supply layer. 配線材料の析出による配線層の形成工程において、配線材料を一方の給電層の上には厚く析出させ、他方の給電層の上には薄く析出させる、請求項1記載の配線基板製造方法。   The wiring board manufacturing method according to claim 1, wherein in the step of forming the wiring layer by depositing the wiring material, the wiring material is deposited thickly on one power feeding layer and thinly deposited on the other power feeding layer. レジスト膜をドライフィルムレジストを使って形成する、請求項1〜3のいずれか一つに記載の配線基板製造方法。   The wiring board manufacturing method according to claim 1, wherein the resist film is formed using a dry film resist. 一方の給電層上の配線層の一部の除去を化学機械研磨により行う、請求項1〜4のいずれか一つに記載の配線基板製造方法。   The wiring board manufacturing method according to any one of claims 1 to 4, wherein a part of the wiring layer on one power feeding layer is removed by chemical mechanical polishing. 前記化学機械研磨が、ポリウレタンを含浸させたポリエステル不織布繊維又はポリウレタン樹脂発泡体の研磨パッドと、有機酸及び砥粒を含む研磨スラリーを使用するものである、請求項1〜5のいずれか一つに記載の配線基板製造方法。   The chemical mechanical polishing uses a polyester non-woven fabric fiber or polyurethane resin foam polishing pad impregnated with polyurethane, and a polishing slurry containing an organic acid and abrasive grains. The wiring board manufacturing method as described in 2. 前記有機酸が、酢酸、クエン酸、リンゴ酸、酒石酸、又はそれらの混合物である、請求項6記載の配線基板製造方法。   The wiring substrate manufacturing method according to claim 6, wherein the organic acid is acetic acid, citric acid, malic acid, tartaric acid, or a mixture thereof. 前記砥粒が、SiO2粉末、アルミナ粉末、又はそれらの混合物である、請求項6記載の配線基板製造方法。 The wiring board manufacturing method according to claim 6, wherein the abrasive grains are SiO 2 powder, alumina powder, or a mixture thereof.
JP2006320674A 2006-11-28 2006-11-28 Method of manufacturing wiring board Pending JP2008135570A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018067706A (en) * 2016-10-21 2018-04-26 南亞電路板股▲ふん▼有限公司 Circuit board and method for manufacturing the same

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JPH01253293A (en) * 1988-03-31 1989-10-09 Yamaha Motor Co Ltd Printed wiring substrate and manufacture thereof
JPH0653660A (en) * 1992-07-29 1994-02-25 Oki Electric Ind Co Ltd Flattening of wiring layers
JPH1167900A (en) * 1997-06-12 1999-03-09 Ngk Spark Plug Co Ltd Manufacture of multi-layer printed-circuit board
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JPS61247091A (en) * 1985-04-24 1986-11-04 日立化成工業株式会社 Wiring board
JPH01253293A (en) * 1988-03-31 1989-10-09 Yamaha Motor Co Ltd Printed wiring substrate and manufacture thereof
JPH0653660A (en) * 1992-07-29 1994-02-25 Oki Electric Ind Co Ltd Flattening of wiring layers
JPH1167900A (en) * 1997-06-12 1999-03-09 Ngk Spark Plug Co Ltd Manufacture of multi-layer printed-circuit board
JP2003273044A (en) * 2002-03-18 2003-09-26 Matsumura Sekiyu Kenkyusho:Kk Component for chemical mechanical polishing, and method of manufacturing copper wiring board using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018067706A (en) * 2016-10-21 2018-04-26 南亞電路板股▲ふん▼有限公司 Circuit board and method for manufacturing the same

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