JP3570388B2 - Memory diagnostic device and diagnostic method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory diagnostic device and a diagnostic method, and more particularly to a memory diagnostic device and a diagnostic method for checking a memory failure by sequentially writing, reading, and comparing all address areas of a memory.
[0002]
[Prior art]
A conventionally known memory diagnostic method is to write test data stored in a register sequentially to all addresses of a memory to be sequentially diagnosed, then sequentially read stored data from all addresses of the memory, and read the read data and the register. This is done by comparing with the test data stored in. In this conventional memory diagnosis method, it is necessary to change all the bits in order to check whether all the bits in all the address areas of the memory operate normally. Therefore, the values of the respective bits are inconsistent as test data. This is performed using two or more data patterns.
[0003]
For example, in a memory for writing and reading 16-bit width data, two patterns of 5555h and AAAAh (h is a hexadecimal notation: the same applies hereinafter) are used as test data, and writing, reading, and comparison are performed for each test data. Sequential processing is performed to check each bit in all address areas of the memory.
[0004]
[Problems to be solved by the invention]
However, in the conventional memory diagnosis method described above, when a failure occurs in the address line to the memory, the failure cannot be found. The reason is that, for example, assuming that a failure in which the address line of bit 7 is fixed to 0 in the memory of the address area “00h to FFh” having the 8-bit width (bit 7 to bit 0), the address area of 80h to FFh is Is actually overwritten in the address area of 00h to EFh, and the data in this address area is also read out at the time of reading. However, because of the same test data, it becomes normal in the comparison match and no failure can be found. The same applies to the case where the address line is fixed at 1 and fails, and the case where the address lines of other bits fail.
[0005]
Further, conventionally, a memory diagnosis method capable of detecting a failure of an address line is also known (for example, Japanese Patent Application Laid-Open No. Hei 4-302045). In this conventional memory diagnosis method, after supplying an address in which any one of the bits of the address line is set to 1 and writing different data to the memory, an address having all bits of 0 is supplied and data is supplied from the memory. The reading is repeated for all the bits of the address line, and when the read value is other than the initial value (for example, 0), the bit itself or the bit line of the memory is diagnosed as a failure.
[0006]
However, the conventional memory diagnosis method described in this publication is a process only for detecting a failure in an address line, and is a process for writing, reading, and comparing the entire address region for diagnosing a failure in a bit in the address region. There is a problem that it takes a long time for the diagnosis because it needs to be performed separately from the diagnosis processing. In addition, there is a problem that a diagnostic circuit such as an address generation unit and a test data holding unit for detecting the failure of the address line is further required.
[0007]
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide a memory diagnostic apparatus and a diagnostic method which can simultaneously perform diagnostic processing for writing, reading, and comparing all address areas and check for a failure in an address line.
[0008]
It is another object of the present invention to provide a memory diagnostic device and a diagnostic method capable of checking presence / absence of a failure in a memory data area and an address line in a short time with a simple circuit configuration.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a memory diagnostic device according to the present invention includes a test data generating unit configured to generate first and second test data of a bit pattern in which bit values are inverted from each other. When writing to Includes first and second specific addresses of bit patterns in which the bit values are inverted from each other Write addresses are generated sequentially, and when reading, Including first and second specific addresses Address generation means for sequentially generating a read address; and sequentially inputting the address from the address generation means to the memory, writing the first or second test data, and then reading the written data from the memory. Is repeated twice, and at the time of the first write by the write / read control means, the address from the address generation means is the first specific address. as well as The first test data is output from the test data generation means at the second specific address, and the second test data is output from the test data generation means at an address other than the first and second specific addresses. At the time of writing to the memory and writing by the write / read control means for the second time, the address from the address generation means is the first specific address. as well as The second test data is output from the test data generating means at the second specific address, and the first test data is output from the test data generating means at an address other than the first and second specific addresses. At the time of the first and second readings by the write data selection means for writing to the memory and the write / read control means, the address generation means sequentially starts from the address generation means. Next The data is sequentially read from all the address areas of the memory based on the addresses output to the memory, and the read data and the first or second test data of the expected value of the same address output from the test data generating means are read out. Sequentially Compare, When the mismatch data read from the memory when the mismatch comparison result is obtained is any of the first and second test data, it is determined that the address line of the memory is faulty, Read from memory Disagreement When the data has a value other than the first and second test data, a comparison / determination unit that determines that a failure has occurred in the data area of the memory.
[0010]
In order to achieve the above object, the memory diagnostic method of the present invention provides a memory Bit patterns that have a bit value inverted relationship with each other The first test data is written to the first and second specific addresses, and the second test data and the first test data are inverted to the addresses other than the first and second specific addresses. A first step of writing test data; and sequentially reading data from all address areas of the memory in which the first and second test data have been written in the first step, the first or second expected value at the same address as the read data. Comparing the second test data with the second test data and determining a failure based on the comparison result; writing the second test data to the first and second specific addresses of the memory; A third step of writing the first test data to an address other than the second specific address, and a memo in which the first and second test data are written by the third step. Data is sequentially read from all the address areas, and the read data is compared with the first or second test data of the expected value of the same address output from the test data generating means, and a failure is determined based on the comparison result. A fourth step, wherein in the second step or the fourth step, When the mismatch data read from the memory when the mismatch comparison result is obtained is any of the first and second test data, it is determined that the address line of the memory is faulty, Read from memory Disagreement When a comparison result of data other than the first and second test data is obtained, it is determined that a failure has occurred in the data area of the memory.
[0011]
In the above-described memory diagnostic device and method of the present invention, one of the first test data and the second test data in which the value of each bit is inverted with respect to the first and second specific addresses is determined. Since the other test data is written to an address other than the first and second specific addresses during writing, if an address line fails, it affects other addresses and is different from test data to be written to the specific address. The test data is overwritten, or the test data at another address is read, and as a result, the expected value of the specific address does not match the read data.
[0012]
Further, in the present invention, when the first or second test data read from the memory at the time of specifying the first or second specific address is different from the expected value of the first specific address or the expected value of the second specific address. When the data read from the memory has a value other than the first and second test data, it can be determined that the data area of the memory is faulty. During the processing, only the test data of the data pattern different from the other addresses is set to the first and second specific addresses, and both the failure of the address line and the failure of the data area can be performed without performing additional memory access processing. Can be detected.
[0013]
In order to achieve the above object, the present invention provides the above-mentioned first test data as an n-bit pattern (n is an integer of 2 or more) in which the values of each bit are alternately arranged with 0s and 1s in the order of bit numbers. , The second test data is an n-bit pattern in which the value of each bit of the first test data is inverted.
[0014]
Also, in the present invention, the first specific address is an m-bit pattern (m is an integer of 2 or more) in which each bit value is alternately arranged with 0s and 1s in the order of bit numbers. Is an m-bit pattern in which the value of each bit of the first specific address is inverted.
[0015]
In the present invention, the first and second test data and the first and second specific addresses are represented by a bit pattern in which 0s and 1s are alternately arranged in the order of bit numbers (for example, in the case of a 16-bit width, 5555h and AAAAh). Therefore, when the address lines and the data buses are physically arranged in the order of the bit numbers, a failure can be detected even if adjacent bits are short-circuited and a failure state that operates only simultaneously occurs.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of a memory diagnostic device according to the present invention. In FIG. 1, a memory diagnostic device 2 for a memory 1 includes an address selection circuit 3 for selecting a memory address S1 for diagnosis and a memory address S2 for normal operation, memory input data S3 for diagnosis and memory input for normal operation. It comprises a data selection circuit 4 for selecting data S4, a diagnosis control unit 5, an address generation unit 6, data registers 7 and 8, a test data selection circuit 9, a data control unit 10, and a comparison matching circuit 11. Is done.
[0017]
The diagnosis control unit 5 controls the address selection circuit 3 and the data selection circuit 4 to select the address S1 and the memory input data S3 during diagnosis or the address S2 and the memory input data S4 during normal operation. The address generator 6 sequentially generates all addresses of the memory 1. The data register 7 and the data register 8 respectively hold bit patterns in which each bit is inverted (for example, 5555h and AAAAh in the case of a 16-bit data width).
[0018]
The test data selection circuit 9 selects one of the bit patterns of the data register 7 and the data register 8 as the memory input data S3 at the time of diagnosis. The data control unit 10 outputs a selection signal S9 to the test data selection circuit 9 based on the instruction signal S8 from the diagnosis control unit 5 and the address value from the address generation unit 6, and selects the test data selection circuit 9. The operation is controlled to output the memory input data S3 at the time of diagnosis.
[0019]
The comparison matching circuit 11 compares the memory output data S5 and the memory input data S3 to check whether the two data match, and outputs a mismatch signal S7 if they do not match. At the time of memory diagnosis, the diagnosis control unit 5 instructs the address generation unit 6 to generate a sequential address, and instructs the data control unit 10 to test data, and outputs a write / read control signal S6 to the memory 1.
[0020]
FIG. 2 shows a configuration diagram of one embodiment of the data control unit 10 in FIG. In FIG. 2, an address register 21 and an address register 22 hold one and the other of two bit patterns (for example, 55h and AAh in the case of an 8-bit address width) in which each bit is inverted. When the memory address S1 from the address generator 6 matches the bit pattern of either address, a match signal is output, and the AND circuit 23 changes the memory input data selection signal S9. In addition, the data initial value selection circuit 24 is controlled by the test data instruction signal S8 from the diagnosis control unit 5, and the output of the AND circuit 23 and the output of the polarity inversion circuit 25 for inverting the polarity of the output are selected and input to the memory input. The data selection signal S9 is set, and the initial value of the test data is selected.
[0021]
Next, the operation of the present embodiment shown in FIGS. 1 and 2 will be described with reference to the flowchart of FIG. Here, as an example, the data width of the memory 1 is 16 bits, and the address width is 8 bits. The data registers 7 and 8 and the address registers 21 and 22 hold bit patterns that are in a mutually contradictory relationship. Here, the value of the bit pattern held in the data register 7 is stored in the data register 8 as 5555h. The value of the stored bit pattern is AAAAh, the value of the bit pattern stored in the address register 21 is 55h, and the value of the bit pattern stored in the address register 22 is AAAh.
[0022]
First, the diagnosis control unit 5 selects the address selection circuit 3 and the data selection circuit 4 as addresses and data at the time of diagnosis, and sets a memory diagnosis enabled state (step 101). Subsequently, the diagnosis control unit 5 outputs a test data instruction signal S8, and causes the data initial value selection circuit 24 in the data control unit 10 to output a selection signal S9 for setting an initial value to the test data selection circuit 9. The test data selection circuit 9 selects the initial value of the test data as the data (5555h) from the data register 7 (step 102).
[0023]
Next, the diagnostic control unit 5 supplies the sequential address in the address generation unit 6 and selects the data selection circuit 4 by the test data selection circuit 9 using the write / read control signal S6 for the memory 1 as a write instruction. The test data input to the memory 1 via the memory is sequentially written to the memory 1 (step 103).
[0024]
Here, when the bit pattern of the address supplied from the address generation unit 6 to the memory 1 via the address selection circuit 3 is the same as the address 55h of the address register 21 or the same as the address AAh of the address register 22, Since a match signal is output from the register 21 or the address register 22 and the output of the AND circuit 23 is inverted to invert the memory input data selection signal S9, the test data selection circuit 9 stores the test data in the data ( AAAAh).
[0025]
On the other hand, when the bit pattern of the address supplied from the address generation unit 6 to the memory 1 via the address selection circuit 3 is different from both the address 55h of the address register 21 and the address AAh of the address register 22, No match signal is output from the address register 22, and the logical value of the output of the AND circuit 23 becomes the same as that at the time of setting the initial value. In order to make the value, the test data selection circuit 9 switches the test data to the data (5555h) from the data register 7. As a result, as shown in FIG. 4, in step 103, the test data AAAAh is written to the addresses 55h and AAh of the memory 1, and the test data 5555h is written to the other addresses.
[0026]
Subsequently, the diagnosis control unit 5 supplies a sequential address by the address generation unit 6 and sequentially reads data from the memory 1 with the write / read control signal S6 for the memory 1 as a read instruction. Here, the operation of the data control unit 10 is the same as that at the time of writing, and when the address of the address generation unit 6 is 55h or AAh, the test data S3 output from the test data selection circuit 9 is transferred from the data register 8 to the data ( AAAh), but selects data (5555h) from the data register 7 at other addresses. The memory output data S5 sequentially read from the memory 1 in accordance with the instruction of the diagnosis control unit 5 is supplied to the comparison matching circuit 11, where it is compared with the test data S3 output from the test data selection circuit 9, and is stored in all the address areas. It is checked whether the read data S5 is the same as the test data S3 (step 104).
[0027]
Next, the diagnostic control unit 5 outputs a test data instruction signal S8 and causes the data initial value selection circuit 24 in the data control unit 10 to output a selection signal S9 for setting an initial value to the test data selection circuit 9. Here, when the data initial value selection circuit 24 has selected the output of the AND circuit 23 in the previous step 102 by the test data instruction signal S8, for example, the output is switched to select the output of the polarity inversion circuit 25. The logical value of the selection signal S9 becomes a logical value opposite to that at the time of setting the initial value in step 102. As a result, the test data selecting circuit 9 selects the data (AAAAAh) from the data register 8 as the initial value of the test data (step). 105).
[0028]
Subsequently, the diagnostic control unit 5 supplies the sequential address in the address generation unit 6 and selects the data selection circuit 4 by the test data selection circuit 9 using the write / read control signal S6 for the memory 1 as a write instruction. The test data input to the memory 1 via the memory is sequentially written to the memory 1 (step 106).
[0029]
Here, when the bit pattern of the address supplied from the address generation unit 6 to the memory 1 via the address selection circuit 3 is the same as the address 55h of the address register 21 or the same as the address AAh of the address register 22, A match signal is output from the register 21 or the address register 22, and the output of the AND circuit 23 is inverted from that at the time of setting the initial value, so that the memory input data selection signal S9 is inverted. 7 (5555h).
[0030]
On the other hand, when the bit pattern of the address supplied from the address generation unit 6 to the memory 1 via the address selection circuit 3 is different from both the address 55h of the address register 21 and the address AAh of the address register 22, No match signal is output from the address register 22, and the logical value of the output of the AND circuit 23 becomes the same as that at the time of setting the initial value. To make the value, the test data selection circuit 9 switches the test data to the data (AAAAAh) from the data register 8. Thus, in this step 106, the test data 5555h is written to the addresses 55h and AAh of the memory 1, and the test data AAAAh is written to the other addresses.
[0031]
Next, the diagnosis control unit 5 supplies a sequential address by the address generation unit 6 and sequentially reads data from the memory 1 with the write / read control signal S6 for the memory 1 as a read instruction. Here, the operation of the data control unit 10 is the same as that at the time of writing in step 106. When the address of the address generation unit 6 is 55h or AAh, the test data S3 output from the test data selection circuit 9 is read from the data register 7. (5555h), but selects data (AAAAAh) from the data register 8 at other addresses. The memory output data S5 sequentially read from the memory 1 in accordance with the instruction of the diagnosis control unit 5 is supplied to the comparison matching circuit 11, where it is compared with the test data S3 output from the test data selection circuit 9, and is stored in all the address areas. It is checked whether the read data S5 is the same as the test data S3 (step 107).
[0032]
Finally, the diagnosis control unit 5 switches the address selection circuit 3 and the data selection circuit 4 to a state of selecting the address S2 and the data S4 in the normal operation, and ends the memory diagnosis (Step 108).
[0033]
Next, the operation of the above embodiment when an address line failure occurs will be described with reference to FIGS. When the bit 7 out of the 8-bit width address (bit 7 to bit 0) is fixed at 0 and fails, the address AAh becomes 2Ah (FIG. 5). In step 103 of FIG. 3, test data 5555h is written to address 2Ah. Further, in the process of writing the test data AAAAh to the address AAAh, the address AAh becomes 2Ah due to a failure, so that the address 2Ah is overwritten with the test data AAAAh.
[0034]
As a result, in step 104 of FIG. 3, the data AAAAh is output at the time of reading the data of the address 2Ah, and a mismatch occurs with the test data 5555h that is the expected value. Here, the data AAAAh should be read from the address 55h or the AAAh of the memory 1. However, the read address 2Ah at the time of occurrence of a mismatch differs from 55h in the value of seven bits. One bit (bit 7) of AAh is fixed to 0 and can be detected as a failure.
[0035]
Similarly, when bit 7 of the 8-bit width address (bit 7 to bit 0) is fixed at 1 and fails, the address 55h becomes D5h (FIG. 6). In this case, in step 103 of FIG. 3, in the process of writing the test data AAAAh to the address 55h, since the address 55h becomes D5h due to a failure, the test data AAAAh is written to the address D5h. Thereafter, the test data 5555h is overwritten on the address D5h.
[0036]
Thus, in the process of reading the address 55h in step 104 of FIG. 3, the address 55h becomes D5h due to a failure, so that the test data 5555h written to the address D5h is read, and the test data AAAAh which is the expected value is read. A mismatch occurs. Here, the data AAAAh is supposed to be read from the address 55h or the AAAh of the memory 1. However, the read address D5h at the time of occurrence of a mismatch differs from the AAAh in the value of seven bits. One bit (bit 7) of 55h is fixed at 1 and can be detected as a failure.
[0037]
Further, even when another bit of the address line fails, the mismatch can be detected in the same manner. For example, if the bit 5 of the 8-bit width address (bit 7 to bit 0) is fixed at 1 and fails, the address 55h becomes the address 75h. In this case, in the process of reading the address 55h in Step 104 of FIG. 3, since the address 55h becomes 75h due to a failure, the test data 5555h written at the address 75h is read, and the test data AAAAh which is the expected value is read. And a mismatch occurs.
[0038]
In this way, at the time of reading at step 104 or step 107, the read data pattern becomes AAAAh when 5555h is expected or 5555h when AAAAh is expected, so that the comparison matching circuit 11 detects a failure of the address line. be able to.
[0039]
Further, when test data of AAAAh or 5555h is written in all data areas of the memory 1 in step 103 and read out in step 104, values other than AAAAh and 5555h are read out from the failed data area (address). Then, in the data area where AAAAh is written in step 103, 5555h is written in step 107, and in the data area where 5555h is written in step 103, AAAAh is written in step 107, and when read in step 108, a failure occurs. Values other than AAAAh and 5555h are read from the data area (address) thus set. Then, the comparison matching circuit 11 can detect which data area (address) has a failure by comparing values other than AAAh and 5555h read in steps 104 and 108.
[0040]
As described above, in the present embodiment, a data pattern different from the other addresses is set only for the specific addresses 55h and AAh. Therefore, when an address line fails, the other addresses are affected. The failure of the address line can be detected by reading the data pattern that does not match the expected value of the data pattern written in the address line. Further, no additional memory access is required, and the failure detection of the address line and the failure detection of all the bits of the entire data area can be performed with the same number of accesses as the conventional check of all the bits of the entire data area of the memory 1. .
[0041]
In the above embodiment, the data held in the data registers 7 and 8 are 5555h and AAAAh, and the data held in the address registers 21 and 22 are 55h and AAAh. However, the purpose of the present invention is to change all the bits of the memory and all the data lines and address lines as a memory diagnosis and check that the memory operates normally. Anything is fine.
[0042]
However, when the data bus signal and the address bus signal are physically adjacent to each other, a failure state in which adjacent bits are short-circuited and only operate simultaneously can be considered. In this case, it is not only necessary that each bit be a mutually inconsistent bit pattern. A mismatch cannot be detected in two inconsistent bit patterns (for example, 0000h and FFFFh) in which adjacent bits have the same value. For this reason, it is desirable that two bit patterns having different values from the adjacent bits have a reciprocal relationship. A bit pattern such as AAAAh (for a 16-bit width) in which the values of each bit are alternately arranged with 0s and 1s in the order of bit numbers is desirable.
[0043]
【The invention's effect】
As described above, according to the present invention, by writing one of the first and second test data to a specific address and writing the other test data to an address other than the specific address, when an address line fails, This affects other addresses and overwrites test data different from the test data to be written to the specific address, or reads test data at another address, resulting in a mismatch between the expected value of the specific address and the read data. As a result, a failure of the address line can be detected.
[0044]
Further, according to the present invention, additional memory access processing can be performed only by setting test data of a data pattern different from other addresses to the first and second specific addresses during sequential processing for detecting a data failure. Since it is possible to detect both a failure in the address line and a failure in the data area without performing the processing, it is not necessary to add a memory access for detecting the failure in the address line in the process of detecting the data failure, and the diagnosis is performed. This prevents an increase in time and eliminates the need for special hardware.
[Brief description of the drawings]
FIG. 1 is a block diagram of a memory diagnostic device according to an embodiment of the present invention.
FIG. 2 is a block diagram of an embodiment of a data control unit in FIG. 1;
FIG. 3 is a flowchart for explaining the operation of the present invention.
FIG. 4 is an explanatory diagram of an example of a data storage state of a memory according to the present invention.
FIG. 5 is an address bit pattern (part 1) when an address line failure occurs in the present invention.
FIG. 6 is an address bit pattern (part 2) when an address line failure occurs in the present invention.
[Explanation of symbols]
1 memory
2 Memory diagnostic device
3 Address selection circuit
4 Data selection circuit
5 Diagnosis control unit
6 Address generator
7, 8 data register
9 Test data selection circuit
10 Data control unit
11 Comparison matching circuit
21, 22 address register
23 AND circuit
24 Data initial value selection circuit
25 polarity inversion circuit

Claims (7)

Test data generating means for generating first and second test data of a bit pattern in which bit values are inverted from each other;
For a memory to be diagnosed, at the time of writing, write addresses including first and second specific addresses of bit patterns in which the bit values are inverted with respect to each other are sequentially generated, and at the time of reading, the first address is read . Address generation means for sequentially generating a read address including a second specific address and a second specific address ;
A write / read control in which addresses from the address generation means are sequentially input to the memory, and the first or second test data is written, and then the data written from the memory is read twice. Means,
The first time of writing by the write / read control means, address from said address generating means, the first specific address and the second of said first test from the test data generating means when the specific address Data, and when the address is other than the first and second specific addresses, the test data generating means outputs the second test data and writes the data in the memory. When the address from the address generation unit is the first specific address and the second specific address, the test data generation unit outputs the second test data, When the address is other than the second specific address, the first test data is output from the test data generating means. And write data selecting means for writing into the memory by,
The write / read control means first and second times when reading by, based on the address outputted from said address generating means sequentially following sequentially reads the data from the entire address area of the memory, the test and the read data The first or second test data of the expected value of the same address output from the data generating means is sequentially compared with the first or second test data, and when a mismatched comparison result is obtained, the mismatched data read from the memory is replaced with the first or second test data . And the second test data, it is determined that the address line of the memory is faulty, and when the mismatch data read from the memory is a value other than the first and second test data, A memory diagnostic device comprising: a comparison / determination unit configured to determine a failure in a data area. The write data selection unit determines whether an address from the address generation unit matches the first specific address or the second specific address, and if so, outputs a match signal; At the time of the first write by the write / read control means, when the coincidence signal is output from the determination means, the test data generation means selects and outputs the first test data, and the coincidence signal is output. If not, the second test data is selected and output from the test data generation means. At the time of the second write by the write / read control means, when the coincidence signal is output from the determination means, the second test data is output. If the second test data is selected and output from the test data generating means, and the coincidence signal is not output, Serial test data selection means from generating means to select and output the first test data to the memory diagnostic apparatus according to claim 1, wherein the more becomes possible. The first test data is an n-bit pattern (n is an integer of 2 or more) in which each bit value is alternately arranged with 0s and 1s in the order of bit numbers, and the second test data is the first test data. 3. The memory diagnostic device according to claim 1, wherein the value of each bit of the data is an inverted n-bit pattern. The first specific address is an m-bit pattern (m is an integer of 2 or more) in which each bit value is alternately arranged with 0s and 1s in the order of bit numbers, and the second specific address is the first specific address. 4. The memory diagnostic apparatus according to claim 1, wherein the value of each bit of the address is an inverted m-bit pattern. In the entire address area of the memory to be diagnosed, the first test data is written to the first and second specific addresses of the bit pattern in which the bit values are inverted with respect to each other , and A first step of writing second test data having an inverted relationship between the first test data and each bit value at an address other than the second specific address;
In the first step, data is sequentially read from all the address areas of the memory in which the first and second test data are written, and the read data and the first or second test data having the same expected value at the same address are read out. Comparing, and determining a failure based on the comparison result;
A third step of writing the second test data to the first and second specific addresses of the memory, and writing the first test data to an address other than the first and second specific addresses; ,
In the third step, data is sequentially read from all the address areas of the memory in which the first and second test data have been written, and the read data and the expected value of the same address output from the test data generating means are output. Comparing the first or second test data with each other and determining a failure based on the comparison result. In the second step or the fourth step, a mismatched comparison result is obtained. when the said discrepancy data read from the memory it is determined that a failure of the memory address line when either of the first and second test data, the mismatch data first read out from said memory And determining a failure in a data area of the memory when a comparison result of a value other than the second test data is obtained. Cross-sectional method. The first test data is an n-bit pattern (n is an integer of 2 or more) in which each bit value is alternately arranged with 0s and 1s in the order of bit numbers, and the second test data is the first test data. 6. The memory diagnostic method according to claim 5, wherein the value of each bit of the data is an n-bit pattern inverted. The first specific address is an m-bit pattern (m is an integer of 2 or more) in which each bit value is alternately arranged with 0s and 1s in the order of bit numbers, and the second specific address is the first specific address. 7. The memory diagnosis method according to claim 5, wherein the address is an m-bit pattern in which the value of each bit is inverted.

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