JP3546582B2 - Semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device in which memories are integrated, and in particular, in a semiconductor device in which a memory having a plurality of I / O lines and a logic circuit are integrated on the same semiconductor chip, an LSI chip for various purposes can be used for a short time. It is intended to provide a method for designing between devices and a product group based on the method, and a method for a highly integrated data transfer circuit capable of changing a data transfer pattern between the memory and the logic circuit at a high speed.
[0002]
[Prior art]
U.S. Pat. No. 5,371,896 is an attempt to integrate parallel computing systems interconnecting a large number of arithmetic units, processors and memories on the same semiconductor chip. In this conventional example, a plurality of memories and a plurality of arithmetic circuits are integrated on the same semiconductor chip, and the two are connected by a network including a crossbar switch. This conventional example is characterized in that it can be switched between a single instruction multi data stream (SIMD) operation and a multi instruction multi data stream (MIMD) operation as required. During the SIMD operation, one of the plurality of memories is used as an instruction memory, and the remaining memories are used as data memories. The instructions from the instruction memory are commonly supplied to the arithmetic circuits. At the time of the MIMD operation, a part of the memory used as the data memory at the time of the SIMD operation is used as an instruction memory, so that instructions from different instruction memories are given to individual arithmetic circuits. The data transfer path between each memory and the arithmetic circuit can be variously switched by a crossbar network.
[0003]
[Problems to be solved by the invention]
In addition to the above, various semiconductor devices with integrated memory have been devised. Recently, in particular, a relatively high-integration memory such as a DRAM (Dynamic Random Access Memory) and a logic circuit are integrated on the same semiconductor chip. Is attracting attention. Such an LSI generally requires a reduction in time to completion of a chip (Time to Customers) since a semiconductor maker starts manufacturing it in response to a user request. However, on the other hand, the required memory capacity and the type of arithmetic circuit differ depending on the application. In order to meet this conflicting demand, it is necessary to reform from the design method. However, the specifications of conventional high-integration memories, especially DRAMs, are standardized, and therefore, the above-described design cannot be met with the same design method.
[0004]
Further, when a highly integrated memory such as a DRAM and a logic circuit are integrated on the same semiconductor chip, it is difficult to obtain a great merit over an individual chip simply by integrating them. Considering cost and required performance, large-capacity memory and large-scale logic circuits and arithmetic circuits are integrated on a semiconductor chip of about 1 cm square, and the number of coupling lines between them is made several hundred or more, The transfer speed needs to be 1 GigaByte / sec or more. Therefore, a high-speed and high-integration circuit is required as a coupling circuit for coupling a memory and a logic circuit. However, when a crossbar switch is used as in the conventional example, if the number of coupling lines increases, the number of switches becomes enormous, the scale of hardware increases, and the delay also increases. When switching the data transfer path between a plurality of independent memories and a plurality of arithmetic circuits as in the above-described prior art, the method used in a conventional parallel computer is generally used because the number of memories and arithmetic circuits is small. It is also possible to realize it on the same chip as it is. However, when switching the correspondence between the I / O line group of several hundred or more memories and the I / O line group of the logic circuit and the arithmetic circuit, the demands for the degree of integration and operation speed are strict, and the conventional method is used. It is difficult to use it as it is.
[0005]
[Means for Solving the Problems]
In order to solve the first problem described above, the present invention provides a memory core having many I / O lines and a module for a coupling circuit designed according to the pitch of the I / O lines of the memory cores having different capacities. A layout pattern is created in advance and stored in a database. Further, a logic library for synthesizing a logic circuit is also created and stored in a database. The database stores data required for design, such as layout patterns, specifications, and characteristics.
[0006]
The module for the coupling circuit includes a switch group and a buffer group, and can be combined to constitute a coupling circuit. The switch group can change the order of input data therein. By connecting a plurality of switch groups and activating the switch group corresponding to the desired transfer pattern in accordance with the transfer pattern, the transfer pattern can be switched at high speed. These modules are made to match the pitch of the I / O lines of the memory core, and can be directly connected to the I / O lines of the memory core without changing the layout pattern.
[0007]
As described above, according to the present invention, the layout patterns of the memory core, the coupling circuit module, and the logic library are registered in the database in advance, and the wiring pitch between the memory core and the coupling circuit module is made uniform. , Can be used as they are. Therefore, the design after the specification of the LSI chip is given by the user can be completed in a short time. In other words, a memory core of the required capacity and a module for creating a transfer circuit that meets the specifications are taken out from the database and combined, and the logic part is further converted from a logic library using a CAD tool for logic synthesis to a desired logic circuit. What is necessary is just to synthesize. The wiring between them can be performed at high speed by the placement and routing CAD tool. Therefore, a chip in which a memory and a logic circuit are integrated can be formed in a short time.
[0008]
Further, in the above-described coupling circuit, high-speed data transfer can be realized because only data of the activated switch group passes through data transferred between the memory and the logic circuit. Furthermore, since the number of stages is increased or decreased in accordance with the number of transfer patterns, there is no useless occupation area when the number of transfer patterns is small.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
[Design method of system LSI using memory core]
FIG. 1 shows the concept of a system LSI incorporating a memory core according to the present invention. An LSI design method according to the present invention will be described with reference to FIG.
[0010]
On the left side of FIG. 1 is a database storage device DB in which layout patterns and characteristics of a core circuit and a logic library are registered. Here, a plurality of memory cores MR with many I / O lines and different capacities, a group of modules for a transfer circuit (coupling circuit) TG designed according to the pitch of the I / O lines of the memory core, and a logic Data necessary for design, such as layout patterns, specifications, and characteristics with a logic library LL consisting of basic gates for synthesizing a circuit is stored in advance.
[0011]
Here, the module for the transfer circuit TG includes a switch group SWG and a buffer group TGBUFi.
And the transfer circuit TG can be synthesized in combination. As will be described in detail later, by connecting a plurality of switch groups, transfer circuits TG having various transfer patterns can be synthesized. Since these modules are made in accordance with the pitch of the I / O lines of the memory core MR, they can be directly connected to the I / O lines of the memory core MR without changing the layout pattern.
[0012]
Given the specification of the LSI chip, the design is performed while transferring necessary data from the database DB to the design workstation WS. Since the wiring pitches of the memory core MR and the transfer circuit TG module are uniform, they can be used as they are. That is, a module for forming a memory core MR having a required capacity and a transfer circuit TG meeting specifications may be taken out from the database DB and combined. For the logic part, a desired logic circuit LC can be easily synthesized from the logic library LL by using a CAD tool for logic synthesis. Finally, the chip layout data is completed by arranging them according to the floor plan of the chip and performing wiring between them using a layout and wiring CAD tool. In this way, it is possible to design a system LSI product group including the memory core MR in a short time.
[0013]
Here, an example in which the logic is synthesized using the logic library LL has been described. However, in some cases, the logic may be synthesized using a part of a chip as a gate array. In this case, there is an advantage that a chip having a common memory core MR and different logic can be easily manufactured.
[0014]
At the lower right of FIG. 1, two examples of the chip designed as described above are shown. The semiconductor chip LSI-A has four blocks A, B, C, and D in which a memory core MR and a logic circuit LC are connected by a transfer circuit TG, and a control circuit CC for controlling the entire chip is arranged at the center of the block. is there. In the semiconductor chip LSI-B, two blocks A and B in which a memory core MR and a logic circuit LC are connected by a transfer circuit TG are arranged, and a control circuit CC for controlling the entire chip is arranged at the center.
[0015]
In the present invention, of course, a chip using one memory core MR can be realized, but a chip in which a plurality of blocks are integrated as in this example can be easily designed. In that case, the memory core MR and the logic circuit LC of each block may be different or may have the same configuration. The former is suitable for performing different processes in parallel on the same chip, and the latter is suitable for performing the same processes in parallel. In particular, the latter is suitable for processing that can perform parallel operations, such as graphics, natural image processing, and neural networks.
[0016]
In both of the semiconductor chips LSI-A and LSI-B, since the logic circuit LC for transmitting and receiving data to and from the memory core MR is close to the memory core MR, the effect of wiring delay is small and high-speed data transfer can be realized. Further, since the distance from the control circuit CC to each block is equal in the semiconductor chip LSI-B and the difference is small in the semiconductor chip LSI-A, there is an advantage that the skew of the control signal can be reduced.
[0017]
In the semiconductor chip LSI-B, the logic circuit LC is close to the control circuit CC, but if it is necessary to shorten the wiring of the control signal of the memory core MR to reduce the wiring delay, the block is connected to the control circuit CC. And the memory core MR may be brought close to the control circuit CC.
In the semiconductor chip LSI-A, there may be a case where the distance from the control circuit CC is different between the blocks A and B and between the blocks A and B. In such a case, two blocks may be arranged on the left and right sides of the control circuit CC by arranging them like the semiconductor chip LSI-B.
[0018]
If the shape of the block is long horizontally, the difference between the short side and the long side of the chip may become too large. In such a case, the input terminals of the control signal are concentrated on one surface of the block while the arrangement of the semiconductor chip LSI-A shown in FIG. By doing so, the input terminal of the control signal can be placed on the surface where the blocks are adjacent to each other. Thereby, the skew of the control signal can be reduced. Hereinafter, the transfer circuit TG shown in FIG. 1 will be described in detail.
[0019]
[LSI with multiple I / O memory cores]
FIG. 2 shows an example of a multi-I / O built-in memory LSI according to the present invention. The semiconductor chip SIC shown in FIG. 2 includes a memory core MR having a plurality of I / O lines MIOi, a logic circuit LC having a plurality of I / O lines LIOi, and data transfer between the memory core MR and the logic circuit LC. The transfer circuit TG for controlling a transfer pattern and the like are integrated on a single semiconductor substrate made of single-crystal silicon or the like.
[0020]
The contents of the logic circuit LC may be synthesized according to the purpose using the logic library LL. Here, an example suitable for an image or graphics is shown. Operation unit group ARW that performs operations on the pixels stored in the memory core MR, display buffer DBR for reading the contents of the memory core MR at a constant speed to display them on the screen, and control them and the memory core MR And a control circuit LCC.
[0021]
The memory core MR includes a plurality of data lines DL, a plurality of word lines WL, and their exchanges.
It has a memory cell MC formed at a point. The memory cell MC is a 1-transistor 1-capacitor DRAM cell, a 4- or 6-transistor SRAM (Static Random Access Memory).
Memory) cell, a one-transistor nonvolatile flash memory cell, or the like can be used. In the following, a so-called RAM type which can perform writing and reading is assumed, but the present invention is also effective when a reading-only so-called ROM type is used. Writing and reading of data to and from the memory core MR is controlled by a read / write circuit RWC, and data can be read and written in parallel from a plurality of I / O lines to a plurality of memory cells MC selected by a peripheral circuit PER. The peripheral circuit PER is connected to buses such as a memory core control signal MRC, a control signal CTL, and an address signal DATA from the logic circuit LC. The memory core MR inputs and outputs a control signal, an address signal, and an I / O signal in synchronization with a clock signal that is a reference signal of the logic circuit LC.
[0022]
The logic circuit LC performs an operation on data read from the memory core MR through the transfer circuit TG and data from outside the semiconductor chip SIC. The result is again written to the memory core MR through the transfer circuit TG or output outside the semiconductor chip SIC.
[0023]
The transfer circuit TG is composed of a switch group SWG connected in multiple stages, and a connection relationship between a plurality of I / O lines MIOi of the memory core MR and a plurality of I / O lines LIOi of the logic circuit LC by a control signal TGCi. (Hereinafter, referred to as a transfer pattern).
[0024]
FIG. 3 shows a case where eight patterns from P0 to P7 are realized as examples of transfer patterns. In this example, MIO0,1,2,3 and LIO0,1 in units of 1/4 (2 to the power of (n-2)) are used for 2 / n power I / O lines MIOi and LIOi. , 2, and 3 are switched. It is needless to say that the transfer units need not be 2 n, and the present invention can be applied even if all the transfer units are not equal. The direction of the arrow indicates the flow of data, and the transfer pattern P1 is used only for writing to the memory, and the remaining patterns (P0, P2 to P7) are used for both reading and writing.
[0025]
The transfer pattern P0 is a pattern for transferring data without replacement. The transfer pattern P1 is for transmitting data input to (LIO0,1) to (MIO0,1), (MIO2,3) and writing the data to the memory. In this example, unlike other patterns, I / O lines of different memories are turned on. For this reason, different data may collide at the time of reading, so it is used only at the time of writing. This pattern is effective for initializing the contents of the memory at a high speed as described later.
[0026]
The transfer patterns P2 and P3 form transfer paths between (LIO0,1) and (MIO0,1) and between (LIO0,1) and (MIO2,3), respectively. The transfer patterns P4 to P7 form transfer paths between (LIO1) and (MIO0), (LIO1) and (MIO1), (LIO1) and (MIO2), and (LIO1) and (MIO3), respectively. .
[0027]
The eight transfer patterns (P0 to P7) can be freely switched by the control signal TGCi. Each transfer pattern can be realized by turning on one switch group SWG in the transfer circuit TG. For example, the transfer pattern P0 can be realized by turning on the switch group SWG # 0 shown in FIG. The specific configuration of the transfer circuit TG will be described later.
[0028]
In this embodiment, since the memory core MR, the transfer circuit TG, and the logic circuit LC are formed on the same semiconductor chip, tens to hundreds of I / O lines can be easily wired.
[0029]
Hereinafter, the operation of the LSI with a multiplexed I / O memory core shown in FIG. 2 will be described.
[0030]
First, the read operation will be described. When one word line WL is selected by the peripheral circuit PER in the memory core MR, data is read from the group of memory cells MC on the word line WL to the data line DL, and a plurality of I / Os are read through the read / write circuit RWC. Data is read in parallel to the line MIOi. When one of the switches SWG in the transfer circuit TG is activated by the control signal TGCi, the transfer pattern between the plurality of I / O lines MIOi of the memory core MR and the plurality of I / O lines LIOi of the logic circuit LC Is determined, data is transferred from the I / O line MIOi to the I / O line LIOi, and input to the logic circuit LC.
[0031]
The write operation is similar except that the data flow is reversed. That is, data output from the logic circuit LC to the plurality of I / O lines LIOi is transferred from the I / O line LIOi to the I / O line MIOi in accordance with the transfer pattern determined by the control signal TGCi, and is read through the read / write circuit. The data is transmitted to the line DL and further written in parallel to the memory cells MC on the selected word line WL.
[0032]
When reading or writing is performed continuously or alternately, the operation can be performed by switching the selected word line WL or transfer pattern for each cycle. Therefore, reading and writing can be performed in parallel on the memory cells MC corresponding to different addresses in each cycle according to the request of the logic circuit LC.
[0033]
According to the present embodiment, transmission and reception of data between the memory core MR and the logic circuit LC is performed through the one-stage switch group SWG, so that extremely high-speed data transfer can be realized. Further, since the memory core MR and the logic circuit LC are arranged so that the I / O lines MIOi and LIOi run in the same direction, the transfer circuit TG can be arranged between the memory core MR and the logic circuit LC. Since the number of stages of the switch group SWG of the transfer circuit TG is determined according to the transfer pattern, when the number of transfer patterns is small, the size of the transfer circuit in the data line direction (horizontal direction in FIG. 2) can be reduced. Therefore, when the transfer circuit TG and the logic circuit LC are laid out so as to fit within the dimension of the memory core MR in the word line WL direction (vertical direction in FIG. 2) as shown in FIG. Can be reduced.
[0034]
Note that the peripheral circuit PER may include only the X decoder for selecting the word line WL as described above, or may include a Y decoder for selecting a part of the data line and connecting to the I / O line. According to this embodiment, since a large number of I / O lines can be provided, usually, the Y decoder may be as simple as selecting, for example, 128 out of 1024 data lines.
[0035]
[First Specific Example of Transfer Circuit]
Next, a specific circuit example of the transfer circuit TG will be described with reference to FIG. FIG. 4 shows a circuit example of the transfer circuit TG for realizing the transfer pattern shown in FIG.
[0036]
In FIG. 4, MIO0, MIO1, MIO2, and MIO3 are I / O lines of the memory core MR, and LIO0, LIO1, LIO2, and LIO3 are I / O lines of the logic circuit LC. SWG0, SWG1,..., SWG7 are switch groups, and TGBUF0, TGBUF1, TGBUF2, TGBUF3 are buffer circuits.
[0037]
TGC0, TGC1, .., TGC7 are signals for turning on / off the switch groups SWG0, SWG1, .., SWG7, respectively. Although it depends on what kind of transistor constitutes the switch SW of the switch group SWG, here, when the control signal TGCi is set to a high potential, the switch SW to which the control signal TGCi is applied is turned on, and when the control signal TGCi is set to a low potential, it is turned off. Then For example, when the control signal TGC3 is set to a high potential and the other control signals are set to a low potential, two switches SW indicated by arrows in the switch group SWG3 are turned on. As a result, a transfer pattern of P3 is formed, and a transfer path is formed between the I / O lines MIO2 and MIO3 of the memory core and the I / O lines LIO0 and LIO1 of the logic circuit LC. Similarly, other transfer patterns can be realized by setting one of the control signals TGCi to a high potential.
[0038]
Buffer circuits TGBUF0, TGBUF1, TGBUF2, TGBUF3 are affected by the additional capacitance of the I / O line.
This is added to avoid delay of the signal. An example of the configuration of this circuit is shown in FIG. The operation of the buffer circuit TGBUFi will be described with reference to FIG.
[0039]
The buffer circuit TGBUFi is a bidirectional buffer that switches the data flow according to the read / write operation of the memory core MR, and also latches the potential of the I / O line LIOi of the logic circuit LC not used when the transfer pattern is formed. It is a circuit that has the function of
[0040]
In the example shown in FIG. 3, except for the transfer pattern P0, none of the I / O lines LIOi of the logic circuit LC is used. If the potential of the unused I / O line is not determined and the state becomes a so-called floating state, there is a possibility that the potential of the unused I / O line becomes an intermediate potential due to electric charge leakage. In that case, if the logic circuit LC is input to the gate of a CMOS (Cmplement Metal Oxide Semiconductor) transistor, an excessive current flows constantly. To avoid this, unused ones of the I / O lines LIOi of the logic circuit LC latch the potential.
[0041]
When the enable signal LIOEi of the buffer circuit TGBUFi of the logic circuit LC is set to a low potential, as is apparent from the logic shown in FIG. Turns off. Further, the MOS transistor Q1 whose signal LIOPRi is input to the gate turns on, and the I / O signal LIOi is latched at a low level. For the I / O signal LIOi to be used, the enable signal LIOEi is set to a high potential. Switching of the data direction is performed as follows.
[0042]
When the memory core MR performs a read operation, the signal TGRW is set to a low potential. Then, when the enable signal LIOEi is at a high potential, only the read clocked inverter RINV is activated, and data is transferred from the I / O line LIOi ′ to the I / O line LIOi. On the other hand, when the memory core MR performs a write operation, the signal TGRW is set to a high potential. Then, when the enable signal LIOEi is at a high potential, only the write clocked inverter WINV is activated, data is transferred from the I / O line LIOi to the I / O line LIOi ', and the I / O line of the memory core MR is switched through the switch SW. Data is transferred to MIOi.
[0043]
As described above, when the embodiment shown in FIGS. 4 and 5 is used, a high-speed operation can be realized because the number of stages of the switch SW through which data to be transferred passes is one. Further, since the number of stages of the switches SW is equal to the number of transfer patterns, useless layout areas are not required, and high integration is possible. Furthermore, among the I / O lines LIOi of the logic circuit LC, the buffer circuit TGBUFi of the unused I / O line is stopped, and furthermore, the potential is prevented from being in a floating state. Excessive current can be prevented from flowing through the gate. Therefore, a transfer pattern that does not use a part of the I / O line can be set freely.
[0044]
In FIG. 4, unnecessary switches among the switches SW in the switch group SWG to which the control signal TGCi is not input are also provided. This is for the following reason. As can be seen from FIG. 4, the switch group SWG of the transfer circuit TG has a common shape irrespective of the transfer pattern except for the wiring required for the connection of the switch SW to the control signal TGCi, the connection to the I / O line MIOi, and the contacts. ing. Therefore, if common parts except for the connection of the switch to the TGCi and the wiring and the contact required for the connection to the MIOi are prepared as a layout library, the layout design of the chip becomes easy. Further, even in the case of correcting the transfer pattern, if all the switches SW in the switch group SWG are formed, it is not necessary to correct the mask of the transistor section constituting the switch SW, so that the number of masks to be corrected can be reduced. In a memory and logic mixed chip as in the present invention, it is necessary to change the memory capacity and the logic configuration depending on the application. Therefore, if several types of basic patterns of the above-mentioned switch SWG group for the memory core MR and the transfer circuit TG are prepared as a library, necessary ones are selected from them, and the logical part is further converted to the logical basic library LL. By combining and arranging and placing the wirings, the mask of the LSI chip can be quickly designed.
[0045]
[Second Specific Example of Transfer Circuit]
Of course, when the number of switches SW connected to the I / O line increases, a delay due to an increase in additional capacitance may become a problem. Therefore, when the number of stages of the switch group SWG is very large, the unnecessary switch SW may be omitted.
[0046]
FIG. 6 shows a second specific example of the transfer circuit TG in which the transfer circuit TG of FIG. 2 is implemented by a smaller number of seven-stage switch groups SWG than that shown in FIG. In FIG. 4, one switch group SWG corresponds to one transfer pattern. However, the transfer patterns P0, P1 and P2 in FIG. 3 have a common point for connecting the MIO0 and MIO1 of the I / O lines of the memory core MR and the I / O lines LIO0 and LIO1 of the logic circuit LC. Further, the transfer patterns P1 and P3 have a common point that connects MIO2 and MIO3 among the I / O lines of the memory core MR and the I / O lines LIO0 and LIO1 of the logic circuit LC. Focusing on this, the embodiment of FIG. 6 changes the switch groups SWG1 and SWG2 by deleting the switch group SWG0.
[0047]
The lower part of FIG. 7 shows how to set the control signals TGCi, TGRW, and LIOEi for realizing each transfer pattern (P0 to P7). Here, "1" indicates a high potential and "0" indicates a low potential. Since the transfer pattern P1 can only perform a write operation for the above-described reason, the control signal TGRW can be set only to "1". The setting of the control signal TGCi for realizing the transfer patterns P0 and P1 is different from the embodiment of FIG.
[0048]
In order to realize the transfer pattern P0, two control signals TGC1 and TGC2 may be set to a high potential. The control signal TGC1 connects MIO2 and LIO2 of the I / O lines, and the MIO3 and LIO3, and the control signal TGC2 connects MIO0 and LIO0 and LIO1 and MIO1 of the I / O lines.
[0049]
In order to realize the transfer pattern P1, the two control signals TGC2 and TGC3 may be set to a high potential. The control signal TGC2 connects MIO0 and LIO0 and LIO1 and MIO1 of the I / O lines, and the control signal TGC3 connects MIO2 and LIO0 and MIO3 and LIO1 of the I / O lines. In this embodiment, the number of stages of the switch group SWG can be reduced in this way. Here, the transfer patterns P0 and P1 are realized by activating the two switch groups SWG. The second feature is that data passes through only one switch SW. This point is different from the case where data passes through a plurality of stages, such as a conventional omega network. As described above, according to the present embodiment, higher speed can be achieved without impairing high speed.
[0050]
[Third Specific Example of Transfer Circuit]
FIG. 8 shows an example in which the number of stages of the switch group SWG is further reduced as compared with the embodiment of FIG. 6 by connecting the switches SW in parallel. In this example, the switch group SWG can be reduced to three stages. The control signal setting method is the same as that of the embodiment shown in FIG. In the example shown in FIG. 8, switches SW are arranged on both sides of the I / O line LIOi 'in each switch group SWG. FIG. 9 shows an example of the circuit configuration and layout of the switch SW. Each switch SW is composed of an nMOS (n-channel MOS) and a pMOS (p-channel MOS), and the control signals TGCi and TGCj are input to the gate of the nMOS, and the inverted signals TGCiB and TGCjB are input to the gate of the pMOS.
[0051]
The right side of FIG. 9 shows a layout example of the switch section. Here, only the nMOS is shown. M2, M1, CONT1, CONT2, L denote a second wiring layer, a first wiring layer, a contact between M1 and L, a contact between the first wiring layer and the second wiring layer, and a diffusion layer, respectively. In the present embodiment, the diffusion layer L between the MOSs constituting the two switches SW can be shared at the I / O line LIOi ', so that the pitch of the I / O line can be reduced. Here, the number of switches SW connected in parallel is two, but if the pitch of the I / O line is wide, three or more switches SW may be connected in parallel to further reduce the number of stages. Of course it is good.
[0052]
[Low power consumption by memory read / write circuit control signal]
In the embodiments shown in FIGS. 4, 6, and 8, the buffer circuit TGBUFi of the transfer circuit TG is controlled by an enable signal to reduce wasteful power consumption and to cause the gate potential of the logic circuit LC to be in a floating state. Is prevented.
[0053]
FIG. 10 further shows that the read / write circuit RWC of the memory core MR is controlled according to the transfer pattern, thereby driving the I / O line MIOi of the unused memory core MR to waste power consumption at the time of reading. An example is shown in which erroneous data is prevented from being written to the memory core MR from I / O lines MIOi that are not used at the time of writing.
[0054]
P2 to P7 of the transfer patterns in FIG. 2 use only a part of the I / O lines MIOi of the memory core MR. Therefore, a signal for controlling the write / read circuit RWC of the memory core MR is provided, and the write / read circuit RWCi for the I / O line MIOi of the unused memory core MR is stopped. In FIG. 10, RWC0, RWC1, RWC2, and RWC3 are circuits constituting the read / write circuit RWC, and are write / read circuits RWCi for the I / O lines MIO0, MIO1, MIO2, and MIO3 of the memory core MR, respectively. MIOE0, MIOE1, MIOE2, MIOE3 are enable signals for controlling the write / read circuits RWC0, RWC1, RWC3, respectively.
[0055]
FIG. 11 shows a setting method of the enable signals MIOE0, MIOE1, MIOE2, MIOE3 for controlling the write / read circuit RWCi and the enable signal LIOEi for the buffer circuit TGBUFi of the logic circuit LC in each transfer pattern. Here, “1” of the enable signal indicates a high potential, and “0” indicates a stopped state at a low potential in an active state. When the enable signals MIOE0, MIOE1, MIOE2, and MIOE3 are generated from the logic circuit LC adjacent to the memory core MR, the layout can be made higher by wiring through the transfer circuit TG as shown in FIG.
[0056]
According to the present embodiment, by controlling the read / write circuit RWC of the memory core MR according to the transfer pattern, unnecessary power consumption at the time of reading by driving unused I / O lines MIOi is reduced, Further, it is possible to prevent erroneous data from being written to the memory core MR from the I / O lines MIOi not used at the time of writing.
[0057]
[Common use of memory read / write circuit and buffer control signal]
In the embodiment shown in FIG. 10, the enable signal MIOEi for controlling the write / read circuit RWC and the enable signal LIOEi for the buffer circuit TGBUFi of the logic circuit LC are independent. In this case, it is necessary to make different settings according to the transfer pattern as shown in FIG. When the number of I / O lines and the number of transfer patterns increase, it is complicated to set the enable signals MIOEi and LIOEi independently.
[0058]
12 to 15 show an example in which a transfer circuit CTG for an enable signal LIOEi of a buffer circuit TGBUFi of a logic circuit LC is provided and an enable signal MIOEi of a write / read circuit RWC is automatically generated from the enable signal LIOEi. Is shown. FIG. 12 shows a transfer pattern of the data shown in FIG. FIG. 13 shows a transfer pattern of the control signal LIOEi of the buffer circuit TGBUFi corresponding to the data transfer pattern of FIG.
[0059]
If the control signal LIOEi of the buffer circuit TGBUFi is transferred to the memory core MR according to this transfer pattern, the signal can be used as it is as the enable signal MIOEi of the write / read circuit RWC of the memory core MR.
[0060]
Here, it should be noted that a control signal for an I / O line not used by data must be transferred to stop the write / read circuit RWC of the memory core MR. That is, even when data uses only some I / O lines as in the transfer patterns P1 to P7, all control signals are transferred as shown in the middle part of FIG.
[0061]
FIG. 14 shows a specific configuration of the transfer circuit CTG of the control signal LIOEi of the buffer circuit TGBUFi.
Is shown in Like the data transfer circuit TG, the switch group SWGEi is included. According to this transfer circuit CTG, the transfer pattern shown in the middle part of FIG. 8 can be realized by setting the control signal ECi according to the transfer pattern as shown in FIG.
[0062]
Here, it can be seen from the transfer patterns shown in FIG. 13 that the shapes of P0, P2, and P5 are the same. Therefore, the switch group SWGE relating to the control signals EC0, EC2, EC5 is collectively input as an OR of the control signals EC0, EC2, EC5. This makes it possible to reduce the number of stages of the switch group SWGE and achieve high integration. The principle of operation is the same as that of the data transfer circuit TG described above, and a description thereof will be omitted.
[0063]
According to the present embodiment, by providing the transfer circuit CTG of the control signal LIOEi of the buffer circuit TGBUFi in addition to the data transfer circuit TG, the enable signal MIOEi of the write / read circuit RWC and the enable signal LIOEi of the buffer circuit TGBUFi are independent of each other. Need not be set to For this reason, even if the number of I / O lines and the number of transfer patterns increase, the setting of the enable signal can be prevented from becoming complicated.
[0064]
[Enable signal that allows fine setting of data transfer unit]
In the embodiments described above, the enable signal MIOEi of the write / read circuit RWC and the enable signal LIOEi of the buffer are applied to the I / O lines (2 (n−2) power in FIG. 2) which are collectively transferred at the time of data transfer. Was provided. However, by making the setting of the enable signal finer, more various transfer patterns can be realized.
[0065]
16 and 17 show examples of enable signals that can be set more finely than data transfer units. In this embodiment, the unit of the I / O lines transferred collectively for the transfer pattern of FIG. 3 is set to 4 bytes, and the enable signal is set in units of 1 byte. That is, as shown in FIG. 16, the eight types of transfer patterns shown in FIG. 3 can be realized between the I / O line MIOi of the memory core MR and the I / O line LIOi of the logic circuit LC in units of 4 bytes, and enable Four signals are separately provided for a 4-byte I / O line group. For example, for the I / O line LIO0, there are four enable signals LIOE-0, LIOE-1, LIOE-2, and LIOE-3.
[0066]
FIG. 17 shows an example of a transfer pattern made possible in the example of FIG. 16 and a method of setting an enable signal therefor. The enable signal MIOEi-j may be generated by transferring the enable signal LIOEi-j, or may be set independently of the enable signal LIOEi-j. FIG. 17A shows a case where all the enable signals are set to "1" while the basic transfer pattern determined by the transfer circuit TG is set to P0. This is the same as the previous pattern. However, as shown in FIG. 17B, if the basic transfer pattern is P0 and the enable signal is "0" and "1" every 2 bytes, another transfer pattern can be created. FIG. 17C shows the basic transfer pattern P3, and FIG. 17D shows the setting of the enable signal changed in P3.
[0067]
Here, only one example of each of the two basic transfer patterns is shown. However, by changing the enable signal, various transfer patterns different from the basic transfer pattern can be formed. When data attributes are different for each byte for image use or the like, it may be necessary to transfer only specific bytes. In such a case, the present embodiment is useful.
[0068]
FIG. 18 shows an example in which the present invention is applied to an LSI that performs rendering processing of three-dimensional computer graphics (hereinafter, referred to as 3D-CG). The basic transfer pattern of the transfer circuit TG is shown in FIG. 3, and the data of the memory core MR is allocated to the I / O lines as shown in the upper part of FIG. Here, RGB-A and RGB-B are the colors of pixels A and B, and ZA and ZB are the depth coordinates of pixels A and B, each 16 bits long.
[0069]
In 3D-CG, a special process called Z comparison is often performed. As is well known, when a new pixel is written to the memory, the pixel at the same position is compared with the Z value. When such processing is performed on the pixel A, as shown in FIG. 18, first, the transfer pattern is set to P5, and the Z value Z-Aold already stored in the memory core MR is read. Subsequently, if Zin is smaller than the Z value Zin of the new pixel by the logic circuit LC, the RGB and Z value of the new pixel are written. Here, if the transfer pattern is switched to P2, RGB and Z values can be written in parallel. In the case of the pixel B, the transfer patterns P7 and P3 may be used. When the RGB value is 3 Bytes and the Z value is 2 Bytes and the number of bits is different, the basic transfer pattern of the transfer circuit TG is set to 3 Byte units. What is necessary is just to provide an enable signal and mask it.
[0070]
In 3D-CG, there is an alpha blending process for expressing transparency. This can be done as shown in the middle part of FIG. As is well known, when writing a new pixel to the memory, the alpha blending process is a process of reading a pixel at the same position, adding the new pixel to the new pixel by weighting with a coefficient α, and writing the result. When such processing is performed on the pixel A, as shown in FIG. 18, first, the transfer pattern is set to P4, and RGB-Aold already stored in the memory core MR is read. Subsequently, the logic circuit LC weights and adds the RGBin of the new pixel and the coefficient α to perform writing. The transfer pattern may be P4. In the case of the pixel B, the transfer pattern P6 may be used. In this case, if there is only one arithmetic circuit for performing weighted addition in the logic circuit, by providing an enable signal for each byte, it is possible to perform the alpha blending process for each of R, G, and B bytes.
[0071]
Furthermore, the process of clearing the screen can be performed at high speed. In this process, data in the memory core MR is initialized. Normally, for RGB, the minimum value or maximum value is written, and for the Z value, the maximum value that maximizes the depth is written. In the embodiment shown in FIG. 18, since there are two pixels of I / O lines, if the transfer pattern P1 is used, two pixels can be written simultaneously, so that the clearing process can be performed at high speed. Further, although not shown in FIG. 18, if the transfer pattern P0 and the enable signal are used, RGB of two pixels can be simultaneously read, so that high-speed screen display can be performed. As described above, high-speed 3D-CG drawing processing can be performed by using the transfer circuit TG of the present invention.
[0072]
[Example of assigning I / O lines by byte]
Until now, for simplicity of explanation, I / O lines MIOi and LIOi have been allocated and illustrated for each transfer unit. If this is done in an actual layout, especially when the transfer unit is large, data is transmitted across many I / O lines, which may have adverse effects such as wiring delay and noise.
[0073]
FIG. 19 shows an example in which the allocation of I / O lines is changed for each byte. The example of FIG. 19 shows a method of nesting one byte at a time when the transfer unit is 4 bytes. In this way, data movement is reduced. For example, in the case of the transfer pattern P3, as shown in FIG. 3, it is necessary to cross an I / O line for 8 bytes, but in the example of FIG. Here, replacement is performed for each byte, but replacement may be performed for each bit. In that case, less movement is required. Of course, in the case of the present embodiment, the receptacle of the logic circuit LC also needs to be designed in accordance with it, but it avoids bad influences such as wiring delay and noise induction, and further reduces the increase in area due to an increase in wiring. be able to.
[0074]
【The invention's effect】
According to the present invention, a semiconductor in which a memory and a logic circuit are integrated can be designed in a short period of time. And realizes high-speed data transfer.
[Brief description of the drawings]
FIG. 1 is a concept of a system LSI with a built-in multiple I / O memory core according to the present invention.
FIG. 2 is an example of an LSI with a built-in multiple I / O memory core according to the present invention.
FIG. 3 is a transfer pattern of the transfer circuit of FIG. 2;
FIG. 4 is a first specific example of a transfer circuit that realizes the transfer pattern of FIG. 3;
FIG. 5 is a specific example of a buffer circuit TGBUFi of a transfer circuit.
FIG. 6 is a second specific example of a transfer circuit that realizes the transfer pattern of FIG. 3;
FIG. 7 is a method for setting a control signal of the transfer circuit of FIG. 6;
FIG. 8 is a third specific example of a transfer circuit that realizes the transfer pattern of FIG. 3;
9 is a circuit configuration and layout example of a parallel switch unit of the transfer circuit in FIG.
FIG. 10 illustrates an example in which power consumption is reduced by a memory read / write control signal.
11 is a setting method of a control signal of the transfer circuit of FIG.
FIG. 12 is a data transfer pattern.
FIG. 13 is a transfer pattern of a buffer control signal.
FIG. 14 illustrates an example of a control signal transfer circuit.
FIG. 15 is a control signal setting method of the control signal transfer circuit of FIG. 14;
FIG. 16 shows an example of an enable signal that can be set more finely than a data transfer unit.
FIG. 17 shows an example of a transfer pattern enabled by the example of FIG. 16;
FIG. 18 is an example of application to three-dimensional computer graphics.
FIG. 19 is an example in which the address of an I / O line is changed for each byte.
[Explanation of symbols]
MR memory core
MC memory cell
DL data line
WL word line
PER peripheral circuit
RWC read / write circuit
LC logic circuit
TG transfer circuit
SWG switch group
TGBUFi buffer group
MIOi, TGCi, LIOi control signal
DB core circuit, logical library database storage
LL logic library
WS design workstation
LSI-A, LSI-B Semiconductor chip.

Claims (7)

A memory core having a plurality of first I / O lines;
A logic circuit having a plurality of second I / O lines;
A data transfer circuit that performs data transfer between the plurality of first I / O lines and the plurality of second I / O lines,
The data transfer circuit has the same pitch as the plurality of first I / O lines, and includes a plurality of third I / O lines for connecting to the plurality of first I / O lines, and data between the plurality of third I / O lines and the logic circuit. And a plurality of switches connected between the plurality of third I / O lines and the plurality of fourth I / O lines,
A data transfer pattern between the plurality of third I / O lines and the plurality of fourth I / O lines is realized by switching the on / off state of the plurality of switches with a switch control signal supplied to the data transfer circuit. A semiconductor integrated circuit device that can be changed with time. In claim 1,
A semiconductor integrated circuit device, wherein a wiring of the switch control signal is arranged orthogonally to a wiring of the plurality of first I / O lines or a wiring of the plurality of second I / O lines. In claim 1 or claim 2,
The plurality of switches are arranged at the same pitch as the plurality of first I / O lines in a direction parallel to the plurality of first I / O lines, and are arranged in a direction orthogonal to the plurality of first I / O lines. A semiconductor integrated circuit device characterized by being arranged side by side. 4. The semiconductor integrated circuit device according to claim 1, wherein:
The logic circuit is synthesized by combining basic logic gates,
A semiconductor integrated circuit device, wherein the plurality of switches are formed of MOS transistors and have a common shape. The semiconductor integrated circuit device according to claim 1, wherein
At least one of the data transfer patterns is connected to a plurality of the second I / O lines for one of a plurality of fourth I / O lines. In any one of claims 1 to 5,
A semiconductor integrated circuit device, wherein the memory core includes a DRAM type cell including one transistor and one capacitor. Creating a memory core having a plurality of first I / O lines, a logical library, and a library of transfer circuit modules;
Synthesizing a desired logic circuit from the logic library;
A method for designing a semiconductor integrated circuit device, comprising: a step of setting a wiring between the logic circuit and the transfer circuit and a wiring between the plurality of first I / O lines and the transfer circuit module. ,
The transfer circuit module has the same pitch as the plurality of first I / O lines, and includes a plurality of second I / O lines for connecting to the plurality of first I / O lines, and A plurality of 3 I / O lines for transmitting and receiving data, and a plurality of switches for connecting the plurality of second I / O lines and the plurality of third I / O lines;
In the step of setting the wiring, by setting a wiring for supplying a switch control signal for switching an on / off state of the plurality of switches to the transfer circuit module, the plurality of second I / O lines and the plurality of third I A method for designing a semiconductor integrated circuit device for setting a data transfer pattern to / from the / O line.

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