JP3565290B2 - Multi-port memory - Google Patents

Description

[0001]
[Industrial applications]
According to the present invention, a memory cell matrix in which memory cells are arranged in a matrix is provided with N sets of word lines in a row direction and N sets of bit lines in a column direction, and independently of N ports. Addresses multiport memory that can be specified and accessed.Especially, by suppressing stray capacitance between ports and reducing mutual interference due to electromagnetic induction while suppressing the extension of access time, the bit of a port during read access is reduced. The present invention relates to a multi-port memory capable of further reducing the noise mixed with the operation of a port during a write access to a line.
[0002]
[Prior art]
Conventionally, a plurality of CPUs (central processing units) have been provided, resources such as storage devices, input / output devices, and data have been shared between CPUs, and data transfer and processing execution among these CPUs by some means. A multi-CPU computer system that executes one or a plurality of given processes in parallel while performing the above-described synchronization. In such a multi-CPU computer system, there are a loosely coupled CPU and a tightly coupled CPU. Some of these tightly coupled and sometimes loosely coupled ones use a dual port memory between CPUs in order to transfer data between CPUs and synchronize processing execution. In addition to the multi-CPU computer system, such a dual-port memory may be used to synchronize data transfer and processing execution between two systems.
[0003]
A multi-port memory having a plurality of ports, such as a dual-port memory, has N sets of word lines in the row direction and N sets in the column direction with respect to a memory cell matrix in which memory cells are arranged in a matrix. , And can be addressed and accessed independently from each of the N ports. Further, in a general multi-port memory, an address decoder, a write circuit, a sense amplifier, an input / output buffer, and the like are provided independently for each port with respect to a common memory cell matrix.
[0004]
FIG. 6 is a block diagram showing a configuration of a conventional dual port memory.
[0005]
In FIG. 6, for a memory cell matrix 1 in which memory cells are arranged in a matrix of 6 rows and 6 columns, six word lines are provided in the horizontal row direction of FIG. 6 bit line pairs are provided in the vertical column direction. Using these word line and bit line pairs, addressing can be performed independently from two ports, that is, the A port and the B port, so that any one memory cell MC in the memory cell matrix 1 can be accessed. ing.
[0006]
Such a dual-port memory includes a row decoder 16 for outputting a signal to the memory cell matrix 1 to a word line for A port and a word line for B port, an A port control circuit 14A, It comprises a data input / output circuit 13A, an A port column decoder 12A, a B port control circuit 14B, a B port column decoder 12B, and a B port data input / output circuit 13B.
[0007]
First, the A-port control circuit 14A and the B-port control circuit 14B receive an address signal AAD or BAD from outside and a read / write control signal ARW or BRW, respectively. According to such an input signal, the A port control circuit 14A16, And controls the A port column decoder 12A and the A port data input / output circuit 13A. The B port control circuit 14B controls the row decoder 16, the B port column decoder 12B, and the B port data input / output circuit 13B.
[0008]
The row decoder 16 first decodes an MSB (most significant bit) side bit of the address signal AAD input via the A port control circuit 14A, and decodes one of the six word lines for the A port. The book is selected. Similarly, the row decoder 16 decodes the MSB side bit of the address signal BAD input via the B port control circuit 14B, and connects one of the six word lines for the B port. Select the state.
[0009]
The A-port column decoder 12A is provided for the memory cell matrix 1 based on a result of decoding the LSB (least significant bit) side bit of the address signal AAD input via the A-port control circuit 14A. One of the six pairs of bit lines for the A port is selected and connected to the A port data input / output circuit 13A. Similarly, according to the result of decoding the LSB side bit of the address signal BAD input via the B port control circuit 14B, the B port column decoder 12B is provided with six pairs of B ports provided in the memory cell matrix 1. One of the paired bit line pairs is connected to the B port data input / output circuit 13B.
[0010]
The A port data input / output circuit 13A is connected to the word line of the A port selected by the row decoder 16 and to the bit line pair of the A port selected by the A port column decoder 12A. It controls input / output of bit data at the time of read access or write access to one of the memory cells MC. The B port data input / output circuit 13B is connected to the word line of the B port selected by the row decoder 16 and to the bit line pair of the B port selected by the B port column decoder 12B. It controls bit data input / output at the time of read access or write access to one of the memory cells MC. The A port data input / output circuit 13A or the B port data input / output circuit 13B controls read access when the read / write control signal ARW or BRW is in the H state. Alternatively, if these read / write control signals ARW or BRW are in the L state, write access control is performed.
[0011]
Here, the A port data input / output circuit 13A and the B port data input / output circuit 13B each have a sense for reading bit data of one selected memory cell MC used at the time of read access. An amplifier is provided.
[0012]
In order to increase the storage capacity per unit area of the integrated circuit, it is necessary to further improve the degree of integration of the memory cell matrix 1. For this reason, the transistors and wirings in the memory cell matrix 1 are miniaturized, and the wiring intervals are narrowed. Therefore, the output drive capability of the flip-flop that holds the bit data to be stored and that constitutes the memory cell matrix 1 is minimized, and the bit line for reading the bit data stored in the flip-flop is thin. Have been. Therefore, the potential difference between the bit line pairs indicating the bit data to be read tends to be smaller. For this reason, the above-described sense amplifier included in the A-port data input / output circuit 13A or the B-port data input / output circuit 13B amplifies the potential difference between the bit line pair thus smaller, and selects the selected memory cell MC. The bit data stored in is read out.
[0013]
However, since the potential difference from the memory cell MC thus read is small, it is easily affected by noise and the like. For example, in a multi-port memory, a bit line pair of each port is provided in parallel with the memory cell matrix 1. For this reason, mutual interference easily occurs due to stray capacitance or electromagnetic induction between the ports of the bit line pair, and there is a problem such as noise. In particular, when the wiring interval is narrowed by fine processing, such a stray capacitance increases.
[0014]
For example, let us consider a case where another port performs a write access while a certain port is performing a read access using a port-specific bit line pair. In this case, the voltage of the bit data to be written is applied to the bit line pair dedicated to the port to be accessed for writing in parallel with the bit line pair of the port being accessed for reading, and the writing current flows. At this time, the voltage of the bit line pair of the port during the write access affects the voltage of the bit line pair of the port during the read access whose voltage is relatively low due to the stray capacitance, and erroneous data is read. Sometimes. Alternatively, a write current flowing through the bit line pair of the port being accessed for writing may generate a voltage due to electromagnetic induction in the bit line pair of the port being accessed for reading, and erroneous data may be read.
[0015]
In JP-A-4-143994 and JP-A-5-234376, by reducing the stray capacitance between ports and mutual interference due to electromagnetic induction, the bit line of the port being accessed for reading is connected to the port being accessed for writing. There is disclosed a technique for reducing the mixing of noise due to the operation. In JP-A-4-143994 and JP-A-5-234376, by twisting a bit line pair provided in a memory cell matrix, the influence of stray capacitance from another bit line pair and electromagnetic induction is reduced.
[0016]
FIG. 7 is a circuit diagram showing a gist of a conventional twist of a bit line pair for reducing mutual interference between ports.
[0017]
In FIG. 7, a memory cell array 10 shows a group of memory cells for one row connected to the same word line in a memory cell matrix. For example, in the memory cell matrix 1 of FIG. 6, a total of six memory cells MC connected to one word line output from the row decoder 16 are included in one of the memory cell arrays 10. Is equivalent to The memory cell array 10 is arranged in the vertical direction in FIG.cellThey are arranged in the column direction of the matrix and are connected to the A port column decoder 12A and the B port column decoder 12B.
[0018]
Here, in JP-A-4-143994 and JP-A-5-234376, the bit line pair BA-BAN for the A port is twisted between the memory cell arrays 10 as shown in FIG. The bit line pair BB-BBN is not twisted. By doing so, the mutual interference between the bit line pair BA-BAN of the A port and the bit line pair BB-BBN of the B port is in the opposite direction between the adjacent memory cell arrays 10 and cancel each other. be able to. As a result, it is possible to reduce a malfunction due to mutual interference between the ports, for example, noise mixing and erroneous data readout due to the noise.
[0019]
Specifically, as shown in FIG. 8, a stray capacitance C exists between the bit line pair BA-BAN and the bit line pair BB-BBN, and one voltage affects the other voltage. And mixed as noise.
[0020]
Here, for example, of the bit line pair BA-BAN, attention is paid to the bit line BA.
[0021]
First, in the memory cell array 10-1, the influence of the bit line BB is greater than the influence of the bit line BBN due to the arrangement distance. Next, in the adjacent memory cell array 10-2, the bit line BA is more affected by the bit line BBN than the bit line BB. In the next adjacent memory cell array 10-3, the effect is further reversed, and the effect on the bit line BA is greater on the bit line BB than on the bit line BBN.
[0022]
Here, since the influence of the bit line BB and the influence of the bit line BBN are opposite to the bit line BA, the memory cell arrays 10-1 to 10-6... The influence of the bit line pair BB-BBN on the bit line BA is reduced by exchanging the magnitude of the influence of the bit lines BB and BBN.
[0023]
FIG. 9 is a time chart showing mutual interference between ports in the dual port memory.
[0024]
In the time chart of FIG. 9, the read / write control signal ARW of the A port and the read / write of the B port when the twisting of the bit line pair is not performed as in the above-mentioned JP-A-4-143994 and JP-A-5-234376. A control signal BRW, an address signal AAD of A port, an address signal BAD of B port, input data BDI and bit line BB or BBN of B port during write access, and a bit line BA of A port during read access , BAN and the timing with the output data ADO.
[0025]
In the time chart of FIG. 9, first, the address signal AAD input to the A port during the read access changes at time t30, and the bit data stored in the memory cell selected in accordance with this changes. At time t31, it is output to the bit line pair BA-BAN of the A port. Thereafter, the bit data of the bit line pair BA-BAN is output as the output data ADO of the A port at time t32.
[0026]
Similarly, the address signal AAD input to the A port during the read access also changes at time t37. Accordingly, the bit data stored in the memory cell selected according to the input address signal AAD is output to the bit line pair BA-BAN at time t39, and the output data of the A port is output at time t40. Read as ADO.
[0027]
In this time chart, write access is performed from port B while read access is being performed from port A.
[0028]
First, at time t33, input data BDI (BDI1) to be written is input to the already input address signal BAD (address B0). Accordingly, at time t34, the voltage of the bit line pair BB-BBN of the B port changes, and a write current flows accordingly.
[0029]
Then, such a write current affects the bit line pair BA-BAN of the A port by electromagnetic induction. For example, between time t34 and time t35 in FIG. 9, the voltage of the bit line pair BA-BAN becomes unstable. Further, as indicated by the hatched portion in FIG. 9, the output data ADO obtained as read data is incorrect data.
[0030]
Subsequently, at time t36, another input data BDI (BDI0) is input as write data to the same address (B0) indicated by the address signal BAD of the B port. Accordingly, at time t38, the voltage of the bit line pair BB-BBN at the B port changes, and accordingly, a write current flows to the bit line pair BB-BBN. Such a write current affects the bit line pair BA-BAN of the A port due to the electromagnetic induction, and the access time until the read data of the A port at the time t39 is determined is extended. I have. Therefore, the output of the output data ADO (ADO0) obtained as the read data of the A port at the time t40 described above is also delayed.
[0031]
When the bit line pair BA-BAN is twisted between the memory cell arrays 10 as shown in FIG. 7 as in the above-mentioned JP-A-4-143994 or JP-A-5-234376, writing from one port is performed. When the bit data stored in the memory cell is read from another port, the logic of the obtained bit data is reversed. For example, in a certain memory cell, "1 (H state)" is written from the A port, but when this is read from the B port, the inverted "0 (L state)" is read. I will.
[0032]
For this reason, in Japanese Patent Laid-Open No. Hei 5-234376, when access is made through a port for twisting a bit line pair, when accessing an even-numbered or odd-numbered address where the logic of data is reversed as described above, the input / output The read data and the write data are inverted in some parts. For example, in the case of a twisted port, an even address or an odd address whose logic is reversed is determined according to one bit of the LSB of the address signal, and read data or write data is inverted.
[0033]
[Problems to be solved by the invention]
However, in Japanese Patent Application Laid-Open No. 4-143994, although the stray capacitance between ports of a multi-port memory and mutual interference due to electromagnetic induction can be reduced, as described above, the logic of read data or write data between different ports is reversed. turn into. Alternatively, in Japanese Patent Laid-Open No. Hei 5-234376, the logic of the read data or the write data is not reversed between different ports, but the read data and the write data are appropriately inverted at the input / output portion of the memory. Need to be done. Therefore, of course, the access time for such read access or write access is extended. For example, it takes time to determine whether to invert read data or write data depending on whether the LSB of an address signal input to a port to be twisted is “0” or “1”. The signal delay time due to the inverter for inversion must also be taken into account, and the access time is extended.
[0034]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is possible to reduce the stray capacitance between ports and mutual interference due to electromagnetic induction while suppressing the extension of access time, so that ports during read access can be prevented. It is an object of the present invention to provide a multi-port memory capable of further reducing the noise mixed with the operation of a port during a write access to a bit line.
[0035]
[Means for achieving the object]
According to the present invention, a memory cell matrix in which memory cells are arranged in a matrix is provided with N sets of word lines in a row direction and N sets of bit lines in a column direction, and independently of N ports. In a multi-port memory that can be addressed and accessed, at least at a port accessible for writing and at least another port accessible for reading, the bit line of any port is also a positive logical bit line. And one port is a twisted bit line pair port, the other port is a fixed bit line pair port, and the bit line pair of the twisted bit line pair port is In the memory cell matrix, the bit data is periodically twisted, and thereby the bit data in which the arrangement positions of the bit line pairs are interchanged. An inversion section and a non-inverted bit data non-inversion section are alternately and periodically present, while the bit line pair of the fixed bit line pair port alternately has the bit data inversion section and the bit data non-inversion section. Wiring that is not twisted in the section to be drawn and is drawn out to each bit line of the bit line pair of the twisted bit line pair portAnd beforeThe fixed bit line pair port bit line paireachTo bit lineThese with the wiring drawn outWiring signal logicWere made in the same direction as each other so thatA positive logic memory cell used as one of the memory cells, and wiring drawn out for each bit line of the bit line pair of the twisted bit line pair portAnd beforeThe fixed bit line pair port bit line paireachTo bit lineThese wirings are made in the opposite directions so that the logic of the signals of these wirings is the same as that of the wiring drawn out., A negative logic memory cell used as one of the memory cells, and the positive logic memory cell is arranged in the bit data non-inversion section.SaidThe above object has been achieved by arranging the negative logic memory cells in the bit data inversion section.
The N sets of word lines, the N sets of bit lines, and the N ports are not particularly limited as long as the functions and effects of the present invention are exhibited. For example, a set of bit lines may be used.
[0036]
Further, in the multi-port memory, the positive logic memory cell and the negative logic memory cell are connected to each other at an input and an output of two inverter gates, one connection point is a positive logic point, and the other is a positive logic point. And a positive logic memory cell is provided between the twisted bit line and the positive logic bit line of the port with respect to the positive logic point, and A pass transistor having a gate connected to a corresponding word line of the corresponding port is provided between the fixed bit line pair and the positive logic bit line of the port, and the twisted bit line is connected to the negative logic point. Between the negative logic bit line of the port and the fixed bit line and the negative logic bit line of the port, Comprising a pass transistor over bets are connected, the negative logic memory cells, wherein for positive logic point, the said twisted bit line pair portsPositive logicA pass transistor having a gate connected to a corresponding word line of a corresponding port between the bit line and the positive logic bit line of the fixed bit line pair port; With respect to the point, the twist bit line pair of the portNegative logicPass transistors each having a gate connected to a corresponding word line of the corresponding port between the fixed bit line and the negative logic bit line of the port.ingThus, the above object is achieved, and the positive logic memory cell and the negative logic memory cell are realized with a smaller number of wiring layers as a semiconductor integrated circuit, so that the multiport memory of the present invention can be provided. .
Further, in the multi-port memory, in each of the positive logic memory cell and the negative logic memory cell, the connection of each pass transistor to the positive logic point and the negative logic point extends the transistor region of each pass transistor. By doing so, the above object has been achieved.
[0037]
[Action]
As described above, when a bit line pair is twisted between adjacent memory cells as described in JP-A-4-143994 and JP-A-5-234376, bit data written between one port and another port is written to another memory cell. If the data is read out from the port, there is a memory cell in which inverted data is read out.
[0038]
For this reason, in the present invention, the memory cell from which such inverted data is read is different from a normally used memory cell, that is, different from what is referred to as a positive logic memory cell in the present invention. In the present invention, what is called a negative logic memory cell is exclusively used. Therefore, in the present invention, it is not necessary to invert the read access data or the write access data at the input / output portion of the memory as needed as in the above-mentioned Japanese Patent Application Laid-Open No. 5-234376.
[0039]
Specifically, first, at least in a port that can be accessed for writing and at least another port that can be accessed for reading, the bit lines related to these ports are particularly formed as a bit line pair, and one of the bit line pairs is connected. It is called a positive logic bit line, and the other is called a negative logic bit line. One of the ports is called a twisted bit line pair port, and the other port is called a fixed bit line pair port. In particular, the bit line pair of the twisted bit line pair port is periodically twisted in the memory cell matrix, and thereby, the bit data inversion section in which the arrangement positions of the bit line pairs are periodically switched and the bit data inversion section are switched. No bit data non-inverted sections alternately and periodically exist. On the other hand, the bit line pair of the fixed bit line pair port is not twisted in a section in which the bit data inversion section and the bit data non-inversion section alternately exist.
[0040]
Under such a premise, in the present invention, the wiring for drawing the positive logic memory cell to each bit line of the bit line pair of the twisted bit line pair port is provided.And beforeThe fixed bit line pair port bit line paireachTo bit lineThese with the wiring drawn outWiring signal logicThese wirings are made in the same direction as each other so thatAnd On the other hand, the negative logic memory cell is a wiring drawn for each bit line of the bit line pair of the twisted bit line pair port.And beforeThe fixed bit line pair port bit line paireachTo bit lineThese wirings are made in the opposite directions so that the logic of the signals of these wirings is the same as that of the wiring drawn outIt has become.
[0041]
For example, in the embodiment described later, the one shown in FIG. 1 is a positive logic memory cell, and the one shown in FIG. 2 is a negative logic memory cell. Here, in FIGS. 1 and 2, one port is an X port accessed by the bit line pair BX-BXN. Another port is a Y port accessed by the bit line pair BY-BYN. Then, for the positive logic memory cell such as the one shown in FIG. 1, the bit data (logical state) written from one of the ports at the X port and the Y port is read from another port as it is. On the other hand, in a negative logic memory cell such as that shown in FIG. 2, the bit data (logical state) written from one of the ports at the X port and the Y port is inverted and read from another port.
[0042]
As described above, in the present invention, by appropriately using the positive logic memory cell and the negative logic memory cell, the bit between the memory cells as described in Japanese Patent Application Laid-Open Nos. 4-143994 and 5-234376 is used. Although the line pair is twisted, it is not necessary to appropriately invert the read data or the write data in the input / output portion of the memory as in the case of Japanese Patent Laid-Open No. Hei 5-234376. Therefore, by reducing the stray capacitance between ports and mutual interference due to electromagnetic induction while suppressing the extension of the access time, noise associated with the operation of the port during write access to the bit line of the port during read access is reduced. Can be further reduced.
[0043]
When the negative logic memory cell is provided together with the positive logic memory cell, the structure of the memory cell becomes dramatically complicated, and the three-dimensional intersection of the wiring in the memory cell increases, so that the metal wiring It is a general impression that the number of wiring layers such as layers and polysilicon layers must be increased. However, according to the inventor, it has been confirmed that the positive logic memory cell and the negative logic memory cell can be provided to the same degree as in the related art, as in an embodiment described later. The present invention pays particular attention to such a point.
[0044]
In the present invention, the twist of the bit line pair that is periodically performed as described above is not necessarily limited to the twist that is performed for each memory cell. For example, the bit line pair may be twisted for every two or more memory cells. However, twisting at a finer pitch can reduce the mutual interference between ports more effectively. In the case where the bit line pair is twisted for every two or more memory cells, it is preferable that the cycle of the number of memory cells to be twisted is constant from the viewpoint of reducing the mutual interference between ports.
[0045]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0046]
FIG. 1 is a circuit diagram of the positive logic memory cell used in the embodiment of the multiport memory to which the present invention is applied. FIG. 2 is a circuit diagram of the negative logic memory cell used in this embodiment.
[0047]
In the present embodiment, the twist of the bit line pair described above with reference to FIGS. 7 and 8 is performed at the cycle of the wiring pitch of one memory cell with respect to the dual port memory of FIG. is there. In particular, in this embodiment, when the bit data written from one port is read from the other port, the logic is inverted between the written bit data and the read bit data caused by such a twist. The negative logic memory cell shown in FIG. 2 is used for the memory cell to be erased, and the positive logic memory cell shown in FIG. 1 is used for the other memory cells.
[0048]
In this embodiment, the A port corresponds to the twisted bit line pair port of the present invention, and the B port corresponds to the fixed bit line pair port.
[0049]
First, the positive logic memory cell of FIG. 1 will be described.
[0050]
As shown in FIG. 1, the positive logic memory cell includes an inverter gate composed of a P-channel MOS transistor TP11 and an N-channel MOS transistor TN11, and an inverter gate composed of a P-channel MOS transistor TP12 and an N-channel MOS transistor TN12. And pass transistors TN1 to TN4. First, the input of the first inverter gate and the output of the second inverter gate are connected to each other (the connection point is hereinafter referred to as a positive logic point), and the output of the first inverter gate and the second inverter gate are connected. The inputs of the gates are mutually connected (the connection point is hereinafter referred to as a negative logic point) to form one flip-flop. In the positive logic memory cell, bit data is stored in the flip-flop.
[0051]
Next, the gates of the pass transistors TN1 and TN2 are both connected to the word line WA of the A port. The source and the drain of the pass transistor TN1 are connected to the positive logic point and the bit line BA of the A port. The source and the drain of the pass transistor TN2 are connected to the negative logic point and the bit line BAN of the A port.
[0052]
The gates of the pass transistors TN3 and TN4 are connected to the word line WB of the B port. First, a source and a drain of the pass transistor TN3 are connected to the positive logic point and the bit line BB of the B port. Next, the source and the drain of the pass transistor TN4 are connected to the negative logic point and the bit line BBN of the B port.
[0053]
Therefore, in such a positive logic memory cell, when performing read access or write access from the A port, if the word line WA of the A port is set to the H state, the pass transistors TN1 and TN2 are turned on. Then, the bit line BA of the A port is connected to the positive logic point, and the bit line BAN is connected to the negative logic point. Therefore, the bit lines BA and BAN enable read access and write access to the flip-flop of the positive logic memory cell.
[0054]
Similarly, when performing a read access or a write access from the B port, the pass transistors TN3 and TN4 are turned on by setting the word line WB of the B port to the H state. Thereby, the bit line BB of the B port is connected to the positive logic point, and the bit line BBN of the B port is connected to the negative logic point. Therefore, these bit lines BB and BBN enable read access and write access to the flip-flop of the positive logic memory cell.
[0055]
Here, the bit line BA on the positive logic side of the A port and the bit line BB on the positive logic side of the B port are both connected to the positive logic point. The bit line BAN on the negative logic side of the A port and the bit line BBN on the negative logic side of the B port are both connected to the negative logic point.
[0056]
Therefore, in the positive logic memory cell, the same bit data written from the A port can be read from the B port, and the same bit data written from the B port is read from the A port. It is possible.
[0057]
Subsequently, the negative logic memory cell of the present embodiment of FIG. 2 will be described.
[0058]
First, FIG. 1 showing the positive logic memory cell includes, in order from the left, the bit line BB on the positive logic side of the B port, the bit line BA on the positive logic side of the A port, and the negative logic of the A port. The bit line BAN on the side and the bit line BBN on the negative logic side of the B port are shown in this order. On the other hand, in FIG. 2 showing the negative logic memory cell of this embodiment, in order from the left, the bit line BB on the positive logic side of the B port, the bit line BAN on the negative logic side of the A port, and the positive logic of the A port The bit line BA and the bit line BBN on the negative logic side of the port B are different from the order of FIG. That is, the bit lines BA and BAN are interchanged due to the twist.
[0059]
However, according to the negative logic memory cell of this embodiment, even if the arrangement positions of these bit lines are switched by twisting, the same bit data written from the A port can be read from the B port. In addition, the same bit data written from the B port can be read from the A port. This is because even if the arrangement positions of the bit lines BA and BAN are exchanged due to the twist of the bit line pair, the positive and negative logical points of the bit lines BA, BAN, BB and BBN, and the flip-flop, This is because the connection relationship between the pass transistors TN1 to TN4 is the same as that of the positive logic memory cell of FIG.
[0060]
FIG. 3 is an integrated circuit layout diagram of the positive logic memory cells and the negative logic memory cells of the present embodiment.
[0061]
FIG. 3 shows a layout diagram of the positive logic memory cell shown in FIG. 1 and the negative logic memory cell shown in FIG. 2, which are adjacent to each other in the bit line direction (column direction). Have been. As shown in FIG. 3, the middle stage is a twist region, the lower logic region is provided with the positive logic memory cells, and the lower logic region is provided with the negative logic memory cells above the twist region.
[0062]
In FIG. 3, a transistor region formed directly on the silicon substrate is shown by a broken line. The two-dot chain line indicates wiring using a polysilicon layer formed on an oxide insulating film on a silicon substrate. The alternate long and short dash line is a wiring of a second aluminum wiring layer formed on the silicon substrate via an oxide insulating film, and also insulated from the polysilicon layer by the oxide insulating film and stacked thereabove. . The solid line is the wiring of the second aluminum wiring layer formed above the first aluminum wiring layer via the oxide insulating film.
[0063]
The crosses indicate contacts connecting the transistor region of the silicon substrate to the wiring formed in the first aluminum wiring layer, or the wiring formed in the polysilicon layer and the wiring formed in the first aluminum wiring layer. Are connected. The □ marks with x marks indicate contacts that connect them from the transistor region on the silicon substrate to the wiring formed in the second aluminum wiring layer, for example, a polysilicon layer or a first aluminum wiring between them. If there is a layer wiring, this is also a contact to be connected. The symbol □ indicates a contact connecting the wiring formed in the first aluminum wiring layer and the wiring formed in the second aluminum wiring layer.
[0064]
First, the word lines WA and WB are formed in the horizontal direction of FIG. 3 as shown by a dashed line. In the vertical direction of FIG. 3, the bit lines BA, BAN, BB, and BBN, and the ground lines GNDa and GNDb are formed as shown by solid lines. Further, a power supply line VDD (not shown) is formed on each of the left and right sides to supply power as described later. In particular, in the above-described twist region, the bit lines BA and BAN are twisted (three-dimensional intersection) by the wiring G1 formed in the first aluminum wiring layer. It should be noted that the same method is used below the positive logic memory cell in the lower part of FIG. 3 and above the negative logic memory cell in the upper part of FIG. 3 while using the wiring formed in the first aluminum wiring layer. Twist has been made.
[0065]
The power supply line VDD may be formed in the horizontal direction as shown in FIG. The power supply line VDD not shown in FIG. 3 (the vertical direction in FIG. 3 as described above) is replaced with the horizontal power supply line VDDa formed in the dashed-dotted first aluminum wiring layer in FIG. , And VDDb. First, the power supply line VDDa is connected to the respective sources of the P-channel MOS transistors TP11 and TP12 of the positive logic memory cell by contacts indicated by crosses. In addition, the power supply VDDb is connected to the respective sources of the P-channel MOS transistors TP11 and TP12 of the negative logic memory cell by contacts indicated by crosses.
[0066]
Next, the positive logic memory cell of the present embodiment shown in the lower part of FIG. 3 will be described with reference to FIG.
[0067]
First, in the transistor region A5, the pass transistors TN1 and TN3 and the N-channel MOS transistor TN12 shown in FIG. 1 are formed. In particular, a crossing portion of the wiring G5 crossing the transistor region A5 is a gate of the pass transistor TN1. The intersection of the transistor area A5 and the wiring G6 that intersects with each other forms the gate of the pass transistor TN3. The intersection of the wiring G8 intersecting with the transistor region A5 is the gate of the N-channel MOS transistor TN12.
[0068]
Next, the pass transistors TN2 and TN4 and the N-channel MOS transistor TN11 are formed in the transistor region A6. In particular, a crossing portion of the wiring G5 crossing the transistor region A6 serves as a gate of the pass transistor TN2. A crossing portion of the wiring G6 crossing the transistor region A6 serves as a gate of the pass transistor TN4. The intersection of the wiring G7 intersecting with the transistor region A6 is the gate of the N-channel MOS transistor TN11.
[0069]
In particular, the transistor region A5 also serves as a wiring connecting the source or drain of each of the pass transistors TN1 and TN3 and the N-channel MOS transistor TN12 between these transistors. The transistor region A6 also serves as a wiring connecting the source or drain of each of the pass transistors TN2 and TN4 and the N-channel MOS transistor TN11 between these transistors.
[0070]
Next, the P-channel MOS transistor TP11 is formed in the transistor region A7. The intersection of the wiring G7 intersecting with the transistor region A7 is the gate of the P-channel MOS transistor TP11. The P-channel MOS transistor TP12 is formed in the transistor region A8. The intersection of the wiring G8 intersecting with the transistor region A8 is the gate of the P-channel MOS transistor TP12.
[0071]
Here, the gate of the N-channel MOS transistor TN11 and the gate of the P-channel MOS transistor TP11 are connected by a wiring G7, and the wiring G7 is an input of the first inverter gate. The drain of the P-channel MOS transistor TP12 and the drain of the N-channel MOS transistor TN12 are connected by a wiring H4, and the wiring H4 is an output of the second inverter gate. Further, the wiring H4 is connected to the wiring G7 of the input of the first inverter gate, and can be said to be the positive logic point. The positive logic point is connected to the pass transistors TN1 and TN3 by extending the transistor regions of the pass transistors TN1 and TN3.
[0072]
The gate of the P-channel MOS transistor TP12 and the gate of the N-channel MOS transistor TN12 are connected by a wiring G8. Therefore, the wiring G8 is an input of the second inverter gate. The drain of the P-channel MOS transistor TP11 and the drain of the N-channel MOS transistor TN11 are connected by a wiring H3, and the wiring H3 is an output of the first inverter gate. Further, the wiring H3 is connected to the wiring G8 of the input of the second inverter gate, and can be said to be the negative logic point. The wiring H3 at such a negative logic point is connected to the pass transistors TN2 and TN4 by extending the transistor regions of the pass transistors TN2 and TN4.
[0073]
Next, the negative logic memory cell in the upper part of FIG. 3 will be described with reference to FIG.
[0074]
First, the pass transistors TN1 and TN3 and the N-channel MOS transistor TN12 are formed in the transistor region A1. The intersection of the wiring G1 intersecting with the transistor region A1 is the gate of the pass transistor TN1. The intersection of the wiring G2 intersecting with the transistor area A1 is the gate of the pass transistor TN3. The intersection of the wiring G4 intersecting with the transistor area A1 is the gate of the N-channel MOS transistor TN12.
[0075]
Next, the pass transistors TN2 and TN4 and the N-channel MOS transistor TN11 are formed in the transistor region A2. The intersection of the wiring G1 that intersects the transistor region A2 is the gate of the pass transistor TN2. A crossing portion of the wiring G2 crossing the transistor region A2 serves as a gate of the pass transistor TN4. The intersection of the wiring G3 intersecting with the transistor region A2 is the gate of the N-channel MOS transistor TN11.
[0076]
Next, the P-channel MOS transistor TP11 is formed in the transistor region A3. The intersection of the wiring G3 intersecting with the transistor area A3 is the gate of the P-channel MOS transistor TP11. The P-channel MOS transistor TP12 is formed in the transistor region A4. The intersection of the wiring G4 intersecting with the transistor region A4 is the gate of the P-channel MOS transistor TP12.
[0077]
Here, the gate of the P-channel MOS transistor TP11 and the gate of the N-channel MOS transistor TN11 are connected by a wiring G3, and thus the wiring G3 is an input of the first inverter gate. The drain of the P-channel MOS transistor TP12 and the drain of the N-channel MOS transistor TN12 are connected by a wiring H2, and the wiring H2 is an output of the second buffer gate. Further, the wiring H2 is connected to the wiring G3 of the input of the first buffer gate, and thus serves as the positive logic point. The positive logic point is connected to the pass transistors TN1 and TN3 by extending the transistor regions of the pass transistors TN1 and TN3.
[0078]
Next, the gate of the P-channel MOS transistor TP12 and the gate of the N-channel MOS transistor TN12 are connected by a wiring G4, and the wiring G4 is an input of the second inverter gate. The drain of the P-channel MOS transistor TP11 and the drain of the N-channel MOS transistor TN11 are connected by a wiring H1, and the wiring H1 is an output of the first buffer gate. Further, the wiring H1 is also connected to the wiring G4 of the input of the second buffer gate, so that the wiring H1 is also the negative logic point. The negative logic point is connected to the pass transistors TN2 and TN4 by extending the transistor regions of the pass transistors TN2 and TN4.
[0079]
The source of each of the N-channel MOS transistors TN12 and TN11 of the negative logic memory cell and the N-channel MOS transistors TN12 and TN11 of the positive logic memory cell in the transistor regions A1, A2, A5 and A6, respectively. Each source is connected to the ground line GNDa or GNDb. Further, the sources of the P-channel MOS transistors TP11 and TP12 of the negative logic memory cell and the P-channel MOS transistors TP11 and TP12 of the positive logic memory cell are respectively located in the transistor regions A3, A4, A7 and A8. In the case of FIG. 3, each source is connected to the power supply line VDD by a wiring (not shown). In addition, in the case of FIG. 4, as described above, the connection of these sources to the power supply VDD (VDDa or VDDb) is also illustrated.
[0080]
FIG. 5 is a time chart illustrating the operation of the present embodiment.
[0081]
FIG. 5 shows timings of respective signals similar to those of the related art shown in FIG. 9 when a write access is performed to the B port while a read access is performed from the A port.
[0082]
First, as for the A port, the read / write control signal ARW is in the H state, and the selection of the read access is input. Here, when the address signal AAD of the A port changes at time t10 (A1), bit data is read from the selected memory cell corresponding to the address A1, and at time t11, the bit line BA of the A port is read. And the logic state of BAN changes. Thereafter, at time t12, the output data (ADO1) of the selected memory cell is read from the output data ADO of the A port.
[0083]
When the address signal AAD changes at time t15 (A0), at time t17, read data is output from the memory cell selected by the read access to the bit lines BA and BAN of the A port. Is done. Then, at time t19, output data ADO (ADO2) corresponding to the read access is output.
[0084]
During such read access, writing to the B port is also performed at the same time.
[0085]
The address signal BAD of the B port is input (B0), and the read / write control signal BRW of the B port is in the L state in response to the write access. First, at time t13, the write data BDI of the B port is Changes (BDI1). Then, at time t14, the logic states of the bit lines BB and BBN of the B port change, and the input bit data is written to the corresponding memory cell.
[0086]
Here, the time t14 corresponds to the time t34 in FIG. Conventionally, at time t34, the logic state of the bit lines BA and BAN becomes unstable between time t34 and t35 due to a sudden change in the write current of the B port, and the erroneous output data ADO is output. It was gone. However, as shown in FIG. 5, in this embodiment, the bit lines BA and BAN are twisted, so that even if a read current suddenly flows at the B port, this is not affected.
[0087]
Subsequently, at time t16, the input data BDI of the B port during the write access changes (BDI0), and thereafter, at time t18, the logical states of the bit lines BB and BBN of the B port change. Write current is generated.
[0088]
Here, the time t18 in FIG. 5 corresponds to the time t38 in FIG. Conventionally, the time until the read data of the bit lines BA and BAN of the A port is stabilized is prolonged, as in the vicinity of the time t39 in FIG. 9, and therefore, the setup time until the read data ADO is output is prolonged. (Time extension from time t37 to t39 to t40). On the other hand, in FIG. 5 of the present embodiment, after the address of the read access is input to the A port at time t15, the address is output to the bit lines BA and BAN of the A port at relatively short time t17. The read data to be read is determined, and the corresponding output data ADO is output at time t19. In the present embodiment, the write access of the B port does not affect the read access of the A port. Therefore, even if the write access of the B port and the read access of the A port are close to each other, the A of the present embodiment is not changed. The read access time of the port is not extended.
[0089]
As described above, according to the present embodiment, by twisting the bit lines BA and BAN of the A port, it is possible to reduce the stray capacitance between the ports and the mutual interference due to electromagnetic induction. It is possible to further reduce noise mixed into the port bit line due to the operation of the port during write access. In the present embodiment, the use of the positive logic memory cell and the negative logic memory cell makes it possible to invert output data at the time of read access or at the time of write access as described in JP-A-5-234376. It is not necessary to invert the input data, and there is no extension of the access time accompanying such inversion of the logic state.
[0090]
In the present embodiment, as described above with reference to FIG. 4, the pass transistors for the positive logic point and the negative logic point in the positive logic memory cell and the negative logic memory cell, respectively. Are formed by extending the transistor region of each pass transistor to form a wiring path. For this reason, even if both the positive logic memory cell and the negative logic memory cell are provided, there are problems such as the integrated circuit pattern being significantly complicated and the number of required wiring layers being increased. There is no.
[0091]
【The invention's effect】
As described above, according to the present invention, it is possible to reduce the stray capacitance between ports and the mutual interference due to electromagnetic induction while suppressing the extension of the access time, thereby enabling the write access to the bit line of the port during the read access. An excellent effect that noise mixing accompanying the operation of the port can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a positive logic memory cell used in a dual port memory to which the present invention is applied.
FIG. 2 is a circuit diagram of a negative logic memory cell used in the embodiment.
FIG. 3 is an integrated circuit layout diagram of a first example of the positive logic memory cells and the negative logic memory cells of the embodiment.
FIG. 4 is an integrated circuit layout diagram of a second example of the positive logic memory cells and the negative logic memory cells of the embodiment.
FIG. 5 is a time chart showing the operation of the embodiment.
FIG. 6 is a block diagram showing a configuration of a conventional dual port memory.
FIG. 7 is a circuit diagram of a memory cell matrix in which bit lines are twisted to reduce mutual interference between ports;
FIG. 8 is a schematic diagram showing an effect of reducing the interference between ports of the bit line twist.
FIG. 9 is a time chart showing mutual interference between ports in a conventional dual port memory;
[Explanation of symbols]
1: Memory cell matrix
10, 10-1 to 10-6 ... memory cell array
12A, 12B ... column decoder
13A, 13B ... data input / output circuit
14A, 14B ... control circuit
16 Row decoder
AAD, BAD ... address signal
ARW, BRW ... read / write control signal
WA, WB ... word line
BA, BAN, BB, BBN ... bit line
TN1 to TN4... N-channel MOS transistors (used as pass transistors)
TP11, TP12... P-channel MOS transistors (used for memory cell flip-flops)
TN11, TN12 ... N-channel MOS transistors (used for memory cell flip-flops)
VDD: Power supply
GND, GNDa, GNDb ... ground

Claims (3)

A memory cell matrix in which memory cells are arranged in a matrix is provided with N sets of word lines in a row direction and N sets of bit lines in a column direction, and independently addresses from each of the N ports, In a multiport memory that can be accessed,
In at least a port where write access is possible and at least another port where read access is possible, the bit line of any port is a bit line pair consisting of a positive logical bit line and a negative logical bit line, and , One port is a twisted bit line pair port, the other port is a fixed bit line pair port,
The bit line pair of the twisted bit line pair port is periodically twisted in the memory cell matrix, whereby a bit data inversion section in which the arrangement position of the bit line pair is switched and a bit data non-inversion in which the bit line pair is not switched are switched. Sections exist alternately and periodically,
On the other hand, the bit line pair of the fixed bit line pair port is not twisted in a section in which the bit data inversion section and the bit data non-inversion section alternately exist,
Wherein a wiring drawn against twisted bit line pair ports of bit line pairs each bit line, and the wiring that is drawn against the front Symbol each bit line of the bit line pair of fixed bit line pair ports, these wirings A positive logic memory cell used as one of the memory cells, wherein these wirings are formed in the same direction as each other so that the signal logic is the same ;
Wherein a wiring drawn against twisted bit line pair ports of bit line pairs each bit line, and the wiring that is drawn against the front Symbol each bit line of the bit line pair of fixed bit line pair ports, these wirings A negative logic memory cell used as one of the memory cells, wherein these wirings are formed in directions opposite to each other so that the logic of the signal is the same ;
Wherein the bit data inverting section is the positive logic memory cell array, whereas, the multi-port memory, wherein the in the bit data inversion interval negative logic memory cells are arranged. In claim 1,
The positive logic memory cell and the negative logic memory cell are connected to each other at the input and output of two inverter gates, one connection point is a positive logic point, and the other connection point is a negative logic point. Equipped with flip-flops
The positive logic memory cell is, with respect to the positive logic point, between the twisted bit line pair port and the positive logic bit line of the port, and between the fixed bit line pair port and the positive logic bit line. Each has a pass transistor having a gate connected to a corresponding word line of a corresponding port, and further includes, for the negative logic point, between the twisted bit line and the negative logic bit line of the port, and A pass transistor having a gate connected to a corresponding word line of the corresponding port between the bit line pair and the negative logic bit line of the port,
The negative logic memory cell is, with respect to the positive logic point, between the twisted bit line pair port and the positive logic bit line of the port, and between the fixed bit line pair port and the positive logic bit line. Each has a pass transistor having a gate connected to a corresponding word line of a corresponding port, and further includes, for the negative logic point, between the twisted bit line and the negative logic bit line of the port, and A multi-port memory comprising pass transistors each having a gate connected to a corresponding word line of a corresponding port, between the bit line pair and the negative logic bit line of the port. In claim 2,
  In each of the positive logic memory cell and the negative logic memory cell, the connection of each pass transistor to the positive logic point and the negative logic point is performed by extending a transistor region of each pass transistor. Features multiport memory.

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