JP3535805B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an M having excellent driving force.
The present invention relates to a semiconductor device having an OS transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, in the development of highly integrated semiconductor devices, so-called VLSI, further miniaturization of MOS transistors, which are constituent elements of VLSI, has been required. In MOS transistors, the dimensions of devices of each generation are being reduced in accordance with the scaling rule.
In order to deal with this, by increasing the substrate concentration, the characteristics of the device are improved while suppressing the so-called short channel effect.

However, it is difficult to reduce the depth of the impurity layer serving as the source or the drain among various dimensions of the device. Therefore, a structure of a MOS transistor for suppressing the short channel effect has been proposed.

Hereinafter, as a conventional example, for example, GG Shah
idi et al, "High-Performance Devices for a 0.15μ
m CMOS Technology ", IEEE Electron Device Letters, v
ol.14, no.10, Octber 1993, the structure and manufacturing method of the MOS transistor (hereinafter, simply referred to as a conventional MOS transistor) will be described with reference to FIG.

As shown in FIG. 20, a conventional MOS transistor is used.
The resistor is formed inside the semiconductor substrate 1^-Mold
And the p-type region formed on the surface of the semiconductor substrate 1
Channel region 3 and a gate insulating film on the channel region 3
Of the semiconductor substrate 1 and the gate electrode 5 formed via
In the regions on both sides of the gate electrode 5 on the surface portion,
N formed⁺-Type source / drain composed of impurity layers
The source / drain in the region 9 and the surface portion of the semiconductor substrate 1
N formed inside the in-region 9⁺From the impurity layer of the mold
The extension region 6 and the surface of the semiconductor substrate 1
The extension area 6 is covered and the upper end is gate-insulated.
P formed so as to extend to the edge film 4 ⁺Mold pocket
And a region 7.

According to the conventional MOS transistor, n ⁺
P formed to cover the extension region 6 of the mold
^{It has a +} type pocket area 7, and the pocket area 7
However, since the depletion layer is prevented from extending from the n ⁺ type extension region 6 and the source / drain region 9, the short channel effect can be suppressed.

Further, even when the depth of the extension region 6 or the source / drain region 9 cannot be made shallow in accordance with the scaling rule, the short channel effect can be suppressed by increasing the impurity concentration of the pocket region 7.

[0008]

However, the conventional MOS transistor has the following problems.

(First Problem) When the impurity concentration of the p ⁺ type pocket region is increased in order to further suppress the short channel effect, the impurity of the extension region is covered because the pocket region covers the n ⁺ type extension region. The concentration is offset and decreases. For this reason, the resistance of the extension region becomes large, which causes a problem that the driving force of the MOS transistor is reduced. Further, if the impurity concentration of the p ⁺ type pocket region is increased, the impurity concentration in the vicinity of the extension region in the channel region is increased, so that the impurity scattering of carriers is increased and the mobility of carriers is decreased. The driving force is further reduced. Further, when the impurity concentration in the vicinity of the extension region in the channel region becomes high, a so-called reverse short channel effect occurs, and there is a problem that the threshold voltage of the transistor largely depends on the channel length of the transistor.

(Second Problem) By the way, in the sidewall, after the n-type impurity ions are ion-implanted to form the extension regions and the p-type impurity ions are ion-implanted to form the pocket regions, the semiconductor substrate is formed. Is formed by depositing an insulating film over the entire surface at a low temperature of 600 ° C. to 850 ° C. for several tens of minutes to several hours, and then performing anisotropic etching on the insulating film. Accelerated diffusion of impurities (Transient Enhanced) due to point defects (vacancy and interstitial silicon) generated during ion implantation.
Diffusion) is caused significantly. As a result, the impurity concentration in the pocket region becomes high, the resistance in the extension region becomes high, and the mobility of carriers decreases, which reduces the driving force of the MOS transistor. In addition, interstitial silicon generated at the time of ion implantation for forming the extension region and the pocket region is diffused and distributed toward the gate insulating film during the low temperature heat treatment (for example, when the insulating film to be the sidewall is deposited). Since a gradient is generated in the channel region, impurities at the end of the gate electrode in the channel region move toward the substrate surface.
The impurity concentration of the surface region at the end of the gate electrode in the channel region becomes high. Therefore, a so-called reverse short channel effect occurs, which causes a problem that the threshold voltage changes. This phenomenon is prominent when boron ions are implanted to form pocket regions.

(Third problem) In the conventional method of manufacturing a MOS transistor, in order to make the distribution of arsenic ions in the n ⁺ type extension region steep, indium ions are ion-implanted in the p ⁺ type pocket region and the pocket is formed. The region is made amorphous.

However, we have found that by heat treatment performed after the amorphization process, it is inside the pocket region (that is, outside the extension region) near the pn junction formed between the extension region and the pocket region. ), A new point defect occurs. When a point defect occurs inside the pocket region, a junction leak current occurs. When a VLSI having such a MOS transistor is incorporated in a mobile device of a mobile communication device, there is a problem in that standby power consumption increases due to a junction leak current.

In view of the above, it is an object of the present invention to improve the driving force of a MOS transistor.

[0014]

In order to achieve the above object, a first semiconductor device according to the present invention comprises a gate electrode formed on a semiconductor substrate via a gate insulating film, and a surface portion of the semiconductor substrate. From a channel region formed of a semiconductor layer of the first conductivity type formed immediately below the gate electrode and an impurity layer of the second conductivity type formed in regions on both sides of the gate electrode on the surface portion of the semiconductor substrate. A source region and a drain region, and a second region formed between the channel region and the upper regions of the source region and the drain region so as to be in contact with the source region or the drain region.
A first conductive layer formed between the conductive type extension region and the channel region and the lower regions of the source region and the drain region so as to be in contact with the source region or the drain region and to be spaced from the gate insulating film. And a mold pocket area.

According to the first semiconductor device, between the channel region and each of the lower regions of the source region and the drain region,
Since the first conductivity type pocket region is formed so as to be in contact with the source region or the drain region and be spaced from the gate insulating film, the impurity concentration of the pocket region is increased to suppress the short channel effect. However, the impurity concentration of the extension region does not decrease and the impurity concentration of the channel region in the vicinity of the extension region does not increase.

Therefore, since the impurity concentration of the extension region does not decrease, the resistance of the extension region does not become high, which makes it possible to suppress the decrease of the driving force of the MOS transistor. In addition, since the impurity concentration in the vicinity of the extension region in the channel region does not increase, it is possible to prevent a situation in which the mobility of carriers is lowered due to the impurity scattering of carriers.
It is possible to prevent the driving force of the S transistor from lowering.

Therefore, according to the first semiconductor device, it is possible to prevent the driving force of the MOS transistor from being lowered while suppressing the short channel effect.

In the first semiconductor device, the first conductivity type low-density semiconductor layer is formed on both sides of the channel region so as to be in contact with the extension region and has a lower concentration of activated impurities than the central portion of the channel region. It is preferable to further include a concentration channel region.

In this way, the low concentration channel region, which is in contact with the extension region and has a lower concentration of activated impurities than the central portion of the channel region, is provided in the regions on both sides of the channel region. The concentration of the activated impurities in the upper region of the region is low concentration-high concentration-low concentration from the source side to the drain side or from the drain side to the source side. That is,
The concentration of activated impurities is low in a region of the channel region which is in contact with the extension region.

Therefore, the resistance of the extension region is further lowered, so that the driving force of the MOS transistor can be further prevented from being lowered.

A second semiconductor device according to the present invention is formed in a gate electrode formed on a semiconductor substrate via a gate insulating film, and in a region directly below the gate electrode on a surface portion of the semiconductor substrate. A channel region made of a doped first conductivity type semiconductor layer, and a source region and a drain region made of a second conductivity type impurity layer respectively formed in regions on both sides of the gate electrode on the surface portion of the semiconductor substrate, The second conductivity type extension region is formed between the channel region and the upper regions of the source region and the drain region so as to be in contact with the source region or the drain region, and the extension regions are formed on both sides of the channel region. And a first conductive layer having a lower concentration of activated impurities than the central portion of the channel region. And a low-concentration channel region of.

According to the second semiconductor device, the low-concentration channel regions which are in contact with the extension regions and have a lower concentration of activating impurities than the central portion of the channel regions are provided in the regions on both sides of the channel region. Therefore, the concentration of activated impurities in the upper region of the channel region is low concentration-high concentration-low concentration from the source side to the drain side or from the drain side to the source side.
That is, the concentration of the activation impurity is low in the region of the channel region which is in contact with the extension region. For this reason, the resistance of the extension region is lowered, so that the driving force of the MOS transistor can be prevented from being lowered.

In the first method of manufacturing a semiconductor device according to the present invention, first conductivity type impurity ions are ion-implanted into a surface portion of a semiconductor substrate to form a first conductivity type semiconductor layer to be a channel region. A step of forming a gate electrode on the semiconductor substrate via a gate insulating film, and impurity ions of the second conductivity type are ion-implanted into the semiconductor layer using the gate electrode as a mask to form a first layer in the upper region of the semiconductor layer. A step of forming a first-conductivity-type impurity layer of two conductivity type; a step of implanting indium ions into the semiconductor layer using the gate electrode as a mask to form a first-conductivity-type impurity layer in a lower region of the semiconductor layer; A step of subjecting the semiconductor substrate to a heat treatment at a temperature of about 950 ° C. to about 1050 ° C. for a short time, a step of forming a sidewall on a side surface of the gate electrode, a second impurity type first impurity layer and a first impurity layer Guide Both sides of the gate electrode in the first conductivity type impurity layer and the second conductivity type first impurity layer by implanting second conductivity type impurity ions into the second conductivity type impurity layer using the gate electrode and the sidewall as a mask. A source region and a drain region made of a second impurity layer of the second conductivity type are formed in one region, and a second region is formed inside each upper region of the source region or the drain region in the first impurity layer of the second conductivity type. Forming a conductive type extension region, and forming a first conductive type pocket region inside each lower region of the source region or drain region in the first conductive type impurity layer.

According to the first method of manufacturing a semiconductor device, indium ions having a larger atomic mass than boron ions are ion-implanted to form a first conductivity type impurity layer to be a pocket region. The peak position of the impurity concentration distribution can be made shallow, and the range in which the pocket region is expanded can be suppressed. Further, since the diffusion coefficient of indium ions is smaller than that of boron ions, the expansion of the pocket region due to thermal diffusion can be suppressed.

By the way, indium ions, like boron ions, may cause accelerated diffusion due to point defects generated during ion implantation. However, in the first method for manufacturing a semiconductor device, after indium ions are ion-implanted to form a first conductivity type impurity layer which becomes a pocket region, a heat treatment is performed at a temperature of about 950 ° C. to about 1050 ° C. for a short time. Therefore, accelerated diffusion due to point defects can be suppressed.

Therefore, according to the method of manufacturing the first semiconductor device, it is possible to reliably manufacture the first semiconductor device having the pocket region spaced apart from the gate insulating film.

In the method of manufacturing the first semiconductor device, the dose amount of indium ions in the step of forming the impurity layer of the first conductivity type is preferably 5 × 10 ¹³ cm ^-2 or less.

By doing so, in the first conductivity type impurity layer which becomes the pocket region, the silicon crystal does not become amorphous, and EOR point defects such as transition loops do not occur.
It is possible to prevent the occurrence of junction leakage current.

In a second method of manufacturing a semiconductor device according to the present invention, first conductivity type impurity ions are ion-implanted into a surface portion of a semiconductor substrate to form a first conductivity type semiconductor layer to be a channel region. Steps, a step of forming a gate electrode on the semiconductor substrate via a gate insulating film, and ions of atoms belonging to Group IV are ion-implanted into the semiconductor layer using the gate electrode as a mask to form a first layer in the upper region of the semiconductor layer. Forming a first conductivity type amorphous layer; and implanting second conductivity type impurity ions into the amorphous layer by using the gate electrode as a mask to implant the second conductivity type first A step of forming an impurity layer,
A step of implanting indium ions into the semiconductor layer using the gate electrode as a mask to form an impurity layer of the first conductivity type in a lower region of the semiconductor layer;
A step of performing a heat treatment at a temperature of 0 ° C. to about 1050 ° C. for a short time, a step of forming a sidewall on a side surface of the gate electrode, a second conductivity type first impurity layer and a first conductivity type impurity layer. , Impurity ions of the second conductivity type are ion-implanted using the gate electrode and the sidewalls as masks, and second ion implantation is performed in regions on both sides of the gate electrode in the first conductivity type first impurity layer and the first conductivity type impurity layer. Forming a source region and a drain region made of a second conductivity type second impurity layer;
A second conductivity type extension region is formed inside each upper region of the source region or the drain region in the conductivity type first impurity layer, and each lower region of the source region or the drain region in the first conductivity type impurity layer. And forming a pocket region of the first conductivity type inside.

According to the second method for manufacturing a semiconductor device, indium ions, which have a larger atomic mass and a smaller diffusion coefficient than boron ions, are ion-implanted in the same way as the first method for manufacturing a semiconductor device, and the pocket region is formed. Since the first conductivity type impurity layer is formed, the peak position of the impurity concentration distribution in the pocket region can be made shallow, the range in which the pocket region expands can be suppressed, and the expansion of the pocket region due to thermal diffusion can be suppressed. You can Therefore, it is possible to reliably manufacture the first semiconductor device having the pocket region spaced apart from the gate insulating film.

In particular, in the second semiconductor device manufacturing method, an amorphous layer is formed in the upper region of the first conductivity type semiconductor layer, and then the second conductivity type impurity ions are ion-implanted. Then, since the second conductivity type first impurity layer to be the extension region is formed, the impurity concentration distribution becomes steep in the second conductivity type first impurity layer, so that the resistance of the extension region is lowered. This can be realized, and thereby, the driving force of the MOS transistor can be improved.

In the second method of manufacturing a semiconductor device, the dose amount of indium ions in the step of forming the impurity layer of the first conductivity type is preferably 5 × 10 ¹³ cm ^-2 or less.

By doing so, in the first-conductivity-type impurity layer serving as the pocket region, the silicon crystal does not become amorphous, and EOR point defects such as transition loops do not occur.
It is possible to prevent the occurrence of junction leakage current.

A third method for manufacturing a semiconductor device according to the present invention comprises a step of implanting indium ions into a surface portion of a semiconductor substrate to form a semiconductor layer of a first conductivity type which becomes a channel region, and a semiconductor substrate. A step of forming a gate electrode on the semiconductor layer via a gate insulating film, and impurity ions of the second conductivity type are ion-implanted into the semiconductor layer using the gate electrode as a mask, and a second conductivity type first ion is implanted in the upper region of the semiconductor layer. 1 step of forming the impurity layer and depositing an insulating film over the entire surface of the semiconductor substrate at a temperature of about 600 ° C. to about 850 ° C. to form the first conductivity type first layer in the upper region of the semiconductor layer. Inside the impurity layer, a step of forming a first-conductivity-type low-concentration channel region having an impurity concentration lower than that of the semiconductor layer, and anisotropic etching of the insulating film to form a sidewall on the side surface of the gate electrode. Form Degree and, the first impurity layer and the semiconductor layer of the second conductivity type, impurity ions of the second conductivity type by ion implantation using the gate electrode and the sidewalls as a mask,
A source region and a drain region made of a second impurity layer of the second conductivity type are formed in regions on both sides of the gate electrode in the first impurity layer of the second conductivity type and the semiconductor layer, and
And a step of forming an extension region of the second conductivity type inside each upper region of the source region or the drain region in the first impurity layer of the second conductivity type.

According to the third method of manufacturing a semiconductor device, a step of ion-implanting indium ions to form a semiconductor layer of the first conductivity type to be a channel region, and ion implantation of impurity ions of the second conductivity type. After forming the second conductivity type first impurity layer to be the extension region, a step of performing a low temperature and long time heat treatment when depositing the insulating film at a temperature of about 600 ° C. to about 850 ° C. is provided. The interstitial silicon atoms generated when the first impurity layer of the second conductivity type that becomes the extension region is formed by ion implantation are
It moves toward the gate insulating film by heat treatment at a low temperature for a long time, and at the time of moving, it combines with indium ions existing in lower regions on both sides of the gate insulating film in the semiconductor layer of the first conductivity type to form indium. Inactivate ions. Therefore, in the lower regions on both sides of the gate insulating film in the first-conductivity-type semiconductor layer that will be the channel region, that is, in the region inside the second-conductivity-type first impurity layer in the first-conductivity-type semiconductor layer, A low-concentration channel region having a lower concentration of activated impurities than that of the first-conductivity-type semiconductor layer is formed.

Therefore, according to the third method of manufacturing a semiconductor device, the second semiconductor having the low-concentration channel region in which the concentration of the activation impurity is lower in the regions on both sides of the channel region than in the central portion of the channel region. The device can be reliably manufactured.

A fourth method for manufacturing a semiconductor device according to the present invention comprises a step of implanting indium ions into a surface portion of a semiconductor substrate to form a semiconductor layer of a first conductivity type which becomes a channel region, and a semiconductor substrate. A step of forming a gate electrode on the semiconductor layer via a gate insulating film, and by ion-implanting ions of group IV atoms into the semiconductor layer using the gate electrode as a mask, a non-conductive layer of the first conductivity type is formed in the upper region of the semiconductor layer. A step of forming a crystalline layer and a second step using the gate electrode as a mask on the amorphous layer
Conductive type impurity ions are ion-implanted to make the second amorphous state.
A step of forming a conductive type first impurity layer, and depositing an insulating film over the entire surface of the semiconductor substrate at a temperature of about 600 ° C. to about 850 ° C. to form a second conductive type in the upper region of the semiconductor layer. Forming a low-concentration first conductivity type channel region having a lower impurity concentration than the semiconductor layer inside the first impurity layer, and anisotropically etching the insulating film to form a side surface of the gate electrode. A step of forming a sidewall on the second
Gate electrodes in the second conductivity type first impurity layer and the semiconductor layer are formed by ion-implanting second conductivity type impurity ions into the conductivity type first impurity layer and the semiconductor layer using the gate electrode and the sidewall as a mask. A source region and a drain region formed of a second impurity layer of the second conductivity type are formed in regions on both sides of the inner side of each upper region of the source region or the drain region in the first impurity layer of the second conductivity type. And a step of forming an extension region of the second conductivity type.

According to the fourth method for manufacturing a semiconductor device, indium ions are ion-implanted to form a semiconductor layer of the first conductivity type which becomes a channel region, as in the method for manufacturing a third semiconductor device. After the second conductivity type impurity ions are ion-implanted to form the second conductivity type first impurity layer serving as the extension region, the insulating film is formed at about 600 ° C. to about 8 ° C.
Since the interstitial silicon atom has a step of performing heat treatment at low temperature for a long time when depositing at a temperature of 50 ° C.,
When moving to the gate insulating film, the indium ions are combined with the indium ions existing in the lower regions on both sides of the gate insulating film in the semiconductor layer of the first conductivity type to inactivate the indium ions. A low-concentration channel region having a lower concentration of activating impurities than that of the first-conductivity-type semiconductor layer can be formed in a region inside the second-conductivity-type first impurity layer in the conductivity-type semiconductor layer.

In particular, in the fourth method of manufacturing a semiconductor device, before the step of implanting the second conductivity type impurity ions to form the second conductivity type first impurity layer to be the extension region. , A group IV atom is ion-implanted to form an amorphous layer in the upper region of the first conductivity type semiconductor layer, so that it is generated in the upper region of the first conductivity type semiconductor layer. Since the number of interstitial silicon atoms that are generated increases, the number of indium ions that are inactivated by the bond with the interstitial silicon atoms also increases. Therefore, it is possible to efficiently form the low-concentration channel region in which the concentration of the activation impurity is lower than that of the first-conductivity-type semiconductor layer.

A fifth method for manufacturing a semiconductor device according to the present invention comprises a step of implanting indium ions into a surface portion of a semiconductor substrate to form a semiconductor layer of a first conductivity type which becomes a channel region, and a semiconductor substrate. A step of forming a gate electrode on the semiconductor layer via a gate insulating film, and impurity ions of the second conductivity type are ion-implanted into the semiconductor layer using the gate electrode as a mask, and a second conductivity type first ion is implanted in the upper region of the semiconductor layer. 1 step of forming an impurity layer and performing a first heat treatment on the semiconductor substrate at a temperature of about 600 ° C. to about 850 ° C. for a long time to form a first conductivity type first layer in the upper region of the semiconductor layer. Inside the impurity layer, a step of forming a first conductivity type low-concentration channel region having an impurity concentration lower than that of the semiconductor layer, and indium ions are ion-implanted into the semiconductor layer using the gate electrode as a mask, Forming an impurity layer of the first conductivity type in the region of about 950 ° C. ~ about 105 to the semiconductor substrate
A step of performing a second heat treatment at a temperature of 0 ° C. for a short time, a step of forming a sidewall on a side surface of the gate electrode, a second step
A conductive type first impurity layer and a first conductive type impurity layer,
By using the gate electrode and the sidewall as a mask, impurity ions of the second conductivity type are ion-implanted, and the first conductivity type of the first conductivity type is implanted.
Source and drain regions formed of a second impurity layer of the second conductivity type are formed in regions on both sides of the gate electrode in the impurity layer of the first conductivity type and the impurity layer of the first conductivity type, and the first impurity of the second conductivity type is formed. A second conductivity type extension region is formed inside each upper region of the source region or drain region in the layer, and a first conductivity type is formed inside each lower region of the source region or drain region in the first conductivity type impurity layer. And forming a pocket region of the.

According to the fifth method of manufacturing a semiconductor device, a step of ion-implanting indium ions to form a semiconductor layer of the first conductivity type to be a channel region, and ion implantation of impurity ions of the second conductivity type. After forming the first impurity layer of the second conductivity type to be the extension region, about 600
C. to about 850.degree. C., a step of performing a low-temperature long-time heat treatment performed at a temperature of about 850.degree. At that time, since the indium ions are inactivated by combining with the indium ions existing in the lower regions on both sides of the gate insulating film in the semiconductor layer of the first conductivity type,
A low-concentration channel region having a lower concentration of activating impurities than that of the first-conductivity-type semiconductor layer may be formed in a region inside the second-conductivity-type first impurity layer in the first-conductivity-type semiconductor layer. it can. Therefore, it is possible to reliably manufacture the semiconductor device having the low-concentration channel regions in which the concentration of the activation impurities is lower in the regions on both sides of the channel region than in the central portion of the channel region.

Further, the method comprises a step of performing a heat treatment at a high temperature for a short time at a temperature of about 950 ° C. to about 1050 ° C. after ion-implanting indium ions to form a first conductivity type impurity layer to be a pocket region. Therefore, similar to the first semiconductor device manufacturing method, the peak position of the impurity concentration distribution in the pocket region can be made shallow, the range in which the pocket region expands can be suppressed, and the expansion of the pocket region due to thermal diffusion can be suppressed. be able to. Therefore, a semiconductor device having a pocket region spaced apart from the gate insulating film can be reliably manufactured.

In a sixth method for manufacturing a semiconductor device according to the present invention, impurity ions of the first conductivity type are ion-implanted into a surface portion of a semiconductor substrate to form a semiconductor layer of the first conductivity type which becomes a channel region. Steps, a step of forming a gate electrode on the semiconductor substrate via a gate insulating film, and ions of atoms belonging to Group IV are ion-implanted into the semiconductor layer using the gate electrode as a mask to form a first layer in the upper region of the semiconductor layer. Forming a first conductivity type amorphous layer; and implanting second conductivity type impurity ions into the amorphous layer by using the gate electrode as a mask to implant the second conductivity type first A step of forming an impurity layer,
An insulating film is deposited on the entire surface of the semiconductor substrate at a temperature of about 600 ° C. to about 850 ° C., and is deposited inside the second conductivity type first impurity layer in the upper region of the semiconductor layer more than the semiconductor layer. A step of forming a low-concentration first-conductivity-type channel region having a low impurity concentration; a step of anisotropically etching the insulating film to form a sidewall on a side surface of the gate electrode; The second conductive type impurity ions are ion-implanted into the first impurity layer and the semiconductor layer by using the gate electrode and the sidewall as a mask, and the gate electrode in the lower region of the second conductive type first impurity layer and the semiconductor layer. A source region and a drain region made of a second impurity layer of the second conductivity type are formed in regions on both sides of the first impurity layer of the second conductivity type, and the upper region of the source region or the drain region in the first impurity layer of the second conductivity type is formed. Forming a second conductivity type extension region on each side, and after removing the sidewall, indium ions are ion-implanted into the semiconductor layer using the gate electrode as a mask to form a source region or a drain region in the lower region of the semiconductor layer. And forming a pocket region of the first conductivity type inside each of the lower regions.

According to the sixth method for manufacturing a semiconductor device, a step of ion-implanting indium ions to form a semiconductor layer of the first conductivity type which becomes a channel region, and ion-implanting ions of atoms belonging to Group IV are carried out. A step of forming an amorphous layer in an upper region of the first conductive type semiconductor layer, and ion-implanting second conductive type impurity ions to form a second conductive type first impurity layer to be an extension region. After doing about 600
C. to about 850.degree. C., a step of performing a low-temperature long-time heat treatment performed at a temperature of about 850.degree. In the region inside the first impurity layer, a low-concentration channel region having a lower concentration of activating impurities than that of the first conductivity type semiconductor layer can be efficiently formed.

Further, the method comprises a step of performing a high-temperature short-time heat treatment performed at a temperature of about 950 ° C. to about 1050 ° C. after implanting indium ions to form a first-conductivity-type impurity layer to be a pocket region. Therefore, similar to the first semiconductor device manufacturing method, the peak position of the impurity concentration distribution in the pocket region can be made shallow, the range in which the pocket region expands can be suppressed, and the expansion of the pocket region due to thermal diffusion can be suppressed. be able to. Therefore, a semiconductor device having a pocket region spaced apart from the gate insulating film can be reliably manufactured.

Further, after forming an amorphous layer in the upper region of the first conductive type semiconductor layer, impurity ions of the second conductive type are ion-implanted to form an extension region of the second conductive type. Since the method includes the step of forming the first impurity layer, the distribution of the impurity concentration in the first impurity layer of the second conductivity type can be made sharp like the method of manufacturing the second semiconductor device, so that the extension region of the extension region can be formed. Low resistance can be realized.

A seventh method of manufacturing a semiconductor device according to the present invention comprises a step of implanting indium ions into a surface portion of a semiconductor substrate to form a semiconductor layer of a first conductivity type which becomes a channel region, and a semiconductor substrate. A step of forming a gate electrode via a gate insulating film on the upper surface of the semiconductor layer, and ions of atoms belonging to group IV are ion-implanted into the semiconductor layer using the gate electrode as a mask, and a group IV atom ion-implanted layer is formed in an upper region of the semiconductor layer And the step of forming the semiconductor substrate, and about 600 ° C. to about 850 ° C. with respect to the semiconductor substrate.
The first conductivity type low-concentration impurity layer having a lower concentration of activated impurities than the semiconductor layer in the group IV atom ion-implanted layer and the upper region of the semiconductor layer is subjected to the first heat treatment at a temperature of ℃ for a long time. Forming a first conductive type impurity layer in the lower region of the semiconductor layer by ion-implanting indium ions into the semiconductor layer using the gate electrode as a mask. The second conductivity type impurity ions are ion-implanted to form the second conductivity type first impurity layer in the upper region of the semiconductor layer, and the first conductivity type is formed inside the second conductivity type first impurity layer. Forming a low-concentration channel region composed of a low-concentration impurity layer, performing a second heat treatment on the semiconductor substrate at a temperature of about 950 ° C. to about 1050 ° C. for a short time, and forming a side surface on the side surface of the gate electrode. Forming a wall Then, the second conductivity type first impurity layer and the first conductivity type impurity layer are ion-implanted with the second conductivity type impurity ions by using the gate electrode and the sidewall as a mask, and the second conductivity type first impurity layer is ion-implanted. Second impurity regions on both sides of the gate electrode in the first impurity layer and the first conductivity type impurity layer;
A source region and a drain region made of a second conductivity type impurity layer are formed, and a second region is formed inside each upper region of the source region or the drain region in the second conductivity type first impurity layer.
Forming a conductive type extension region, and
Forming a pocket region of the first conductivity type inside each lower region of the source region or the drain region in the conductivity type impurity layer.

According to the seventh method of manufacturing a semiconductor device, a step of ion-implanting indium ions to form a semiconductor layer of the first conductivity type which becomes a channel region, and ion-implanting ions of atoms belonging to Group IV are carried out. A step of forming a group IV atom ion implantation layer, and a temperature of about 600 ° C. to about 85 with respect to the semiconductor substrate.
Since the first heat treatment is performed at a temperature of 0 ° C. for a long time, the first conductivity type semiconductor layer is formed in a region inside the second conductivity type first impurity layer in the first conductivity type semiconductor layer. It is possible to efficiently form a low-concentration channel region having a lower concentration of activated impurities than that of the semiconductor layer.

Further, the method comprises a step of performing a heat treatment at a high temperature for a short time at a temperature of about 950 ° C. to about 1050 ° C. after indium ions are ion-implanted to form an impurity layer of the first conductivity type which becomes a pocket region. Therefore, the peak position of the impurity concentration distribution in the pocket region can be made shallow, the range in which the pocket region expands can be suppressed, and the expansion of the pocket region due to thermal diffusion can be suppressed. Therefore, a semiconductor device having a pocket region spaced apart from the gate insulating film can be reliably manufactured.

Further, after indium ions are ion-implanted to form a first-conductivity-type impurity layer which will be a pocket region, second-conductivity-type impurity ions are ion-implanted to be a second-conductivity-type impurity layer which will be an extension region. The second impurity in the first impurity layer of the second conductivity type to form the first impurity layer.
The channeling phenomenon of conductivity type impurity ions is suppressed. Therefore, the concentration distribution of impurities in the extension region made of the first impurity layer of the second conductivity type becomes sharp, so that the parasitic resistance value of the extension region can be reduced and the short channel effect can be suppressed.

[0051]

DETAILED DESCRIPTION OF THE INVENTION (First Embodiment) A semiconductor device according to a first embodiment of the present invention will be described below with reference to FIG.

As shown in FIG. 1, a semiconductor substrate 100 made of a p-type silicon substrate is doped with p-type impurities such as boron ions to form a p ^- type well region 1.
01 is formed. Further, on the semiconductor substrate 100, the gate insulating film 103 made of, for example, a silicon oxide film.
A gate electrode 104 made of a polysilicon film is formed through the via, and a side wall 107 made of, for example, a silicon oxide film is formed on the side surface of the gate electrode 104.

In the region immediately below the gate electrode 104 on the surface of the semiconductor substrate 100, a p-type channel region 1 formed by doping with p-type impurities such as boron ions is formed.
No. 02 is formed, and in regions on both sides of the gate electrode 104 on the surface portion of the semiconductor substrate 100, a source or drain of an n ⁺ type impurity active layer doped with n type impurities, for example, arsenic ions is formed. Area 108
Are formed.

An n ⁺ type extension region 105 is formed between the channel region 102 and each upper region of the source or drain region 108 so as to be in contact with the source or drain region 108.

Between the channel region 102 and each lower region of the source or drain region 108, a p ⁺ type pocket region 106 for punch-through suppression is formed so as to be in contact with the source or drain region 108. ing.

As a feature of the first embodiment, the pocket region 106 is formed by doping indium ions and is formed so as to be spaced apart from the gate insulating film 103.

According to the first embodiment, the depletion layer extending from the n ⁺ type extension region 105 is generated from the lower end portion of the extension region 105, but the p ⁺ type pocket is formed below the extension region 105. Since the region 106 is formed, the depletion layer extending from the n ⁺ type extension region 105 is suppressed, so that the short channel effect can be suppressed.

Further, the p ⁺ type pocket region 106 is formed so as to be in contact with each lower region of the region 108 to be a source or drain and to be spaced from the gate insulating film 103, that is, the extension region. Since it is not formed inside 105, even if the impurity concentration of the pocket region 106 is increased to suppress the short channel effect, the impurity concentration of the extension region 105 does not decrease. For this reason, the resistance of the extension region 105 does not increase, so that the driving force of the MOS transistor can be prevented from decreasing.

In addition, the p ⁺ -type pocket region 106 is n
^Since it is formed below the ⁺ type extension region 105, that is, it is not in contact with the upper region of the channel region 102, even if the impurity concentration of the pocket region 106 is increased, the vicinity of the extension region 105 in the channel region 102 is formed. The impurity concentration in the area does not increase. Therefore, it is possible to prevent the carrier mobility from being lowered due to the carrier impurity scattering, so that it is possible to prevent the driving force of the MOS transistor from being lowered and to prevent the reverse short channel effect from occurring. .

(Second Embodiment) A semiconductor device according to a second embodiment of the present invention will be described below with reference to FIG.

As shown in FIG. 2, a p ⁻ type well region 2 formed by doping a semiconductor substrate 200 made of a p type silicon substrate with p type impurities such as boron ions.
01 is formed. Further, on the semiconductor substrate 200, a gate insulating film 203 made of, for example, a silicon oxide film is formed.
A gate electrode 204 made of a polysilicon film is formed through the via, and a side wall 207 made of, for example, a silicon oxide film is formed on the side surface of the gate electrode 204.

Gate on the surface of semiconductor substrate 200
In the region immediately below the electrode 204, an impurity that is a p-type impurity
P-type channel region formed by doping with d-ion
While the area 202 is formed, the semiconductor substrate 200
In the regions on both sides of the gate electrode 204 on the surface portion,
n-type impurities such as arsenic ion-doped n ⁺
Type source / drain region 2 made of an impurity active layer
08 is formed.

An n ⁺ type extension region 205 is formed between the channel region 202 and each upper region of the source or drain region 208 so as to be in contact with the source or drain region 208.

A feature of the second embodiment is that the upper region on both sides of the p-type channel region 202 is in contact with the extension region 205 and has a concentration of activated impurities higher than that of the central region of the channel region 202. low p ^-
Low-concentration channel regions 206 of the mold are formed respectively.

Therefore, according to the second embodiment, the concentration of the activating impurities in the upper region of the channel region 202 is low concentration-high concentration depending on whether it is from the source side to the drain side or from the drain side to the source side. -Low concentration. Thus, since the concentration of the activation impurity in the region of the channel region 202 which is in contact with the n ⁺ type extension region 205 is low, the extension region 2
Since the resistance of 05 becomes low, it is possible to prevent the driving force of the MOS transistor from decreasing.

(Third Embodiment) A semiconductor device according to a third embodiment of the present invention will be described below with reference to FIG.

[0067] As shown in FIG. 3, the semiconductor substrate 300 made of p-type silicon substrate, p-type impurity such as boron ions, which are doped p ^- type well region 3
01 is formed. Further, on the semiconductor substrate 300, a gate insulating film 303 made of, for example, a silicon oxide film is formed.
A gate electrode 304 made of a polysilicon film is formed via the via, and a sidewall 308 made of, for example, a silicon oxide film is formed on the side surface of the gate electrode 304.

Gate on surface of semiconductor substrate 300
In the region immediately below the electrode 304, an impurity that is a p-type impurity
P-type channel region formed by doping with d-ion
The area 302 is formed and the semiconductor substrate 300
In the regions on both sides of the gate electrode 304 on the surface portion,
n-type impurities such as arsenic ion-doped n ⁺
Type source / drain region 3 formed of an impurity active layer
09 are formed.

An n ⁺ type extension region 305 is formed between the channel region 302 and each upper region of the source or drain region 309 so as to be in contact with the source or drain region 309.

As a feature of the third embodiment, the regions on both sides of the p-type channel region 302 are in contact with the extension regions 305 and the channel regions 30 are provided.
The p ⁻ -type low-concentration channel regions 306 each having a lower concentration of activated impurities than the central portion 2 are formed.

A p ⁺ type pocket region 307 for punch-through suppression is formed between the channel region 302 and each lower region of the source or drain region 309 so as to be in contact with the source or drain region 309. ing.

As a feature of the third embodiment, the pocket region 307 is formed by doping indium ions and is formed so as to be spaced apart from the gate insulating film 303.

According to the third embodiment, as in the first embodiment, since the p ⁺ type pocket region 307 is formed below the extension region 305, the p ⁺ type pocket region 307 causes Since the depletion layer extending from the n ⁺ type extension region 305 is suppressed, the short channel effect can be suppressed.

The p ⁺ -type pocket region 307 is formed so as to be in contact with each lower region of the region 309 serving as a source or drain and to be spaced from the gate insulating film 303, that is, the extension region. Since it is not formed inside the 305, even if the impurity concentration of the pocket region 307 is increased to suppress the short channel effect, the impurity concentration of the extension region 305 does not decrease. Therefore, the resistance of the extension region 305 does not increase, so that the driving force of the MOS transistor can be prevented from decreasing.

The p ⁺ -type pocket region 307 is n
^Since it is formed below the ⁺ type extension region 305, that is, it is not in contact with the upper region of the channel region 302, even if the impurity concentration of the pocket region 307 is increased, the vicinity of the extension region 305 in the channel region 302 is formed. The impurity concentration in the area does not increase. Therefore, it is possible to prevent the carrier mobility from being low due to the impurity scattering of the carriers, so that it is possible to prevent the driving force of the MOS transistor from decreasing and the reverse short channel effect from occurring.

Further, according to the third embodiment, as in the second embodiment, the concentration of activated impurities is higher in the upper regions on both sides of the p-type channel region 302 than in the central portion of the channel region 302. Since the low-concentration p ⁻ -type low-concentration channel region 306 is formed, the impurity concentration in the upper region of the channel region 302 is low from the source side to the drain side and from the drain side to the source type. High concentration-low concentration. In this way, the n ⁺ type extension region 3 in the channel region 302 is formed.
05, the resistance of the extension region 305 can be lowered because the concentration of the activated impurities in the region in contact with 05 is low.
It is possible to prevent the driving force of the OS transistor from decreasing.

(Fourth Embodiment) A semiconductor device manufacturing method according to a fourth embodiment of the present invention will be described below with reference to FIG.
A description will be given with reference to (a) to (c) and FIGS. 5 (a) to (c). The fourth embodiment is the first manufacturing method of the semiconductor device according to the first embodiment.

First, as shown in FIG. 4A, a semiconductor substrate 100 made of a p-type silicon substrate is implanted with p-type impurities such as boron ions at an implantation energy of 300 keV to 2000 keV and a dose of 1 × 10 ¹³ cm ^-2 to 1. × 10 ¹⁴ cm ^-2
After the p ⁻ -type well region 101 is formed by implanting ions with a dose of, a p-type impurity such as boron ions is added to the surface of the semiconductor substrate 100 at 20 keV to 60 k.
The p-type impurity layer 102A is formed on the well region 101 by performing ion implantation with eV and a dose amount of 4 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² . By injecting indium ions instead of boron ions as p-type impurities into the surface of the semiconductor substrate 100, p
The type impurity layer 102A may be formed.

Next, as shown in FIG. 4B, the surface of the semiconductor substrate 100 is oxidized to form a first silicon oxide film 103A having a thickness of 2 nm to 5 nm.

Next, after depositing a polysilicon film having a thickness of 200 nm to 300 nm over the entire surface of the first silicon oxide film 103A, the polysilicon film and the first silicon oxide film 103A are patterned. By doing so, as shown in FIG. 4C, the gate insulating film 103 and the gate electrode 104 are formed.

Next, as shown in FIG. 5A, the p-type impurity layer 102A is formed using the gate electrode 104 as a mask and n.
Type impurities such as arsenic ions with an implantation energy of 5 keV to 10 keV and 5 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ cm
By implanting ions at a dose of ^-2, an n ⁺ -type impurity layer 105A is formed in the upper region of the p-type impurity layer 102A.

Next, 50 to 1 of indium ions are added to the p-type impurity layer 102A using the gate electrode 104 as a mask.
Implantation energy of 50 keV and 1 × 10 ¹³ cm ^{−2 to} 5
Ion implantation is performed at a dose of × 10 ¹³ cm ^-2 to form the p ⁺ -type impurity layer 106A in the lower region of the p-type impurity layer 102A. Then, with respect to the semiconductor substrate 100, for example, at 1000 ° C. in an inert gas atmosphere.
The heat treatment for 10 seconds at the temperature of 1, that is, the first heat treatment at high temperature for a short time is performed.

Next, after depositing a second silicon oxide film over the entire surface of the semiconductor substrate 100, anisotropic etching is performed on the second silicon oxide film to form the structure shown in FIG. ), The side wall 107 is formed on the side surface of the gate electrode 104.

Next, the n ⁺ -type impurity layer 105A and p ⁺
After implanting an n-type impurity, for example, arsenic ions into the impurity-type impurity layer 106A, heat treatment is performed to activate the arsenic ions, and thereafter, in order to recover the crystal point defects, 10
A heat treatment for 10 seconds at a temperature of 00 ° C, that is, a second heat treatment at a high temperature for a short time is performed.

In this way, as shown in FIG. 5C, the n ⁺ -type impurity layer 105A and the p ⁺ -type impurity layer 1 are formed.
In the regions on both sides of the gate electrode 104 in 06A, n
⁺ -Type also source consists impurity active layer region 108 of the drain is formed, the source or the inside of the respective upper region of the drain region 108 in the n ⁺ -type impurity layer 105A made of, n ⁺ -type impurity layers 105A Extension The region 105 is formed and the p ⁺ -type impurity layer 1 is formed.
A pocket region 106 made of ap ⁺ -type impurity layer 106A is formed inside each lower region of the source or drain region 108 in 06A.

According to the fourth embodiment, indium ions having a larger atomic mass than boron ions are ion-implanted to form the p ⁺ -type impurity layer 106A which becomes the p ⁺ -type pocket region 106. The peak position of the impurity concentration distribution in the region 106 can be made shallow, and the range in which the pocket region 106 expands can be suppressed. Further, at the time of thermal equilibrium, since the diffusion coefficient of indium ions is about half that of boron ions, it is possible to suppress the spread of impurity ions due to thermal diffusion as compared with the case of implanting boron ions.

By the way, the diffusion coefficient of indium ions at the time of thermal equilibrium is smaller than that of boron ions, but in terms of accelerated diffusion due to point defects generated at the time of ion implantation, indium ions are almost the same as boron ions. large.

[0088] Therefore, in the fourth embodiment, indium ions are implanted p ⁺ -type impurity layer 106
Immediately after forming A, the first heat treatment is performed at high temperature for a short time to suppress the generation of accelerated diffusion due to point defects.
Therefore, the expansion of the pocket region 106 made of the p ⁺ -type impurity layer 106A can be suppressed.

Therefore, according to the fourth embodiment, the pocket region 106 can be formed so as to be in contact with each lower region of the source or drain region 108 and be spaced apart from the gate insulating film 103. The semiconductor device according to the first embodiment can be reliably manufactured.

In the fourth embodiment, the first heat treatment at a high temperature for a short time is performed at a temperature of 1000 ° C. for 10 seconds, but the present invention is not limited to this, and the temperature range is about 950 ° C. to about 1050 ° C. In addition, in the time range of about 0.1 second to about 30 seconds, the effect of suppressing the expansion of the pocket region 106 can be obtained. The temperature of the first high-temperature short-time heat treatment is about 950 ° C.
When the temperature is lower than 1050 ° C., point defects are generated, so that accelerated diffusion of indium ions occurs, and when the temperature of the first high-temperature short-time heat treatment is higher than about 1050 ° C., the speedup caused by point defects is increased. No diffusion occurs, but indium ions themselves diffuse. Therefore, the temperature range of 950 ° C. to about 1050 ° C. is preferable for the first heat treatment at high temperature for a short time.

By the way, p ⁺ which becomes the pocket region 106
In the ion implantation step for forming the p-type impurity layer 106A, if indium ions are implanted with a dose amount larger than 5 × 10 ¹³ cm ⁻² , the silicon crystal becomes amorphous. Therefore, heat treatment is performed after the ion implantation. When applied, as shown in FIG. 6A, the p ⁺ -type impurity layer 106 is formed.
A, EOR (End of Range) point defect 1 such as transition loop
09 will occur. The EOR point defect 109 is generated almost without depending on the temperature or time of the heat treatment after the ion implantation, and once generated, it is difficult to completely eliminate it even if the heat treatment is performed thereafter. Therefore, in FIG.
As shown in (b), the EOR point defect 109 remains without disappearing even after the final MOS transistor is obtained.

By the way, when a bias voltage is applied to the extension region 105 to operate the MOS transistor, the depletion layer spreads from the extension region 105 toward the pocket region 106, but if the EOR point defect 109 exists in the pocket region 106. The depletion layer reaches the EOR point defect 109, which causes a junction leakage current. When a VLSI chip having such a MOS transistor is incorporated in a mobile communication device,
The junction leakage current increases power consumption during standby, which is not preferable.

However, in the fourth embodiment, in the ion implantation process for forming the p ⁺ -type impurity layer 106A to be the pocket region 106, indium ions are dosed at a dose of 5 × 10 ¹³ cm ^-2 or less. for the ion implantation, the p ⁺ type silicon crystal does not amorphization in impurity layer 106A of, since EOR point defects 109 in the impurity layer 106A of p ⁺ -type is not generated, the junction leakage current is less likely to occur.

(Fifth Embodiment) Hereinafter, a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIG.
A description will be given with reference to (a) to (c) and FIGS. 8 (a) to (c). The fifth embodiment is a second manufacturing method of the semiconductor device according to the first embodiment.

First, as shown in FIG. 6A, a semiconductor substrate 100 made of a p-type silicon substrate is implanted with p-type impurities such as boron ions at an implantation energy of 300 keV to 2000 keV and a dose of 1 × 10 ¹³ cm ^-2 to 1. × 10 ¹⁴ cm ^-2
After the p ⁻ -type well region 101 is formed by implanting ions with a dose of, a p-type impurity such as boron ions is added to the surface of the semiconductor substrate 100 at 20 keV to 60 k.
The p-type impurity layer 102A is formed on the well region 101 by performing ion implantation with eV and a dose amount of 4 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² .

Next, as shown in FIG. 7B, the surface of the semiconductor substrate 100 is oxidized to form a first silicon oxide film 103A having a thickness of 2 nm to 5 nm.

Next, after depositing a polysilicon film having a thickness of 200 nm to 300 nm over the entire surface of the first silicon oxide film 103A, the polysilicon film and the first silicon oxide film 103A are patterned. By doing so, as shown in FIG. 7C, the gate insulating film 103 and the gate electrode 104 are formed.

Next, using the gate electrode 104 as a mask on the p-type impurity layer 102A, ions of group IV atoms, such as germanium ions, are implanted with an energy of 5 keV to 10 keV and 5 × 10 ¹⁴ cm ⁻² to 1 × 10 5. ¹⁵ cm ^-2
Is ion-implanted to form a p-type amorphous layer 110 in the upper region of the p-type impurity layer 102A.

Next, as shown in FIG. 8A, n-type impurities such as arsenic ions are implanted into the p-type amorphous layer 110 using the gate electrode 104 as a mask and the implantation energy is 5 keV to 10 keV and 5 × 10 ^{14 is applied.} The amorphous layer 110 is formed by implanting ions at a dose of cm ⁻² to 1 × 10 ¹⁵ cm ^−2.
Then, an n ⁺ type impurity layer 105A is formed.

Next, with the gate electrode 104 as a mask, the p-type impurity layer 102A is exposed to 50 to 1 indium ions.
Implantation energy of 50 keV and 1 × 10 ¹³ cm ^{−2 to} 5
Ion implantation is performed at a dose of × 10 ¹³ cm ^-2 to form the p ⁺ -type impurity layer 106A in the lower region of the p-type impurity layer 102A. Then, with respect to the semiconductor substrate 100, for example, at 1000 ° C. in an inert gas atmosphere.
The heat treatment for 10 seconds at the temperature of 1, that is, the first heat treatment at high temperature for a short time is performed.

Next, after depositing a second silicon oxide film over the entire surface of the semiconductor substrate 100, anisotropic etching is performed on the second silicon oxide film to form the structure shown in FIG. ), The side wall 107 is formed on the side surface of the gate electrode 104.

Next, the n ⁺ type impurity layers 105A and p ⁺
After implanting an n-type impurity, for example, arsenic ions into the impurity-type impurity layer 106A, heat treatment is performed to activate the arsenic ions, and thereafter, in order to recover the crystal point defects, 10
A heat treatment for 10 seconds at a temperature of 00 ° C, that is, a second heat treatment at a high temperature for a short time is performed.

By doing so, as shown in FIG. 8C, the n ⁺ -type impurity layer 105A and the p ⁺ -type impurity layer 1 are formed.
In the regions on both sides of the gate electrode 104 in 06A, n
⁺ -Type also source consists impurity active layer region 108 of the drain is formed, the source or the inside of the respective upper region of the drain region 108 in the n ⁺ -type impurity layer 105A made of, n ⁺ -type impurity layers 105A Extension The region 105 is formed and the p ⁺ -type impurity layer 1 is formed.
A pocket region 106 made of ap ⁺ -type impurity layer 106A is formed inside each lower region of the source or drain region 108 in 06A.

According to the fifth embodiment, as in the fourth embodiment, indium ions having a larger atomic mass than boron ions are ion-implanted, and the p ⁺ -type pocket region 1 is formed.
Since the p ⁺ -type impurity layer 106A to be 06 is formed and the first heat treatment is performed at high temperature for a short time after ion implantation of indium ions, the pocket region 106 is formed.
Can be suppressed. Therefore, the p ⁺ -type impurity layer 106A to be the pocket region 106 can be formed so as to be spaced apart from the gate insulating film 103.

Also, in the fifth embodiment, as in the fourth embodiment, 5 × 10 ¹³ indium ions are added in the ion implantation process for forming the p ⁺ -type impurity layer 106A to be the pocket region 106. Since the ion implantation is performed with a dose amount of cm ⁻² or less, the silicon crystal does not become amorphous in the p ⁺ -type impurity layer 106A, and the p ⁺ -type impurity layer 106
Since the EOR point defect 109 does not occur in A, a junction leak current is unlikely to occur.

[0106] Incidentally, the distribution of the impurity concentration in the n ⁺ -type impurity layers 105A serving as extension region 105 is formed n ⁺ -type by ion implantation of arsenic ions hardly becomes steep.

Therefore, in the fifth embodiment, germanium ions are ion-implanted to form the amorphous layer 110, and then arsenic ions are ion-implanted to form the n ⁺ -type impurity layer 105A. , N ⁺ -type impurity layer 10
In the extension region 105 made of 5A, the distribution of the impurity concentration becomes steep, so that the extension region 105 can be made low in resistance.

The ion implantation position of germanium ion is
N ⁺ type impurity layer 1 to be the extension region 105
05A, the amorphous layer 110 is made shallower than the arsenic ion implantation position, and the amorphous layer 110 is an n ⁺ -type impurity layer 10
It is preferable not to spread below 5A. By doing so, as shown in FIG. 9A, the EOR point defect 109 generated by the subsequent heat treatment does not spread below the n ⁺ -type impurity layer 105A, that is, FIG. 9B. As shown in, the EOR point defect 109 does not occur in the pocket region 106.

Therefore, when a bias voltage is applied to the extension region 105, even if the depletion layer spreads from the extension region 105 toward the pocket region 106, the depletion layer reaches the EOR point defect and a junction leak current is generated. You can prevent the situation.

In the fifth embodiment, germanium ions are used as the ions for forming the amorphous layer 110, but instead of this, group IV ions such as silicon ions or carbon ions are used. The same effect can be obtained by using ions of other atoms belonging to.

(Sixth Embodiment) A semiconductor device manufacturing method according to a sixth embodiment of the present invention will be described below with reference to FIG.
Description will be given with reference to (a) to (c) and FIGS. 11 (a) and 11 (b). The sixth embodiment is the first manufacturing method of the semiconductor device according to the second embodiment.

First, as shown in FIG. 10A, a semiconductor substrate 200 made of a p-type silicon substrate is implanted with p-type impurities such as boron ions at an implantation energy of 300 keV to 2000 keV and a dose of 1 × 10 ¹³ cm ^-2 to 1. × 10 ¹⁴ cm
^{After the} p ⁻ type well region 201 is formed by implanting ions at a dose of ⁻² , indium ions are applied to the surface of the semiconductor substrate 200 at 50 keV to 150 keV and 5 keV.
A p-type impurity layer 202A is formed on the well region 201 by ion implantation at a dose amount of × 10 ¹² cm ^-2 to 1 × 10 ¹⁴ cm ^-2 .

Next, the surface of the semiconductor substrate 200 is oxidized to form a first silicon oxide film having a thickness of 2 nm to 5 nm, and then 200 nm to the entire surface of the first silicon oxide film. By depositing a polysilicon film having a thickness of 300 nm and then patterning the polysilicon film and the first silicon oxide film, FIG.
As shown in FIG.
4 is formed.

Next, as shown in FIG. 10C, the gate electrode 204 is used as a mask on the p-type impurity layer 202A.
An n-type impurity such as arsenic ion is added at 5 keV to 10 keV
Implantation energy and 5 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ c
By implanting ions at a dose of m ⁻² , the n ⁺ -type impurity layer 205A is formed in the upper region of the p-type impurity layer 202A.
To form.

Next, after depositing a second silicon oxide film over the entire surface of the semiconductor substrate 200 at a temperature of about 600 ° C. to about 850 ° C. for about 10 minutes to about 200 minutes,
Anisotropic etching is performed on the second silicon oxide film to form a sidewall 2 made of the second silicon oxide film on the side surface of the gate electrode 204, as shown in FIG.
07 is formed. In this case, since the semiconductor substrate 200 is subjected to the first heat treatment at a low temperature for a long time in the step of depositing the second silicon oxide film, the upper region of the p-type impurity layer 202A is formed. A p-type impurity layer 202A is formed inside the n ⁺ -type impurity layer 205A.
The p ⁻ -type low-concentration channel region 206 having a lower concentration of activated impurities than that of the above is formed.

Next, after implanting n-type impurities such as arsenic ions into the n ⁺ -type impurity layer 205A and the p-type impurity layer 202A, heat treatment is performed to activate the arsenic ions, and then the crystal point defects are generated. 100 to recover
A heat treatment for 10 seconds at a temperature of 0 ° C., that is, a second heat treatment at a high temperature for a short time is performed.

By doing so, as shown in FIG. 11C, the n ⁺ -type impurity layer 205A and the p-type impurity layer 2 are formed.
In the regions on both sides of the gate electrode 204 in 02A, n
^A source or drain region 208 made of a ⁺ type impurity active layer is formed, and an n ⁺ type impurity layer 205A is formed.
Inside each upper region of the source or drain region 208 in, an extension region 205 made of an n ⁺ -type impurity layer 205A is formed.

According to the sixth embodiment, indium ions are ion-implanted to form the p-type impurity layer 202A on the well region 201, and the n ⁺ -type impurity layer 20 is formed.
Since the semiconductor substrate 200 is heat-treated at low temperature for a long time after forming 5A, the p-type impurity layer 202A is formed.
A p ⁻ -type low-concentration channel region 206 having a lower concentration of activated impurities than the p-type impurity layer 202A can be formed inside the n ⁺ -type impurity layer 205A in the upper region of the. Hereinafter, the p ⁻ -type low-concentration channel region 20
The mechanism by which 6 is formed will be described.

It is known that indium ions combine with interstitial silicon to inactivate them (eg, P. Bou.
illonet al., "Anomalus short channel effects in Ind
iumimplanted nMOSFETs ", Digest of Tech. Report of
IEDM, pp.-, 1997).

When arsenic ions are ion-implanted to form the n ⁺ -type impurity layer 205A, the p-type impurity layer 202A is formed.
The interstitial silicon atoms generated in the inside of the gate insulating film 20 are subjected to heat treatment at a low temperature for a long time which is performed thereafter.
Move toward 3.

According to the sixth embodiment, since indium ions are ion-implanted to form the p-type impurity layer 202A, the gate insulating film 2 in the p-type impurity layer 202A is formed.
Area on both sides of 03 (extension area 205
Indium ions existing in a region (contacting with) are inactivated by combining with interstitial silicon atoms that have moved from the n ⁺ -type impurity layer 205A toward the gate insulating film 203, and thus in the p-type impurity layer 202A. Lower regions on both sides of the gate insulating film 203, that is, the p-type impurity layer 2
In the region inside the n ⁺ -type impurity layer 205A in the upper region of 02A, the p ⁻ -type low-concentration channel region 206 in which the concentration of the activation impurity is lower than that of the p-type impurity layer 202A.
Is formed.

In addition, in the sixth embodiment, indium ions are ion-implanted to form the p-type impurity layer 202A to be the channel region 202. Therefore, in the channel region 202, the reason will be described below. It is possible to prevent a decrease in carrier mobility. That is, since the indium ion has a larger atomic mass than the boron ion and thus has a concentration distribution peak in the lower region of the p-type impurity layer 202A, the concentration decreases toward the surface, forming a so-called retrograde channel. can do. For this reason, the mobility of carriers in the channel region is less likely to decrease, so that the driving force of the MOS transistor can be improved.

(Seventh Embodiment) A method for manufacturing a semiconductor device according to a seventh embodiment of the present invention will be described below with reference to FIG.
Description will be given with reference to (a) to (c) and FIGS. 13 (a) to (c). The seventh embodiment is a second manufacturing method of the semiconductor device according to the second embodiment.

First, as shown in FIG. 12A, a semiconductor substrate 200 made of a p-type silicon substrate is implanted with p-type impurities such as boron ions at an implantation energy of 300 keV to 2000 keV and a dose of 1 × 10 ¹³ cm ^-2 to 1. × 10 ¹⁴ cm
^{After the} p ⁻ type well region 201 is formed by implanting ions at a dose of ⁻² , indium ions are applied to the surface of the semiconductor substrate 200 at 50 keV to 150 keV and 5 keV.
A p-type impurity layer 202A is formed on the well region 201 by ion implantation at a dose amount of × 10 ¹² cm ^-2 to 1 × 10 ¹⁴ cm ^-2 .

Next, the surface of the semiconductor substrate 200 is oxidized to form a first silicon oxide film having a thickness of 2 nm to 5 nm, and then 200 nm to the entire surface of the first silicon oxide film. By depositing a polysilicon film having a thickness of 300 nm and then patterning the polysilicon film and the first silicon oxide film, FIG.
As shown in FIG.
4 is formed.

Next, as shown in FIG. 12C, the gate electrode 204 is used as a mask on the p-type impurity layer 202A.
An ion of an atom belonging to group IV, for example, a germanium ion, is implanted with an injection energy of 5 keV to 10 keV and 5 × 1.
Ion implantation is performed at 0 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² to p-type amorphous layer 210 in the upper region of p-type impurity layer 102A.
To form.

Next, as shown in FIG. 13A, n-type impurities such as arsenic ions are implanted into the p-type amorphous layer 210 using the gate electrode 204 as a mask and the implantation energy is 5 to 10 keV and 5 × 10 ^{14 is applied.} By implanting ions at a dose of cm ⁻² to 1 × 10 ¹⁵ cm ⁻² , n is added to the amorphous layer 210.
^{A +} type impurity layer 205A is formed.

Next, after depositing a second silicon oxide film over the entire surface of the semiconductor substrate 200 at a temperature of about 600 ° C. to about 850 ° C. for about 10 minutes to about 200 minutes,
By anisotropically etching the second silicon oxide film, as shown in FIG. 13B, the sidewall 2 made of the second silicon oxide film is formed on the side surface of the gate electrode 204.
07 is formed. In this case, since the semiconductor substrate 200 is subjected to the first heat treatment at a low temperature for a long time in the step of depositing the second silicon oxide film, the upper region of the p-type impurity layer 202A is formed. A p-type impurity layer 202A is formed inside the n ⁺ -type impurity layer 205A.
The p ⁻ -type low-concentration channel region 206 having a lower concentration of activated impurities than that of the above is formed.

Next, an n-type impurity such as arsenic ion is ion-implanted into the n ⁺ -type impurity layer 205A and the p-type impurity layer 202A, and then heat treatment is performed to activate the arsenic ion. 100 to recover
A heat treatment for 10 seconds at a temperature of 0 ° C., that is, a second heat treatment at a high temperature for a short time is performed.

By doing so, as shown in FIG. 13C, the n ⁺ -type impurity layer 205A and the p-type impurity layer 2 are formed.
In the regions on both sides of the gate electrode 204 in 02A, n
^A source or drain region 208 made of a ⁺ type impurity active layer is formed, and an n ⁺ type impurity layer 205A is formed.
Inside each upper region of the source or drain region 208 in, an extension region 205 made of an n ⁺ -type impurity layer 205A is formed.

According to the seventh embodiment, indium ions are ion-implanted to form the p-type impurity layer 202A and the n ⁺ -type impurity layer 205A is formed, and then the semiconductor substrate 200 is subjected to a low temperature for a long time. Since the heat treatment is performed, n ⁺ in the upper region of the p-type impurity layer 202A is increased.
Inside the p-type impurity layer 205A, the p-type impurity layer 202 is formed.
A p ⁻ -type low-concentration channel region 206 having a lower concentration of activated impurities than A is formed. The mechanism by which the p ⁻ -type low-concentration channel region 206 is formed is described in
It is similar to the embodiment.

In addition, in the seventh embodiment, arsenic ions are ion-implanted to form the n ⁺ -type impurity layer 205A, and germanium ions are ion-implanted to form the amorphous layer 210. The p-type impurity layer 2
Since the interstitial silicon atoms generated inside 02A are larger than in the case of the sixth embodiment (when not implanting germanium ions), the gate insulating film 203 in the p-type impurity layer 202A. Bonding between indium ions existing in the lower regions of both sides of the interstitial silicon atoms and interstitial silicon atoms is increased as compared with the case of the sixth embodiment. Therefore, the n ⁺ -type impurity layer 20 in the lower region on both sides of the gate insulating film 203 in the p-type impurity layer 202A, that is, in the upper region of the p-type impurity layer 202A.
Since indium ions are further inactivated in the region inside 5A, the p ⁻ -type low-concentration channel region 206 can be formed more efficiently.

In addition, in the seventh embodiment, germanium ions are ion-implanted to form the amorphous layer 210, and then arsenic ions are ion-implanted to form the n ⁺ -type impurity layer 205A. Therefore, the n ⁺ -type impurity layer 20
Since the extension region 205 made of 5A becomes steep, the resistance of the extension region 205 can be reduced.

Further, in the seventh embodiment, indium ions are ion-implanted to form the p-type impurity layer 202A to be the channel region 202.
Since a so-called retrograde channel can be formed in the same manner as in the above embodiment, it is possible to prevent a decrease in carrier mobility in the channel region 202.

(Eighth Embodiment) A method for manufacturing a semiconductor device according to an eighth embodiment of the present invention will be described below with reference to FIG.
A description will be given with reference to (a) to (c) and FIGS. 15 (a) to (c). The eighth embodiment is the first manufacturing method of the semiconductor device according to the third embodiment.

First, as shown in FIG. 14A, a semiconductor substrate 300 made of a p-type silicon substrate is implanted with p-type impurities such as boron ions at an implantation energy of 300 keV to 2000 keV and a dose of 1 × 10 ¹³ cm ^-2 to 1. × 10 ¹⁴ cm
^{After the} p ⁻ type well region 301 is formed by implanting ions at a dose of ⁻² , indium ions are applied to the surface of the semiconductor substrate 300 at 50 keV to 150 keV and 5 keV.
A p-type impurity layer 302A is formed on the well region 301 by ion implantation at a dose amount of × 10 ¹² cm ^-2 to 1 × 10 ¹⁴ cm ^-2 .

Next, the surface of the semiconductor substrate 300 is oxidized to form a first silicon oxide film having a thickness of 2 nm to 5 nm, and then 200 nm to the entire surface of the first silicon oxide film. By depositing a polysilicon film having a thickness of 300 nm and then patterning the polysilicon film and the first silicon oxide film, FIG.
As shown in FIG.
4 is formed.

Next, as shown in FIG. 14C, the gate electrode 304 is used as a mask on the p-type impurity layer 302A.
An n-type impurity such as arsenic ion is added at 5 keV to 10 keV
Implantation energy and 5 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ c
By implanting ions at a dose of m ^−2, an n ⁺ -type impurity layer 305A is formed in the upper region of the p-type impurity layer 302A.
To form.

Next, with respect to the semiconductor substrate 300, about 60
By performing the heat treatment for about 10 minutes to about 200 minutes at the temperature of 0 ° C. to about 850 ° C., that is, the first heat treatment at a low temperature for a long time, as shown in FIG.
A p ⁻ -type low-concentration channel region 306 having an impurity concentration lower than that of the p-type impurity layer 302A is formed inside the n ⁺ -type impurity layer 305A in the upper region of 2A.

Next, with the gate electrode 304 as a mask, the p-type impurity layer 302A is exposed to 50 to 1 indium ions.
Implantation energy of 50 keV and 5 × 10 ¹² cm ⁻² to 1
By implanting ions at a dose of × 10 ¹⁴ cm ^-2 , a p ⁺ -type impurity layer 307A is formed in the lower region of the p-type impurity layer 302A. Then, with respect to the semiconductor substrate 300, for example, at 1000 ° C. in an inert gas atmosphere.
The heat treatment is performed for 10 seconds under the above temperature, that is, the second heat treatment at a high temperature for a short time is performed.

Next, after depositing a second silicon oxide film over the entire surface of the semiconductor substrate 300, anisotropic etching is performed on the second silicon oxide film to form the structure shown in FIG. ), A sidewall 308 is formed on the side surface of the gate electrode 304.

Next, the n ⁺ -type impurity layers 305A and p ⁺
N-type impurities such as arsenic ions are ion-implanted into the impurity layer 307A of the same type, heat treatment is performed to activate the arsenic ions, and thereafter, in order to recover the crystal point defects, 10
A heat treatment for 10 seconds at a temperature of 00 ° C., that is, a third heat treatment at a high temperature for a short time is performed.

By doing so, as shown in FIG. 15C, in the regions on both sides of the gate electrode 304 in the n ⁺ -type impurity layer 305A and the p ⁺ -type impurity layer 306A,
A source or drain region 309 made of an n ⁺ type impurity active layer is formed, and an n ⁺ type impurity layer 305A is formed inside each upper region of the source or drain region 308 in the n ⁺ type impurity layer 305A. The extension region 305 is formed and the p ⁺ -type impurity layer 3 is formed.
A pocket region 307 made of ap ⁺ -type impurity layer 307A is formed inside each lower region of the source or drain region 308 in 07A.

According to the eighth embodiment, the step of ion-implanting indium ions to form the p-type impurity layer 302A and the step of forming the n ⁺ -type impurity layer 305A and then the semiconductor substrate 300 at a low temperature for a long time are performed. Heat treatment step of p-type impurity layer 302A inside the n ⁺ -type impurity layer 305A in the upper region of the p-type impurity layer 302A. ^-
A lightly doped channel region 306 of the mold can be formed. The mechanism of forming the p ⁻ -type low-concentration channel region 306 is the same as in the sixth embodiment.

Further, according to the eighth embodiment, as in the fourth embodiment, indium ions having a larger atomic mass than boron ions are ion-implanted and the pocket regions 30 are formed.
Since the second heat treatment is performed at a high temperature for a short time after forming the p ⁺ -type impurity layer 307A to be 7, the generation of accelerated diffusion due to point defects is suppressed, so that the p ⁺ -type impurity layer is formed. The expansion of the pocket area 307 made of 307A can be suppressed. Therefore, the p ⁺ -type impurity layer 307A to be the pocket region 307 can be formed so as to be spaced from the gate insulating film 303.

In the eighth embodiment, the first high-temperature short-time heat treatment is performed at a temperature of 1000 ° C. for 10 seconds. However, the present invention is not limited to this, and the temperature range is about 950 ° C. to about 1050 ° C. In addition, in the time range of about 0.1 second to about 30 seconds, the effect of suppressing the expansion of the pocket region 307 can be obtained.

Further, in the eighth embodiment, indium ions are ion-implanted to form the p-type impurity layer 302A which becomes the channel region 302.
Since a so-called retrograde channel can be formed in the same manner as in the first embodiment, it is possible to prevent a decrease in carrier mobility in the channel region 302.

(Ninth Embodiment) A method for manufacturing a semiconductor device according to a ninth embodiment of the present invention will be described below with reference to FIG.
A description will be given with reference to (a) to (c) and FIGS. 17 (a) to (c). The ninth embodiment is the second manufacturing method of the semiconductor device according to the third embodiment.

First, as shown in FIG. 16A, a semiconductor substrate 300 made of a p-type silicon substrate is implanted with p-type impurities such as boron ions at an implantation energy of 300 keV to 2000 keV and at a dose of 1 × 10 ¹³ cm ^-2 to 1. × 10 ¹⁴ cm
^{After the} p ⁻ type well region 301 is formed by implanting ions at a dose of ⁻² , indium ions are added to the surface of the semiconductor substrate 300 at 20 keV to 200 keV and 4
A p-type impurity layer 302A is formed on the well region 301 by ion implantation with a dose amount of × 10 ¹² cm ^-2 to 1 × 10 ¹³ cm ^-2 .

Next, the surface of the semiconductor substrate 300 is oxidized to form a first silicon oxide film having a thickness of 2 nm to 5 nm, and then 200 nm to the entire surface of the first silicon oxide film. By depositing a polysilicon film having a thickness of 300 nm and then patterning the polysilicon film and the first silicon oxide film, FIG.
As shown in FIG.
4 is formed.

Next, using the gate electrode 304 as a mask on the p-type impurity layer 302A, ions of group IV atoms, such as germanium ions, are implanted with an energy of 5 keV to 10 keV and 5 × 10 ¹⁴ cm ⁻² to 1 × 10 5. ¹⁵ cm ^-2
Ion implantation is performed to form a p-type amorphous layer 310 in the upper region of the p-type impurity layer 302A.

Next, as shown in FIG. 16C, with the gate electrode 304 used as a mask in the amorphous layer 310, n-type impurities such as arsenic ions are implanted with an energy of 5 keV to 10 keV and 5 × 10 ¹⁴ cm ^{−. The} n ⁺ -type impurity layer 305A is formed in the amorphous layer 310 by performing ion implantation with a dose amount of ² to 1 × 10 ¹⁵ cm ⁻² .

Next, after depositing a second silicon oxide film over the entire surface of the semiconductor substrate 300 at a temperature of about 600 ° C. to about 850 ° C. for about 10 minutes to about 200 minutes,
Anisotropic etching is applied to the second silicon oxide film to form side walls 3 of the second silicon oxide film on the side surfaces of the gate electrode 304, as shown in FIG.
08 is formed. In this case, since the semiconductor substrate 300 has been subjected to the first heat treatment at a low temperature for a long time in the step of depositing the second silicon oxide film, the p-type impurity layer 302A in the upper region is exposed. Inside the n ⁺ -type impurity layer 305A, the p-type impurity layer 302A is formed.
P ⁻ -type low-concentration channel region 306 having a lower concentration of activated impurities than that of

Next, as shown in FIG. 17B, n-type impurities, such as arsenic ions, are ion-implanted into the n ⁺ -type impurity layer 305A and the p-type impurity layer 302A to form the n ⁺ -type impurity layer. 305A in the area of both sides of the gate electrode 304 in and p-type impurity layer 302A, with n ⁺ -type source and consisting of impurity layer forms a region 309 of the drain, n ⁺ -type source and the drain of the impurity layer 305A of An extension region 305 made of an n ⁺ type impurity layer 305A is formed inside each upper region of the region 309.

Next, as shown in FIG. 17C, after removing the side wall 308, the p-type impurity layer 302A is formed.
With the gate electrode 304 as a mask, indium ions are implanted with energy of 100 to 200 keV and 1 × 10 5.
By implanting ions at a dose amount of ¹³ cm ⁻² to 4 × 10 ¹³ cm ⁻² , p is implanted below the extension region 305 and inside the source or drain region 309 in the lower region of the p-type impurity layer 302A. ^{A +} type pocket region 307 is formed.

Next, the semiconductor substrate 300 is subjected to a heat treatment at a temperature of 1000 ° C. for 10 seconds, that is, a second heat treatment at a high temperature for a short time to activate the arsenic ions in the source or drain region 309. At the same time, the crystal point defects are recovered.

In the ninth embodiment, indium ions are ion-implanted to form the p-type impurity layer 302A, germanium ions are ion-implanted to form the amorphous layer 310, and n ^+. Type impurity layer 305
Since the semiconductor substrate 300 is heat-treated at low temperature for a long time after forming A, the n ⁺ -type impurity layer in the upper region of the p-type impurity layer 302A is provided as in the seventh embodiment. The p-type impurity layer 3 is formed inside the 305A.
It is possible to efficiently form the p ⁻ -type low-concentration channel region 306 in which the concentration of the activated impurities is lower than that of 02A.

According to the ninth embodiment, germanium ions are ion-implanted to form the amorphous layer 310, and then arsenic ions are ion-implanted to form the n ⁺ -type impurity layer 305A. Therefore, the n ⁺ -type impurity layer 305
Since the distribution of the impurity concentration in the extension region 305 made of A becomes steep, the extension region 3
A low resistance of 05 can be realized.

According to the ninth embodiment, similarly to the fourth embodiment, immediately after the indium ion having a larger atomic mass than the boron ion is ion-implanted to form the p ⁺ -type pocket region 307. Since the second heat treatment is performed at a high temperature for a short time, the expansion of the pocket region 307 can be suppressed. Therefore, the p ⁺ -type impurity layer 307A to be the pocket region 307 can be formed so as to be spaced from the gate insulating film 303.

Further, in the ninth embodiment, indium ions are ion-implanted to form the p-type impurity layer 302A which will become the channel region 302.
Since a so-called retrograde channel can be formed in the same manner as in the first embodiment, it is possible to prevent a decrease in carrier mobility in the channel region 302.

(Tenth Embodiment) The first embodiment of the present invention will be described below.
A method for manufacturing a semiconductor device according to the No. 0 embodiment will be described with reference to FIGS. 18 (a) to 18 (c) and FIGS. 19 (a) to 19 (c). The tenth embodiment is a third manufacturing method of the semiconductor device according to the third embodiment.

First, as shown in FIG. 18A, a semiconductor substrate 300 made of a p-type silicon substrate is implanted with p-type impurities such as boron ions at an implantation energy of 300 keV to 2000 keV and a dose of 1 × 10 ¹³ cm ^-2 to 1. × 10 ¹⁴ cm
^{After the} p ⁻ type well region 301 is formed by implanting ions at a dose of ⁻² , indium ions are added to the surface of the semiconductor substrate 300 at 20 keV to 200 keV and 4
A p-type impurity layer 302A is formed on the well region 301 by ion implantation with a dose amount of × 10 ¹² cm ^-2 to 1 × 10 ¹³ cm ^-2 .

Next, the surface of the semiconductor substrate 300 is oxidized to form a first silicon oxide film having a thickness of 2 nm to 5 nm, and then 200 nm to the entire surface of the first silicon oxide film. By depositing a polysilicon film having a thickness of 300 nm and then patterning the polysilicon film and the first silicon oxide film, FIG.
As shown in FIG.
4 is formed.

Next, using the gate electrode 304 as a mask on the p-type impurity layer 302A, ions of a group IV atom, for example, silicon ions, are implanted with an implantation energy of 5 keV to 10 keV and 1 × 10 ¹⁴ cm ^{−2 to} 5 × 10 5. Ions are implanted at ¹⁴ cm ⁻² to form a silicon implantation layer 311 in the upper region of the p-type impurity layer 302A.

Next, with respect to the semiconductor substrate 300, about 60
By performing a heat treatment for about 10 minutes to about 200 minutes at a temperature of 0 ° C. to about 850 ° C., that is, a first heat treatment at a low temperature for a long time, as shown in FIG.
A p ⁻ -type low-concentration impurity layer 306A having a lower concentration of activating impurities than the p-type impurity layer 302A is formed so as to extend over the upper region of 1 and the upper region of the p-type impurity layer 302A.

Next, as shown in FIG. 19B, the gate electrode 304 is used as a mask on the p-type impurity layer 302A.
By implanting indium ions with an implantation energy of 50 to 200 keV and a dose amount of 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² , the p-type impurity layer 302A is formed.
A p ⁺ -type impurity layer 307A is formed in the lower region of.

Next, using the gate electrode 304 as a mask, the p ⁻ -type low-concentration impurity layer 306A and the p-type impurity layer 302A are doped with n-type impurities such as arsenic ions at 5 keV to 1 keV.
Implantation energy of 0 keV and 5 × 10 ¹⁴ cm ⁻² to 1 ×
By implanting ions at a dose of 10 ¹⁵ cm ^-2 ,
p ⁻ type low-concentration impurity layer 306A and p type impurity layer 3
An n ⁺ -type impurity layer 305A is formed in the upper region of 02A, and thereafter, with respect to the semiconductor substrate 300, for example, 100
A heat treatment for 10 seconds at a temperature of 0 ° C., that is, a second heat treatment at a high temperature for a short time is performed.

Next, after depositing a second silicon oxide film over the entire surface of the semiconductor substrate 300, anisotropic etching is performed on the second silicon oxide film, so that FIG. ), A sidewall 308 is formed on the side surface of the gate electrode 304.

Next, the n ⁺ type impurity layers 305A and p ⁺
N-type impurities such as arsenic ions are ion-implanted into the impurity layer 307A of the same type, heat treatment is performed to activate the arsenic ions, and thereafter, in order to recover the crystal point defects, 10
A heat treatment for 10 seconds at a temperature of 00 ° C., that is, a third heat treatment at a high temperature for a short time is performed.

By doing so, as shown in FIG. 8C, the n ⁺ -type impurity layer 105A and the p ⁺ -type impurity layer 3 are formed.
In the regions on both sides of the gate electrode 304 in 07A, n
⁺ -Type also source consists impurity active layer region 309 of the drain is formed, on the inside of the respective upper regions of the n ⁺ -type source and drain regions 309 in the impurity layer 305A of, consisting impurity layer 305A of the n ⁺ -type extension The region 305 is formed and the p ⁺ -type impurity layer 3 is formed.
A pocket region 307 made of ap ⁺ -type impurity layer 307A is formed inside each lower region of the source or drain region 309 in 07A.

According to the tenth embodiment, the steps of ion-implanting indium ions to form the p-type impurity layer 302A, the steps of ion-implanting silicon ions to form the silicon-implanted layer 311, and the semiconductor substrate 300. because and a step of performing first heat treatment of low temperature long time relative to, the upper region of the p-type impurity layer 302A, the concentration of activated impurities in comparison with the p-type impurity layer 302A low p ^-
The low-concentration impurity layer 306A of the mold can be efficiently formed. The mechanism of forming the p ⁻ -type low-concentration impurity layer 306A is the same as in the sixth embodiment.

Further, according to the tenth embodiment, indium ions having a larger atomic mass than boron ions are ion-implanted to form the p ⁺ -type impurity layer 307A which becomes the pocket region 307, immediately after high temperature and short time. Since the second heat treatment is performed, it is possible to suppress the expansion of the p ⁺ -type impurity layer 307A that will be the pocket region 307.
Therefore, the p ⁺ type impurity layer 3 to be the pocket region 307 is formed.
07A can be formed so as to be spaced apart from the gate insulating film 303.

Further, in the tenth embodiment, indium ions are ion-implanted to form the p ⁺ -type impurity layer 307A which becomes the pocket regions 307, and then arsenic ions are ion-implanted to become the extension regions 305. ^{Since the +} type impurity layer 305A is formed, the arsenic ion channeling phenomenon in the n ⁺ type impurity layer 305A is suppressed. For this reason, the impurity concentration distribution in the extension region 305 made of the n ⁺ -type impurity layer 305A becomes steep, so that the extension region 305 is formed.
It is possible to reduce the parasitic resistance value and to suppress the short channel effect.

Further, in the tenth embodiment, indium ions are ion-implanted to form the channel region 302.
Since the p-type impurity layer 302A to be formed is formed, a so-called retrograde channel can be formed as in the sixth embodiment, so that the mobility of carriers in the channel region 302 can be prevented from lowering.

[0175]

According to the first semiconductor device, since the pocket region is formed so as to be spaced apart from the gate insulating film, the short channel effect is suppressed and the MO transistor is formed.
It is possible to prevent the driving force of the S transistor from being lowered.

According to the second semiconductor device, since the low-concentration channel regions in which the concentration of the activation impurities is lower than that in the central portion of the channel region are provided in the regions on both sides of the channel region, the resistance of the extension region is reduced. As a result, the driving power of the MOS transistor can be prevented from being lowered.

According to the first or second method of manufacturing a semiconductor device, indium ions are ion-implanted to form a first conductivity type impurity layer to be a pocket region, so that a space is provided between the gate insulating film and the first conductivity type impurity layer. It is possible to reliably manufacture the first semiconductor device having the pocket region.

Particularly, according to the second semiconductor device manufacturing method, the amorphous layer is formed in the upper region of the first conductivity type semiconductor layer, and then the second conductivity type impurity ions are ion-implanted. The first of the second conductivity type which becomes the extension region.
Since the impurity layer is formed, the resistance of the extension region can be reduced, so that the driving force of the MOS transistor can be improved.

According to the third or fourth method of manufacturing a semiconductor device, indium ions are ion-implanted to form a semiconductor layer of the first conductivity type serving as a channel region, and impurity ions of the second conductivity type are ion-implanted. After implantation to form a second conductivity type first impurity layer to be an extension region,
And a step of performing a heat treatment at a temperature of about 600 ° C. to about 850 ° C. for a long time at a low temperature, so that the concentration of activated impurities in the regions on both sides of the channel region is lower than that in the central portion of the channel region. It is possible to reliably manufacture the second semiconductor device having the concentration channel region.

Particularly, according to the fourth method of manufacturing a semiconductor device, ions of group IV atoms are ion-implanted before the step of forming the second conductivity type first impurity layer to be the extension region. Since the step of forming the amorphous layer is performed, the number of indium ions that are inactivated by the bond with the interstitial silicon atoms increases, so that the number of activated impurities of the indium ion is higher than that of the semiconductor layer of the first conductivity type. The low-concentration channel region having a low concentration can be efficiently formed.

According to the fifth, sixth or seventh method of manufacturing a semiconductor device, low concentration channel regions having a lower concentration of activating impurities than the central portion of the channel region are formed in the regions on both sides of the channel region. At the same time, it is possible to reliably manufacture a semiconductor device having a pocket region spaced apart from the gate insulating film.

In particular, according to the sixth method of manufacturing a semiconductor device, the distribution of the impurity concentration in the first impurity layer of the second conductivity type can be made steep, so that the resistance of the extension region can be reduced.

In particular, according to the seventh semiconductor device manufacturing method, the parasitic resistance value of the extension region can be reduced and the short channel effect can be suppressed.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIGS. 4A to 4C are cross-sectional views showing each step of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

5A to 5C are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

6A and 6B are cross-sectional views for explaining the problems of the conventional method for manufacturing a semiconductor device.

7A to 7C are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

8A to 8C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.

9A and 9B are cross-sectional views illustrating the effect of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.

10A to 10C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention.

11A and 11B are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention.

12A to 12C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the seventh embodiment of the present invention.

13A to 13C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the seventh embodiment of the present invention.

14A to 14C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the eighth embodiment of the present invention.

15A to 15C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the eighth embodiment of the present invention.

16A to 16C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the ninth embodiment of the present invention.

17A to 17C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the ninth embodiment of the present invention.

18A to 18C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the tenth embodiment of the present invention.

19A to 19C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the tenth embodiment of the present invention.

FIG. 20 is a sectional view showing a conventional semiconductor device.

[Explanation of symbols]

100 semiconductor substrate 101 well region 102A p-type impurity layer 102 channel region 103 gate insulating film 103A first silicon oxide film 104 gate electrode 105A n ⁺ -type impurity layer 105 extension region 106A p ⁺ -type impurity layer 106 pocket region 107 Sidewall 108 Source or drain region 109 EOR defect 110 Amorphous layer 200 Semiconductor substrate 201 Well region 202 Channel region 202A p-type impurity layer 203 gate insulating film 204 gate electrode 205A n ⁺ -type impurity layer 205 extension region 206 low Concentration channel region 207 Sidewall 208 Source or drain region 210 Amorphous layer 300 Semiconductor substrate 301 Well region 302 Channel region 302A p-type impurity layer 303 Gate insulating film 304 Over gate electrode 305A n ⁺ -type impurity layer 305 extension region 306 the low concentration channel region 307A p ⁺ -type impurity layer 307 pocket regions 308 sidewall 309 source or drain region 310 amorphous layer 311 silicon implanted layer of the

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-11-261069 (JP, A) JP-A-8-306923 (JP, A) JP-A-4-158529 (JP, A) JP-A-10- 270687 (JP, A) JP 10-294454 (JP, A) JP 10-65149 (JP, A) JP 4-343437 (JP, A) JP 2000-299447 (JP, A) Open 2000-49344 (JP, A) JP 7-22619 (JP, A) International Publication 97/050115 (WO, A1) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (7)

(57) [Claims] 1. A channel composed of a gate electrode formed on a semiconductor substrate via a gate insulating film, and a first conductivity type impurity layer formed in a region immediately below the gate electrode on a surface portion of the semiconductor substrate. A region, a source region and a drain region formed of impurity layers of the second conductivity type formed in regions on both sides of the gate electrode on the surface of the semiconductor substrate, the channel region, the source region and the drain region An extension region of the second conductivity type formed so as to contact the source region or the drain region, respectively, and each upper region of the channel region, and each of the lower regions of the source region and the drain region. Between the gate insulating film and the source region or the drain region in contact with the gate insulating film. A first conductivity type pocket region and regions on both sides of the channel region are formed so as to be in contact with the extension region, respectively, and have a lower concentration of activating impurities than the central region of the channel region.
A semiconductor device having a conductivity type low concentration channel region. 2. A gate electrode formed on a semiconductor substrate via a gate insulating film, and a first conductivity type doped with indium ions formed in a region directly below the gate electrode on a surface portion of the semiconductor substrate. Channel region formed of an impurity layer, source and drain regions formed of an impurity layer of a second conductivity type formed in regions on both sides of the gate electrode on the surface portion of the semiconductor substrate, the channel region and the The second conductivity type extension region is formed between the source region and each upper region of the drain region so as to be in contact with the source region or the drain region; They are formed so as to be in contact with the extension regions, respectively. First low concentration
A semiconductor device having a conductivity type low concentration channel region. 3. A first conductivity type first region which becomes a channel region by implanting indium ions into a surface portion of a semiconductor substrate.
Forming an impurity layer of (a), forming a gate electrode on the semiconductor substrate via a gate insulating film after the step (a), and forming a first impurity layer on the first impurity layer. A step (c) of implanting second conductivity type impurity ions by using the gate electrode as a mask to form a second conductivity type second impurity layer in an upper region of the first impurity layer; After (c), an insulating film is deposited over the entire surface of the semiconductor substrate at a temperature of about 600 ° C. to about 850 ° C. to form the second impurity layer in the upper region of the first impurity layer. A step (d) of forming a first-conductivity-type low-concentration channel region having an impurity concentration lower than that of the first impurity layer, and anisotropically etching the insulating film to form the gate electrode Of forming a sidewall on the side surface of the (e)
And second-conductivity-type impurity ions are ion-implanted into the second impurity layer and the first impurity layer using the gate electrode and the sidewalls as a mask, and the second impurity layer and the first impurity layer. A source region and a drain region made of a third impurity layer of the second conductivity type are formed in regions of the impurity layer on both sides of the gate electrode, and the inside of each upper region of the source region or the drain region is formed. And (f) forming a second conductivity type extension region made of a second impurity layer. 4. A first conductivity type first region which becomes a channel region by implanting indium ions into a surface portion of a semiconductor substrate.
Forming an impurity layer of (a), forming a gate electrode on the semiconductor substrate via a gate insulating film after the step (a), and forming a first impurity layer on the first impurity layer. I using the gate electrode as a mask
By implanting ions of atoms belonging to Group V, the first
(C) forming an amorphous layer of the first conductivity type in the upper region of the impurity layer, and implanting impurity ions of the second conductivity type into the amorphous layer using the gate electrode as a mask, A step (d) of forming a second impurity layer of the second conductivity type in the amorphous layer; and, after the step (d), an insulating film is formed on the entire surface of the semiconductor substrate at about 600 ° C. A low-concentration channel of the first conductivity type, which is deposited at a temperature of about 850 ° C. and has an impurity concentration lower than that of the first impurity layer inside the second impurity layer in the upper region of the first impurity layer. A step (e) of forming a region; and a step (f) of anisotropically etching the insulating film to form a sidewall on a side surface of the gate electrode.
And impurity ions of the second conductivity type are ion-implanted into the second impurity layer and the first impurity layer by using the gate electrode and the sidewall as a mask, and the second impurity layer and the first impurity layer are implanted. A source region and a drain region made of a third impurity layer of the second conductivity type are formed in regions on both sides of the gate electrode in the impurity layer, and the first region is formed inside each upper region of the source region or the drain region. Two
And a step (g) of forming a second conductivity type extension region formed of the impurity layer. 5. An indium ion is ion-implanted into a surface portion of a semiconductor substrate to form a first conductivity type first region which becomes a channel region.
Forming an impurity layer of (a), forming a gate electrode on the semiconductor substrate via a gate insulating film after the step (a), and forming a first impurity layer on the first impurity layer. A step (c) of implanting second conductivity type impurity ions by using the gate electrode as a mask to form a second conductivity type second impurity layer in an upper region of the first impurity layer; After (c), about 60 with respect to the semiconductor substrate.
A first heat treatment is performed at a temperature of 0 ° C. to about 850 ° C. for a long time so that an impurity concentration higher than that of the first impurity layer is inside the second impurity layer in the upper region of the first impurity layer. (D) forming a low-concentration first-conductivity-type low-concentration channel region, and indium ions are ion-implanted into the first impurity layer using the gate electrode as a mask to form a lower region of the first impurity layer. And (e) forming a third impurity layer of the first conductivity type on the semiconductor substrate, and after the step (e), about 95% of the semiconductor substrate is formed.
A step (f) of performing a second heat treatment for a short time at a temperature of 0 ° C. to about 1050 ° C., a step (g) of forming a sidewall on a side surface of the gate electrode after the step (f), Impurity ions of the second conductivity type are ion-implanted into the second impurity layer and the third impurity layer using the gate electrode and the sidewalls as masks to form the second impurity layer and the third impurity layer. A source region and a drain region made of a fourth impurity layer of the second conductivity type are formed in regions on both sides of the gate electrode, and the second impurity is provided inside each upper region of the source region or the drain region. A second conductivity type extension region formed of a layer, and a first conductivity type pocket region formed of the third impurity layer inside each lower region of the source region or the drain region. Method of manufacturing a semiconductor device characterized in that it comprises a step (h) forming. 6. A step (a) of implanting impurity ions of the first conductivity type into a surface portion of a semiconductor substrate to form a first impurity layer of the first conductivity type to be a channel region, and the step (a). After step a), a step (b) of forming a gate electrode on the semiconductor substrate via a gate insulating film; and I) using the gate electrode as a mask on the first impurity layer.
By implanting ions of atoms belonging to group V, the first
(C) forming an amorphous layer of the first conductivity type in the upper region of the impurity layer, and implanting impurity ions of the second conductivity type into the amorphous layer using the gate electrode as a mask, A step (d) of forming a second impurity layer of the second conductivity type in the amorphous layer, and forming an insulating film over the entire surface of the semiconductor substrate at about 600 ° C.
Deposited at a temperature of about 850 ° C., inside the second impurity layer in the upper region of the first impurity layer, and having a lower impurity concentration than the first impurity layer, a first conductivity type low concentration A step (e) of forming a channel region, and a step (f) of anisotropically etching the insulating film to form a sidewall on a side surface of the gate electrode.
And second-conductivity-type impurity ions are ion-implanted into the second impurity layer and the first impurity layer using the gate electrode and the sidewalls as a mask, and the second impurity layer and the first impurity layer. A source region and a drain region made of a third impurity layer of the second conductivity type are formed in regions on both sides of the gate electrode in the lower region of the impurity layer, and the upper region of each of the source region and the drain region is formed. A step (g) of forming extension regions of the second conductivity type made of the second impurity layer inside, and a step of removing the sidewalls after the step (g), and then forming a second impurity layer on the first impurity layer. Indium ions are ion-implanted using the gate electrode as a mask, and each of the source region and the drain region is formed in the lower region of the first impurity layer. Method of manufacturing a semiconductor device characterized in that it comprises a step (h) forming a pocket region of the first conductivity type inside the range. 7. A first conductivity type first region which becomes a channel region by implanting indium ions into a surface portion of a semiconductor substrate.
Forming an impurity layer of (a), forming a gate electrode on the semiconductor substrate via a gate insulating film after the step (a), and forming a first impurity layer on the first impurity layer. I using the gate electrode as a mask
By implanting ions of atoms belonging to Group V, the first
(C) forming a group IV atom ion-implanted layer in the upper region of the impurity layer, and subjecting the semiconductor substrate to a first heat treatment at a temperature of about 600 ° C. to about 850 ° C. for a long time, Forming a low-concentration first-conductivity-type impurity layer having a lower concentration of activating impurities than the first impurity layer in the upper region of the group IV atom ion-implanted layer and the first impurity layer (d). And, after the step (d), indium ions are ion-implanted into the first impurity layer using the gate electrode as a mask, and a second region of the first conductivity type is formed in a lower region of the first impurity layer.
Step (e) of forming an impurity layer of, and after the step (e), second conductivity type impurity ions are ion-implanted into the low-concentration impurity layer and the second impurity layer using the gate electrode as a mask. Then, a third impurity layer of the second conductivity type is formed in an upper region of the low-concentration impurity layer and the second impurity layer, and a low-concentration impurity layer formed of the low-concentration impurity layer is formed inside the third impurity layer. A step (f) of forming a concentration channel region, and after the step (f), about 95
A step (g) of performing a second heat treatment for a short time at a temperature of 0 ° C. to about 1050 ° C., a step (h) of forming a sidewall on a side surface of the gate electrode after the step (g), Impurity ions of the second conductivity type are ion-implanted into the third impurity layer and the second impurity layer by using the gate electrode and the sidewall as a mask, and the third impurity layer and the second impurity layer. A source region and a drain region made of a fourth impurity layer of a second conductivity type are formed in regions on both sides of the gate electrode, and the third impurity is formed inside each upper region of the source region or the drain region. A second conductivity type extension region formed of a layer, and a first conductivity type pocket region formed of the second impurity layer inside each lower region of the source region or the drain region. Method of manufacturing a semiconductor device characterized in that it comprises a step (i) to form a.