JP2001007325A - Field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a field-effect transistor which is fast in its operating speed, while ensuring reliability. SOLUTION: A source region 2 and a drain region 3 are formed in the surface of a P-type single-crystal silicon substrate 1 at a prescribed interval. The region 2 is constituted of a heavily-doped diffused layer 2a and a lightly-doped diffused layer 2b, and the region 3 is constituted of a heavily-doped diffused layer 3a and a lightly-doped diffused layer 3b, consisting of an N- layer. A gate electrode 6, consisting of a polysilicon film, is formed on a channel region 4 between the regions 2 and 3 via a gate oxide film 5. The electrode 6 is reduced in resistance by doping P(phosphorus), which is used as an N-type impurity to the electrode 6 and the impurity concentration in an outside end part 6a (the side surface on the outside of the electrode 6 and the upper surface on the outside of the electrode 6) of the electrode 6 is set lower than the impurity concentration in the central part 6b of the electrode 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor such as a MIS transistor.

[0002]

2. Description of the Related Art In recent years, elements have been rapidly miniaturized in order to achieve high integration and high speed of LSI (Large Scale Integrated Circuit). In a field effect transistor such as a metal-insulating film (oxide film) -semiconductor field effect transistor (MISFET), the gate length becomes shorter and shorter with the miniaturization of elements, and it is very difficult to process the gate with high accuracy. It's getting harder.

It is effective to shorten the gate length in order to improve the driving capability of the MISFET. However, as described above, since the gate processing has become extremely difficult, the gate electrode and the source / drain are kept as they are. (Hereinafter, referred to as overlap) to increase the effective gate length (the length between the source and the drain). Also, as the thickness of the gate insulating film becomes thinner, it becomes difficult to secure the reliability of hot carriers and the like, and the overlap tends to be increased from the viewpoint of ensuring the reliability.

However, if the overlap is increased, the capacitance between the gate and the source / drain (hereinafter referred to as overlap capacitance) increases, which is generally disadvantageous in terms of the operating speed of the MISFET. Therefore, a method of reducing the overlap capacitance by increasing the thickness of the oxide film at the gate end by re-oxidation (gate bird's beak) has been proposed.
For example, it is disclosed in JP-A-7-321309.

[0005]

In the conventional example, there is a problem that the impurity in the channel portion diffuses at the time of re-oxidation, and it becomes difficult to control the threshold voltage (Vt) of the short channel MISFET. In addition, it is difficult to control the thickness of the oxide film by re-oxidation. For example, the amount of gate bird's beak varies and the overlap capacitance varies,
(Lightly Doped Drain) formation has a problem that the ion implantation amount varies.

An object of the present invention is to provide a field-effect transistor having a high operating speed while ensuring reliability.

[0007]

The field effect transistor according to the first aspect of the present invention comprises a first conductivity type and a second conductivity type formed on a semiconductor substrate or a semiconductor layer at predetermined intervals. An impurity region, a gate insulating film formed on a channel region between the first and second impurity regions, and a gate electrode made of a semiconductor formed on the gate insulating film. The resistance is reduced by including the impurity, and the end overlaps with at least one of the first and second impurity regions, and the impurity concentration at the end of the overlapping gate electrode is: The gist is that the concentration is lower than the impurity concentration in the central part.

In this way, even if the amount of overlap between the gate electrode and the first or second impurity region is increased, the impurity concentration at the end of the gate electrode is low. The overlap capacity with the area is small.

Further, the gate electrode into which the impurities are introduced,
Since the concentration at the central portion (the portion in contact with the central portion and the channel region) remains sufficiently high, depletion of the gate electrode can be prevented.

In the above-mentioned field effect transistor, the first and second impurity regions are extended toward the channel region, respectively, and are of one conductivity type having a lower concentration than the first and second impurity regions. It is desirable to further include first and second low concentration impurity regions. LD like this
By providing a D (Lightly Doped Drain) structure, when a voltage is applied between the first or second low-concentration impurity regions,
The first or second low-concentration impurity region having a relatively high resistance value suppresses a sharp increase in the electric field generated near the end of the first or second low-concentration impurity region. Further, in addition to the low impurity concentration at the end of the gate electrode, the presence of the first or second low-concentration impurity region further increases the overlap capacitance between the gate electrode and the first or second impurity region. Become smaller.

In the above-mentioned field effect transistor, the region having a low impurity concentration in the gate electrode may be:
It is preferable that the gate electrode into which the impurity is introduced is subjected to a heat treatment so that the impurity introduced at the end of the gate electrode is diffused outward.

This makes it possible to easily realize the gate electrode structure without increasing the number of steps.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described with reference to the drawings. FIG. 1 shows an LD according to the present embodiment.
N-channel MOSF with D (Lightly Doped Drain) structure
FIG. 2 is a schematic cross-sectional view illustrating a structure of an ET.

In FIG. 1, a p-type single crystal silicon substrate 1
The source region 2 and the drain region 3 are formed at predetermined intervals on the surface of the substrate. Note that the silicon substrate 1 corresponds to a “semiconductor substrate” in the present invention, and the source region 2 and the drain region 3 correspond to “first and second impurity regions” in the present invention.

The region of the silicon substrate 1 between the source region 2 and the drain region 3 becomes the channel region 4. The source region 2 includes a high-concentration diffusion layer 2a formed of an n ⁺ layer and a low-concentration diffusion layer 2b formed of an n ⁻ layer on the channel region 4 side. The drain region 3 includes a high-concentration diffusion layer 3a formed of an n ⁺ layer and a low-concentration diffusion layer 3b formed of an n ⁻ layer on the channel region 4 side. P (phosphorus) is used as the n-type impurity.

A gate electrode 6 made of polysilicon (polycrystalline silicon) is formed on channel region 4 via a gate oxide film 5 made of silicon oxide. The resistance of the gate electrode 6 is reduced by doping P (phosphorus) as an n-type impurity, and the impurity concentration of the outer end 6a (side surface and upper surface) becomes lower than the impurity concentration of the central portion 6b. ing. The outer end of the gate electrode 6 mainly overlaps with the source region 2 and the drain region 3. Thus, the MOSFET 7 including the source region 2, the drain region 3, the channel region 4, the gate oxide film 5, and the gate electrode 6 is formed on the silicon substrate 1.

On both sides of the gate electrode 6, spacers 8 made of silicon oxide are formed. The end of the spacer 8 is self-aligned with the high concentration diffusion layers 2a and 3a. The MOSFET 7 and the spacer 8 are covered with an interlayer insulating film 9 made of a silicon oxide film.
The source electrode 1 is connected to the source region 2 and the drain region 3 through a contact hole 10 formed in
1 and the drain electrode 12 are connected.

Next, the n-channel MOSFET 7 shown in FIG.
1 will be described with reference to FIGS.

Step 1 (see FIG. 2): A film 1 made of SiO ₂ is formed on an n-type single crystal silicon substrate 1 by a thermal oxidation method.
A gate oxide film 5 of 10 to 10 nm is formed, and further thereon,
A doped polysilicon film 20 having a thickness of 50 to 300 nm is formed using a CVD method.

Here, there are the following methods for forming the doped polysilicon film 20.

Method 1: When a polysilicon film is formed by using the LPCVD method, a gas containing impurities is mixed into a source gas.

Method 2: After forming a non-doped polysilicon film by using the LPCVD method, an impurity diffusion source layer (such as POCl ₃ ) is formed on the polysilicon film, and an impurity is diffused from the impurity diffusion source layer to the polysilicon film. To spread.

Method 3: After forming a non-doped polysilicon film by LPCVD, impurity ions are implanted by ion implantation.

In this embodiment, the doped polysilicon film
Using P (phosphorus) as an impurity to dope
Impurity concentration in the polysilicon film 20 is 1 × 10¹⁸
cm ^-3~ 1 × 10^{twenty two}cm^-3It is set to be.

Next, Si (silicon) ions are implanted into the doped pre-silicon film 20 by using an ion implantation method. The injection condition at this time is acceleration energy;
eV to 40 keV, dose amount: 1 × 10 ¹⁴ cm ⁻² to 1 ×
10 ¹⁶ cm ^-2 . As a result, the doped polysilicon film 20 becomes amorphous and becomes an amorphous silicon film 20a.

Step 2 (see FIG. 3): amorphous silicon film 2
0a, a resist pattern (not shown) is formed,
The gate electrode 6 made of the amorphous silicon film 20a is processed by etching the amorphous silicon film 20a using the resist pattern as a mask.

Next, using the resist pattern as a mask,
On the surface of the silicon substrate 1 on both sides of the gate electrode 6,
By implanting P ions, low-concentration diffusion layers 2b and 3b that become part of n-type source region 2 and drain region 3 are formed, respectively. The ion implantation conditions at this time are: acceleration energy; 0.1 keV to 30 keV, dose amount: 1 ×
It is 10 ¹³ cm ^-2 1 × 10 ¹⁶ cm ^-2 . Low concentration diffusion layer 2
The region between b and 3b (between the source region 2 and the drain region 3) becomes the channel region 4.

In this case, after removing the resist pattern, ion implantation may be performed using the gate electrode 6 as a mask. By doing so, the impurity concentration of the gate electrode 6 can be increased.

Next, by performing a heat treatment using the RTA method, the gate electrode 6 is again polycrystallized and the impurities in the low concentration diffusion layers 2b and 3b are activated. The heat treatment is performed in an N ₂ atmosphere or a mixed atmosphere of N ₂ and O ₂ .
Temperature: 800 ° C. to 1200 ° C., Time: 0.1 second to 30 seconds. As a result, the ends of the low concentration diffusion layers 2 b and 3 b overlap the ends of the gate electrode 6.
Further, at this time, since the upper surface and the side surface of the gate electrode 6 are not in contact with other members, impurities at the outer end 6a (the upper surface and the side surface) of the gate electrode 6 diffuse outward. Therefore, the impurity concentration at the outer end 6a is lower than the impurity concentration at the center 6b of the gate electrode 6.

Step 3 (see FIG. 4): The entire surface of the silicon substrate 1 is formed by CVD to a thickness of 50 to 250 nm.
A spacer 8 is formed on each side surface of the gate electrode 6 by forming an iO ₂ film and further performing anisotropic overall etching.

Next, using the spacer 8 as a mask,
P is ionized on the surface of the silicon substrate 1 on both sides of the
The n-type source region 2 and the drain
The high-concentration diffusion layers 2a and 3a, which are a part of the region 3,
Form. The ion implantation conditions at this time are the acceleration energy
-; 5 keV to 50 keV, dose amount: 1 × 10¹⁴cm
^-2~ 1 × 10¹⁷cm^-2It is.

Next, heat treatment using the RTA method or an electric furnace is performed to activate the impurities in the high concentration diffusion layers 2a and 3a. The conditions of the heat treatment are N ₂ atmosphere or N ₂ and O
_In a mixed atmosphere with ₂ , temperature: 800 ° C to 1200 ° C,
Time: 5 seconds to 60 minutes. At this time, the gate electrode 6
Since the crystal has already been crystallized in Step 2, the impurities of the gate electrode 6 are unlikely to diffuse outward. Thus, MOSFE
Complete T7.

Step 6 (see FIG. 1): An interlayer insulating film 9 made of SiO ₂ is formed on the entire surface of the silicon substrate 1 by using the CVD method, and the interlayer insulating film 9 on the source region 2 and the drain region 3 is formed. Then, a contact hole 10 is formed, and a source electrode 11 and a drain electrode 12 made of Al (aluminum) are formed in the contact hole 10, respectively.

As described above, this embodiment has the following functions and effects.

(1) Source region 2 (low concentration diffusion layer 2b)
Since the impurity concentration at the outer end 6a of the gate electrode 6 overlapping with the drain region 3 (low-concentration diffusion layer 3b) is low, the overlap capacitance at this portion is reduced. As a result, the operation speed of the MOSFET 7 can be increased.

FIG. 5 shows a MOSFET 7 of the present embodiment and a conventional example (in which the impurity concentration of the gate electrode is uniform in all regions).
, The overlap capacitance of the gate electrode 6 with the source region 2 and the drain region 3 and the saturation current value (I
_(sat ) and the result of measuring the operating frequency.

As shown in the figure, the MOSFET 7 of this embodiment has an overlap capacitance of about 25 times that of the conventional example.
It can be seen that the operating frequency can be increased by suppressing the decrease in the saturation current value and the transistor operation can be speeded up.

(2) Since the concentration of the central portion 6b of the gate electrode 6 (the portion in contact with the central portion and the channel region 4) does not decrease, depletion of the gate electrode can be prevented. As a result, the driving capability (saturation current value) of the MOSFET 7 does not decrease.

The above embodiment can be modified as follows, and even in such a case, the same operation and effect can be obtained.

(A) In the above embodiment, the impurity concentration of the outer end 6a (upper surface and side surface) of the gate electrode 6 is set low. However, it is not necessary to lower the impurity concentration of the entire outer end 6a. It suffices that the impurity concentration at least at the portion facing the source region 2 and the drain region 3 is set low. Therefore, the “end portion of the gate electrode” in the present invention
The term “corresponds to” means a portion facing the source region or the drain region 3 at the outer end 6a, not at the entire outer end 6a.

(B) Instead of P as an n-type impurity, A
s (arsenic), N (nitrogen), Sb (antimony), Bi
(Bismuth) or the like is used.

(C) By changing the conductivity type of the p-type single crystal silicon substrate 1 to n-type and changing the conductivity type of the n-type impurities forming the source region 2 and the drain region 3 to p-type, MOSFET 7 is a p-channel MO
Replace with SFET. In this case, as a p-type impurity,
B (boron), In (indium), Ga (gallium)
And so on.

(D) The conductivity type of the gate electrode 6 is p-type. In this case, B, In, Ga, or the like is used as the p-type impurity.

(E) As (arsenic), Ar (argon), P (phosphorus), G
e (germanium), Kr (krypton), Xe (xenon) or the like is used.

(F) In step 1, when an impurity (P) is introduced into the polysilicon film by using the ion implantation method, the amount of the impurity is set to a value sufficient to make the polysilicon film amorphous. As a result, doping of the polysilicon film with impurities and amorphization of the polysilicon film are simultaneously performed.

(G) The ion implantation is performed from an oblique direction. By doing so, channeling in ion implantation can be suppressed and the outer end 6 of the gate electrode 6 can be formed.
a can be mainly made amorphous.

(H) In the above embodiment, the M of the LDD structure
Although an OSFET has been described as an example, a normal MOSFET having no LDD structure and a MOSF having a raised source / drain structure in which source / drain regions are formed on a silicon substrate are described.
It may be applied to ET.

(Iii) The single crystal silicon substrate 1 is replaced with a single crystal silicon film, a polycrystalline (poly) silicon film, and an amorphous silicon film.

(V) The single crystal silicon film 1 is replaced with a substrate or a film of various compound semiconductors (GaAs, SiC, GaN, etc.).

(G) The present invention is applied to a MISFET by replacing the gate oxide film 5 with an appropriate insulating film (nitride film, alumina, etc.) other than the oxide film.

[0051]

According to the present invention, by reducing the overlap capacitance between the gate and the source or the drain, it is possible to provide a field effect transistor having a high operating speed while ensuring reliability. .

[Brief description of the drawings]

FIG. 1 shows an n-channel type MO according to an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view illustrating a structure of an SFET.

FIG. 2 is a process sectional view illustrating the method for manufacturing the MOSFET of FIG.

FIG. 3 is a process sectional view illustrating the method for manufacturing the MOSFET of FIG.

FIG. 4 is a process sectional view illustrating the method of manufacturing the MOSFET in FIG. 1;

FIG. 5 is a characteristic diagram for explaining an effect of the MOSFET of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type single crystal silicon substrate 2 Source region 2a High concentration diffusion layer 2b Low concentration diffusion layer 3 Drain region 3a High concentration diffusion layer 3b Low concentration diffusion layer 4 Channel region 5 Gate oxide film 6 Gate electrode 6a Central part of gate electrode 6b Outer end of gate electrode 7 MOSFET 8 Spacer

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Shuji Fujiwara 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Toru Dan 2-chome Keihanhondori, Moriguchi-shi, Osaka No.5-5 Sanyo Electric Co., Ltd. F term (reference) 4M104 AA01 AA03 AA04 AA08 BB01 BB02 BB40 CC05 DD43 DD55 DD63 DD80 DD81 DD83 DD89 FF21 GG09 HH20 5F040 DA01 DA11 DC01 DC02 DC03 EC05 EC07 ED03 ED04 EF02 EF03 FA03 FA19 FB02 FB04 FC14 FC15

Claims (3)

[Claims] A first conductivity type first and second impurity region formed at a predetermined interval in a semiconductor substrate or a semiconductor layer; and a channel region formed between the first and second impurity regions. A gate insulating film, and a gate electrode made of a semiconductor formed on the gate insulating film. The gate electrode has low resistance by containing an impurity, and ends thereof are the first and second ends. Wherein the impurity concentration at the end of the gate electrode overlapping with at least one of the impurity regions is lower than the impurity concentration at the center. 2. The semiconductor device according to claim 1, wherein the first and second impurity regions extend toward the channel region, respectively.
2. The field effect transistor according to claim 1, further comprising first and second low-concentration impurity regions of one conductivity type having a lower concentration than the impurity region of (a). 3. A region having a low impurity concentration in the gate electrode, wherein an amorphous state of the gate electrode into which the impurity is introduced is heat-treated to diffuse the impurity introduced into the end of the gate electrode outward. The field effect transistor according to claim 1, wherein the field effect transistor is formed by: