JP3535296B2 - Read-only memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read-only memory capable of performing a stable read operation even at a low power supply voltage operation.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a configuration of a core portion of a conventional read-only memory (hereinafter referred to as ROM).

The ROM shown in FIG. 4 is a NOR type having a 4-bit 2-column structure, and an N-channel FET (field effect transistor) N1 whose gate terminals are connected to corresponding word lines WL0 to WL3 to form cells. Is the bit line BL
Data is fixedly stored depending on whether it is formed by being connected between 0 and BL1 and the ground potential. Bit line B
L0 and BL1 are column selection signals C0 and C at their gate terminals.
1 is given to each corresponding N-channel FET N
The storage data connected to the common data output line DO via C0 and NC1 and read from the cell to the bit lines BL0 and BL1 are read to the data output line DO via the FETs NC0 and NC1 and the data output line DO. The stored data read out to the output terminal OUT via the sense inverter 1.
Is output to.

The data output line DO has a clock signal (CL
P-channel FET for precharging whose conduction is controlled by a clock inversion signal (CLK bar) which is the inverse of K).
The bit lines BL0, B pre-charged to the power supply voltage (VDD) by P1 and selected and the storage data is read
L1 is (power supply voltage-Vthn) (Vthn is FETNC0, NC via FETP1 and FETNC0, NC1)
Precharged to a voltage of 1).

The column selection signals C0 and C1 are the addresses A
The word selection signals W0 to W generated by the circuit having the configuration shown in FIG. 5, which receives 0, and selects the word lines WL0 to WL3.
3 is generated as shown in the truth value of FIG. 7 by the configuration of the configuration shown in FIG. 6 which is synchronized with the clock signal with the addresses A1 and A2 as inputs.

In such a structure, as shown in the timing chart of FIG. 8, the rising edge of the clock signal causes the FET P1 to become conductive, the data output line DO is precharged to the power supply voltage, and the addresses A0 to A2 are set.
The input makes the FET NC0 or NC1 conductive, and the bit line BL0 or BL from which the stored data is read out.
1 is selected, and the selected bit line BL1 or BL2 is precharged to the voltage of (power supply voltage −Vthn) via the FET NC0 or NC1 in the conductive state.

In such a state, when the clock signal falls, the precharge FET P1 becomes non-conductive, the word selection signals W0 to W3 are selectively selected, and the selected word lines WL0 to WL3 are connected. When a cell is formed between the selected bit line BL0 or BL1 and the potential of the bit line BL0 or BL1 becomes the ground potential, high level data is output to the output terminal OUT,
When no cell is formed between the selected word line WL0 to WL3 and the selected bit line BL0 or BL1, the potential of the bit line BL0 or BL1 is held at the precharge voltage and low level data is stored. Output terminal OU
The data is output to T and the read operation of the stored data is performed.

As described above, in the ROM shown in FIG. 4, the bit lines BL0 and BL1 are supplied with the power supply voltage by setting the precharge voltage of the bit lines BL0 and BL1 to a voltage lower than the power supply voltage (power supply voltage −Vthn). Compared with the case of precharging to, the speed of lowering the bit lines BL0 and BL1 from the high level to the ground potential is increased to speed up the reading of stored data, and the power consumption during precharge is reduced. .

However, by setting the precharge voltage of the bit lines BL0 and BL1 to be lower than the power supply voltage, noise is generated in the FETs NC0 and NC1 during data output.
Of the FET NC0 or N in the conductive state by adding to the gate terminal of
FETNC in which the gate potential of C1 is temporarily higher than (power supply voltage + Vthn) or noise is non-conducting
0 or NC1 added to the gate terminal of FET NC0 or C
1 becomes a conductive state temporarily, the output line DO of the power supply voltage
Current flows to the bit line BL0 or BL1 via the conductive FET NC0 or NC1, and the potential of the data output line DO changes from the power supply voltage to the precharge voltage (power supply voltage −Vthn) of the bit line BL0 or BL1 or a value close thereto. Will be lowered. In such a case, the sense inverter 1 designed to detect the change of the input from the high level to the low level with high sensitivity detects the voltage drop of the data output line DO and outputs the incorrect data. There was a risk of it.

Such a problem becomes remarkable as the power supply voltage of the memory becomes lower, and as the threshold value of the FET becomes higher or the bit line BL.
This was remarkable when the capacitance of 0 and BL1 was larger than the capacitance of the data output line DO.

[0011]

As described above,
In a conventional ROM in which the bit line is precharged to a voltage lower than the precharge voltage of the data output line, it is advantageous in terms of the read speed of stored data and power consumption, but on the other hand, when it is operated at a low power supply voltage. There is a risk of malfunction, resulting in reduced reliability.

Therefore, the present invention has been made in view of the above, and an object thereof is to provide a read-only memory capable of preventing malfunction in low power supply voltage operation.

[0013]

In order to achieve the above object, the invention according to claim 1 is of a first conductivity type in which conduction is controlled by a bit line from which stored data is read and a bit line selection signal. An FET (field effect transistor) and a second conductivity type FET are connected in parallel, a transfer gate, a data output line connected to the bit line through the transfer gate, and a power supply voltage of the memory not more than a predetermined voltage. In the case where the power supply voltage is lowered, a detection circuit that detects a decrease in the power supply voltage, a detection result of the detection circuit, and a bit line selection signal are received, and the detection circuit detects that the power supply voltage has dropped to a predetermined voltage or less. In this case, the second conductivity type FET of the transfer gate is controlled to conduct in the same manner as the first conductivity type FET, and the power supply voltage is set to a predetermined voltage by the detection circuit. If the can drops down not detected, the second conductivity type FET of the transfer gate
Is connected to the data output line and the data output line is precharged to a power supply voltage, and the detection circuit detects that the power supply voltage has dropped below a predetermined voltage. In this case, the bit line is precharged to the power supply voltage via the transfer gate, and if the detection circuit does not detect that the power supply voltage has dropped to a predetermined voltage or lower, It is configured to have a precharge FET for precharging the bit line to a voltage lower than the power supply voltage via a conductive type FET.

According to a second aspect of the present invention, the bit line from which the stored data is read, the FET of the first conductivity type whose conduction is controlled by a bit line selection signal, and the FET of the first conductivity type are provided. A data output line connected to the bit line; a detection circuit for detecting a decrease in the power supply voltage when the memory power supply voltage is operated at a predetermined voltage or lower; and a data output line connected to the data output line. A first precharge to a power supply voltage and a precharge of the bit line to a voltage lower than the power supply voltage via the first conductivity type FET
Precharge FET and second precharge FET using the precharge voltage of the bit line as a power supply voltage
When the detection circuit detects that the power supply voltage has dropped to a predetermined voltage or less in response to the detection result of the detection circuit and the bit line selection signal, the second line is precharged when the bit line is precharged. When the FET for precharging is controlled to be conductive and the detection circuit does not detect that the power supply voltage has dropped to a predetermined voltage or less, the second precharging F at the time of precharging the bit line.
It is configured to have a control gate formed by controlling ET in a non-conducting state.

According to a third aspect of the present invention, the bit line from which the stored data is read, the N-channel FET whose conduction is controlled by the bit-line selection signal, and the N-channel FET are connected to the bit line. And a detection circuit that detects a decrease in the power supply voltage when the memory power supply voltage is operated below a predetermined voltage, and the detection result and the bit line selection signal from the detection circuit When the circuit detects that the power supply voltage has dropped below a predetermined voltage, the gate voltage of the sum of the power supply voltage and the threshold voltage is supplied to the gate terminal of the N-channel FET at the time of precharging the bit line. However, when the detection circuit does not detect that the power supply voltage has dropped to a predetermined voltage or less, the F-channel of the N channel is precharged when the bit line is precharged. A booster circuit for supplying a gate voltage of a power supply voltage to the gate terminal of T and a data output line are connected, the data output line is precharged to the power supply voltage, and the detection circuit lowers the power supply voltage to a predetermined voltage or less. If it is detected that the bit line is precharged to the power supply voltage through the N-channel FET, and the detection circuit does not detect that the power supply voltage has dropped to a predetermined voltage or lower, The precharge FET is configured to precharge the bit line to a voltage lower than the power supply voltage via the N-channel FET.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the structure of a read-only memory according to an embodiment of the invention described in claim 1.

In FIG. 1, a characteristic of the read-only memory is that a P-channel FET and an N-channel FET are used instead of the N-channel FETs NC0 and NC1 forming the core portion of the read-only memory shown in FIG. Bit line BL via transfer gates T0, T1
0, BL1 and the data output line DO are connected to each other, and a low voltage detection circuit 2 for detecting a decrease in the power supply voltage when the memory is used by decreasing the power supply voltage is provided.
The N-channel FETs forming 0 and T1 are conductively controlled by corresponding column selection signals C0 and C1, respectively, and the P-channel FETs forming the transfer gate T0 are detected by the column selection signal C0 and the low voltage detection circuit 2. NAND gate which is controlled by the output of a NAND (NAND) gate G0 which receives as input, and which is a P-channel FET which constitutes the transfer gate T1 and which receives as input the column selection signal C1 and the detection result of the low voltage detection circuit 2. Since the conduction is controlled by the output of G1, other configurations are the same as those shown in FIG.

In such a structure, when the power supply voltage of the memory is used at a voltage during normal use, for example, a power supply voltage of about 5 V, the low voltage detection circuit 2 does not detect the decrease of the power supply voltage and detects the low voltage. The circuit 2 outputs a low level. In such a case, the P-channel FETs of the transfer gates T0 and T1 become non-conducting regardless of the selection of the column selection signals C0 and C1, and like the configuration shown in FIG.
The bit lines BL0 and BL1 are precharged to a voltage lower than the power supply voltage via the N-channel FETs of the transfer gates T0 and T1, and the same effect as the memory shown in FIG. 4 can be obtained in terms of read speed and power consumption. it can.

On the other hand, when the memory is used with its power supply voltage lowered, for example, the power supply voltage during normal use is approximately 70%.
When the memory is used at a power supply voltage of about% or less, for example, about 3.3V, the low voltage detection circuit 2 detects a decrease in the power supply voltage and outputs a high level as a detection result. As a result, the output of the NAND gate G0 or G1 selected and supplied with the high level column selection signal C0 or C1 becomes low level, and the transfer gate T0 or T on the side to which the selected column selection signal C0 or C1 is supplied.
Both FETs 1 are in a conductive state. Therefore, the bit line BL0 or BL1 is connected to the data output line D from the precharge FET P1 via the transfer gate T0 or T1.
It is precharged to the same power supply voltage as O. Therefore, when the memory is operated with a low power supply voltage, a current flows from the data output line DO to the bit lines BL0 and BL1 as in the conventional case, the potential of the data output line DO is lowered, and erroneous data is output. That will disappear.

FIG. 2 is a diagram showing the structure of a read-only memory according to an embodiment of the present invention.

The feature of the embodiment shown in FIG. 2 is that, compared with the configuration shown in FIG. 1, N-channel FETs NC0, N are used instead of the transfer gates T0, T1 shown in FIG.
Bit lines BL0, BL1 and data output line D via C1
Connect O and connect bit lines BL0 and BL1 to power supply (VDD)
Between P-channel FETs P2 and P for precharging
Channel FETP3 is connected in series, NAND gate G
The FETP2 is controlled to be conductive by the output signals of 0 and G1, the FETP3 is controlled to be conductive by the inverted signal (CLK bar) of the clock signal, and the FETP1 for precharging is operated at the time of low power supply voltage operation.
Through the FETs NC0, NC1 to the bit line BL0,
When precharging BL1, the FETs P2 and P3 are rendered conductive so that the precharge voltage of the bit lines BL0 and BL1 is used as the power supply voltage, and other configurations are similar to those shown in FIG. .

With such a structure, the same effect as that of the embodiment shown in FIG. 1 can be achieved.

FIG. 3 is a diagram showing the structure of a read-only memory according to an embodiment of the present invention.

The feature of the embodiment shown in FIG. 3 is that a low voltage detection circuit 2 similar to the embodiment shown in FIGS. 1 and 2 is provided as compared with the configuration shown in FIG. , C1 and the detection result of the low voltage detection circuit 2 as an input, the bit lines BL0, BL
FETNC0, NC1 connecting 1 and the data output line DO
The gate terminal of is provided with a booster circuit 3 for supplying a boosted selection signal of (power supply voltage + Vthn) or more, and when precharging the bit lines BL0 and BL1 during low power supply voltage operation,
The gate potentials of the FETs NC0 and NC1 are set to (power supply voltage + Vth
n) above, the precharge voltage of the bit lines BL0 and BL1 is used as the power supply voltage, and other configurations are the same as those shown in FIG.

With such a structure, the same effect as that of the embodiment shown in FIG. 1 can be achieved.

In the above embodiment, the P-channel FET P1 for precharging may be an N-channel FET.

Further, without using the low voltage detection circuit 2, F
When the threshold of ET is high or the capacity of the bit line is larger than the capacity of the data output line, the low voltage detection circuit 2 is previously provided in order to prevent malfunction as in the low power supply voltage operation. Disconnects the output of the low voltage detection circuit 2
Alternatively, the power supply level may be fixedly provided instead of the output.

Alternatively, when the precharge voltage of the bit line is always used as the power supply voltage for each product, the output of the low voltage detection circuit 2 is disconnected in advance, and the ground level is fixed instead of the output of the low voltage detection circuit 2. You may give it. Such a change can be easily implemented in the wiring process in the memory manufacturing process.

Further, in the embodiment shown in FIG. 3, when the column selection signals C0 and C1 are generated by the circuit having the configuration shown in FIG. 5, the address A0 shown in FIG. A booster circuit may be provided and the power supply voltage of the inverter circuit shown in FIG. 5 may be the same boosted voltage as the output of the booster circuit.

[0031]

As described above, according to the present invention, the decrease in the power supply voltage is detected and the precharge voltage of the bit line is set to the same voltage as the precharge voltage of the data output line. Therefore, it is possible to provide a read-only memory that can prevent malfunctions when operating with a low power supply voltage.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a read-only memory according to an embodiment of the invention as set forth in claim 1;

FIG. 2 is a diagram showing a configuration of a read-only memory according to an embodiment of the invention described in claim 2;

FIG. 3 is a diagram showing a configuration of a read-only memory according to an embodiment of the invention as set forth in claim 3;

FIG. 4 is a diagram showing a configuration of a conventional read-only memory.

5 is a diagram showing a partial configuration of the memory shown in FIG. 4. FIG.

FIG. 6 is a diagram showing a partial configuration of the memory shown in FIG.

FIG. 7 is a diagram showing truth values of the circuit shown in FIG. 6;

8 is a diagram showing a timing chart of the memory shown in FIG.

[Explanation of symbols]

1 sense inverter 2 Low voltage detection circuit 3 Booster circuit P1, P2, P3 P channel FET N1, NC0, NC1 N channel FET T0, T1 transfer gate G0, G1 NAND gate WL0 to WL3 word lines BL0, BL1 bit line DO data output line

Front page continuation (72) Inventor Tsuneaki Kudo 25-1 Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics Stock Company In-house (72) Inventor Kojiro Murayama 25-1 Ekimaehonmachi, Kawasaki-ku, Kawasaki, Kanagawa Toshiba Microelectronics Stock Society In-house (72) Inventor Masao Kumaki 25-1 Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics Stock Association In-house (56) Reference JP-A-2-179997 (JP, A) JP-A-5-62490 ( JP, A) JP 7-141890 (JP, A) JP 6-119793 (JP, A) JP 4-48492 (JP, A) JP 7-254288 (JP, A) JP Flat 7-130189 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 17/00-17/18 G11C 16/00-16/34

Claims (3)

(57) [Claims] 1. A bit line from which stored data is read, and a first conductivity type F whose conduction is controlled by a bit line selection signal.
A transfer gate in which an ET (Field Effect Transistor) and a second conductivity type FET are connected in parallel, a data output line connected to the bit line through the transfer gate, and a power supply voltage of the memory of a predetermined voltage or less. A detection circuit that detects a decrease in the power supply voltage when operating with, and a detection result of the detection circuit and a bit line selection signal,
When the detection circuit detects that the power supply voltage has dropped to a predetermined voltage or less, the second conductivity type FET of the transfer gate is conduction-controlled in the same manner as the first conductivity type FET, and the detection circuit detects When it is not detected that the power supply voltage has dropped to a predetermined voltage or less, the transfer gate is connected to a control gate configured to control the second conductivity type FET of the transfer gate to be in a non-conduction state, and When the data output line is precharged to the power supply voltage and the detection circuit detects that the power supply voltage has dropped below a predetermined voltage,
When the bit line is precharged to the power supply voltage via the transfer gate and the detection circuit does not detect that the power supply voltage has dropped to a predetermined voltage or lower, the first conductivity type FET of the transfer gate is turned on. A read-only memory, comprising: a precharge FET for precharging the bit line to a voltage lower than a power supply voltage via the via. 2. A bit line from which stored data is read, and a first conductivity type F whose conduction is controlled by a bit line selection signal.
ET, a data output line connected to the bit line via the first conductivity type FET, and a detection circuit for detecting a decrease in the power supply voltage when the power supply voltage of the memory is operated below a predetermined voltage. For a first precharge connected to the data output line, precharging the data output line to a power supply voltage, and precharging the bit line to a voltage lower than the power supply voltage via the FET of the first conductivity type A second FET that uses a precharge voltage of the bit line as a power supply voltage
Receiving a detection result of the detection circuit and a bit line selection signal,
When the detection circuit detects that the power supply voltage has dropped to a predetermined voltage or lower, the second precharge FET is controlled to be conductive when the bit line is precharged, and the detection circuit supplies the power supply voltage. Is not detected to be lower than a predetermined voltage, the second precharge FET is precharged at the time of precharging the bit line.
A read-only memory having a control gate configured to control a non-conducting state. 3. A bit line from which stored data is read, and an N-channel F whose conduction is controlled by a bit line selection signal.
ET, a data output line connected to the bit line through the N-channel FET, a detection circuit that detects a decrease in the power supply voltage when the memory power supply voltage is operated at a predetermined voltage or less, and Upon receiving the detection result of the detection circuit and the bit line selection signal,
When the detection circuit detects that the power supply voltage has dropped to a predetermined voltage or less, the gate voltage of the sum of the power supply voltage and the threshold voltage is applied to the gate terminal of the N-channel FET at the time of precharging the bit line. And when the detection circuit does not detect that the power supply voltage has dropped to a predetermined voltage or less, the gate voltage of the power supply voltage is supplied to the gate terminal of the N-channel FET at the time of precharging the bit line. When a booster circuit is connected to the data output line, the data output line is precharged to a power supply voltage, and the detection circuit detects that the power supply voltage has dropped below a predetermined voltage,
The bit line is precharged to the power supply voltage via the N-channel FET, and if the detection circuit does not detect that the power supply voltage has dropped to a predetermined voltage or less, the bit is supplied via the N-channel FET. F for precharge that precharges the line to a voltage lower than the power supply voltage
A read-only memory having ET.