JP3518310B2 - Capacitive load drive circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a capacitive load, and more particularly to a drive circuit for a flat panel display such as a plasma display panel.

[0002]

2. Description of the Related Art A conventional flat panel display driving circuit as shown in FIG . 4 is a level shift circuit for converting a low amplitude level signal of, for example, 3 to 5 V into a high amplitude level of, for example, 50 V to 200 V. If, based on the output of the level shift circuit, and a high voltage output circuit for applying a high voltage to the display. this
Prior art panel display driving circuit as is described in JP-A-5-249916. Conventional shown in FIG.
In the driving circuit technology, P-channel type MOS field effect transistor (hereinafter, referred to as P-MOSFET) and N-channel type MOS field effect transistor (hereinafter, referred to as N-MOSFET) and a driver circuit including a complementary MOS transistor Equipment
I am . The driving of this circuit will be described below.

When the input signal IN is at a high level (for example, 5V), N-MOSFET.MN1 is off, N-MOSFET.MN2 is on,
N-MOSFET.MN3 is turned off. Also, P-MOSFET.MP1 is turned on, P-MOSFET.MP2 is turned off, and P-MOSFET.MP3 is turned on.
At this time, the output signal OUT rises to the high potential side power supply HV. Further, the voltage of the high potential side power source HV is applied to the gate electrode of the P-MOSFET.MP2.

When the input signal IN is at the GND level, NM
OSFET.MN1 is on, N-MOSFET.MN2 is off, N-MOSFET.MN
3 is turned on. In addition, P-MOSFET.MP1 is off, P-MOSFE
T.MP2 turns on and P-MOSFET.MP3 turns off. Therefore, the output signal OUT becomes the GND level. At this time, P-MOSFET.
MP1 and P-MOSFET. The high potential side power supply H is applied to the gate electrode of MP3.
A voltage of V is applied.

As described above, the operation of this circuit can be summarized as follows: the input signal IN is level-shifted and the high voltage output circuit is
Driving a <br/> panel display by controlling the P-MOSFET.MP3 and N-MOSFET.MN3 tracts.

In a circuit using such complementary MOS transistors, if there is no leakage of the MOS transistors, the current consumption is 0 in terms of direct current and a low power consumption circuit becomes possible. As described above, in order to obtain the complementary circuit, since the voltage of the high-potential side power supply HV is applied to the gate electrode of the P-MOSFET, a P-MOSFET having a high gate breakdown voltage structure that can withstand the voltage is required. Become. The necessary condition for the gate oxide film thickness to have this high gate breakdown voltage structure is, for example, 150 nm to 600 when the high potential side power supply HV is 50 V to 200 V.
It is considered that a gate oxide film thickness of about nm is required.
This means that the gate applied voltage is, for example, 3 to 5 V, and the oxide film thickness is 10 times or more as compared with the N-MOSFET having the gate oxide film thickness of about 15 to 30 nm.

In the circuit using the P-MOSFET having the high breakdown voltage gate structure for the output on the source side, the output current characteristic depends on the power source current on the high potential side. This is because the gate voltage of the source output P-MOSFET is equal to the high potential side power supply HV. Generally, in a display represented by a plasma display panel, there are optimum values for driving voltage / current (driving condition) depending on the panel structure and screen size. Further, even with the same structure and size, it is necessary to set the driving conditions in consideration of manufacturing variations. High gate breakdown voltage
In a drive circuit that uses a P-MOSFET for the source output, the current characteristics depend on the power supply voltage.Therefore, in order to share the drive circuit with a wide variety of panels, the breakdown voltage is specified on the maximum operating voltage side. The current characteristics are specified on the minimum operating voltage side, and if a design satisfying both requirements is made, it will lead to an increase in the chip area in the case of an integrated circuit. Furthermore, the high gate breakdown voltage P-MOSFET has a higher threshold voltage than the N-MOSFET that drives the gate voltage at a low amplitude level.
High on-resistance.

[0008]

In the drive circuit of the prior art as described above, the P-MOSFET .MP3 on the upper side of the high voltage output circuit is
However, the gate has a high gate breakdown voltage structure, and the voltage applied to the gate becomes the high-potential side voltage. Therefore, the driving current capability changes due to the fluctuation of the driving voltage. On the other hand, when the P-MOSFET .MP3 is formed according to the maximum voltage of the fluctuation of the driving voltage, the gate oxide film becomes thick and the driving current capability deteriorates. In order to compensate for this, the size must be increased, and the chip area will increase when the integrated circuit as shown in FIG. 5 is formed . Also,
P-MOSFET .MP3 high gate breakdown voltage structure has low current capability in <br/> voltage region a gate voltage is not low, or an increase in the rise time of the output signal voltage, disabled using LC circuits from the high-potential power supply The power loss becomes large when the power is recovered.
The present invention has been made in consideration of the above points, and realizes standardization of circuit constituent elements, reduction of a chip area of an integrated circuit, and reduction of power consumption.

[0009]

A display driving circuit of the present invention In order to achieve the above object, according to a circuit for driving a load using a voltage drive type semiconductor device, connected to a power supply terminal for applying a power supply, the load
An output terminal for a reference terminal as a reference potential, and a series circuit of the first 1P channel type MOS field effect transistor and the 1N-channel MOS field effect transistor connected to the reference terminal connected to said power supply terminal ,
A series connection circuit of a second P-channel type MOS field effect transistor connected to the power supply terminal and a first semiconductor device having a first main electrode, a second main electrode and an insulated gate electrode, and a first P-channel type MOS A serial connection portion of the field effect transistor and the first N-channel MOS field effect transistor is connected to the gate electrode of the second P-channel MOS field effect transistor, and the second P-channel MOS field effect transistor and the first semiconductor device are connected. Is connected to the insulated gate electrode of the first P-channel MOS field effect transistor , and further has a third main electrode, a fourth main electrode and an insulated gate electrode, and the third main electrode is connected to the power supply terminal. and, in the fourth main electrode connected to said output terminal, said insulated gate electrode is first 2P channel type MO
A second semiconductor device connected in series connecting portion between the S field effect transistor and the first semiconductor device, diodes <br/> over de element connected between the insulated gate electrode and the output terminal of the second semiconductor device e Bei the door, inverted signal of the drive control input signal
The first N-channel type MOS field effect transistor
Input to the insulated gate electrode of the
Input to the insulated gate electrode of the first semiconductor device.

In the capacitive load drive circuit of the present invention, the drive circuit of the present invention described above is formed on the same semiconductor substrate.

[0011] According to the semiconductor circuit, the voltage applied to the insulated gate electrode of the second semiconductor device is a low amplitude level, a second semiconductor device can be driven by the gate voltage of the low amplitude level. As a result, the second high voltage output circuit
The gate oxide film thickness of the semiconductor device can be made thin, and the voltage applied to the gate does not depend on the power supply voltage from the power supply terminal.

That is, even if the drive voltage changes depending on the type of capacitive load, the semiconductor device can have the same gate oxide film thickness and the same capacitive load drive capability .
Can the structure and size of the optimum semiconductor device, FIG is to optimize the chip area. Further, the current capability is higher than that of a semiconductor device having a high gate breakdown voltage structure even when the gate applied voltage is at a low amplitude level, and power loss during switching can be reduced.

[0013]

FIG. 1 shows a panel display driving circuit according to an embodiment of the present invention. The drive circuit includes a level shift circuit 10 for converting a signal with a low amplitude level into a signal with a high amplitude level, and a high voltage output circuit for applying a high voltage to an external load based on the output of the level shift circuit 10. 20 and.

In this embodiment, the level shift circuit 10 and a high voltage output circuit 20 arranged at the subsequent stage of the level shift circuit 10 are coupled to each other, and a MOSFET is applied as a constituent element. The level shift circuit 10 is a series connection circuit of a high gate breakdown voltage P-MOSFET.MP1 having a high-potential power supply HV and a source electrode connected thereto, and a series connection circuit of an N-MOSFET.MN1 having a ground GND and a source electrode connected thereto. High-gate withstand voltage P-MOSFET.MP2 with high-potential power supply HV and source electrode connected, and ground GND
And a series connection circuit of N-MOSFET.MN2 to which the source electrode is connected, and an inverter IN for inverting the input signal IN
And V. The series connection of MOSFET.MP1 and MN1 is connected to the gate electrode of MOSFET.MP2, and MOSFET.M
The series connection point of P2 and MN2 is connected to the gate electrode of MOSFET.MP1. The input signal IN is sent to the MO via the inverter INV.
Directly coupled to the gate electrode of SFET.MP2 and directly
2 gate electrodes.

The high voltage output circuit 20 has a high potential side power source HV.
N-MOSFET.MO1 coupled to the zener diode Z
1 and the ground GND forming the level shift circuit
And MOSFET.MN2 to which the source electrode is connected. Series connection of MOSFET.MP2 and MN2 and MOSFET.M
The gate electrode of O1 is connected to the cathode electrode of the Zener diode, and the source electrode of MOSFET.MO1 is connected to the anode electrode of Zener diode Z1. This connection point serves as an output OUT node of the high voltage output circuit 20, and a load CL such as a panel display is connected to this output node.

When the input signal IN is low level, the MOSFE
T.MN2 is turned off and MOSFET.MN1 is turned on. Also, MOS
Since the drain electrode of FET.MN1 becomes low level, MOSFE
T.MP2 turns on. Since the drain electrode of the MOSFET.MN2 is at the voltage level of the high potential side power supply HV, the MOSFET.MO1 is turned on. Therefore, the output signal OUT rises to the high-potential-side power supply HV level. However, the potential between the gate and drain of MOSFET.MO1 is clamped by the Zener voltage of Zener diode Z1. On the other hand, when the input signal IN is at high level, the MOSFET.MN2 is turned on and the MOSFET.MN1 is turned off. At this time, the drain electrode of MOSFET.MN2 becomes low level, so that MOSFET.MP1 is turned on and MOSFET.MO1 is turned off. Moreover, since MOSFET.MP1 is turned on, MOSFET.MP2 is turned off. Therefore, the output signal OUT is at low level. In this way, the input signal IN having a low amplitude level is changed in level, and the output signal OUT can be controlled from the high voltage output circuit. The level of the input signal IN is not particularly limited, but is 3 to
It is set to 5V. That is, the high level is +3 to +5 with reference to the ground GND, and the low level is the ground GND.

In this embodiment, the number of semiconductor elements included in the drive circuit of the panel display is small, and MOSFET.MO1 included in the high voltage output circuit is an N-channel MOSFET.
Since the gate applied voltage has a low amplitude level, the dependency of the output voltage on the high-potential side power supply voltage is small, the structure and size can be standardized, and the chip size can be optimized by applying it to an integrated circuit. This is more effective for multi-output integrated circuits. Further, since complementary MOSFETs are used, in terms of direct current operation, current consumption is almost equal to 0 and power loss is small.

Next, another embodiment of the present invention is shown in FIG. In the present embodiment, the output signal OUT terminal is connected to the cathode side of the diode D1 and the ground GND terminal is connected to the anode side of the diode D1 in the circuit shown in FIG. In this case, charges can be extracted from the ground GND side to the output signal OUT side. That is, the electric power loss can be reduced by recovering the charges.

Next, another embodiment of the present invention is shown in FIG. In this embodiment, the circuit shown in FIG. 1 is used for P-MOSFET.MP2 and N-MOSF.
Connect the ET.MN2 series connection part with a high gate withstand voltage P-MOSFET.MP3
And a series connection circuit of a P-MOSFET.MP3 connected to the high potential side power source HV and the source electrode and an N-MOSFET.MN3 connected to the ground GND and the source electrode are connected. The connection point is connected to the gate electrode of N-MOSFET.MO1. A resistor R is connected between the connection point and the output terminal OUT. In this case, it is possible to guarantee that the sink-side output and the source-side output are simultaneously turned off.
That is, a high impedance state is possible.

Although the present invention has been specifically described based on the embodiments, it is needless to say that the invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention.

[0021]

As described above, according to the present invention, the panel display drive circuit can be configured with a small number of semiconductor elements and standardized semiconductor elements, and the drive circuit can be optimized.
In the case of a semiconductor integrated circuit, there is an effect that the chip area can be reduced. The current consumption is also extremely low. Further, since the high voltage output circuit is a gate applied voltage drive type semiconductor device having a low amplitude level, the drive current capability is also high.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional display drive circuit.

FIG. 5 is a block diagram of a semiconductor integrated circuit display drive circuit.

[Explanation of symbols]

1, 3, 61 ... P-MOSFET, 2, 4, 5, 62 ... N-MOSF
ET, 6 ... Zener diode, 7 ... Protection diode, 8
... inverter, 10 ... level shift circuit, 20 ... high voltage output circuit, 30 ... input terminal, 31 ... output terminal, 32 ...
High potential side power source, 33 ... Ground level terminal, 51 ... Panel display drive circuit, 52 ... Logic circuit, 53 ...
Driver IC, 63 ... Resistance.

Continuation of front page (56) Reference JP-A-2-291719 (JP, A) JP-A-2-92111 (JP, A) JP-A-2-61696 (JP, A) JP-A-8-106267 (JP , A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 17/687 G09G 3/20 G09G 3/28 H03K 17/10

Claims (4)

(57) [Claims] 1. A level shifter using a voltage-driven semiconductor device.
And DOO circuit, driving the capacitive load and a high voltage output circuit
In the circuit , a power supply terminal to which a power supply is applied, an output terminal to which a load is connected, a reference terminal serving as a reference potential, a first P-channel type MOS field effect transistor connected to the power supply terminal, and the reference terminal The first N
N-channel type circuit having a series connection circuit with a channel type MOS field effect transistor, a second P-channel type MOS field effect transistor connected to the power supply terminal, a first main electrode , a second main electrode and an insulated gate electrode MO
A series connection circuit of the first semiconductor device is a S field effect transistor, said a second 1P channel type MOS field effect transistor, said third 1N channel MOS field effect series connection point of said first 2P channel MOS field effect transistor connected to the gate electrode of the transistor, connecting the series connection portion of said first 2P channel MOS field effect transistor and the first semiconductor device to the insulated gate electrode of the first 1P channel type MOS field effect transistors, further, the third main electrode , a fourth main electrode and the insulated gate electrode, said third main electrode connected to said power supply terminal, said fourth main electrode connected to said output terminal, said insulated gate electrode is pre
Note 2nd P-channel MOS field effect transistor and before
Note N channel connected to the serial connection point with the first semiconductor device
A second semiconductor device which is a channel MOS field effect transistor ; and a zener diode element connected between the insulated gate electrode of the second semiconductor device and the output terminal , wherein the level shift circuit has the first P channel Type MOS
A field effect transistor and a first N-channel MOS transistor.
Field effect transistor and second P-channel MOS electric field
An effect transistor and a first semiconductor device, wherein the high-voltage output circuit includes the first semiconductor device and the second semiconductor device.
And a device for inverting the drive control input signal to the first N channel.
Insulated gate electrode of a nell-type MOS field effect transistor
And input the drive control input signal to the first semiconductor device.
Insulated gate A drive circuit for a capacitive load that inputs to the gate electrode . 2. The driving of the capacitive load according to claim 1.
The circuit features a plasma display as a load
Drive circuit for capacitive load. 3. The odor according to claim 1 or claim 2.
A plurality of the capacitive load driving circuits are semiconductor integrated circuits.
Drive circuit for capacitive load characterized by being mounted on
Road. 4. The driving of the capacitive load according to claim 3.
Applying 50-200V to the power supply terminal of the circuit,
Capacitive negative characterized by input signal less than 5V
Load drive circuit.