JP3505016B2 - Thin film transistor substrate - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a thin film transistor.
It relates TFT substrate using, in particular, relates to a thin film transistor substrate which is used in the reflection type active matrix liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have been widely used in products such as word processors, laptop personal computers and pocket TVs. Liquid crystal display devices generally used at present are roughly classified into a simple matrix type display device and an active matrix type display device. A simple matrix display device is one in which vertical wirings are provided on one substrate and horizontal wirings are provided on the other substrate across a liquid crystal layer, and one pixel is formed by the intersection of each wiring. is there. On the other hand, the active matrix type display device uses a substrate in which active elements typified by thin film transistors are arranged in a matrix, and drives each pixel by associating one transistor with each pixel. . Compared to the simple matrix type display device, the active matrix type display device is superior in gradation and responsiveness, but it requires a large number of transistors to be formed on the substrate, which complicates the manufacturing process and reduces the cost. Will also be higher.

In a general thin film transistor, a gate electrode is formed on a substrate, a semiconductor channel layer made of an intrinsic semiconductor is formed on the gate electrode via a gate insulating layer, and a source electrode and a drain electrode are formed on the semiconductor channel layer. It is configured by connecting. By controlling the voltage applied to the gate electrode, the semiconductor channel layer is made conductive,
It can be brought into a non-conducting state, and can operate as a switching element in which a source electrode and a drain electrode are turned on / off. In an active matrix type display device, a thin film transistor substrate is formed by vertically arranging each transistor in a matrix so that one transistor corresponds to one pixel, and liquid crystal is filled between the thin film transistor substrate and a counter substrate. It will be. In this thin film transistor substrate, for example, if the gate electrode is extended in the lateral direction of this matrix array, the source electrode is extended in the vertical direction of this matrix array, and the drain electrode is connected to the display electrode corresponding to each pixel, The combination with the source electrode makes it possible to control the potential of the display electrode corresponding to an arbitrary pixel.

[0004]

SUMMARY OF THE INVENTION In order to improve the resolution of an active matrix type display device,
It is necessary to miniaturize the transistors formed on the thin film transistor substrate and improve the degree of integration. In general,
A photolithography process using a predetermined photomask is required for the thin film transistor manufacturing process,
In order to miniaturize the thin film transistor, it is necessary to align the mask with high precision in this manufacturing process. In particular, the parasitic capacitance between the gate electrode / drain electrode,
Since the parasitic capacitance between the gate electrode and the source electrode greatly changes according to the alignment error of the mask, it is impossible to manufacture a display device having uniform display characteristics unless the alignment is performed with high accuracy. . in this way,
In order to perform a manufacturing process that requires a highly accurate photolithography process, expensive equipment is required, and the manufacturing cost is inevitably high.

Therefore, an object of the present invention is to provide a thin film transistor substrate which can be manufactured by a process as simple as possible.

[0006]

[Means for Solving the Problems] (1) A first aspect of the present invention is to form a gate electrode on a substrate, and form a semiconductor channel layer on the gate electrode via a gate insulating layer. matrix thin film transistor formed by connecting the source and drain electrodes, vertically and horizontally with respect to
The thin film transistor substrate formed by arranging multiple stripes
The insulating substrate and the lateral direction formed on this substrate.
Multiple laterally arranged elongated electrode layers
Gates with the function of controlling
The entire surface of the substrate so that the pole and this gate electrode are embedded
This gate and a physically single gate insulating layer formed on
Physically a single semiconductor formed over the top surface of the insulating layer
The body channel layer and the top surface of the semiconductor channel layer are
A plurality of island-shaped electrode layers arranged in the shape of a lix and vertically
Completely encloses each individual island electrode layer placed
It is composed by connecting multiple annular electrode layers,
A vertically elongated strip formed on the top surface of the body channel layer
A plurality of ladder-shaped electrode layers, and an island-shaped electrode layer and a ring shape
One of the electrode layers is the source electrode and the other is the drain electrode.
So that the thin film transistor to be the pole is constructed,
The gap between the island-shaped electrode layer and the ring-shaped electrode layer.
Thin film transistor by the region in the semiconductor channel layer
The channel region that controls the ON / OFF operation of
It was done so.

[0007]

[0008]

(2) A second aspect of the present invention is based on the above-mentioned first aspect.
In the thin film transistor substrate according to the first aspect, each island electrode layer and each ladder electrode layer, a semiconductor channel layer,
An impurity diffusion layer for ensuring ohmic contact between both layers is formed between them.

(3) A third aspect of the present invention relates to the above-mentioned first aspect .
In the thin film transistor substrate according to the first or second aspect, an insulating layer is formed on the upper surfaces of the island-shaped electrode layer and the ladder-shaped electrode layer, and a conductive reflective display electrode layer corresponding to each transistor is formed on the insulating layer. The reflective display electrode layer is electrically connected to the corresponding island-shaped electrode layer of a transistor through a contact hole formed in the insulating layer.

[0011]

DETAILED DESCRIPTION OF THE INVENTION

<Conventional General Thin-Film Transistor Substrate> Hereinafter, the present invention will be described based on illustrated embodiments. First, the structure of a conventional general thin film transistor substrate will be briefly described. FIG. 1 is a top view showing a transistor configuration of a thin film transistor substrate used in a general transmissive active matrix type liquid crystal display device. The portion indicated by a broken line in the drawing is the gate electrode layer 2. The gate electrode layer 2 extends in the lateral direction of the drawing and a main portion corresponding to the scanning line of the display, and extends from the main portion to the lower portion of the drawing,
And a gate portion that acts as a gate for each transistor element. On the other hand, the portion shown by the solid line in the figure is the source electrode layer 6, which extends in the vertical direction of the figure and functions as the data line of the display. Thus, a large number of squares are formed by the plurality of gate electrode layers 2 arranged in the horizontal direction and the plurality of source electrode layers 6 arranged in the vertical direction, and the display electrode layer 9 (shown in FIG. (Indicated by the dashed line) is formed.
In order to make electrical contact with each of the display electrode layers 9,
Each drain electrode layer 8 (shown by a dashed line in the figure) is formed, and the semiconductor channel layer 4 (shown by a dotted line in the figure) is formed between each source electrode layer 6 and the drain electrode layer 8. . The gate portion of the gate electrode layer 2 overlaps each semiconductor channel layer 4, and the channel in the semiconductor channel layer 4 is turned on by the voltage applied to the gate electrode layer 2.
N / OFF control is possible.

In the above structure, one set of thin film transistors includes a part of the source electrode layer 6, the drain electrode layer 8,
A semiconductor channel layer 4 formed between them, and a gate electrode layer 2 for controlling the semiconductor channel layer 4
The gate section of FIG. 1 shows a state in which four sets of thin film transistors are formed, but in reality, a large number of transistors are arranged in a matrix in the vertical and horizontal directions on a two-dimensional plane, and each display electrode 9 constitutes one pixel. A display is formed. By applying a predetermined voltage to the gate electrode layer 2 corresponding to a specific one scanning line, the semiconductor channel layers 4 of the thin film transistors arranged in a row in the drawing can be turned on, and each source as a data line can be turned on. The signal value given to the electrode 6 can be written in the display electrode 9. In other words, by selectively applying a voltage to the plurality of gate electrode layers 2 arranged in the horizontal direction of the drawing and the plurality of source electrode layers 6 arranged in the vertical direction of the drawing, A desired charge can be accumulated in a desired electrode among the large number of display electrodes 9 arranged on the two-dimensional plane.

FIG. 2 shows a part of the cross section corresponding to the section line XX 'in FIG. A gate electrode layer 2 is formed on a glass substrate 1, and a semiconductor channel layer 4 is formed on the gate electrode layer 2 with a gate insulating layer 3 interposed therebetween. Further, the source electrode layer 6 is formed via the source-side impurity diffusion layer 5, and the drain electrode layer 8 is formed via the drain-side impurity diffusion layer 7. The source-side impurity diffusion layer 5 and the drain-side impurity diffusion layer 7 are intermediate layers for ensuring ohmic contact with the semiconductor channel layer 4.

In the thin film transistor having such a structure, the generation of parasitic capacitance becomes a problem. This will be explained based on FIG. FIG. 3 shows the cross-sectional view of FIG. 2 in a different way. Here, focusing on the spatial positional relationship between the gate electrode layer 2, the source electrode layer 6, and the drain electrode layer 8, It can be understood that parasitic capacitance is generated.
That is, the gate electrode layer 2 and the source electrode layer 6 overlap in the section Δ1 in the figure, and the gate electrode layer 2 and the drain electrode layer 8 overlap in the section Δ2 in the figure. Therefore, the portions indicated by thick lines of the respective electrodes form the counter electrodes at the top and bottom, and the capacitive element is formed. Such parasitic capacitance has the effect of deforming the waveform of the gate pulse applied to the gate electrode layer 2, and if the parasitic capacitance value varies, the display characteristics of each pixel also vary. To make this parasitic capacitance value uniform,
It is necessary to keep the widths of the sections Δ1 and Δ2 in FIG. 3 uniform. As described above, in the related art, the alignment error in the photolithography process is kept minute and the parasitic capacitance is made uniform by the advanced alignment technique.

<Thin Film Transistor Substrate According to the Present Invention> FIG. 4 is a top view showing a transistor configuration of the thin film transistor substrate according to the present invention. The portion shown by the broken line in the figure is the gate electrode layer 12, which has an elongated structure extending in the lateral direction of the figure. On the other hand, the portion shown by the solid line in the figure is the source electrode layer 16, which has a ladder-like structure extending in the vertical direction of the figure and having square openings at predetermined intervals. The portion indicated by the alternate long and short dash line in the drawing is the drain electrode layer 18, and has a square structure arranged in each opening of the source electrode layer 16. Each of the electrode layers shown in FIG. 4 is formed on a glass substrate, and an insulating layer and a semiconductor channel layer (not shown) are formed on the glass substrate. Such a structure is clearly shown in the side sectional views of FIGS. FIG. 5 shows FIG.
6 is a side sectional view corresponding to a section line XX 'in FIG. 6, and FIG. 6 is a side sectional view corresponding to a section line YY' in FIG. As can be seen from these side sectional views, the gate electrode layer 12 is formed on the glass substrate 11, and the semiconductor channel layer 14 is formed on the gate electrode layer 12 with the gate insulating layer 13 interposed therebetween.
Are formed. In addition, the source electrode layer 16 is disposed on the drain side impurity diffusion layer 1 via the source side impurity diffusion layer 15.
A drain electrode layer 18 is formed via each of them. The source-side impurity diffusion layer 15 and the drain-side impurity diffusion layer 17 are intermediate layers for ensuring ohmic contact with the semiconductor channel layer 14.

FIG. 7 is an exploded perspective view of the structure shown in FIGS. 4-6, which shows the structure more clearly. The lower half of the figure shows a laminated structure of the glass substrate 11, the gate electrode layer 12, the gate insulating layer 13, and the semiconductor channel layer 14, and the upper half of the figure shows the source-side impurity diffusion layer 1.
5, source electrode layer 16, drain side impurity diffusion layer 17,
The stacked structure of the drain electrode layer 18 is shown. The structure shown in the upper half of the figure will be placed on the upper surface of the structure shown in the lower half of the figure.

In the thin film transistor substrate having such a structure, one set of thin film transistors includes a part of the source electrode layer 16 (an annular part surrounding one opening),
One island-shaped drain electrode layer 18, a part of the semiconductor channel layer 14 located under both electrode layers, and a part of the gate electrode layer 12 located under the semiconductor channel layer 14. Become. FIG. 4 shows a state in which four sets of thin film transistors are formed, but in reality, a large number of transistors are arranged in a matrix in the vertical and horizontal directions on a two-dimensional plane, and the drain electrode of each transistor is formed. Display electrodes (not shown) that form a display are electrically connected to the layer 18. The source electrode layer 16 has a ladder-like structure elongated in the vertical direction of the figure, and the island-shaped drain electrode layers 18 are arranged inside the respective openings. Therefore, for the thin film transistor substrate as a whole,
A large number of ladder-shaped source electrode layers 16 are arranged so as to be adjacent to each other on the left and right sides of the drawing, and drain electrode layers 18 are arranged in the openings of the source electrode layers 16, respectively. The layers 18 will be arranged in a matrix.

As shown in the top view of FIG. 4, the gate electrode layer 12 functions as a common gate electrode for a plurality of transistors arranged in the lateral direction of the drawing, and the source electrode layer 16 is shown in the drawing. It functions as a common source electrode for a plurality of transistors arranged in the vertical direction. As described above, the source / drain electrodes of one set of thin film transistors are composed of one island-shaped drain electrode layer 18 and an annular portion of the source-electrode layer 16 surrounding the island-shaped drain electrode layer 18 (one opening). (A ring-shaped portion surrounding the portion), and a “mouth” -shaped void portion is formed between the source / drain. Semiconductor channel layer 1
4, a region corresponding to the “mouth” -shaped void portion becomes a channel region that controls the ON / OFF operation of the transistor, and is a voltage applied to the gate electrode layer 12 disposed below the semiconductor channel layer 14. This makes it possible to control the current flowing through this channel region.

That is, if a predetermined voltage is applied to the gate electrode layer 12 corresponding to one specific scanning line, the channel regions of the thin film transistors arranged in a line in the figure can be turned on, and the thin film transistors can be turned on. The signal value given to each source electrode 16 can be written to the drain electrode layer 18 side. In other words, by selectively applying a voltage to the plurality of gate electrode layers 12 arranged in the horizontal direction of the drawing and the plurality of source electrode layers 16 arranged in the vertical direction of the drawing, A desired charge can be accumulated in a desired electrode of the large number of drain electrode layers 18 arranged on the two-dimensional plane.

<Advantages of Thin Film Transistor Substrate According to the Present Invention> The above-mentioned thin film transistor substrate has the following two advantages that simplify the manufacturing process. The first advantage is that the allowable error range for mask alignment becomes large. In the thin film transistor substrate according to the present invention, as can be seen from the top view of FIG. 4, even if the relative positions of the gate electrode layer 12, the source electrode layer 16 and the drain electrode layer 18 are slightly deviated, the gate / source The parasitic capacitance value and the gate / drain parasitic capacitance value do not change. In other words, even when the position of the gate electrode layer 12 shown by the broken line in FIG. 4 is slightly shifted, the area of the overlapping portion of the gate electrode layer 12 and the source electrode layer 16 or the gate electrode layer 12 and the drain electrode layer 18
There is no change in the area of the overlapping part with. Therefore, the positional accuracy of the photomask in the photolithography process for patterning the gate electrode layer 12, the source electrode layer 16 and the drain electrode layer 18
Although the positional accuracy of the photomask in the photolithography process for patterning is lower than the positional accuracy when manufacturing a conventional thin film transistor substrate, there is no variation in the parasitic capacitance value for each transistor. It is possible to realize a display device which has no unevenness.

The second merit is the semiconductor channel layer 14
This is an advantage that patterning can be omitted. As shown in FIG. 1, in the conventional thin film transistor substrate, the semiconductor channel layer 4 is a physically independent layer for each transistor. If this is a physically continuous single semiconductor channel layer, it leaks between the source electrode layer 6 and the drain electrode layer 8 through a region other than the channel region controlled by the gate electrode layer 2. This is because an electric current will flow. Therefore, in the conventional thin film transistor substrate as shown in FIG. 1, the patterning process for the semiconductor channel layer is indispensable. On the other hand, in the thin film transistor substrate according to the present invention shown in FIG. 4, the patterning process for the semiconductor channel layer is unnecessary. As shown in the exploded perspective view of FIG. 7, the semiconductor channel layer 14 is a physically continuous single layer, and a common semiconductor channel layer is formed for a large number of transistors arranged in a matrix in the vertical and horizontal directions. I am configuring. As described above, even if a single common semiconductor channel layer is formed, there is no possibility that a significant leak current will flow between the source electrode layer 16 and the drain electrode layer 18. This is because, as shown in the top view of FIG. 4, each drain electrode layer 18 has a structure in which the periphery thereof is completely surrounded by the source electrode layer 16, and a channel having a “mouth” shape is formed. This is because the conduction characteristics of the region have a structure that can be reliably controlled by the gate electrode layer 12.

Generally, in a semiconductor planar process, patterning steps for one layer include resist coating, drying, photomask alignment, exposure, and development.
This is a time-consuming and time-consuming process that consists of numerous processes such as etching and resist stripping. In the thin film transistor substrate according to the present invention, the patterning process for the semiconductor channel layer 14 can be completely omitted, so that the whole manufacturing process can be greatly simplified.

<Embodiment Forming Reflective Display Electrode Layer>
When the thin film transistor substrate is used in an active matrix type liquid crystal display device, it is necessary to provide a display electrode layer for applying a voltage to liquid crystal and electrically connect each drain electrode layer. For example, in the case of the conventional thin film transistor substrate shown in FIG. 1, a display electrode layer 9 is provided for each transistor and connected to each drain electrode layer 8. This display electrode layer 9 is a layer corresponding to one pixel region of the display, and it is desirable to secure a large area as much as possible. However, in the case of a so-called transmissive liquid crystal display device, since the display electrode layer 9 needs to transmit light from the back surface side of the substrate, the display electrode layer 9 is planarly overlapped with the non-translucent layer. I'm not feeling well if I do. This is the reason why the display electrode layer 9 is formed so as to avoid the other layers in the thin film transistor substrate shown in FIG.

When the thin film transistor substrate according to the present invention shown in FIG. 4 is used in an active matrix type liquid crystal display device, a display electrode layer corresponding to one pixel region is also provided and electrically connected to each drain electrode layer. There is a need. However, it is difficult to form the display electrode layer so as to avoid a planar overlap with other non-translucent layers.
It is very difficult for the thin film transistor substrate having the structure shown in FIG. Therefore, the thin film transistor substrate according to the present invention is not suitable for use in a so-called transmissive liquid crystal display device, and is preferably used exclusively in a reflective liquid crystal display device.

FIG. 8 is a top view showing a state in which a reflective display electrode layer 19 is further added to the thin film transistor substrate shown in FIG. The area shown by a chain double-dashed line in the figure shows the reflective display electrode layer 19. The three-dimensional structure with the addition of the reflective display electrode layer 19 is clearly shown in the side sectional views of FIGS. 9 and 10. FIG. 9 shows a section line XX in FIG.
10 is a side sectional view corresponding to ', and FIG. 10 is a side sectional view corresponding to the cutting line YY' in FIG. As can be seen from these side sectional views, the insulating layer 2 is formed on the upper surfaces of the source electrode layer 16 and the drain electrode layer 18 which form the transistor.
0 is formed, and a conductive reflective display electrode layer 19 (for example, an aluminum layer) corresponding to each transistor is formed on the insulating layer 20. A contact hole H is opened in the insulating layer 20, and a part of the reflective display electrode layer 19 is connected to the upper surface part of the drain electrode layer 18 through the contact hole H. In the thin film transistor substrate used for the reflective liquid crystal display device, since the display electrode layer does not need to transmit light from the back surface side of the substrate, the display electrode layer can be formed above the transistor formation portion, and a unique structure can be formed. Even if the thin film transistor according to the present invention is adopted, no problem occurs.

Although the present invention has been described above based on the illustrated embodiments, the present invention is not limited to these embodiments and can be implemented in various other forms. In essence, the present invention provides:
An island-shaped electrode layer and an annular electrode layer surrounding the island-shaped electrode layer are formed, and one of the island-shaped electrode layer and the annular electrode layer is used as a source electrode and the other is used as a drain electrode. If it is possible, it may be implemented in any form. Further, in the above-described embodiments, the structure in which the source electrode layer surrounds the island-shaped drain electrode layer is shown, but in general, the names “drain electrode” and “source electrode” in the FET transistor are referred to as the direction of current flow. It is determined in consideration of the above, and has a commutativity. Therefore, conversely, the present invention can be implemented as a thin film transistor having a structure in which the drain electrode layer surrounds the island-shaped source electrode layer.

[0027]

As described above, according to the present invention, since the source / drain of the transistor is constituted by the island-shaped electrode layer and the annular electrode layer formed on the upper surface of the semiconductor channel layer, the thin film transistor whose manufacturing process is simple. A substrate can be realized.

[Brief description of drawings]

FIG. 1 is a top view showing a transistor configuration of a thin film transistor substrate used in a general transmissive active matrix type liquid crystal display device.

FIG. 2 is a side sectional view corresponding to a section line XX ′ in FIG.

FIG. 3 is a diagram showing the side cross-sectional view of FIG. 2 in another way of drawing in order to explain a parasitic capacitance.

FIG. 4 is a top view showing a transistor configuration of a thin film transistor substrate according to the present invention.

5 is a side sectional view corresponding to a section line XX 'in FIG.

FIG. 6 is a side sectional view corresponding to a section line YY ′ in FIG.

FIG. 7 is an exploded perspective view of the structure shown in FIGS. 4 to 6;

8 is a top view showing a state in which a reflective display electrode layer 19 is further added to the thin film transistor substrate shown in FIG.

9 is a side sectional view corresponding to a section line XX 'in FIG.

10 is a side sectional view corresponding to section line YY 'in FIG.

[Explanation of symbols]

1 ... Glass substrate 2 ... Gate electrode layer 3 ... Gate insulating layer 4 ... Semiconductor channel layer 5 ... Source-side impurity diffusion layer 6 ... Source electrode layer 7 ... Drain side impurity diffusion layer 8 ... Drain electrode layer 9 ... Display electrode layer 11 ... Glass substrate 12 ... Gate electrode layer 13 ... Gate insulating layer 14 ... Semiconductor channel layer 15 ... Source-side impurity diffusion layer 16 ... Source electrode layer 17 ... Drain side impurity diffusion layer 18 ... Drain electrode layer 19 ... Reflective display electrode layer 20 ... Insulating layer H ... Contact hole

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-2-58028 (JP, A) JP-A-7-92494 (JP, A) JP-A 64-82674 (JP, A) JP-A 60- 73617 (JP, A) JP 61-147573 (JP, A) JP 7-92493 (JP, A) JP 5-315328 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 G02F 1/1368

Claims (3)

(57) [Claims] 1. A thin film transistor formed by forming a gate electrode on a substrate, forming a semiconductor channel layer on the gate electrode via a gate insulating layer, and connecting a source electrode and a drain electrode to the semiconductor channel layer. Vertically and horizontally.
Thin film transistor substrate with a plurality of tricks arranged
And an insulating substrate and a laterally extending elongated electrode layer formed on the substrate.
Control multiple transistors arranged horizontally
A plurality of gate electrodes having a function to cover the entire surface of the substrate so that the gate electrodes are embedded.
The formed physically single gate insulating layer and the physically single gate insulating layer formed on the entire upper surface of the gate insulating layer.
One semiconductor channel layer and a matrix arrangement on the upper surface of the semiconductor channel layer
The island-shaped electrode layers and the individual island-shaped electrode layers arranged in the vertical direction.
It is constructed by connecting multiple annular electrode layers that surround it.
In the vertical direction formed on the upper surface of the semiconductor channel layer.
A plurality of elongated ladder-shaped electrode layers extending , any one of the island-shaped electrode layer and the annular electrode layer
A thin film transistor with one of them as the source electrode and the other as the drain electrode.
A transistor, and the island-shaped electrode layer
The semiconductor corresponding to the void portion between the annular electrode layer
Depending on the region in the channel layer, the O
A channel region that controls N / OFF operation is formed
A thin film transistor substrate, characterized in that 2. The thin film transistor substrate according to claim 1 , wherein an impurity diffusion layer for ensuring ohmic contact between the island-shaped electrode layers and the ladder-shaped electrode layers and the semiconductor channel layer is provided. A thin film transistor substrate, wherein: 3. The thin film transistor substrate according to claim 1 , wherein an insulating layer is formed on upper surfaces of the island-shaped electrode layer and the ladder-shaped electrode layer, and conductive reflection corresponding to each transistor is formed on the insulating layer. Type display electrode layer is formed, and the reflection type display electrode layer and the corresponding island-shaped electrode layer of a transistor are electrically connected via a contact hole opened in the insulating layer. substrate.