JP3475107B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device in which a transistor for high frequency use and a capacitor are formed. 2. Description of the Related Art In a semiconductor integrated circuit, a capacitive element is often formed simultaneously with an active element such as a transistor. As the capacitance element, there are a method using a junction capacitance of a PN junction and a method using a high dielectric thin film such as a silicon oxide film or a silicon nitride film (for example, Japanese Patent Laid-Open No.
147). The former is easy to manufacture because the diffusion step in the process can be diverted, but has the drawback of not being able to obtain a high capacitance value.The latter is characterized by the need to add a manufacturing step, but has a high capacitance value. have. In a capacitor using a dielectric thin film, for example, as shown in FIG. 5, an opening 2 is formed on an insulating film 1 on a semiconductor chip, and a silicon nitride film or the like is formed so as to cover the opening 2. A dielectric thin film 3 is formed, and a lower electrode 4 and an upper electrode 5 are formed so as to sandwich the dielectric thin film 3. [0004] In recent years, MMICs (monolithic microwave integrated circuits) have been used in specific fields such as high frequency applications. In such an IC, passive elements such as a capacitor element and a resistor element are often integrated together with the transistor element. However, in the integrated circuit, due to the influence of the process of manufacturing other elements on the dielectric thin film, there are still many factors that cause variations in the capacitance value. Therefore, it has been desired to form a more accurate capacitive element because it becomes more severe. SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has a step of forming a reverse conductivity type epitaxial layer on a semiconductor substrate of one conductivity type, and separating the epitaxial layer. Forming an island region by performing
Forming an opening in an insulating film covering two surfaces;
Forming a dielectric thin film covering the opening, forming a contact hole in an insulating film covering another surface of the island region, forming a polysilicon layer;
Forming a diffusion source film for emitter diffusion by photo-etching, leaving the polysilicon layer on the dielectric thin film covering the opening, and diffusing impurities from the diffusion source film. Forming an emitter region; forming an emitter electrode on the diffusion source film; and forming an upper electrode of the capacitor on a polysilicon layer formed on the dielectric thin film. It is characterized by doing. An embodiment of the present invention will be described below. First step: Referring to FIG. 1A, a P-type semiconductor substrate 11 is prepared. An oxide film 12 is formed by thermally oxidizing the surface, and an opening is formed in the oxide film by a photoetching technique. Arsenic (As) is diffused into the surface of the semiconductor substrate 11 exposed at the opening to form an N + type buried layer 13. Subsequently, the oxide film is formed again, an opening is formed again in the oxide film 12 by a photoetching technique, and boron (B) is ion-implanted into the surface of the substrate 11 to form a P + type isolation region 14. Second step: Referring to FIG. 1B, after removing the oxide film mask for ion implantation, an N-type epitaxial layer 15 is formed by a vapor phase growth method. The film thickness is 2-5 μm, and the specific resistance ρ = 0.5-
5 Ω · cm. After forming the epitaxial layer, a thin oxide film 16 is formed on the surface of the epitaxial layer 15, and a resist mask 17 is formed on the oxide film 16. Phosphorus (P) ions are implanted through the opening of the resist mask to
A collector low-resistance region 18 and a lower electrode region 19 of a capacitor are formed. Third step: Refer to FIG. 1C. After removing the resist mask, an oxidation resistant film (not shown) is formed by forming a silicon nitride film and photoetching, and partially exposing the surface of the epitaxial layer 15. After that, selective oxidation is performed to form a LOCOS oxide film 20 on the surface of the epitaxial layer 15. The LOCOS oxide film 20 contacts the P + isolation region 14 and separates the epitaxial layer 15 therefrom to form an island region 21. Fourth step: Referring to FIG. 1D, a resist mask 22 for ion implantation is formed on the oxide film on the surface of the epitaxial layer 15, and boron (B) is formed.
Is ion-implanted. The ion-implanted boron is in the island region 2
The base region 23 is formed on the surface of the substrate 1. Fifth step: Referring to FIG. 2A, the resist mask 22 is removed, and a silicon nitride film 2
4 is formed. Subsequently, the film thickness is 0.1 to 0.5 μm on the entire surface.
Is formed, and phosphorus (P) is ion-implanted over the entire surface. This is then annealed to give the polysilicon layer the desired conductivity. Note that the annealing also serves as thermal diffusion of the base region 23 which has been ion-implanted earlier. Then, the polysilicon layer is photo-etched to form a polysilicon resistor 25 on the LOCOS oxide film 20. The polysilicon resistor 25 is formed to have a constant line width and a length at which a desired resistance value is obtained, like an aluminum wiring. Then, an opening 26 for opening the silicon nitride film 24 and the oxide film is formed on the lower electrode region 19 of the capacitive element by photoetching. Sixth step: Referring to FIG. 2B, a silicon nitride film 27 is formed on the entire surface. This silicon nitride film 27 is a thin film serving as a dielectric thin film of the capacitor, and has a thickness of 300 to 1000 °. This silicon nitride film 2
7 also covers the upper part of the polysilicon resistor 25. Seventh step: Refer to FIG. 2C. Subsequently, an NSG film is formed on the entire surface, and this is photoetched to cover the upper part of the polysilicon resistor 25.
A film 28 is formed. Then, a contact hole 29 is formed by photoetching the silicon nitride film and the oxide film on the surface of the island region 21. Eighth step: Referring to FIG. 3A, a second polysilicon layer 30 is formed with a thickness of about 0.1 to 1.0 μm on the entire surface, and an N-type impurity such as arsenic is ion-implanted. An impurity for emitter diffusion is introduced into the second polysilicon layer 30. Ninth step: Referring to FIG. 3B, the second polysilicon layer 30 is photo-etched by an anisotropic dry etching technique in fluorine + chlorine gas.
Polysilicon electrodes 31, 32, 33, 34 are formed.
The electrode 31 is a diffusion source film for emitter diffusion and forms a part of an electrode wiring. The electrode 32 constitutes a collector, the electrode 33 constitutes a lower electrode of the capacitor, and the electrode 34 constitutes a part of an upper electrode of the capacitor. The upper electrode 34 is left so as to cover the entire opening 26 of the capacitor. By leaving the upper electrode 34 at the upper portion, the dielectric thin film 27 is prevented from being eroded by the above-described etching. Tenth step: Referring to FIG. 3C, a resist mask 35 is formed on the entire surface, and a contact hole 29 on the surface of the base region 23 is opened. Then, using the resist mask 35 and the contact hole 30 as a mask, boron ions are implanted so as to overlap the base region 23. Eleventh step: As shown in FIG. 4A, arsenic is diffused from the electrode 31 by applying a heat treatment at 900 to 1100 ° C. for 30 minutes as a whole to form an emitter region 36. The P-type impurity implanted in the previous step is also diffused to form the base contact region 37.
Arsenic is also diffused from the electrodes 32 and 33 to reduce their contact resistance. Twelfth step: Referring to FIG. 4B, a dielectric thin film 27 covering the polysilicon resistor 25 and N
The SG film 28 is photo-etched to form a contact hole, and then an electrode material such as Ti / Pt / Au is formed.
Electrodes 38, 39, 40, 41, 42, 43, 44, 45
To form This electrode material also serves as a connection wiring between each element and the polysilicon resistor 26. In such a semiconductor device, an extremely shallow diffusion region can be formed by diffusion from the polysilicon emitter, and a high-frequency transistor can be formed. A first feature of the present invention is that a polysilicon electrode 34 for forming a diffusion source film 31 for emitter diffusion is left on the dielectric thin film 27 of the capacitor. Since the anisotropic dry etching for etching the polysilicon layer also etches the silicon nitride film of the dielectric thin film 27, exposing the dielectric thin film 27 to such an etchant causes the film thickness to vary, and the capacitance to be increased. This results in variation in values. The present invention protects the dielectric thin film 27 by covering the upper portion of the dielectric thin film 27 with the polysilicon electrode 34, and suppresses variation in the capacitance value. Further, since the polysilicon electrode 34 is doped with a high impurity concentration for emitter diffusion, the series resistance can be reduced. As described above, according to the present invention , one of the island regions is formed after the step of forming the dielectric thin film.
Base and emitter capacitors on the insulating film covering the surface of the
Form a tact hole and cover the surface of other island areas.
Form a contact hole for the lower electrode of the capacitor in the edge film
Process and thereby forming a diffusion source film for emitter diffusion in advance.
And a polysilicon layer can be left on the dielectric thin film.
Selective removal of polysilicon layer in source contact hole
At the same time, the emitter electrode, upper electrode and base electrode
The forming step has an advantage that the high-frequency transistor and the capacitor can be manufactured in a simple step. By forming the polysilicon electrode 34 at the same time as the formation of the polysilicon electrode 31 for emitter diffusion, the dielectric thin film 27 can be protected from an etchant. Has the advantage that

[Brief description of the drawings] FIG. 1 is a cross-sectional view for explaining the present invention. FIG. 2 is a cross-sectional view for explaining the present invention. FIG. 3 is a cross-sectional view for explaining the present invention. FIG. 4 is a cross-sectional view for explaining the present invention. FIG. 5 is a cross-sectional view for explaining a conventional example.

────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/73 (72) Inventor Hiroyuki Nakamoto 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56 References JP-A-10-112507 (JP, A) JP-A-4-154160 (JP, A) JP-A-62-166555 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H01L 27/04 H01L 27/06 H01L 29/73 H01L 21/822 H01L 21/8222 H01L 21/331

Claims (1)

(57) Claims 1. A step of forming a reverse conductivity type epitaxial layer on a semiconductor substrate of one conductivity type, and a step of forming a plurality of island regions by separating the epitaxial layer. Forming a base region on the surface of one of the island regions
Forming an opening in the insulating film covering the surface of the other island region; forming a dielectric thin film covering the opening portion; and an insulating film covering the surface of the one island region Base and
Form a contact hole for the emitter , and
Contact for the lower electrode of capacitance on the insulating film covering the surface
Forming a hole, forming a polysilicon layer and injecting impurities of the opposite conductivity type,
This by photoetching to form a diffusion source film for emitter diffusion, the step of allowed to remaining said polysilicon layer on the dielectric thin film that covers the opening, the said base Ichisu contact hole Polysilicon layer
Removed and conductive through the base contact hole
Implanting an impurity of a mold type, diffusing the impurities from the diffusion source film to form an emitter region, depositing an electrode material on the surface, and forming an emitter on the diffusion source film.
Electrode, a polysilicon layer formed on the dielectric thin film
Forming the upper electrode and base electrode of the capacitive element
A method for manufacturing a semiconductor device, comprising: