JP2000216254A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [PROBLEMS] To form a polysilicon resistor with higher precision by covering the upper part of the polysilicon resistor with a dielectric thin film of a capacitor. SOLUTION: An N-type epitaxial layer 15 is formed on a P-type substrate 11 and separated to form an island region 21. LO
Forming a silicon nitride film 24 on the COS oxide film 20;
A polysilicon resistor 26 is formed thereon. After forming the opening 27 of the capacitive element, a dielectric thin film 28 covering the opening 27 and also covering the surface of the polysilicon resistor 26
To form Each diffusion region is formed, a contact hole is formed, and an electrode wiring is formed. Since the upper portion of the polysilicon resistor 26 is covered with the dielectric thin film at the initial stage of the process, the variation in the resistance value can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a polysilicon resistor and a capacitor formed thereon.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, a resistor element is often formed simultaneously with an active element such as a transistor. As the resistor element, there are a method using a P-type or N-type diffusion region, and a method using a polysilicon layer doped with impurities (for example, Japanese Utility Model Laid-Open No. 61-1575).
No. 5). The former is easy to manufacture because the diffusion step in the process can be diverted, but has the disadvantage that it is easy to vary. The latter has the characteristic that it requires an additional manufacturing step but is excellent in accuracy.

As shown in FIG. 5, for example, a polysilicon resistor is formed by forming a polysilicon layer 2 on an insulating film 1 on a semiconductor chip and doping a desired impurity into the polysilicon layer. It was done. The semiconductor chip has N
An NPN transistor is formed by forming a P-type base region 4 and an N-type emitter region 5 on the surface of a type collector layer 3, and a polysilicon layer 2 formed on a surface insulating film 1 is connected to a diffusion layer by an electrode 6. To be integrated.

[0004]

In recent years, MMICs (monolithic microwave integrated circuits) have been used in specific fields such as high frequency applications. Since such ICs are easily affected by stray capacitance and the like, the latter polysilicon resistor is often used.

[0005] However, in the integrated circuit, due to the influence on the polysilicon layer due to the process of manufacturing other elements, there are still a number of factors that cause variations in the resistance value. Therefore, it has been desired to form a polysilicon resistor with higher precision because the resistance becomes more severe.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and comprises a step of forming a reverse conductivity type epitaxial layer on a semiconductor substrate of one conductivity type; Forming a region, forming a polysilicon resistance layer on the insulating film on the surface of the epitaxial layer, forming an opening in the insulating film covering one surface of the island region, Forming a dielectric thin film covering the same, simultaneously covering the polysilicon resistance layer with the dielectric thin film, and forming a contact hole in an insulating film covering another surface of the island region; Forming an electrode in contact with the silicon surface through the contact hole, and forming a capacitive element using the dielectric thin film as a dielectric above the dielectric thin film covering the opening; It is characterized in that it comprises a step of forming a part electrode.

[0007]

Embodiments of the present invention will be described below.

First step: See FIG. 1A. A P-type semiconductor substrate 11 is prepared. An oxide film 12 is formed by thermally oxidizing the surface, and an opening is formed in the oxide film by a photoetching technique. Arsenic (As) is diffused into the surface of the semiconductor substrate 11 exposed at the opening to form an N + type buried layer 13. Subsequently, the oxide film is formed again, an opening is formed again in the oxide film 12 by a photoetching technique, and boron (B) is ion-implanted into the surface of the substrate 11 to form a P + type isolation region 14.

Second Step: See FIG. 1B Subsequently, after removing the oxide film mask for ion implantation, an N-type epitaxial layer 15 is formed by a vapor phase growth method. The film thickness is 2 to 10 μm, and the specific resistance ρ = 0.5
５5 Ω · cm.

After forming the epitaxial layer, a thin oxide film 16 is formed on the surface of the epitaxial layer 15, and a resist mask 17 is formed on the oxide film 16. Phosphorus (P) ions are implanted through the opening of the resist mask to
A collector low-resistance region 18 and a lower electrode region 19 of a capacitor are formed.

Third step: See FIG. 1C. After removing the resist mask, an oxidation resistant film (not shown) is formed by forming a silicon nitride film and photoetching, and partially exposing the surface of the epitaxial layer 15. After that, selective oxidation is performed to form a LOCOS oxide film 20 on the surface of the epitaxial layer 15. The LOCOS oxide film 20 contacts the P + isolation region 14 and separates the epitaxial layer 15 therefrom to form an island region 21.

Fourth Step: See FIG. 2A Subsequently, a resist mask 22 for ion implantation is formed on the oxide film on the surface of the epitaxial layer 15, and boron (B) is formed.
Is ion-implanted. The ion-implanted boron is in the island region 2
The base region 23 is formed on the surface of the substrate 1.

Fifth step: see FIG. 2B. The resist mask 22 is removed, and the silicon nitride film 2
4 is formed. Subsequently, the film thickness is 1000 to 5000 on the entire surface.
Forming a polysilicon layer 25 of Å;
The whole surface is ion-implanted with phosphorus (P). Thereafter, it is annealed to give the polysilicon layer 25 a desired conductivity.
Note that the annealing also serves as thermal diffusion of the base region 23 which has been ion-implanted earlier.

Sixth step: See FIG. 2C. The polysilicon layer 25 is photo-etched to
A polysilicon resistor 26 is formed on oxide film 20.
The polysilicon resistor 26 is formed with a constant line width and a length that can obtain a desired resistance value like an aluminum wiring. Then, an opening 27 for opening the silicon nitride film 24 and the oxide film is formed on the lower electrode region 19 of the capacitive element by photoetching.

Seventh step: See FIG. 3A A silicon nitride film 28 is formed on the entire surface. The silicon nitride film 28 is a thin film serving as a dielectric thin film of the capacitance element, and has a thickness of 500 to 2000 °. This silicon nitride film 2
8 also covers the upper part of the polysilicon resistor 26.

Eighth step: Refer to FIG. 3B. Subsequently, an NSG film is formed on the entire surface, and this is photoetched to cover the upper portion of the polysilicon resistor 26.
A film 29 is formed. Then, the contact hole 30 is formed by photo-etching the silicon nitride film and the oxide film on the surface of the island region 21.

Ninth step: See FIG. 3 (C) A second polysilicon layer is formed on the entire surface, and an N-type impurity such as arsenic is ion-doped, followed by photoetching to form polysilicon electrodes 31 and 32. , 33 and 34 are formed. Electrode 31 is an emitter, electrode 32 is a collector, electrode 3
Reference numeral 3 denotes a lower electrode of the capacitor, and electrode 34 denotes an upper electrode of the capacitor, each of which forms a part thereof.

Tenth Step: See FIG. 4A A resist mask 35 is formed on the entire surface, and a contact hole 30 on the surface of the base region 23 is opened. Then, boron is ion-implanted using the resist mask 35 and the contact hole 30 as a mask.

Eleventh step: See FIG. 4B By applying a heat treatment at 900 to 1100 ° C. for 30 minutes as a whole, arsenic is diffused from the electrode 31 to form the emitter region 36. The P-type impurity implanted in the previous step is also diffused to form the base contact region 37.
Arsenic is also diffused from the electrodes 32 and 33 to reduce their contact resistance.

Twelfth step: As shown in FIG. 4C, a dielectric thin film 28 covering the polysilicon resistor 26 and N
The SG film 29 is photo-etched to form a contact hole, and then an electrode material such as Ti / Pt / Au is formed.
Electrodes 38, 39, 40, 41, 42, 43, 44, 45
To form This electrode material also serves as a connection wiring between each element and the polysilicon resistor 26.

The first feature of the present invention is that the polysilicon resistor 26 is covered with a dielectric thin film 28. By completely covering the polysilicon layer of the polysilicon resistor 26 with a silicon nitride film having a high gettering effect, there is no variation in the impurity concentration or thickness of the polysilicon layer, and the resistance element has less variation. Can be formed. This effect is due to the polysilicon resistor 2
6 is further increased by forming a silicon nitride film 24 also underneath.

Further, since the upper portion of the polysilicon resistor 26 is covered by using the dielectric thin film of the capacitor, the manufacturing process can be simplified.

Further, since a process of forming the polysilicon resistor 26, forming the opening 27 of the capacitive element, and forming the dielectric thin film 28 is performed almost immediately after the formation of the polysilicon resistor 26, 26 can be protected from a manufacturing process in which the resistance value fluctuates, which can also reduce the variation in the resistance value.

Further, by forming an NSG film 29 above the polysilicon resistor 26 in addition to the dielectric thin film 28, an electrode wiring can be cross-wired above the polysilicon resistor 26, and a pattern design can be performed. And the degree of integration can be increased.

[0025]

As described above, according to the present invention, by covering the polysilicon resistor 26 with the silicon nitride film, there is an advantage that the resistor with less variation in resistance value can be integrated. .

By forming such a resistive element in accordance with the formation of the dielectric thin film 28 of the capacitive element,
This has the advantage that it can be formed together with the capacitor in a simple manufacturing process.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a cross-sectional view for explaining the present invention.

FIG. 4 is a cross-sectional view for explaining the present invention.

FIG. 5 is a cross-sectional view for explaining a conventional example.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/73 (72) Inventor Yoshiaki Matsumiya 2-5-5 Keihanhondori, Moriguchi-shi, Osaka SANYO ELECTRIC Co., Ltd. (72) Inventor Hiroyuki Nakamoto 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. F-term (reference) 5F003 BA25 BA97 BJ18 BJ20 BP06 BP93 BZ05 5F038 AC03 AC05 AC15 AC17 AR09 EZ12 EZ13 EZ14 EZ15 EZ16 EZ17 EZ20 5F082 AA06 BA04 BA07 BC13 BC18 DA09 EA04 EA13 EA15

Claims (2)

[Claims] A step of forming a reverse conductivity type epitaxial layer on a semiconductor substrate of one conductivity type; a step of separating the epitaxial layer to form an island region; and a step of forming an island region on the surface of the epitaxial layer. Forming a polysilicon resistance layer, forming an opening in an insulating film covering one surface of the island region, forming a dielectric thin film covering the opening, and simultaneously forming the polysilicon resistance layer Forming a contact hole in an insulating film covering another surface of the island region; forming an electrode in contact with a silicon surface through the contact hole; And forming an upper electrode for forming a capacitive element using the dielectric thin film as a dielectric above the dielectric thin film covering the opening. Manufacturing method of a semiconductor device. A step of forming a reverse conductivity type epitaxial layer on the one conductivity type semiconductor substrate; a step of separating the epitaxial layer to form an island region; and a step of forming an island region on the surface of the epitaxial layer. Forming a polysilicon resistance layer, forming an opening in an insulating film covering one surface of the island region, forming a dielectric thin film covering the opening, and simultaneously forming the polysilicon resistance layer Forming a contact hole in an insulating film covering another surface of the island region, forming a second polysilicon layer, and forming the second polysilicon layer through the contact hole. A step of forming a diffusion source film in contact with the silicon surface and an upper electrode for forming a capacitive element using the dielectric thin film as a dielectric above the dielectric thin film covering the opening; Performing a diffusion of impurities from the diffusion source film to the silicon layer.