JP3440987B2 - Method for manufacturing insulated gate semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly, to an insulated gate semiconductor device such as a vertical power MOSFET and a conductivity modulation type MOSFET and a method of manufacturing the same.

[0002]

2. Description of the Related Art A vertical power MOSFET as an insulated gate semiconductor device usually has an EQR (Equivalent
A channel stopper structure with a potential ring is provided. 1 of Japanese Unexamined Patent Application Publication No. 9-321282, a field stopper film is provided as a channel stopper structure in which a gate oxide film is interposed at a position inside a predetermined distance from the outer peripheral edge of the chip and an inner edge is in contact with the gate oxide film. Disclosed is a MOSFET in which an EQR metal electrode of aluminum is electrically connected to the surface of an EQR polysilicon electrode formed through the above and the surface of an N + diffusion region formed at the outer peripheral edge of the chip in a self-aligned manner with the EQR polysilicon electrode. ing. By the way, the base region and the source region of this MOSFET are formed in a self-aligned manner with the gate electrode formed at the same time as the EQR polysilicon electrode, but in order to make the base region and the source region electrically contact with the source electrode in a later process. When forming the source region, a part of the base region is exposed to the surface by using a photolithography method so that ions are not implanted into the part of the base region.

On the other hand, the applicant of the present application has filed an application for an insulated gate type semiconductor device in which a source region is formed in a self-aligned manner with a gate electrode without using a photolithography method and a method for manufacturing the same, in Japanese Patent Application No. 9-261433. ing.
Although this application does not describe the channel stopper structure on the outer peripheral portion of the chip constituting the MOSFET,
A case where the channel stopper structure shown in FIG. 1 of JP-A-9-321282 is applied will be described below with reference to FIG. The field portion having the gate polysilicon wiring layer on the field oxide film shown in Japanese Patent Application No. 9-261433 will not be illustrated and described, and only the cell portion and the outer peripheral portion will be described. In the figure, reference numeral 1 denotes a semiconductor body, which is composed of a high-concentration N-type N + type semiconductor substrate 2 and an epitaxial layer 3 provided on the surface of the semiconductor substrate 2. The epitaxial layer 3 is divided into a cell portion A and an outer peripheral portion B in the plane direction. In the cell portion A, a P-type first base region 4 selectively provided on this surface layer and a surface layer of this base region 4 are formed. It includes an N + type source region 5 selectively provided, and a low concentration N type N− type drain region 6 which is an original region of the epitaxial layer 3 provided with the base region 4 and the source region 5. A groove 7 penetrating the source region 5 from the surface of the source region 5 is formed. Outer B
A P-type second base region 14 selectively provided simultaneously with the base region 4 on this surface layer, and an N + type diffusion region 15 selectively provided simultaneously with the source region 5 at the surface layer of this base region 14. , Including a cell region A and a common drain region 6,
Simultaneously with the groove 7, from the surface of the N + type diffusion region 15 to the base region 1
A step 19 up to 4 is formed. On the surface of the cell portion A, a polysilicon gate electrode 9 is provided at a position between the source region 5 and the drain region 6 on the surface of the base region 4 with a gate oxide film 8 interposed therebetween. On the surface of the outer peripheral portion B, a field oxide film 13 provided in the field portion is provided so as to extend to a position separated from the outer peripheral end on the drain region 6 by a predetermined distance, and further, from the N + type diffusion region 15 to the field oxide film 13. An EQR polysilicon electrode 17 whose edge on the field oxide film 13 side is on the field oxide film 13 is provided via the gate oxide film 16, and a groove 18 penetrating the EQR polysilicon electrode 17 is formed. still,
Depending on the thickness of the EQR polysilicon electrode 17, the groove 18 is formed only in the EQR polysilicon electrode 17. Except for a part of the surface of the source region 5 on the groove 7 side on the cell part A and on the surface of the gate electrode 9 and on the outer peripheral part B, a part of the surface of the EQR polysilicon electrode 17 on the groove 18 side is excluded. Position, on the field oxide film 13 and N +
The interlayer insulating film 10 is provided on the surface of the mold diffusion region 15 except for a part on the step 19 side. On the cell portion A, the source electrode 11 made of aluminum is formed on the surface of the interlayer insulating film 10, a part of the surface of the source region 5 on the groove 7 side and in the groove 7.
Is provided. On the outer peripheral portion B, on the surface of the interlayer insulating film 10, in the groove 18, on a part of the surface of the N + -type diffusion region 15 on the step 19 side and at a position except the scribe region D of the step 19, the EQR metal is formed at the same time as the source electrode 11. An electrode 20 is provided. A drain electrode 12 is provided on the back surface of the semiconductor substrate 2.

[0004]

In the MOSFET having the above structure, the EQR metal electrode 20 is formed in the drain region 6 in the groove 18 depending on the thickness of the EQR polysilicon electrode 17.
Therefore, the depletion layer from the field portion side cannot extend from the position of the groove 18 to the outer circumference, and there is a risk that the depletion layer will not function as a channel stopper structure. Therefore, the present invention has been made to solve the above-described problems, and an insulation functioning as a channel stopper structure is obtained by making electrical contact between an EQR polysilicon electrode and an EQR metal electrode at an end surface of the EQR polysilicon electrode. and to provide a method of manufacturing a gate semiconductor equipment.

[0005]

According to a first aspect of the present invention, there is provided a method of manufacturing an insulated gate semiconductor device, which comprises a low-concentration one conductivity type having a cell portion and an outer peripheral portion surrounding the cell portion in a plane direction. A field oxide film is formed on the surface of the semiconductor body, and the field oxide film is removed from the outer peripheral edge of the cell portion and the outer peripheral portion of the semiconductor body surface to a position separated by a predetermined distance to the inside. Forming a first gate oxide film and a second gate oxide film on the outer peripheral surface,
After that, a polysilicon film is deposited on the semiconductor body, the polysilicon film is selectively removed, and a gate electrode is formed through the first gate oxide film and an EQR polysilicon electrode is formed through the second gate oxide film. Using the gate electrode as a mask, another conductivity type first base region is formed on the surface layer of the cell portion of the semiconductor body, and a high-concentration one conductivity type source region is formed on the surface layer of the first base region, and the semiconductor is masked using the EQR polysilicon electrode. A first step of forming another conductivity type second base region simultaneously with the first base region on the outer peripheral surface layer of the body, and a high concentration one conductivity type diffusion region simultaneously with the source region on the second base region surface layer; After completion of one step, an interlayer insulating film is deposited on the semiconductor body, and the source region, the edge on the one conductivity type diffusion region side of the EQR polysilicon electrode and the one conductivity type diffusion region are formed thereon. A second step of forming a resist pattern having a window on the surface, and after the second step is completed, the interlayer insulating film is wet-etched using the resist pattern as a mask to form the source region surface and one conductivity type of the EQR polysilicon electrode. A third step of exposing the surfaces of the edge and the end surface on the side of the diffusion region; and, after completing the third step, the source region exposed with the resist pattern as a mask, and EQR
Ions are etched from the edge of the polysilicon electrode on the one conductivity type diffusion region side and the surface of the one conductivity type diffusion region to penetrate the source region and the one conductivity type diffusion region to form the first base region and the second base region. A fourth step of forming a groove up to a part, and after completing the fourth step, the resist pattern is removed, an aluminum film is deposited on the semiconductor body, and the aluminum film is selectively removed to form a groove on the surface of the source region. Forming a source electrode electrically connected to a part of the side and the inner surface of the groove of the source region and the first base region, and forming a part of the surface of the one conductivity type diffusion region on the groove side and the surface of the one conductivity type diffusion region to the groove. , E
A fifth step of forming an EQR metal electrode electrically connected to the surface and the end surface of the edge of the QR polysilicon electrode on the one conductivity type diffusion region side. According to the above means, the source region is formed by self-alignment without using the photolithography method, and the source electrode and the base region are connected to each other by forming the groove penetrating the source region by using the opening of the resist pattern. In this case, when the resist pattern is formed, the EQR metal electrode electrically connected to the high-concentration one-conductivity type diffusion region is formed by forming the resist pattern having an opening at the edge position of the EQR polysilicon electrode.
When the EQR metal electrode is contacted to the EQR polysilicon electrode without increasing the photolithography process, it is electrically connected to the R polysilicon electrode at the surface and end face of the edge, so that the EQR metal electrode contacts the EQR polysilicon electrode. The penetration does not make contact with the drain region, and the EQR metal electrode and the EQR polysilicon electrode can sufficiently function as a channel stopper. A method for manufacturing an insulated gate semiconductor device according to a second aspect of the present invention is the method according to the first aspect , wherein the resist pattern has a mesh-shaped opening pattern on one conductivity type diffusion region. According to the above means, since the resist pattern has the mesh-shaped opening on the high-concentration one-conductivity type diffusion region in the outer peripheral portion, the one-conductivity type diffusion region penetrates from the surface of the one-conductivity type diffusion region to the outer peripheral part. It is possible to manufacture an insulated gate semiconductor device in which a groove is formed in a mesh shape and can be connected to an EQR metal electrode with sufficient contact with the one conductivity type diffusion region around the groove inner surface and one conductivity type diffusion region surface. When the manufactured insulated gate semiconductor device is cut from the wafer as a chip in the scribe region, the cut surface has the same potential on the back surface and the front surface due to processing strain, and one conductivity type diffusion area is exposed on the front surface side of the cut surface to cause EQR. The electrode surely has the same potential as the drain electrode,
The EQR metal electrode functions as a channel stopper. A method for manufacturing an insulated gate semiconductor device according to a third aspect of the present invention is the method according to the first aspect , wherein the resist pattern has a vertical stripe-shaped opening pattern on the outer peripheral edge on one conductivity type diffusion region. According to the above means, the resist pattern has the stripe-shaped opening perpendicular to the outer peripheral edge on the high-concentration one-conductivity type diffusion region in the outer peripheral portion, so that the one-conductivity type diffusion region is formed in the outer peripheral part from the one-conductivity type diffusion region surface. A groove penetrating the diffusion region is formed in a stripe shape perpendicular to the outer peripheral edge,
It is possible to manufacture an insulated gate semiconductor device which can be connected to the EQR metal electrode with sufficient contact with the one conductivity type diffusion region around the groove inner surface and the one conductivity type diffusion region surface, and the insulated gate semiconductor device manufactured by this method can be manufactured. When the wafer is cut in the scribe region as a chip, the cut surface has the same potential on the back surface and the front surface due to processing strain, and one conductivity type diffusion region is exposed on the front surface side of the cut surface, and the EQR electrode is surely the same as the drain electrode. A potential is applied and the EQR metal electrode functions as a channel stopper. Further, claim 4 of the present invention
The method for manufacturing an insulated gate semiconductor device according to claim 1,
In the method according to, the wet etching consists of just etching and over-etching. With the resist pattern as a mask, the interlayer insulating film is just-etched and then over-etched for a predetermined time. Can be exposed.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION A MOSFET and a method of manufacturing the same according to a first embodiment of the present invention will be described below with reference to FIGS.
Will be described with reference to. First, the configuration will be described. In FIG. 1, (a) is a cross-sectional view of the cell portion, (b) is a plan view of the surface of the semiconductor body 21 in the outer peripheral portion B, and (c) is A- in the plan view. A sectional view, (d) is B- in the plan view
FIG. 2 is a sectional view taken along the line B, in which a semiconductor body 21 is composed of an N + type semiconductor substrate 22 of a high concentration and one conductivity type, and an epitaxial layer 23 provided on the surface of the semiconductor substrate 22. The epitaxial layer 23 is divided into a cell portion A and an outer peripheral portion B surrounding the cell portion in the plane direction, and the cell portion A has a P-type first base region 24 as another conductivity type selectively provided on the surface layer. The N + type source region 25 selectively provided in the surface layer of the base region 24 and the low concentration N type which is the region as it is in the epitaxial layer 23 provided with the base region 24 and the source region 25. N- type drain region 2
6 is formed, the groove 27 penetrating the source region 25 from the surface of the source region 25 is formed. In the outer peripheral portion B, a P-type second base region 34 selectively provided simultaneously with the base region 24 in this surface layer, and an N + type diffusion region selectively provided simultaneously with the source region 25 in the surface layer of this base region 34. Area 35
And a drain region 26 common to the cell portion A,
Simultaneously with 7, a groove 39 penetrating the N + type diffusion region 35 from the surface of the N + type diffusion region 35 is formed in a mesh shape. On the surface of the cell portion A, a polysilicon gate electrode 29 is provided on the surface of the base region 24 at a position sandwiched by the source region 25 and the drain region 26 with a gate oxide film 28 interposed therebetween. On the surface of the outer peripheral portion B, a field oxide film 33 provided in the field portion is provided so as to extend to a position separated from the outer peripheral edge on the drain region 26 by a predetermined distance, and further, from the N + type diffusion region 35 to the field oxide film 33. An EQR polysilicon electrode 37 having an edge on the side of the field oxide film 33 on the field oxide film 33 via the gate oxide film 36 is provided. On the cell part A, the source region 2
5 on the surface except for a part on the groove 27 side and on the surface of the gate electrode 29, and on the outer peripheral portion B on a position on the surface of the EQR polysilicon electrode 37 except for a part on the groove 39 side, the field oxide film 33. An interlayer insulating film 30 is provided on the top and on the position of the surface of the N + type diffusion region 35 excluding the groove periphery 41. On the cell portion A, an aluminum source electrode 31 is provided on the surface of the interlayer insulating film 30, a part of the surface of the source region 25 on the groove 27 side and in the groove 27. On the outer peripheral portion B, the interlayer insulating film 3 at the position excluding the scribe region D
0 at the same time as the source electrode 31 on the surface 0, in the groove 39, and on the groove 41 on the surface of the N + -type diffusion region 35.
A QR metal electrode 40 is provided. A drain electrode 32 is provided on the back surface of the semiconductor substrate 22.

According to the above structure, when the MOSFET is cut from the wafer as a chip in the scribe region D, the cut surface E has the same potential on the back surface and the front surface due to processing strain, and the cut surface E has the N + type on the front surface side. The diffusion region 35 is exposed, and the inner surface of the groove 39 formed in the N + type diffusion region 35 in a mesh shape and the groove periphery 41 on the surface of the N + type diffusion region 35.
Since the EQR metal electrode 40 connected with sufficient contact with the back electrode is surely at the same potential as the back surface electrode, and the EQR metal electrode 40 is electrically connected to the EQR polysilicon electrode 37 at the edge surface and the end surface, the photolithography process is performed. To the EQR polysilicon electrode 37 without increasing
When making contact with the QR metal electrode 40, the EQR metal electrode 40 does not come into contact with the drain region by penetrating the EQR polysilicon electrode 37, and the EQR metal electrode 40 does not come into contact with the drain region.
The metal electrode 40 and the EQR polysilicon electrode 37 can sufficiently function as a channel stopper.

Next, the manufacturing method will be described with reference to FIGS.
Will be described with reference to. In the following description, (a)-
Each item symbol of (d) corresponds to each of (a) to (d) of FIG. (A) A field oxide film 33 is formed by a thermal oxidation method on the surface of a semiconductor body 21 in which an epitaxial layer 23 containing a low concentration of N-type impurities is grown on the surface of an N + type semiconductor substrate 22 to form an epitaxial layer 23. It is divided into a cell portion A and an outer peripheral portion B. Then, the field oxide film 33 on the cell portion A having a predetermined width is removed from the outer peripheral edge on the outer peripheral portion B by the photolithography method and the etching method, and on the surface of the cell portion A on which the field oxide film 33 is removed by the thermal oxidation method. Then, a second gate oxide film 36 is formed on the first gate oxide film 28 and the outer peripheral portion B. Next, these oxide films 33, 28, 3
6 a polysilicon film is deposited on the surface, the polysilicon film and the gate oxide films 28 and 36 are selectively removed by the photolithography method and the etching method, and left on the cell portion A via the gate oxide film 28. The gate electrode 29 is formed of the polysilicon film and the EQR polysilicon electrode 37 is formed of the polysilicon film left on the outer peripheral portion B via the gate oxide film 36 adjacent to the field oxide film 33. The edge of the EQR polysilicon electrode 37 on the field oxide film 33 side is formed on the field oxide film 33. Next, using the gate electrode 29 in the cell portion A and the field oxide film 33 and the EQR polysilicon electrode 37 in the outer peripheral portion B as a mask, boron and arsenic are sequentially ion-implanted and thermally diffused to the cell portion A to form the P-type first electrode.
The base region 24 and the N + type source region 25 are formed, and the P type second base region 34 and the N + type diffusion region 35 are formed in the outer peripheral portion B. The original region of the epitaxial layer 23 in which these regions are formed becomes the N-type drain region 26. (B) Next, an interlayer insulating film 30 is deposited on the semiconductor body 21 after the step (a) is completed, and the N + type of the EQR polysilicon electrode 37 and the surface of the source region 25 are formed on the interlayer insulating film 30 by photolithography. Openings 51 and 52 are formed on the edge of the diffusion region 35 side and on the surface of the N + type diffusion region 35, respectively.
A resist pattern 53 having is formed. The opening 52 is a mesh pattern. (C) Next, each opening 51 of the resist pattern is formed by wet etching using the resist pattern 53 as a mask.
52, the interlayer insulating film 30 under the source region 25 and the EQ.
Just etching is performed until the surface and end surface of the edge of the R polysilicon electrode 37 on the N + type diffusion region 35 side and the surface of the N + type diffusion region 35 are exposed, and overetching is performed for a predetermined time so that the exposed area is a resist pattern. Contact holes 54 and 55 larger than the opening areas of 53 are formed. (D) Next, the resist pattern 53 used in the step (c)
Using the mask as a mask again, trenches 27 and 39 are formed from the exposed surface of the semiconductor main body 21 by penetrating the source region 25 and the N + type diffusion region 35 by ion etching. At this time, at the same time, the edge of the exposed EQR polysilicon electrode 37 on the N + type diffusion region 35 side is also etched according to the opening 52 of the resist pattern 53. Depending on the thickness of the EQR polysilicon electrode 37, the EQR polysilicon electrode 37 may not be etched down. After the above steps are completed, the resist pattern 53 is removed as shown in FIG. 1, an aluminum film is deposited on the semiconductor body 21 by vacuum vapor deposition, and the aluminum film is selectively formed by photolithography and etching. The source electrode 31 that is removed and electrically connected to the source region 25 and the base region 24, the edge of the EQR polysilicon electrode 37 on the N + type diffusion region 35 side, the N + type diffusion region 35, and the base region 34 are electrically connected. The EQR metal electrode 40 to be electrically connected is formed, and metal is vapor-deposited on the back surface of the semiconductor body 21 to form the drain electrode 32.

According to the above method, the source region 25 is formed in a self-aligned manner with the gate electrode without using the photolithography method, and the source electrode 31 and the base region 24 are connected to each other by a resist pattern for contacting the source electrode. Forming a groove 27 that penetrates the source region 25 using the opening of
In the step (b), the EQR polysilicon electrode 3 on the outer peripheral portion B
7, an outer peripheral portion B is formed by forming a resist pattern 53 having a mesh-shaped opening 52 on the edge of the N + type diffusion region 35 side and the surface of the N + type diffusion region 35.
A groove 39 penetrating from the surface of the N + type diffusion region 35 to the N + type diffusion region 35 is formed in a mesh shape, and the N + type diffusion region is formed on the inner surface of the groove 39 and around the groove 41 on the surface of the N + type diffusion region 35. 35 can form an EQR metal electrode 40 connected with sufficient contacts, and when this MOSFET is cut as a chip from the wafer in the scribe region D,
The cut surface E has the same potential on the back surface and the front surface due to processing strain, the N + type diffusion region 35 is exposed on the front surface side of the cut surface E, and the EQR metal electrode 40 surely has the same potential as the drain electrode 32. Since the metal electrode 40 is electrically connected to the EQR polysilicon electrode 37 at the edge surface and the end face, when the EQR metal electrode 40 is contacted with the EQR polysilicon electrode 37 without increasing the photolithography process, the EQR metal electrode The EQR metal electrode 40 and the EQR polysilicon electrode 37 can sufficiently function as a channel stopper without being in contact with the drain region by penetrating the EQR polysilicon electrode 37.

Next, the MOS of the second embodiment according to the present invention will be described.
The FET will be described with reference to FIG. In the figure, (a)
Is a cross-sectional view of the cell portion, (b) is a plan view of the surface of the semiconductor body 61 in the outer peripheral portion B, and (c) is A in the plan view.
-A sectional view, (d) is a BB sectional view in the plan view,
(E) is a cross-sectional view taken along the line CC of the plan view,
Reference numeral 61 denotes a semiconductor body, which comprises an N + type semiconductor substrate 62 and an epitaxial layer 63 provided on the surface of the semiconductor substrate 62. The epitaxial layer 63 is divided into a cell portion A and an outer peripheral portion B in the plane direction. In the cell portion A, a P-type first base region 64 selectively provided in this surface layer and a surface layer of this base region 64 are formed. N + type source region 65 selectively provided
And the N − -type drain region 66 which is the original region of the epitaxial layer 63 in which the base region 64 and the source region 65 are provided, and a groove 67 which penetrates the source region 65 from the surface of the source region 65 is formed. ing. In the outer peripheral portion B, P which is selectively provided on this surface layer at the same time as the base region 64 is provided.
A second type base region 74, an N + type diffusion region 75 selectively provided at the same time as the source region 65 in the surface layer of the base region 74, a drain region 66 common to the cell portion A, and a groove 67. At the same time, trenches 79 penetrating the N + type diffusion region 75 from the surface of the N + type diffusion region 75 are formed in stripes. On the surface of the cell portion A, the gate electrode 6 made of polysilicon is formed at a position between the source region 65 and the drain region 66 on the surface of the base region 64 with the gate oxide film 68 interposed therebetween.
9 is provided. The drain region 66 is formed on the surface of the outer peripheral portion B.
A field oxide film 73 provided in the field portion is provided so as to extend to a position separated from the upper peripheral edge by a predetermined distance, and further, a field oxide film is provided from the N + type diffusion region 75 to the field oxide film 73 via a gate oxide film 76. An EQR polysilicon electrode 77 whose edge on the 73 side is on the field oxide film 73 is provided. On the cell portion A, on the position of the surface of the source region 65 excluding a part on the groove 67 side, on the surface of the gate electrode 69, and in the outer peripheral portion B, EQR
On the surface of the polysilicon electrode 77 except for a part on the groove 79 side, on the field oxide film 73 and the N + type diffusion region 7.
The interlayer insulating film 70 is provided on the surface of the surface 5 except the groove 81. On the cell portion A, on the surface of the interlayer insulating film 70, on a part of the surface of the source region 65 on the groove 67 side, and on the groove 6.
A source electrode 71 made of aluminum is provided inside 7. On the outer peripheral portion B, the EQR is formed simultaneously with the source electrode 71 on the surface of the interlayer insulating film 70 except the scribe region, in the groove 79, and on a part of the surface of the N + type diffusion region 75 on the groove 79 side.
A metal electrode 80 is provided. A drain electrode 72 is provided on the back surface of the semiconductor substrate 62.

According to the above structure, when the MOSFET is cut as a chip from the wafer in the scribe region D, the cut surface E has the same potential on the back surface and the front surface due to processing strain, and the cut surface E has an N + type on the front surface side. The diffusion region 75 is exposed and the inner surface of the groove 79 formed in a stripe shape in the N + type diffusion region 75 and the groove periphery 8 on the surface of the N + type diffusion region 75
EQR metal electrode 80 connected with one sufficient contact
Is surely at the same potential as the back surface electrode 72, and the EQR metal electrode 80 is electrically connected to the EQR polysilicon electrode 77 at the front surface and the end surface of the edge. Therefore, the EQR polysilicon electrode 77 is not increased in the photolithography process.
When making contact with the EQR metal electrode 80 to
The R metal electrode 80 does not come into contact with the drain region 106 by penetrating the EQR polysilicon electrode 77, and the EQR metal electrode 80 and the EQR polysilicon electrode 77 can sufficiently function as a channel stopper. As for the method of manufacturing the MOSFET having the above-described structure, the first embodiment uses the resist pattern 53 having the mesh-shaped opening 52 at the position on the surface of the N + type diffusion region 35 in the outer peripheral portion B, while the stripe-shaped resist pattern 53 is used. The description is omitted because it is the same as that of the first embodiment except that a resist pattern having a pattern opening is used.

Next, the MOS of the third embodiment according to the present invention will be described.
The FET will be described with reference to FIG. In the figure, (a)
Is a cross-sectional view of the cell portion, (b) is a plan view of the surface of the semiconductor body 101 in the outer peripheral portion B, and (c) is a cross-sectional view taken along the line AA in the plan view. ,
An N + type semiconductor substrate 102 of one conductivity type of high concentration;
The epitaxial layer 103 is provided on the surface of the semiconductor substrate 102. The epitaxial layer 103 is divided into a cell portion A and an outer peripheral portion B in the plane direction, and in the cell portion A, a P-type first base region 104 as another conductivity type selectively provided on this surface layer and this base region. An N + type source region 105 selectively provided on the surface layer of 104 and a base region 10
4 and the epitaxial layer 1 provided with the source region 105
N- type drain region 106 which is the original region of 03.
From the surface of the source region 105 to the source region 105.
To form a groove 107 that penetrates through. In the outer peripheral portion B, a P-type second base region 114 selectively provided in the surface layer simultaneously with the base region 104, and an N + type diffusion region selectively provided in the surface layer of the base region 114 at the same time as the source region 105. The region 115 and the drain region 106 common to the cell portion A
At the same time as the groove 107, a step 119 from the surface of the N + type diffusion region 115 to the base region 104 is formed. On the surface of the cell portion A, a polysilicon gate electrode 109 is provided on the surface of the base region 104 at a position sandwiched by the source region 105 and the drain region 106 with a gate oxide film 108 interposed therebetween. On the surface of the outer peripheral portion B, a field oxide film 113 provided in the field portion is provided so as to extend to a position apart from the outer peripheral end on the drain region 106 by a predetermined distance, and further, from the N + type diffusion region 115 to the field oxide film 113. The edge on the side of the field oxide film 113 through the gate oxide film 116 is the field oxide film 113.
An EQR polysilicon electrode 117 to be the upper side is provided.
On the cell portion A, the groove 107 on the surface of the source region 105.
EQR polysilicon electrode 117 on the position except a part of the side, on the surface of the gate electrode 109, and on the outer peripheral portion B.
The interlayer insulating film 110 is provided on the position except for a part of the surface on the step 119 side and on the field oxide film 113.
On the cell portion A, an aluminum source electrode 111 is provided on the surface of the interlayer insulating film 110, a part of the surface of the source region 105 on the groove 107 side and in the groove 107. On the outer peripheral portion B, a step 119 is formed on the surface of the interlayer insulating film 110.
An EQR metal electrode 120 is provided inside the source electrode 111 at the same time. A drain electrode 112 is provided on the back surface of the semiconductor substrate 102.

According to the above structure, when the MOSFET is cut from the wafer as a chip in the scribe region D, the cut surface E has the same potential on the back surface and the front surface due to processing strain, and the cut surface E has the N + type on the front surface side. Diffusion area 115
Is exposed and the step 11 formed in the N + type diffusion region 115 is exposed.
9. The EQR metal electrode 120 connected on the inner surface is the back electrode 1
12 has the same potential, and the EQR metal electrode 120 has E
Since it is electrically connected to the QR polysilicon electrode 117 at the surface and the end face of the edge, the EQR to the EQR polysilicon electrode 117 can be increased without increasing the photolithography process.
When making contact with the metal electrode 120, the EQR metal electrode 120 does not come into contact with the drain region 106 by penetrating the EQR polysilicon electrode 117, and the EQR metal electrode 120 and the EQR polysilicon electrode 117 function as channel stoppers. be able to. In this embodiment, the N + type diffusion region 115 is partially left near the edge of the EQR polysilicon electrode 117, and the surface side of the cut surface E has the N + type diffusion region 115 connected to the EQR metal electrode 120. Since it is not exposed and is the P type base region 114, the function as a channel stopper is weaker than in the first and second embodiments. It should be noted that the manufacturing method of the MOSFET having the above-mentioned configuration is described in
Is a resist pattern 53 having a mesh-shaped opening 52 at a position on the surface of the N + type diffusion region 35 in the outer peripheral portion B.
1 is used, but a resist pattern having an opening up to the edge of the EQR polysilicon electrode is used, and the description thereof is omitted.

In the above embodiment, the N type is used as one conductivity type and the P type is used as the other conductivity type. However, the one conductivity type may be P type and the other conductivity type may be N type. Further, the semiconductor substrate has been described as one conductivity type of high concentration, but it may be of another conductivity type of high concentration. In this case, it can be used for a conductivity modulation type MOSFET. Further, although the semiconductor body has been described as the one in which the epitaxial layer is grown on the semiconductor substrate, it may be only the semiconductor substrate. In this case, the drain region, the base region and the source region are included in the semiconductor substrate.

[0015]

According to the manufacturing method of the present invention, the source region is formed by self-alignment without using the photolithography method, and the connection between the source electrode and the base region is made through the source region by utilizing the opening of the resist pattern. When forming a groove to be formed in the groove, a resist pattern having an opening at an edge position of the EQR polysilicon electrode is formed when the resist pattern is formed. The connected EQR metal electrode is EQ
When the EQR metal electrode is contacted to the EQR polysilicon electrode without increasing the photolithography process, it is electrically connected to the R polysilicon electrode at the surface and end face of the edge, so that the EQR metal electrode contacts the EQR polysilicon electrode. An EQR metal electrode and an EQR polysilicon electrode can sufficiently function as a channel stopper without penetrating and contacting a drain region, and a highly reliable method of manufacturing an insulated gate semiconductor device is provided. it can.

[Brief description of drawings]

FIG. 1 is a vertical MOSFET according to a first embodiment of the present invention.
Drawing showing the structure of. (A) is a sectional view of a cell portion, (b) is a plan view of an outer peripheral portion, (c) is a sectional view taken along line AA of (b),
(D) is a BB sectional view of (b).

FIG. 2 is a sectional view of a main portion showing a manufacturing process of the vertical MOSFET shown in FIG.

FIG. 3 is a vertical MOSFET according to a second embodiment of the present invention.
Drawing showing the structure of. (A) is a sectional view of a cell portion, (b) is a plan view of an outer peripheral portion, (c) is a sectional view taken along line AA of (b),
(D) is a sectional view taken along line BB of (b), and (e) is taken along line C- of (b).
It is C sectional drawing.

FIG. 4 is a vertical MOSFET that is a third embodiment of the present invention.
Drawing showing the structure of. (A) is sectional drawing of a cell part, (b) is a top view of an outer peripheral part, (c) is an AA sectional view of (b).

FIG. 5: Vertical MOSFET formed using a conventional technique
Main section cross-section

[Explanation of symbols]

21, 61, 101 Semiconductor body 22, 62, 102 N + type semiconductor substrate 23,63,103 Epitaxial layer 24, 64, 104 P type first base region 25,65,105 N + type source region 26, 66, 106 N- type drain region 27, 67, 107 groove 28, 68, 108 First gate oxide film 29,69,109 Gate electrode 30, 70, 110 Interlayer insulation film 31, 71, 111 Source electrode 33,73,113 Field oxide film 53 resist pattern 34,74,114 P type second base region 35,75,115 N + type diffusion region 36,76,116 Second gate oxide film 37,77,117 EQR polysilicon electrode 39, 79, 119 Groove or step A cell section B outer circumference D scribe area

Claims (4)

(57) [Claims] 1. A field oxide film is formed on a surface of a low-concentration one conductivity type semiconductor body having a section of a cell portion and a peripheral portion surrounding the cell portion in a plane direction, and a field oxide film is formed on the surface of the semiconductor body. The field oxide film is removed from the outer peripheral edge to a position separated by a predetermined distance, and the first gate oxide film is formed on the cell part where the field oxide film is removed and the second part is formed on the outer peripheral surface.
A gate oxide film is formed, a polysilicon film is then deposited on the semiconductor body, the polysilicon film is selectively removed, and an EQR is formed through the first gate oxide film and the gate electrode and the second gate oxide film. A polysilicon electrode is formed, another conductive type first base region is formed on the surface layer of the cell portion of the semiconductor body using the gate electrode as a mask, and a high-concentration one conductive type source region is formed on the surface layer of the first base region. First with the polysilicon electrode as a mask on the outer surface layer of the semiconductor body
At the same time as the base region, the second base region of the other conductivity type and the second base region
A first step of forming a high-concentration one-conductivity type diffusion region at the same time as the source region in the surface layer of the base region, and after completing the first step, depositing an interlayer insulating film on the semiconductor body, Forming a resist pattern having a window on the edge of the one-conductive type diffusion region side of the EQR polysilicon electrode and on the one-conductive type diffusion region
After the step and the second step are completed, the interlayer insulating film is wet-etched using the resist pattern as a mask to form the source region surface and the surface and end face of the one-conductive-type diffusion region side edge of the EQR polysilicon electrode. A third step of exposing the surface of the one conductivity type diffusion region, and a source region exposed by the resist pattern as a mask after completion of the third step, an edge of the EQR polysilicon electrode on the one conductivity type diffusion region side, A fourth step of ion etching from the surface of the one-conductivity type diffusion region to form a groove or a step penetrating the source region and the one-conductivity type diffusion region to a part of the first base region and the second base region; After the completion of the fourth step, the resist pattern is removed, an aluminum film is deposited on the semiconductor body, and the aluminum film is selectively removed to form a groove on the surface of the source region. Forming a source electrode electrically connected to a part of the source region and the inner surface of the groove of the source region and the first base region, and forming a part of the surface of the one conductivity type diffusion region on the groove side and the inner surface of the groove of the one conductivity type diffusion region; A fifth step of forming an EQR metal electrode electrically connected to a surface and an end surface of the edge of the EQR polysilicon electrode on the one-conductivity type diffusion region side, and a fifth step of manufacturing the insulated gate semiconductor device. 2. A method according to claim 1 Symbol with the resist pattern is meshed opening pattern in the one conductivity type diffusion region
Method for manufacturing mounted insulated gate semiconductor device. 3. The process for producing the resist pattern according to claim 1, further comprising a vertical stripe-shaped opening pattern on the outer peripheral edge at the one conductivity type diffusion region insulated gate semiconductor device. 4. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein the wet etching includes just etching and over etching.