JP3421895B2 - Zener diode - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance of a semiconductor device.
The present invention relates to a Zener diode used for trimming. [0002] 2. Description of the Related Art Devices mounted on a VLSI are highly accurate.
There is trimming as a technique to make it more sophisticated. For example, a resistor bird
Laser cutting, aluminum huing
And Zener Zap. According to the above zener zap
Trimming is easy with existing device measuring equipment.
-Useful because zapping of diodes is possible
It has begun to be adopted as a trimming technique. FIG. 8 shows a circuit used in the trimming circuit.
It is sectional drawing of a Zener diode. This zener die
Ode 8 is epitaxially grown on silicon substrate 81
N-type silicon epitaxial layer
Layer) 82 and a P layer disposed on the surface layer of the N epi layer 82.
83 made of a type impurity layer;
Cathode 84 composed of an N-type impurity layer disposed on the surface layer
And The anode 83 and the cathode 84
Are connected to wirings 85 made of aluminum, respectively.
ing. The anode 83 and the cathode 84 are
By diffusing impurities into the surface layer of the
And the anode 83 and the cathode 84
Between the homojunction of N-type silicon and P-type silicon
An action is formed. In addition, the NPN transistor
Since Zener yielding occurs between the transmitter and base,
As shown, an NPN transistor using the N epi layer 82 as a collector
In the transistor, the base of the transistor is
With a cathode 83 and an emitter with a cathode 84
It may be a diode. In this case, the N epi layer
82 is connected to the N-type embedded layer 85 via an N-type
Short-circuits the lag region 86 and the cathode 84 that becomes the emitter
It can also be used. [0004] Then, the resistance trimming by zener zap
In FIG. 9, the Zener diode shown in FIG.
Such a trimming circuit is configured. This trimming times
The path is connected in series with a resistor r₁~ R_ThreeResistor R
And the resistance r_Two, R_ThreeZener connected in parallel to
-Diode d₁, D_TwoAnd have these Zenadas
Iod d₁, D_TwoIs the Zener diode
d ₁, D_TwoReverse bias between anode and cathode
Trimming pad p for applying and zapping₁
~ P_ThreeIs connected. Trimming circuit with the above configuration
Indicates that the elements formed on the IC normally operate.
Zener diode d₁, D_TwoReverse bias is applied to
To be implemented on the IC. The trimming circuit performs trimming.
If not, the voltage for normal operation of the IC
Diode d₁, D_TwoReverse anode between anode and cathode
Applied as ias. In this state, Zena
-Diode d₁, D_TwoResistance is very high.
Ener diode d₁, D_TwoNo current flows through the resistor R
= R₁+ R_Two+ R_Threebecome. Meanwhile, by trimming
Resistance R = r₁If you want to use
₁~ P_TwoUsing a Zener diode d₁, D _TwoReverse
An excessive current flows by applying bias and Zener diode
d₁, D_TwoZapping. This allows Zener
Diode d₁, D_TwoWith a resistance of about 20 to 30Ω
Low resistance and resistance r_Two, R_ThreeAnd bypass the resistor R
= R₁To [0006] However, the above-mentioned Zener
In trimming by zap, the zener diode
Before trimming, the trimming resistor is
Since the resistance value is smaller than that of the
Excessive current from the trimming pad is
To other elements connected to the For this reason,
Flow to other elements connected to the trimming circuit.
Electrical damage causes reliability problems
Is concerned. [0007] To prevent this, the anode and the capacitor
Increase the impurity concentration in the sword to lower the reverse bias.
The zener diode breaks down by applying
Need to be updated. However, the impurity concentration in silicon
Has a solid solution limit, so the Zener die
Limit to reduce withstand voltage against reverse bias with ode
There is. [0008] SUMMARY OF THE INVENTION Therefore, the zener of the present invention is disclosed.
In diodes, less of the anode and cathode
Or one of them, Zener than silicon and silicon
It is composed of a compound semiconductor made of a semiconductor material that easily yields.
Is a means for solving the above problem. Ma
In addition, germanium is used as the semiconductor material. In the above Zener diode, the anode and the
One of the cathode and cathode is silicon and silicon
Compound consisting of semiconductor material that is more susceptible to Zener breakdown than
Since it is composed of semiconductors, silicon
Compared to a Zener diode with a mojunction
Therefore, the breakdown voltage when a reverse bias is applied,
-The breakdown voltage decreases. Because of this, this Zenada
In a trimming circuit using an ion,
The zener diode is zapped. [0010] BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a Zener diode according to the present invention will be described.
The first to third embodiments of the present invention will be sequentially described based on the drawings.
You. In the description of each embodiment, the same component
Are denoted by the same reference numerals, and overlapping description will be omitted. FIG. 1 shows a Zener diode according to a first embodiment.
FIG. This Zener diode 1 is
An anode 11 disposed on the anode 10;
And a cathode 12 disposed thereon. Also,
The node 11 and the cathode 12 are each made of aluminum.
Wiring 15 is connected, and
Reverse bias is applied to the cathode 11 and the cathode 12.
It is configured as follows. The anode 11 is made of silicon (Si).
Consists of a semiconductor material that is more susceptible to Zener breakdown than Si
A layer formed by diffusing a P-type impurity in a compound semiconductor.
You. Here, the above-mentioned semiconductor material that easily undergoes Zener breakdown includes:
For example, germanium (Ge) is used. Ge is that
Is 8 [V / μm] and the breakdown field of Si is 30
Lower than [V / μm] and the transfer of electrons in Ge
The degree is 3900 [cm^Two/ Vsec] and the mobility of electrons in Si
1350 [cm^Two/ Vsec].
Even Zener surrenders easily. Further, the above-mentioned compound semiconductor of Ge and Si
(Si_1-xGe_x, Hereinafter referred to as SiGe).
1, the concentration of Ge in the SiGe
Means that when the anode 11 is heated,
Due to the difference in lattice constant from SiGe
The anode 11 is plastically deformed and does not generate crystal defects.
Value. Therefore, preferably, the substrate 10 is made of Si.
In this case, the content of Ge in SiGe was reduced to 15 wt.
Set to less than%. Further, Ge in SiGe
The concentration and the concentration of P-type impurity are
A trimming circuit using Zener Zap
At the voltage to operate the IC normally, the Zener diode
Withstand voltage as low as possible without zapping
Set to On the other hand, the cathode 12 has an N type in Si.
A layer formed by diffusing impurities or the anode 11
A layer formed by diffusing an N-type impurity into the same SiGe
You. When the cathode 12 is made of SiGe,
In this case, the concentration of Ge in the SiGe
The anode 11 and the cathode are heated when the cathode 11 and the cathode are heated.
Due to the difference in lattice constant from SiGe constituting the sword 12
As a result, the anode 11 and the cathode 12 are plastically deformed.
The value is set to a value that does not cause crystal defects. In addition, the Caso
The concentration of Ge and the concentration of impurities in the
Trim using zener diode for zener zap
Voltage for normal operation of an IC incorporating a switching circuit
As long as the zener diode is not zapped,
Set to have as low a breakdown voltage as possible. The cathode 12 is made of SiGe.
In this case, the anode 11 (first impurity layer) is made of Si.
It may be configured. In this case, too,
Concentration of Ge in SiGe Constituting Mode 12 and Cathode
The concentration of the N-type impurity in the gate 12 is set in the same manner as described above.
I do. Further, the Zener diode 1 is disposed.
The substrate 10 to be formed is, for example, a silicon substrate 101,
N-type silicon epitaxial layer formed on
Below, described as an N-epi layer) 102 and the N-epi layer 102
LOCOS (Local Oxidation of S
and an oxide film 106. And L
On the N epi layer 102 separated by the OCOS oxide film 106
The Zener diode 1 is disposed in the N-epi layer 102.
Plug region 107 formed on the N-type cathode 12
Is short-circuited by the wiring 15 so that the anode 11
An electrical separation state from the silicon substrate 101 is ensured.
You. In the Zener diode 1 having the above configuration, the A
One of the node 11 and the cathode 12 is S
A semiconductor material that is more likely to cause Zener breakdown than i and Si (for example,
Ge). this
Therefore, a tool with a homojunction made of Si
Compared to Zener diode, the above Zener diode
1 has a low withstand voltage against reverse bias. But
Therefore, this zener diode 1 is used as a zener zap.
The trimming circuit used in
The zener diode is zapped at a lower voltage
You. Therefore, the I in which the trimming circuit is incorporated is
In C, trimming of elements constituting the IC is performed.
Trimming with minimum voltage effect
It becomes possible. The trimming circuit is a conventional circuit.
A circuit similar to that described with reference to FIG.
Therefore, a detailed description of the circuit configuration is omitted. Hereinafter, the Zener diode will be described with reference to FIG.
A method for forming the mode 1 will be described. Here, the same substrate
The Zener diode and NPN bipolar transformer
The description will be made by taking the case of forming a resistor as an example. Destination
First, as shown in FIG. 2A, a P-type silicon substrate 10 is formed.
On top of this, an N layer having a resistivity of about 1 Ω · cm and a thickness of about 1 μm
The layer 102 is formed. This N epi layer 102 is
It becomes the collector layer of the bipolar transistor. Next, heat
The surface of the N-epi layer 102 is oxidized by about 30 nm.
A pad oxide film 103 having a film thickness is grown,
About 65μm by D (Chemical Vapor Deposition) method
The silicon nitride film 104 having a thickness of about
03 is formed. The pad oxide film 103 is performed next.
It serves as a buffer film during LOCOS oxidation.
The silicon oxide film 104 is used to prevent oxidation during the LOCOS oxidation.
It becomes a stop film. Next, a silicon nitride film is formed by lithography.
Forming a resist pattern 105 on the recon film 104
You. This resist pattern 105 is a LOCOS oxide film
Having an opening on a portion of the N-epi layer 102 where
Shape. After that, the resist pattern 105
(Reactive IonEtching) using
Thus, the silicon nitride film 104, the pad oxide film 103, and
The N epi layer 102 is etched. Next, as shown in FIG.
After removing the pattern (105), the temperature of about 1050 ° C.
Exposed from the silicon nitride film 104 by steam oxidation
The LO having a thickness of about 1.0 μm
A COS oxide film 106 is grown. Then, add hot phosphoric acid
By the wet etching used, the silicon nitride film 1
04 is removed. Next, a resist not shown here
By ion implantation using the pattern as a mask,
An N-type impurity such as phosphorus (P) is¹⁶
Pieces / cm^TwoIntroduce a degree. After that, at a temperature of about 1000 ° C
The N-type impurity activation heat treatment is performed in
The N-type impurity is not diffused to the surface side in the layer 102.
A plug region 107 is formed. Next, the resist pattern was removed.
Later, a new resist pattern (not shown) is masked.
LOCOS oxide film 10
6 such as boron (B) in the substrate 10 along the lower surface of
10 mold impurities¹⁴Pieces / cm^TwoIntroduce a degree. Then 9
The heat treatment for activating the P-type impurities at a temperature of about 50 ° C.
Then, the above P-type is formed on the lower surface of the LOCOS oxide film 106.
The isolation region 108 formed by diffusing impurities
Form. Next, after removing the resist pattern,
By wet etching using hydrofluoric acid-based chemicals,
The pad oxide film 103 on the N epi layer 102 is removed. Less than
By the above, the substrate 10 is formed. Next, as shown in FIG.
(Molecular Beam epitaxy), UHV (Ultra High Vac)
uum)-Includes P-type impurities by film forming technology such as CVD.
A first semiconductor layer 11a made of SiGe having a substrate 10
The epitaxial growth is performed thereon. This first semiconductor layer 11
a becomes the anode of the Zener diode and NP
It is a layer constituting the base of an N bipolar transistor.
You. Then, the first semiconductor layer 11a is continuously formed.
To contain an N-type impurity on the first semiconductor layer 11a.
Epitaxial growth of second semiconductor layer 12a made of Si
Let it. Next, as shown in FIG.
A resist pattern is formed on the second semiconductor layer 12a by the fee method.
Pattern 110 is formed, and the resist pattern 110 is
The second semiconductor layer 12a is etched using a mask. This
Thereby, the cathode made of the second semiconductor layer 12a
12 is formed. In addition, an NPN by-pass (not shown)
From the second semiconductor layer 12a to the polar transistor region
To form an emitter. Next, as shown in FIG.
After removing the strike pattern (110), the cathode 12 is
The resist pattern 1 is formed on the first semiconductor layer 11a in a state of covering.
11 is formed, and the resist pattern 111 is used as a mask.
Is used to etch the first semiconductor layer 11a. This
Thus, the anode 11 made of the first semiconductor layer 11a is
Form. Also, an NPN bipolar not shown here
A transistor made of the first semiconductor layer 11a is formed in the transistor region.
Form a base. Next, the resist pattern 11 is removed.
After that, as shown in FIG.
On the substrate 10 covering the node 11 and the cathode 12
A silicon oxide film 13 is formed. Then, silicon oxide
The resist pattern (not shown) formed on the film 13 is
The anode 11 and the cathode
To the plug region 107 on the surface of the substrate 12 and the substrate 10, respectively.
Each contact hole 14 that reaches the silicon oxide film
13 is formed. Thereafter, the lower layer is formed by sputtering film formation.
30 nm thick Ti (titanium) and 70 nm thick T
iON (titanium oxynitride), 30 nm thick Ti
A film is formed as a metal and aluminum
A wiring layer having a thickness of 0.7 μm is formed. Next,
A resist pattern (not shown) is formed on the line layer.
Using the resist pattern as a mask, the above wiring layer and burr
Etch a metal. Thereby, the anode 1
, Cathode 12 and plug region 10
7 is short-circuited to the wiring 15 connected to them.
Form. However, the wiring 15 is not necessarily a cathode.
It is not necessary to short-circuit 12 and plug region 107. Ma
In addition, by this etching, NP not shown here
The base, emitter and
The connection to each plug layer (collector extraction layer)
Form a line. As described above, the NPN bipolar transistor
The above Zener diode is manufactured in the same manufacturing process as
It is formed. FIG. 3 shows a Zener according to a second embodiment.
It is sectional drawing of an iod. The tool of the second embodiment shown here
Zener diode 2 and Zener die of the first embodiment
The difference from the ode lies in the configuration of the substrate 20. Sand
That is, the Zener diode 2 of the second embodiment has a high breakdown voltage.
On the substrate 20 constituting the NPN bipolar transistor
Is formed. Therefore, the Zener diode 2
Is the same manufacturing as high voltage NPN bipolar transistor
It is formed in a process. Note that the anode disposed on the substrate 20
The cathode 11 and the cathode 12 are the same as in the first embodiment.
It is constituted in. The Zener diode will be described below with reference to FIG.
A method for forming the mode 2 will be described. First, as shown in FIG.
As described above, by steam oxidation at about 950 ° C.,
The surface layer of the silicon substrate 101 has a thickness of about 300 nm.
A silicon oxide film 202 is grown. Next, here is the figure
Etching using resist pattern not shown as mask
Etching the silicon oxide film 202 with N⁺Buried
The silicon oxide film 202 on the region where the embedded layer is formed
Is removed. Next, for example, S
b_TwoO_ThreeSolid diffusion sources like (antimony oxide)
To diffuse Sb at a temperature of about 1200 ° C.
N on the surface layer of the recon substrate 101⁺Buried layer 203
To achieve. Next, as shown in FIG.
After removing the recon film (202), the capacitor of the first embodiment is removed.
2 (1) in the manufacturing of the
In the same manner as described above, the above
An N-epi layer 204 similar to that of the first embodiment is formed.
Then, the pad oxide film 205 and the silicon nitride
A con film 206 is formed. After that, the N epi layer 204
On the part to be plug area and NPN bipolar transistor
With openings on and above the collector
A pattern 207 is formed on the silicon nitride film 206.
Next, using the resist pattern 207 as a mask
Silicon nitride film 206, pad oxide film 205,
The layer 204 is etched. Next, as shown in FIG.
After removing the pattern (407), the first embodiment
In the same manner as described with reference to FIG.
To form a LOCOS oxide film 208 on the surface of the N epi layer 204.
Lengthen. Next, as shown in FIG.
The same steps as those described with reference to FIG.
Thus, the plug region 20 is formed on the surface side in the N epi layer 204.
9 on the lower surface of the LOCOS oxide film 208.
The isolation region 210 is formed along. more than
Thus, the substrate 20 is formed. Thereafter, the steps shown in FIGS.
Will be described with reference to FIGS. 2 (3) to (5) of the first embodiment.
The first semiconductor layer 1 is formed on the substrate 20 in the same manner as described above.
An anode 11 made of 1a and a second semiconductor layer 12a
The cathode 12 is formed by lamination. The following steps are also performed in the first step.
This is performed in the same manner as in the embodiment, whereby the zener shown in FIG.
Forming a diode 2; Next, FIG.Third embodimentThe Zenada
It is sectional drawing of an iod. Shown hereThird embodimentNotsu
The Zener diode 3 and the Zener diode of the first and second embodiments described above.
The difference from the anode diode is that impurities in the anode 11
In the object distribution. That is, the Zener die of the third embodiment
In anode 3, the anode exposed from cathode 12
The impurity concentration of the portion 11 is lower than the anode 11 under the cathode 12.
It is higher than the impurity concentration of the portion. Therefore,
When the cathode 12 is formed in the following manufacturing process
The anode 11 exposed from the cathode 12
Even if the film thickness of the minute is reduced by over-etching,
The resistance value of the anode 11 portion to which the wiring 15 is connected
The rise can be kept low. And the substrate 20
For example, the Zener diode (2) of the second embodiment and
It may be configured similarly. The formation of the Zener diode 3 will be described below.
The method will be described. First, as shown in FIG.
FIG. 4 shows the process of manufacturing the Zener diode according to the second embodiment.
Substrate in the same manner as the process described using (1) to (4)
After forming 20, the same as described with reference to FIG.
And the first semiconductor layer 11a and the second semiconductor
The body layer 12a is formed. After that, the second semiconductor layer 1
2a, a silicon nitride film 301 having a thickness of about 60 nm
Is formed. This silicon nitride film 301 will be described later with reference to FIG.
In the ion implantation step described using (8),
It is a layer that becomes a mask. Next, the steps shown in FIGS. 7 (6) and (7) are as follows.
Description will be given with reference to FIGS. 5 (6) and (7) of the second embodiment.
And the anode is placed on the substrate 20.
11 and the cathode 12 are laminated. Cathode 12
The silicon nitride film 301 remains on the upper surface
I have. Thereafter, in the step shown in FIG.
And the silicon nitride film 301 on the cathode 12
And a side made of silicon oxide on the side wall of the anode 11
A wall 302 is formed. This sidewall 302
Has a thickness of about 400 nm formed by the CVD method.
RIE of a silicon oxide film (not shown)
It is formed. Next, a resist pattern 3 is formed on the substrate 20.
03 is formed. After that, the resist pattern 303
Of the cathode 12 by ion implantation using
To the exposed anode 11^FifteenPieces / cm^TwoOf degree
Boron ion or boron fluoride ion (BF_Two)
Such a P-type impurity is implanted. As a result, the anode 11 portion is not
The concentration of the pure substance is made higher than the other anode 11 portions. Soshi
As a result, the first step of forming the cathode 12 shown in FIG.
2 Etching of the semiconductor layer 12a, over-etching
Anode 11 due to reduced thickness of first semiconductor layer 11a
Suppress the rise in resistance. Thereafter, as shown in FIG.
(303) and the silicon nitride film (301) are removed.
After that, the wiring 15 is connected in the same manner as in the first and second embodiments.
Form. In each of the above embodiments, the NPN bipolar
A transistor arranged on the same substrate in the same process as the transistor
The description has been given by taking a knurl diode as an example. For this reason,
The structure of the Zener diode is mounted on the substrates 10 and 20.
An anode 11 is arranged, and a cathode is placed on the anode 11.
12 has been described. However, the present invention
The Zener diode is not limited to the above,
Used as zener zap for resistance trimming
It should just be. Therefore, the anodes on the substrates 10 and 20
The arrangement state of the cathode 11 and the cathode 12
If the cathode 12 and the cathode 12 are in a joined state, it is limited to the above configuration.
It is not something to be done. [0041] As described above, according to the Zener diode of the present invention.
One of the anode and cathode
Semiconductor materials that are more likely to yield Zener than silicon and silicon
By forming with compound semiconductor consisting of
Zener diode with homojunction
Withstand voltage against reverse bias can be reduced compared to
You. Therefore, a resistor trim using a Zener diode
Circuit for zener diodes at lower voltage.
It is possible to zapping and trimming
Do not apply excessive current to the resistors and elements connected to the circuit.
It is possible to perform resistance trimming.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a Zener diode according to a first embodiment. FIG. 2 is a manufacturing process diagram of the Zener diode of the first embodiment. FIG. 3 is a sectional view of a Zener diode according to a second embodiment. FIG. 4 is a manufacturing process diagram (part 1) of the Zener diode of the second embodiment. FIG. 5 is a manufacturing process diagram (part 2) of the Zener diode of the second embodiment. FIG. 6 is a cross-sectional view of a Zener diode according to a third embodiment. FIG. 7 is a manufacturing process diagram of the Zener diode of the third embodiment. FIG. 8 is a sectional view of a conventional zener diode. FIG. 9 is a circuit diagram of resistance trimming by zener zap. [Explanation of Signs] 1, 2, 3 Zener diode 10, 20 Substrate 11 Anode 12 Cathode

Claims (1)

(57) A zener diode having an anode and a cathode arranged to be joined to the anode, wherein at least one of the anode and the cathode is made of silicon and A zener diode comprising a compound semiconductor made of germanium .