JP3383523B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device and a driving method thereof.

[0002]

2. Description of the Related Art A solid-state image pickup device having an amplification function inside a pixel by modulating the potential of a signal charge storage portion with a signal charge generated by photoelectric conversion and modulating an amplification transistor inside the pixel by the potential is It is called an amplification type solid-state imaging device, and is expected as a solid-state imaging device suitable for reducing the pixel size by increasing the number of pixels or reducing the image size.

The basic structure of a pixel in an amplification type solid-state imaging device is a photodiode for performing photoelectric conversion, a read transistor for reading charges from the photodiode, and a read line connected to the gate of the read transistor. A reset transistor for discharging signal charges, a reset line connected to the gate of the reset transistor, an amplification transistor for signal amplification, a transistor or capacitor for line selection, and a photodiode and a gate of the amplification transistor. Is a wiring (address line) for connecting the.

Further, a wiring (signal line) for reading a signal amplified by the amplification transistor and a wiring (drain line) for discharging a signal charge are respectively wired. Usually, the read line, the reset line, the line selection line (address line), the signal line, and the drain line are independently wired.

[0005]

As described above, in the conventional amplification type solid-state imaging device, the signal line, the drain line, the read line wired to the gate of the read transistor, and the reset transistor for discharging the signal charge are provided. At least five wirings such as a reset line wired to the gate and an address line for line selection are required, and these wirings are wired independently.

Therefore, when the element is miniaturized, there is a problem that the interval between the wirings becomes short, which causes a short circuit. Also, these wires are
Since it has to be performed through an insulating film or the like, there is a problem that a step is generated in the element and the wiring is broken.

Further, there is a problem in that the structure is complicated due to the large number of wirings, which is an obstacle to the miniaturization of the device. Further, a solid-state imaging device having a unit cell wiring structure suitable for miniaturization of elements is known.

FIG. 10 is a diagram showing a configuration of a unit cell of such a solid-state image pickup device, and FIG. 11 is a diagram showing a layout of such a unit cell. In the figure, 3
Although only one unit cell is shown, it is assumed that the unit cells are arranged two-dimensionally. Further, as shown in the figure, the unit cell 121 includes a photodiode 115 a that converts light into electric charges, an address transistor 117 a that selects a line from which signal charges are read out, and a detection signal of the photodiode is amplified and output to the signal line 1. It includes an amplification transistor 114a for resetting and a reset transistor 116a for resetting the electric charge accumulated in the detection unit.

Here, the unit cell 121 will be described, but it is assumed that the same configuration is adopted for other unit cells. The gate of the address transistor 117b and the gate of the reset transistor 116a of the unit cell adjacent to the unit cell 112 in the column direction are connected to the address / reset line 113a. address/
The reset line 113a transmits a signal for selecting a read row from the vertical shift register and a signal for resetting the charges accumulated in the detection unit.

The drain of the reset transistor 116a is connected to the detector, and the source is connected to the drain line 112 for discharging the charge accumulated in the detector. The gate of the amplification transistor 114a is connected to the detection unit, the drain is connected to the drain line 112, and the source is connected to the signal line 111.

In the solid-state image pickup device having the unit cell configured as shown in FIG. 10, it is possible to solve the above-mentioned problem of realizing miniaturization of elements. However, in the solid-state imaging device having the unit cell having such a configuration, the address / reset line turns on the address transistor of the unit cell adjacent to the lower part in the column direction and turns on the reset transistor of the upper unit cell in the column direction. Each independently.

In this case, a reset current flowing when the reset transistor is turned on and a drain current flowing when the address transistor is turned on flow through the drain line 112.

Therefore, the potential of the drain line 112 must be adjusted to the drain potential of the reset transistor and the source potential of the amplification transistor, which causes a problem that the drain line 112 is overloaded.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a solid-state imaging device and a driving method thereof that can easily realize miniaturization of elements. It is another object of the present invention to provide a solid-state imaging device that can realize miniaturization of elements and does not burden the drain line, and a driving method thereof.

[0015]

Therefore, first, in order to achieve the above object, a first invention is a solid-state image pickup device in which a plurality of unit cells are arranged in a matrix direction. At least one photoelectric conversion means for converting, a charge holding means for holding charges output from the at least one photoelectric conversion means, and connected between the at least one photoelectric conversion means and the charge holding means, respectively. A transfer gate that transfers the charge output from the photoelectric conversion unit to the charge holding unit when it is on, and a reset gate that resets the charge held by the charge holding unit when the part is on Transmitting a signal for turning on at least one transfer gate of the unit cell,
Further, a wiring for transmitting a signal for turning on the reset gates of the unit cells adjacent in the column direction to the some unit cells is provided, and the unit cells adjacent in the column direction are provided .
The threshold of the reset gate is the transfer gate of some of the unit cells.
It is characterized in that the value is smaller than the threshold value of

[0016]

Further, the second invention is at least one photoelectric conversion means for converting light into an electric charge, and the at least one photoelectric conversion means.
Charge holding means for holding charges output from one photoelectric conversion means, and the charge holding means connected to the at least one photoelectric conversion means and the charge holding means, respectively, and holding the charges output from the photoelectric conversion means by the charge holding means. A transfer gate for transferring to the means when it is on, and a reset gate for resetting the charge held in the charge holding means when it is on,
Unit cells having voltage output means for outputting a voltage corresponding to the charges held in the charge holding means are arranged in a plurality of matrix directions, and at least one transfer gate of some unit cells is turned on. A method for driving a solid-state imaging device, comprising: a wiring that transmits a signal and that transmits a signal for turning on a reset gate of the unit cell that is adjacent to a portion of the unit cells in the column direction. A voltage is applied to the unit cells adjacent to each other in the column direction to turn on reset gates of the unit cells adjacent to each other in the column direction to reset the charges held in the charge holding means, At least one transfer gate of the unit cell is turned on to transfer the electric charge output from the photoelectric conversion unit of the part of the unit cells to the electric charge holding unit, And outputs a voltage corresponding to the charge held in the charge holding means of some of the unit cells.

Further, a third invention is a solid-state image pickup device comprising a plurality of unit cells, wherein the unit cells hold a charge outputted from a photoelectric conversion means for converting light into a charge, A unit for resetting the charge held in the charge holding unit when it is turned on and an address unit for outputting the voltage corresponding to the charge held in the charge holding unit when the unit is turned on A wiring is further provided for transmitting a signal for turning on the reset means of the cell and transmitting a signal for turning on the address means of the part of the unit cells.

Further, a fourth aspect of the present invention is a charge holding means for holding the electric charge output from the photoelectric conversion means for converting light into an electric charge, and a reset for resetting the electric charge held in the electric charge holding means when it is turned on. Means and a plurality of unit cells each having an address means for outputting a voltage corresponding to the charges held in the charge holding means when the unit is on, and for turning on the reset means of a part of the unit cells. In the method for driving a solid-state imaging device, further comprising a wiring for transmitting a signal for transmitting the signal and for transmitting a signal for turning on the address means of the part of the unit cells, a voltage is applied to the wiring, Part of the unit cells to reset the electric charge held in the charge holding means of the part of the unit cells, and apply a voltage to the wiring to add the part of the unit cells. A scan means is turned on and outputs a voltage corresponding to the charge held in the charge holding unit.

Next, the operation of each invention will be described. First, the first invention transmits a signal for turning on at least one transfer gate of some unit cells, and resets the unit cells adjacent to the some unit cells in the column direction. Since the wiring for transmitting the signal for turning on the gate is provided, the wiring for transmitting the signal for turning on the transfer gate and the wiring for transmitting the signal for turning on the reset gate are separately provided. Compared with the case of providing
The miniaturization of the unit cell can be easily realized. Well
Also, the threshold value of the reset gate of the unit cells adjacent in the column direction
Smaller than the threshold of the transfer gate of the unit cell
Since the value is set, the reset gate can be controlled independently.
You can

[0021]

A second invention transmits a signal for turning on at least one transfer gate of some unit cells,
In addition, a voltage is applied to a wiring that transmits a signal for turning on the reset gates of the unit cells that are adjacent to the some unit cells in the column direction so that the reset gates of the unit cells that are adjacent to the column direction are applied. The charge held in the charge holding means of the unit cells adjacent to each other in the column direction is reset to ON, and at least one transfer gate of the partial unit cells is turned ON to perform photoelectric conversion of the partial unit cells. The charge output from the means is transferred to the charge holding means, and the voltage output means outputs a voltage corresponding to the charge held in the charge holding means of the part of the unit cells, so that the transfer gate and the reset gate are connected. It is possible to drive the solid-state imaging device including the shared wiring.

According to a third aspect of the present invention, wiring for transmitting a signal for turning on the resetting means of some unit cells and transmitting a signal for turning on the addressing means of the some unit cells is provided. By including it, a solid-state imaging device with few image defects can be provided.

A fourth aspect of the present invention provides a wiring for transmitting a signal for turning on the reset means of some unit cells and transmitting a signal for turning on the address means of the some unit cells. A voltage is applied to turn on the reset means of the part of the unit cells to reset the charges held in the charge holding means of the part of the unit cells.

Next, a voltage is applied to the wiring to turn on the address means of the part of the unit cells to output a voltage corresponding to the charges held in the charge holding means. It is possible to drive the solid-state imaging device including the wiring that shares the reset unit and the reset unit.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a diagram showing a configuration of a unit cell of an amplification type solid-state imaging device according to a first embodiment of the present invention. Note that FIG. 1 shows the configuration of three unit cells, which is an amplification type solid-state imaging device having one pixel and one unit cell configuration.

Although only three unit cells are shown in the figure, it is assumed that the unit cells of the amplification type solid-state imaging device of this embodiment are arranged two-dimensionally. As shown in the figure, the unit cell 12 selects a photodiode 5a for converting light into an electric charge, a read transistor 8a for reading out the electric charge accumulated in the photodiode 5a to the detection unit 13a, and a line for reading out the signal electric charge. Address capacitor 9a, amplification transistor 4a that amplifies the detection signal of the photodiode and outputs it to the signal line 1, and reset transistor 6 that resets the charge accumulated in the detection unit 13a.
a.

Although the unit cell 12 has been described here, it is assumed that the same configuration is adopted for other unit cells. The gate of the read transistor 8a and the reset transistor 6b of the unit cell adjacent in the column direction
Is connected to the common read / reset line 3a. The read / reset line 3a transmits a signal for turning on the read transistor 8a from the vertical shift register and the reset transistor 6b of the unit cell adjacent in the column direction.

Further, one end of the address capacitor 9a is connected to the address line 7a. The address line 7a transmits a signal for selecting a read row from the vertical shift register.

The gate of the reset transistor 6a is connected to the wiring common to the read transistor of the unit cell adjacent to the upper portion in the column direction. This wiring transmits a signal for resetting the electric charge accumulated in the detection unit 13a from the vertical shift register.

Further, the drain of the reset transistor 6a is connected to the detector 13a, and the source is connected to the drain line 2 for discharging the charge accumulated in the detector 13a.

The gate of the amplification transistor 4a is the detector 1
3a, the drain is connected to the drain wire 2,
The source is connected to the signal line 1. The signal line 1 is provided with a noise canceller for removing noise of the signal output to the signal line 1.

The signal from the noise canceller from which the noise is removed is sequentially output to the horizontal signal line through the horizontal selection transistor driven by the selection pulse supplied from the horizontal shift register.

Next, a method of forming the amplification type solid-state image pickup device having such a structure will be described with reference to the plan view of FIG. In this amplification type solid-state imaging device, p ⁺ (element isolation region) 10 and n ⁺ layers (photodiodes) 5a to 5c are formed on a surface layer of a p-type silicon semiconductor substrate, and a signal charge is generated in the photodiode section 5. Let

Then, the read transistors 8a to 8
c, an n layer is formed in a region where the reset transistors 6a to 6c are formed. After that, the surface is covered with an oxide film, and an electrode wiring material (for example, polysilicon) is further deposited.

Then, the read transistors 8a to 8
c, the read / reset lines 3a to 3c, the gates of the reset transistors 6a to 6c, and the reset line, the electrode wiring material is processed into a desired shape to form the read line and the reset transistor wiring. At this time,
Since the read line and the reset line are also used, the read / reset lines 3a to 3c can be formed by patterning at once.

After that, after forming the element portion of the amplification type solid-state image pickup device as described above, a wiring (signal line 1) for reading a signal current and a wiring (drain line 2) for discharging a signal charge are formed. Wire.

In FIG. 2, the signal line 1 and the drain line 2
Only the contact portion for obtaining electrical continuity is shown. The signal line 1 and the drain line 2 are wired in the vertical direction,
Electrical continuity is obtained at the contact part.

Further, in FIG. 2, as the wiring material,
Although polysilicon is used, other than that, for example, amorphous silicon mixed with impurities, metal such as AI (aluminum), tungsten (W), molybdenum (Mo), titanium (Ti), or at least one or more of the above metals is used. It is also possible to use compounds including metal alloys and silizide compounds.

Next, the operation of the amplification type solid-state image pickup device of the present embodiment will be described with reference to the timing chart of FIG. First, in the horizontal blanking period H-BLK1, the transfer pulse 21 is added to the read / reset line 3a so that the signal charge of the photodiode 5a is detected.
It is read out and stored in the address capacity 9a.

At this time, at the same time, the reset transistor 6b of the unit cell adjacent to the lower part in the column direction is turned on, the charge accumulated in the detecting portion 13b is reset, and the charge accumulated in the detecting portion 13b is drained. Is discharged to.

Next, the address pulse 22 is applied to the address capacitor 9a via the address line 7a. When the address pulse 22 is applied to the address capacitor 9a, the potential of the channel of the amplification transistor 4a rises as compared to other lines, and the load transistor and the amplification transistor 4a form a source follower circuit.

Therefore, a voltage substantially equal to the signal voltage obtained by impedance-converting the signal charge of the photodiode 5a is output to the signal line 1. The signal output to the signal line 1 is output to the horizontal signal line by being selected by the horizontal shift register via the noise removing circuit.

After sampling the output voltage of the photodiode of the first row in this manner, the read / reset line 3b of the second line is similarly similarly sampled within the next horizontal blanking period.
The transfer pulse 23 is applied to the second line to read the signal charge of the photodiode 5b of the second line to the detection unit 13b and accumulate it in the address capacitor 9b.

At this time, at the same time, the reset transistor 6c of the unit cell adjacent to the lower part in the column direction is turned on, the charge accumulated in the detecting portion 13c is reset, and the charge accumulated in the detecting portion 13c is drained. Is discharged to.

Next, the address pulse 24 is applied to the address capacitor 9b through the address line 7b. When the address pulse 24 is applied to the address capacitor 9b, the potential of the channel of the amplification transistor 4b rises as compared with other lines, and the load transistor and the amplification transistor 4b form a source follower circuit.

Therefore, a voltage substantially equal to the signal voltage obtained by impedance conversion of the signal charge of the photodiode 5b is output to the signal line 1. The signal output to the signal line 1 is output to the horizontal signal line by being selected by the horizontal shift register via the noise removing circuit.

By repeating the above-described operation for each line in sequence, it is possible to read out the signals of all the photodiodes arranged two-dimensionally. Therefore,
According to the solid-state imaging device of the present embodiment, the unit cell can be miniaturized by connecting the gate of the read transistor and the gate of the reset transistor of the unit cell adjacent to the lower part in the column direction with a common wiring. You can

Further, with such a structure,
When the element is miniaturized, insulation due to a short circuit due to a narrow interval between wirings and a step in the unit cell does not occur.

Further, according to the solid-state image pickup device of the present embodiment, the current flowing in the drain line 2 by applying the pulse to the read / reset line is only the electric charge discharged through the reset transistor. The drain line 2 need only be adjusted with the drain voltage of the reset transistor, and as a result, the drain line 2 is not burdened. <Second Embodiment> Next, an amplification type solid-state imaging device according to a second embodiment of the present invention will be described.

FIG. 4 is a diagram showing the structure of a unit cell of an amplification type solid-state image pickup device according to the second embodiment of the present invention.
In addition, in FIG. 4, the configuration of the three unit cell is shown.
It is an amplification type solid-state imaging device having a configuration of two pixels and one unit cell. Further, the same parts as those in FIG.

Although only three unit cells are shown in the figure, it is assumed that the unit cells of the amplification type solid-state imaging device of this embodiment are arranged two-dimensionally. As shown in the figure, the unit cell 14 includes photodiodes 5a-1 and 5a-2 that convert light into electric charges and a photodiode 5a.
Read transistors 8a-1 and 8a for reading the charges accumulated in -1, 5a-2 to the detection unit 13a, respectively.
a-2, an address capacitor 9a that selects a line from which signal charges are read, an amplification transistor 4a that amplifies the detection signal of the photodiode and outputs the signal to the signal line 1, and a reset transistor 6 that resets the charges accumulated in the detection unit 13a.
a.

Although the unit cell 14 has been described here, it is assumed that the same configuration is adopted for other unit cells. The gate of the read transistor 8a-1 is connected to the read line 11a. Read line 1
1a transmits a signal for turning on the read transistor 8a-1.

The gate of the read transistor 8a-2 and the reset transistor 6 of the unit cell adjacent in the column direction
The gate of b is connected to the common read / reset line 3a. The read / reset line 3a transmits the signal from the vertical shift register. The read / reset line 3a transmits the signal from the vertical shift register.

Further, one end of the address capacitor 9a is connected to the address line 7a. The address line 7a transmits a signal for selecting a read row from the vertical shift register.

The gate of the reset transistor 6a is connected to the wiring common to the read transistor of the unit cell adjacent to the upper portion in the column direction. This wiring transmits a signal for resetting the electric charge accumulated in the detection unit 13a from the vertical shift register.

Further, the drain of the reset transistor 6a is connected to the detection section 13a, and the source is connected to the drain line 2 for discharging the electric charge accumulated in the detection section 13a.

The gate of the amplification transistor 4a is the detector 1
3a, the drain is connected to the drain wire 2,
The source is connected to the signal line 1. The signal line 1 is provided with a noise canceller for removing noise of the signal output to the signal line 1.

Then, the noise-free signal output from the noise canceller is sequentially output to the horizontal signal line through the horizontal selection transistor driven by the selection pulse supplied from the horizontal shift register.

Next, the operation of the amplification type solid-state imaging device of the present embodiment will be described with reference to the timing chart of FIG. First, in the horizontal blanking period H-BLK1, when the transfer pulse 31 is applied to the read / reset line 3a, the charge accumulated in the detection unit 13b is reset, and the charge accumulated in the detection unit 13b is reset. It is discharged to the drain wire 2.

Next, the read pulse 32 is applied to the read transistor 8b-1 via the read line 11b. By applying the read pulse to the read transistor 8b-1, the charge accumulated in the photodiode 5b-1 is read by the detection unit 13b.

Next, the address pulse 33 is applied to the address capacitor 9b via the address line 7b. When the address pulse 32 is applied to the address capacitor 9b, the potential of the channel of the amplification transistor 4a rises as compared with other lines, and the load transistor and the amplification transistor 4b form a source follower circuit.

Therefore, a voltage substantially equal to the signal voltage obtained by impedance conversion of the signal charge of the photodiode 5b-1 is output to the signal line 1. The signal output to the signal line 1 is output to the horizontal signal line by being selected by the horizontal shift register via the noise removing circuit.

Next, the transfer pulse 34 is applied to the read / reset line 3a to reset the electric charge accumulated in the detecting portion 13b, and the electric charge accumulated in the detecting portion 13b is discharged to the drain line 2.

Next, the read pulse 35 is applied to the read transistor 8b-2 via the read / reset line 3b. By applying the read pulse to the read transistor 8b-2, the photodiode 5b-
The charges accumulated in 2 are read out to the detection unit 13b.

Next, the address pulse 36 is applied to the address capacitor 9b via the address line 7b. When the address pulse 36 is applied to the address capacitor 9b, the channel potential of the amplification transistor 4a rises as compared with the other lines, and the load transistor and the amplification transistor 4b form a source follower circuit.

Therefore, a voltage substantially equal to the signal voltage obtained by impedance-converting the signal charge of the photodiode 5b-2 is output to the signal line 1. The signal output to the signal line 1 is output to the horizontal signal line by being selected by the horizontal shift register via the noise removing circuit.

By repeating the above-described operation for each line in sequence, it is possible to read out the signals of all the two-dimensionally arranged photodiodes. In the above description of the embodiment, the case where reading and resetting are performed at the same time has been described. However, by setting the threshold value of the reset transistor to a value smaller than the threshold value of the reading transistor, it is possible to set a certain timing. Only the reset can be performed by reading the voltage and applying it to the reset line.

In such a case, when it is desired to perform both reading and resetting at the same time, reading /
By applying a voltage higher than the threshold value of the reading transistor to the reset line, reading and reset can be performed at the same time. Such driving can be realized by using a ternary pulse as the pulse applied to the read / reset line.

Therefore, according to the solid-state imaging device of the present embodiment, by connecting the gate of the read transistor and the gate of one reset transistor of one of the unit cells adjacent to the lower part in the column direction with a common wiring, the unit The cell can be miniaturized.

Further, with such a structure,
When the element is miniaturized, insulation due to a short circuit due to a narrow interval between wirings and a step in the unit cell does not occur.

Further, according to the solid-state imaging device of the present embodiment, the current flowing in the drain line 2 by applying the pulse to the read / reset line is only the electric charge discharged through the reset transistor. The drain line 2 need only be adjusted with the drain voltage of the reset transistor, and as a result, the drain line 2 is not burdened. <Third Embodiment> FIG. 6 is a diagram showing a configuration of a unit cell of an amplification type solid-state imaging device according to a third embodiment of the present invention, and FIG. It is a figure which shows the layout of the unit cell of a solid-state imaging device.

Incidentally, FIG. 6 shows the structure of two unit cells, which is an amplification type solid-state image pickup device having one pixel and one unit cell structure. Further, the same parts as those in FIG.

Although only three unit cells are shown in the figure, it is assumed that the unit cells of the amplification type solid-state imaging device of this embodiment are arranged two-dimensionally. As shown in the figure, this unit cell amplifies the detection signal of the photodiode 5a that converts light into electric charge, the address transistor 41a that selects a line from which signal electric charge is read out, and outputs the amplified signal to the signal line 1. The amplifier transistor 4a and the reset transistor 6a for resetting the electric charge accumulated in the detection portion are provided.

The gate of the address transistor 41a and the gate of the reset transistor 6a are connected to the address / reset line 42a. The address / reset line 42a transmits a signal for turning on the address transistor 41a and the reset transistor 6a.

That is, in the solid-state image pickup device of this embodiment, the wiring of the address transistor and the reset transistor is shared in one unit cell. The address transistor and the reset transistor are MOS type transistors, and the threshold values of these transistors are different. The threshold value is controlled by changing the doping amount in the channel of each MOS transistor or increasing the thickness of the insulating film.

As described above, the address transistor and the reset transistor can be independently controlled by changing the threshold values of the address transistor and the reset transistor.

That is, by applying a reset pulse to the address / reset line 42a, the reset transistor 41a is turned on, and the electric charge accumulated in the detecting portion is discharged to the drain line 2.

Next, the address transistor 6a is turned on by applying an address pulse to the address / reset line 42a. As a result, the charges corresponding to the charges accumulated in the detection unit are output from the amplification transistor 4a to the signal line 1.

By repeating the above-described operation for each line in sequence, it is possible to read out the signals of all the two-dimensionally arranged photodiodes. Although one unit cell has been described here, it is assumed that the same configuration is adopted for other unit cells.

Therefore, according to the solid-state imaging device of the present embodiment, the unit cell can be miniaturized by connecting the gate of the address transistor and the gate of the reset transistor in one unit cell with a common wiring. You can

Further, with such a structure,
When the element is miniaturized, insulation due to a short circuit due to a narrow interval between wirings and a step in the unit cell does not occur.

Further, the solid-state image pickup device of the present embodiment has the following advantages over the case where the wiring between the address means and the reset means between the two unit cells is shared.

That is, first, in the solid-state image pickup device according to the above-described first and second embodiments, when a problem occurs in the function of the common wiring due to disconnection or the like, a pixel defect of two pixels occurs. However, according to the solid-state imaging device of the present embodiment, even if such a problem occurs, an image defect occurs in only one pixel, so that the pixel defect can be minimized.

When the wiring of the reset transistor and the address transistor is shared by the two pixels, the lower signal is addressed and the upper signal is reset at the timing of a normal signal for resetting after addressing. If you can only read in one direction and you want to add and read the signals of two or more pixels above and below, you cannot read the pixels above and below at the same time, and you can roughly extract the pixels or use high-speed transfer depending on the application. Therefore, there is a problem that the application range of the device, such as combining and processing two pixels, is lacking, and as a result, the application of the device is narrowed.

However, according to the solid-state image pickup device of the present embodiment, since the wiring is shared within one unit cell, the upper and lower pixels can be read out at the same time, so that signals of two or more upper and lower pixels can be read. It is possible to add and read out, and it is possible to realize processing such as processing by combining two pixels for high-speed transfer.

Therefore, according to the solid-state imaging device of the present embodiment, the range of application of the device can be expanded, and as a result, the applications of the solid-state imaging device of the user can be expanded.

In the description of the solid-state image pickup device of the present embodiment, the example in which the address function is given to the MOS transistor has been described, but the address function may be given to the capacitor as shown in FIG. Note that, also in FIG. 8, the same parts as those in FIG. 6 are denoted by the same reference numerals.

Also in this case, the gate electrode of the reset MOS transistor and the gate electrode of the address MOS transistor in one pixel are connected by a common address / reset line.

Even if such a structure is adopted, it is possible to obtain the same effect as when the address transistor has the address function. Further, FIG. 9 shows the configuration of the unit cell of the amplification type solid-state imaging device when the transfer MOS transistor 51 is incorporated in the unit cell. Also in this case, by connecting the gate electrode of the reset MOS transistor and the gate electrode of the address MOS transistor with a common address / reset line, the same effect as in the case where the address transistor has the address function can be obtained. .

[0091]

As described above in detail, according to the present invention,
It is possible to provide a solid-state imaging device that can realize miniaturization of elements and a driving method thereof. Further, according to the present invention, it is possible to provide a solid-state imaging device that enables miniaturization of an element and does not burden the drain line, and a driving method thereof. Further, according to the present invention, it is possible to provide a solid-state imaging device with few image defects on a reproduction screen and a driving method thereof.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a unit cell of an amplification type solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a planar structure diagram of the amplification type solid-state imaging device according to the first embodiment.

FIG. 3 is a timing chart showing an operation of the amplification type solid-state imaging device according to the first embodiment.

FIG. 4 is a diagram showing a configuration of a unit cell of an amplification type solid-state imaging device according to a second embodiment of the present invention.

FIG. 5 is a timing chart showing an operation of the amplification type solid-state imaging device according to the second embodiment.

FIG. 6 is a diagram showing a configuration of a unit cell of an amplification type solid-state imaging device according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a layout of unit cells of the amplification type solid-state imaging device according to the third embodiment.

FIG. 8 is a diagram showing a configuration of a unit cell when a capacitor of the amplification type solid-state imaging device according to the third embodiment has an address function.

FIG. 9 is a diagram showing a configuration of a unit cell having a transfer gate of the amplification type solid-state imaging device according to the third embodiment.

FIG. 10 is a diagram showing a configuration of a unit cell of a conventional solid-state imaging device.

FIG. 11 is a diagram showing a layout of a unit cell of a conventional solid-state imaging device.

[Explanation of symbols]

1 ... signal line, 2 ... the drain wire, 3a to 3c ... Read / reset line, 4a-4c ... Amplifying transistor, 5a-5c ... Photodiode, 5a-1, 5a-2 ... Photodiode, 5b-1, 5b-2 ... Photodiode, 5c-1, 5c-2 ... Photodiode, 6a to 6c ... Reset transistor, 7a to 7c ... address line, 8a to 8c ... Read transistor, 8a-1, 8a-2 ... Read transistor, 8b-1, 8b-2 ... Read transistor, 8c-1, 8c-2 ... Read transistor, 9a to 9c ... Address capacity, 10 ... Element isolation region, 11a to 11c ... Read-out line, 12 ... Unit cell, 13a to 13c ... Detection unit, 14 ... Unit cell, 21 ... Transfer pulse, 22 ... Address pulse, 23 ... Transfer pulse, 24 ... Address pulse, 31 ... Transfer pulse, 32 ... Read out pulse, 33 ... Address pulse, 34 ... Transfer pulse, 35 ... Read out pulse, 36 ... Address pulse, 41a ... Address transistor, 111 ... signal line, 112 ... the drain wire, 113a to 113c ... Address / reset line, 114a to 114c ... Amplifying transistors, 115a to 115c ... Photodiodes, 116a-116c ... Reset transistor, 117a to 117c ... Address transistors.

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Tetsuya Yamaguchi 1 Komukai Toshiba Town, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Toshiba Research and Development Center (72) Inventor Yoshinori Iida Komukai Toshiba Town, Kawasaki City, Kanagawa Prefecture No. 1 in Toshiba Research & Development Center (72) Inventor Hidetoshi Nozaki Komukai, Komu, Kawasaki City, Kanagawa Prefecture No. 1 In Toshiba Research & Development Center (72) Inventor Keiji Mabuchi Komukai, Kouki-ku, Kawasaki, Kanagawa Prefecture Toshiba Town No. 1 in Toshiba Research & Development Center (72) Inventor Hiroshi Yamashita Komukai Komukai-ku, Kawasaki City, Kanagawa Prefecture No. 1 Toshiba Town R & D Center, Inc. (72) Inventor Hidefumi Oba Kawasaki City, Kanagawa Prefecture Komukai Toshiba Town No. 1 In Toshiba Research & Development Center Co., Ltd. (72) Inventor Michio Sasaki Sachi Ward, Kawasaki City, Kanagawa Prefecture Mukaihigashi Shibamachi address 1 Corporate Research and Development in the Center (56) Reference Patent Sho 57-181155 (JP, A) (58 ) investigated the field (Int.Cl. ^7, DB name) H01L 27/146 H04N 5 / 335

Claims (4)

(57) [Claims] 1. A fixed array of unit cells arranged in a matrix.
In the body imaging device, the unit cell includes at least one photoelectric conversion unit that converts light into an electric charge, and a charge output from the at least one photoelectric conversion unit.
Holding means for holding a charge, said at least one photoelectric conversion means and said charge holding means
Output from the photoelectric conversion means.
Transfer the generated charge to the charge holding means when it is on.
When the charge held in the transfer gate and the charge holding means is turned on, it is reset.
And a reset gate to turn on at least one transfer gate of some unit cells.
For transmitting a signal for
The reset gates of the unit cells adjacent to each other in the column direction.
Comprises a wiring for transmitting a signal to turn on, the threshold of the reset gate of the unit cells adjacent to said column direction, characterized in that than the threshold of the transfer gate of the unit cell of said portion is a small value Solid-state imaging device. 2. At least one light that converts light into an electric charge
And a charge output from the at least one photoelectric conversion means.
Holding means for holding a charge, said at least one photoelectric conversion means and said charge holding means
Output from the photoelectric conversion means.
Transfer the generated charge to the charge holding means when it is on.
When the charge held in the transfer gate and the charge holding means is turned on, it is reset.
Output a voltage corresponding to the charge held in the charge holding means and the reset gate to be set.
A plurality of unit cells with a voltage output means
And turn on at least one transfer gate in some unit cells
A signal for transmitting and said pair in a part of the unit cell
The reset gates of the unit cells adjacent to each other in the column direction.
Solid-state imaging with wiring for transmitting signal to turn on
In a method of driving an image device , a voltage is applied to the wiring to apply the unit cells that are adjacent in the column direction.
Turn on the reset gate of the column and adjoin in the column direction.
The charge held in the charge holding means of the unit cell is reset.
And at least one of the unit cells
Turning on the transfer gate of the light of the unit cell
The electric charge output from the electric charge conversion means is transferred to the electric charge holding means.
And the voltage output means holds the charges of the part of the unit cells.
To output a voltage corresponding to the charge held by the means
A method of driving a characteristic solid-state imaging device. 3. A solid-state image pickup device having a plurality of unit cells
In the unit cell, the electric charge output from the photoelectric conversion unit that converts light into electric charge is stored in the unit cell.
The charge holding means for holding the charge and the charge held in the charge holding means are reset when turned on.
Reset means for switching on and a voltage corresponding to the charge held in the charge holding means.
And an addressing means for outputting in the case of turning on the resetting means of some unit cells.
It transmits a signal and the address of the some unit cells
Further wiring for transmitting a signal for turning on the means
A solid-state imaging device characterized by being provided. 4. A photoelectric conversion means for converting light into an electric charge.
The charge holding means for holding the applied charge, and the charge held by the charge holding means is reset when the charge is turned on.
Reset means for switching on and a voltage corresponding to the charge held in the charge holding means.
Unit cell with addressing means for outputting
A plurality of units for turning on the reset means of some unit cells
It transmits a signal and the address of the some unit cells
Further wiring for transmitting a signal for turning on the means
In the method for driving a solid-state image pickup device , the voltage of the wiring is applied to the part of the unit cell,
The setting means is turned on to turn on the electric charges of the unit cells.
The electric charge held in the holding means is reset, and a voltage is applied to the wiring to address the part of the unit cells.
The charge held in the charge holding means when the charge holding means is turned on.
Solid-state imaging device characterized by outputting a voltage corresponding to
Drive method.