JP3064380B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device and a driving method thereof, and more particularly, to an amplification-type solid-state imaging device having an amplifying element for each light receiving unit and a driving method thereof.

<Summary of the Invention> The present invention relates to a solid-state imaging device having an amplifying MOS transistor for each pixel and a resetting MOS transistor for resetting the gate potential of the amplifying MOS transistor. Element), and the signal charge obtained by the photoelectric conversion is completely transferred to the amplification MOS transistor side by the CCD, and the reset MOS transistor is connected to the gate electrode of the amplification MOS transistor and the first reset signal line. And the gate electrode thereof is connected to the second reset signal line.

<Prior Art> A basic CCD solid-state imaging device is configured to transfer signal charges accumulated in a photoelectric conversion unit of each pixel in accordance with the amount of incident light to an output unit as they are using a CCD. Therefore, there is a problem that the noise component is mixed during the charge transfer by the CCD, so that the S / N tends to deteriorate.

Conventionally, as a solid-state imaging device designed to solve such a problem, a photoelectric conversion unit that accumulates signal charges according to the amount of incident light, a unit that amplifies the signal charges accumulated in the photoelectric conversion unit, 2. Description of the Related Art There is known an amplification type solid-state imaging device having a configuration in which a light receiving unit having means for resetting an input is provided for each of a plurality of pixels arranged two-dimensionally (for example, Japanese Patent Application Laid-Open No. 1-154678). reference).

<Problems to be Solved by the Invention> However, in the amplification type solid-state imaging device, with respect to fixed pattern noise including a flaw defect, although noise can be reduced by technical improvement of a manufacturing process, resetting due to element characteristics and the like is possible. Since noise is fundamental, there is a problem in that if a pixel cell is miniaturized in order to reduce the size of a solid-state imaging device, S / N deteriorates.

Also, in order to perform vertical and horizontal scanning in pixel units,
A solid-state imaging device having a configuration in which a photogate transistor including three elements is provided for each pixel is also known (for example, see Japanese Patent Application Laid-Open No. 63-100879).

By the way, it is used as a photogate transistor
The source and drain of a MOS transistor are made under conditions that do not deplete no matter how much voltage is applied, that is, there are always electrons. That is, when transferring signal charges through the photogate transistor, the profile is such that much charge remains in the photoelectric conversion unit (for example, a photodiode). On the other hand, in a photodiode, a dark current component is present, and the signal charge that has been photoelectrically converted is added to the dark current component, and the amount of the additional charge is transferred as a signal charge through a photogate transistor. There is uncertainty, which is the so-called kTC noise.

As described above, in a pixel structure using a MOS transistor as a photogate transistor, when signal charges are transferred through the photogate transistor, charge transfer remains due to the profile of the MOS transistor, so that kTC noise is generated. There was a problem.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a solid-state imaging device which has high sensitivity due to low noise and can be downsized by miniaturization of a pixel cell, and a driving method thereof.

<Means for Solving the Problems> A solid-state imaging device according to the present invention includes a storage for storing signal charges corresponding to the amount of incident light, an output gate forming a 1-bit CCD together with the storage, and a storage through the output gate. An amplifying MOS transistor that amplifies and outputs an output signal charge, and is connected between a gate electrode of the amplifying MOS transistor and the first reset signal line, and has a gate electrode connected to the second reset signal line. And a plurality of pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions, and a first reset signal is applied to the reset MOS transistor through a first reset signal line. The horizontal line is selected by performing the above operation, and the gate voltage of the reset MOS transistor of the selected horizontal line is selected. The gate potential of the amplifying MOS transistor is reset by applying the second reset signal to the pole through the second reset signal line, and then the output gate of the selected horizontal line is turned on and stored in the storage. A vertical scanning circuit for transferring signal charges to the gate electrode of the amplification MOS transistor through the output gate.

Further, in the driving method of the solid-state imaging device according to the present invention, each of a plurality of pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions includes a storage for storing signal charges corresponding to the amount of incident light, and one bit together with the storage. And an amplification gate that amplifies and outputs signal charges output from the storage through the output gate.
A solid-state imaging device having a MOS transistor and a reset MOS transistor connected between the gate electrode of the amplification MOS transistor and the first reset signal line and having a gate electrode connected to the second reset signal line; A reset MOS through a first reset signal line;
A horizontal line is selected by applying a first reset signal to the transistor, and amplification is performed by applying a second reset signal to a gate electrode of a reset MOS transistor of the selected horizontal line through a second reset signal line. The gate potential of the MOS transistor for use is reset, and then the output gate of the selected horizontal line is turned on, and the signal charge stored in the storage is transferred to the gate electrode of the MOS transistor for amplification through the output gate.

<Operation> In the present invention, in a solid-state imaging device having an amplification MOS transistor for each pixel and a reset MOS transistor for resetting the gate potential of the pixel, a 1-bit CCD is configured by a storage and an output gate, and the CCD is obtained by photoelectric conversion. The signal charge is completely transferred to the amplification MOS transistor side by the CCD. In driving the vertical scanning, first, a horizontal line is selected by applying a first reset signal to a reset MOS transistor through a first reset signal line. The gate potential of the amplification MOS transistor is reset by applying a second reset signal to the gate electrode of the reset MOS transistor of the selected horizontal line through the second reset signal line. Are turned on. As a result, the signal charge stored in the storage is completely transferred to the amplification MOS transistor by the 1-bit CCD as described above.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing only a main part of an embodiment of a solid-state imaging device according to the present invention. In this figure, for convenience of explanation, the circuit configuration of only one pixel of each of two adjacent n-th and (n + 1) -th lines among a plurality of pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions is shown. It is assumed that all the remaining pixels have the same circuit configuration.

In the figure, when light is incident on each pixel, a signal charge corresponding to the amount of incident light is stored in a storage (ST) 1.
This storage 1 and its output gate (OG) switch 2
Storage 1 as a storage unit and an output gate switch 2
1-bit (one-stage) CCD (Charge Couple)
d Device) is configured. The reset MOS-FET 3 and the source follower amplifier M
OS-FET4 is made, and the gate of MOS-FET4 for amplification is floating diffusion.
To form a floating diffusion amplifier (FDA) 5.

In the floating diffusion amplifier 5, the gate electrode of the output gate switch 2 is connected to the output gate (OG) signal line 6, and the reset MOS-FET 3
The gate electrode is a reset gate (RG) signal line (second reset signal line) 7a, the drain electrode is a reset drain (RD) signal line (first reset signal line) 7b, and the source electrode is a MOS- Each is connected to the gate electrode of FET4. Then, the output gate pulse φ _{OG is supplied} from the vertical scanning shift register 8 to the gate electrode of the output gate switch 2.
But also a reset gate pulse to the gate electrode of the reset MOS-FET 3 (first reset signal) phi _RG is reset drain pulse to the drain electrode (second reset signal)
A horizontal line is selected by applying φ _RD . The power supply voltage V _DD is applied to the drain electrode of the amplification MOS-FET 4, and the source electrode is connected to the vertical signal line 9 as the output terminal V _out .
Then, when one horizontal line is selected, the signal charges of the pixels on the selected horizontal line are amplified by the amplification MOS-FET 4 and output to the vertical signal line 9.

The vertical signal line 9 is connected to the load transistor 11 through the transfer gate switch 10, the amplified output of each pixel output to the vertical signal 9 is stored in the noise eliminating capacitor C _0. The output end of the capacitor C ₀ is connected clamp switch 12, by which is turned by the clamp switch 12 is a clamp pulse phi _cL to the gate electrode is applied, the output end of the capacitor C ₀ The potential is clamped to the clamp level _VcLp . The noise removing capacitor C ₀ and the clamp switch 12,
A CDS (correlated double sampling) circuit 15 for reducing noise such as reset noise included in the source output of the amplification MOS-FET 4 is configured.

The output of the noise removal capacitor C _0, the buffer amplifier
13 first by switching the switch 14 after a are alternatively supplied to the sample / hold capacitor C _1, C ₂ is the second signal holding means, is sampled / held by the capacitors C _1, C ₂ . The switching control of the selector switch 14 is performed for each line by a sample / hold pulse φ _SH generated in a horizontal blanking period. Thus, for example, the pixel output of the even lines in the capacitor C _1, the pixel output of the odd line is to be held respectively in the capacitor C _2.

The hold outputs of capacitors C ₁ and C ₂ are connected to buffer amplifier 1
After passing through 6 _-1 and 16 _-2, they are led out to horizontal signal lines 18 _-1 and 18 _-2 by switching by the horizontal gate switches 17 _-1 and 17 _-2 . Switching control of the horizontal gate switches 16 _-1 and 16 _-2 is performed by a horizontal shift pulse φ _H output from the horizontal scan shift register 19.

FIG. 2 shows a sectional structure of the solid-state imaging device according to the present invention having such a configuration. FIG. 2 is a cross-sectional view of the drain electrode (V _DD ) -gate electrode-source electrode (V _out ) of ST-OG-RG-RD... FET4 in one unit cell. As is clear from the figure, the solid-state imaging device according to the present invention has an electrode element group constituting a floating diffusion amplifier (FDA) on the surface of a thin silicon substrate 20, and further has a CVD (Chemical Vapor Vapor Deposition) thereon. The SiO ₂ film 21 is deposited by a method such as Deposition) while the horizontal aluminum wires 23 and the vertical aluminum wires 23 are patterned and arranged in an XY matrix on the SiO ₂ film 22 disposed on the back surface of the silicon substrate 20 as shown in FIG. Reset drain (RD) and MOS-FET for amplification on aluminum wire 24
4 output terminals (V _out ) are connected to each other,
Has a so-called back-illuminated structure in which irradiation light is taken in from the back side.

As described above, the solid-state imaging device has a back-illuminated structure.
Since only the 23 and the vertical aluminum wires 24 are patterned, the aperture ratio can be dramatically improved.

Subsequently, in the solid-state imaging device according to the present invention, one pixel selected by the vertical scanning shift register 8 and the horizontal scanning shift register 19 will be described with reference to the cell sectional view of FIG. 2 and the potential distribution diagram of FIG. The operation will be described with reference to the time chart of FIG.

First, in the horizontal blanking period, as shown in FIG. 3, only for the n-th horizontal lines to be selected in the vertical direction RD (reset drain), at time t ₁ the reset drain pulse phi _RD with high levels ( For example, 5V)
Of applying a reset voltage V _RD, the RD of the remaining horizontal lines by applying a voltage of low level (e.g., 1.5V), performs the line selection. At this time, if the FD of the pixel on the selected horizontal line is reset by the reset gate pulse _φRG , the potential of the FD becomes high level, thereby
The gate potential of the S-FET 4 also becomes high. On the other hand, in the pixels of the horizontal line which are not selected, the FD potential is held at a low level, so that the gate potential of the amplifying MOS-FET 4 is lower than the FD potential by a threshold level as shown by a dotted line in FIG. Low level by V _th (for example, 0.5
V) and a cutoff state is established.

Next, the reset gate pulse phi _RG at time t ₂ is changed to the low level, MOS-FET 3 is reset becomes cut off. In this state, securing the output end of the capacitor C ₀ to the clamp level V _CLP clamp switch 12 by the clamping pulse phi _cL is turned on. And
By clamp pulse phi _cL disappears at time t _3, the clamp switch 12 is turned off.

Due to the action of the capacitor C ₀ and the clamp switch 12 in the CDS circuit 15, fixed pattern noise (FPN) including a flaw, _Vth unevenness due to input offset variation of the source follower, low frequency (1 / f) noise of the source follower and
Reset noise generated when the FDA is reset, as well as smear caused by light entering signal lines and CCDs, can be canceled. This eliminates the need for the FPN removal frame memory conventionally used in the signal processing system of the output signal of the solid-state imaging device.

Then, by the output gate (OG) 2 turned on at time t _4, the output gate pulse phi _OG, to transfer signal charges that are stored in the storage (ST) 1 to the FD, the output gate pulse phi _OG transferring all signal charges to the FD until time t ₅ to disappear. Then, the sample / hold pulse φ
Capacitor signal voltage switches the switch 14 switching at time t ₆ to the sample / hold capacitor C ₁ side by _SH
Type in C _1, the sample / hold pulse phi _SH off switch 14 switchable time t ₇ which disappears state (neutral position in the figure)
It holds the signal voltage of the capacitor C ₁ as.

The n-th signal charges of the horizontal line and amplified by the amplifying MOS-FET 4 by the operation timing described above, if the stored in the capacitor C ₁ of the CDS circuit 15, n + 1 th signal charges of horizontal lines by the same operation timing continues Amplify MO
It is amplified by the S-FET 4 and stored in the capacitor C ₂ of the CDS circuit 15.
As a result, the horizontal gate switches 17 _-1 , 1 _-1 by the horizontal shift pulse φ _H generated from the horizontal scan shift register 19 are _output .
Vertically adjacent 2 by switching control of 7 _-2
Pixel signals can be read out independently during the horizontal scanning effective period. During the horizontal scanning valid period, the reset gate (RG) is set to high level and the reset drain (RD)
To a low level (about 1.5V).

In this reading, a non-interlaced television signal can be obtained by sequentially reading out the hold outputs of the capacitors C ₁ and C ₂ . Alternatively, the hold outputs of the capacitors C ₁ and C ₂ may be simultaneously read out. In this case, the read signals are appropriately processed by a signal processing system (not shown), so that the readout is performed in the same manner as in the case of sequential reading. In addition, a non-interlaced television signal can be obtained.

When the storage (ST) 1 overflows with signal charges, the signal charges are discarded by a horizontal overflow from ST → OG → FD → RD. Thus, the reset MO
By using the drain electrode (RD) of the S-FET 3 for selecting a horizontal line and sharing the overflow drain, the configurations of the horizontal line selection element and the overflow train can be simplified.

<Effects of the Invention> As described above, according to the present invention, in a solid-state imaging device having an amplification MOS transistor for each pixel and a reset MOS transistor for resetting the gate potential thereof, one bit of storage and output gates is used. Since the CCD is configured and the signal charge is completely transferred to the amplification MOS transistor side, kTC noise generated at the time of pixel reset can be suppressed so as not to be generated. Sensitivity and miniaturization of the pixel cell can be achieved, and further, the miniaturization of the pixel cell has the effect of reducing the size of the device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing only a main part of an embodiment of a solid-state imaging device according to the present invention, FIG. 2 is a sectional structural view showing a structure of one unit cell, and FIG. 3 corresponds to FIG. FIG. 4 is a rear view showing part of the solid-state imaging device according to the present invention, and FIG. 5 is a time chart for explaining the circuit operation of FIG. 1 ... Storage (ST), 2 ... Output gate (OG), 3 ... Reset MOS-FET, 4 ... Amplification MOS-FET, 5 ... FDA (floating diffusion amplifier), 12 ... clamp switch, 15 ...... CDS (correlated double sample-and-hold) circuit, C _1, C ₂ ...... sample / hold capacitors.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/30-5/335 H01L 27/146

Claims (2)

(57) [Claims] 1. A storage for storing a signal charge according to the amount of incident light, an output gate forming a 1-bit charge-coupled device together with the storage, and a signal charge output from the storage through the output gate is amplified and output. And a reset MOS transistor connected between the gate electrode of the amplification MOS transistor and the first reset signal line and having a gate electrode connected to the second reset signal line. A plurality of pixels two-dimensionally arranged in a matrix in the horizontal and vertical directions; and the reset MOS through the first reset signal line.
A horizontal line is selected by applying a first reset signal to the transistor, and a second reset signal is applied to the gate electrode of the reset MOS transistor on the selected horizontal line through the second reset signal line. This resets the gate potential of the amplifying MOS transistor, and then turns on the output gate of the selected horizontal line, and transfers the signal charges stored in the storage through the output gate to the amplifying MOS transistor. A solid-state imaging device, comprising: a vertical scanning circuit for transferring data to a gate electrode. 2. A storage in which each of a plurality of pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions stores a signal charge corresponding to the amount of incident light, and an output which constitutes a 1-bit charge-coupled device together with the storage. A gate, an amplifying MOS transistor for amplifying and outputting the signal charge output from the storage through the output gate, and a gate connected to the gate electrode of the amplifying MOS transistor and the first reset signal line; A reset MOS transistor having a gate electrode connected to a second reset signal line, wherein the reset MOS transistor is driven through the first reset signal line.
Selecting a horizontal line by applying a first reset signal to a transistor, and applying a second reset signal through the second reset signal line to the gate electrode of the reset MOS transistor on the selected horizontal line. For said amplification
Resetting the gate potential of the MOS transistor, and thereafter turning on the output gate of the selected horizontal line, and transferring the signal charges stored in the storage to the gate electrode of the amplifying MOS transistor through the output gate; A method for driving a solid-state imaging device, comprising: